PDU14-30M [ETC]
Delay Line ; 延迟线\n
| 型号： | PDU14-30M |
| 厂家： | 
ETC |
| 描述： | Delay Line
|
| 文件： | 总5页 (文件大小：61K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
PDU14F
Ò
4-BIT PROGRAMMABLE
DELAY LINE
(SERIES PDU14F)
data
delay
3
devices, inc.
FEATURES
PACKAGES
OUT/
OUT
EN/
VCC
A0
1
2
3
4
5
6
7
8
9
24
23
22
21
20
19
18
17
16
·
·
·
·
·
·
·
·
Digitally programmable in 16 delay steps
Monotonic delay-versus-address variation
Two separate outputs: inverting & non-inverting
Precise and stable delays
PDU14F-xx
DIP
PDU14F-xxA4
Gull-Wing
PDU14F-xxB4
J-Lead
A1
GND
N/C
IN
A2
Input & outputs fully TTL interfaced & buffered
VCC
N/C
N/C
N/C
VCC
A3
10 T2L fan-out capability
Fits standard 24-pin DIP socket
Auto-insertable
N/C
GND
N/C
N/C
EN/
PDU14F-xxM
Military DIP
PDU14F-xxMC4
Military Gull-Wing
10 15
11 14
12 13
N/C
N/C
GND
PIN DESCRIPTIONS
FUNCTIONAL DESCRIPTION
IN
Delay Line Input
The PDU14F-series device is a 4-bit digitally programmable delay line.
The delay, TDA, from the input pin (IN) to the output pins (OUT, OUT/)
depends on the address code (A3-A0) according to the following formula:
OUT Non-inverted Output
OUT/ Inverted Output
A0-A3 Address Bits
EN/ Output Enable
VCC +5 Volts
TDA = TD0 + TINC * A
GND Ground
where A is the address code, TINC is the incremental delay of the device,
and TD0 is the inherent delay of the device. The incremental delay is
specified by the dash number of the device and can range from 0.5ns through 100ns, inclusively. The
enable pins (EN/) are held LOW during normal operation. These pins must always be in the same state
and may be tied together externally. When these signals are brought HIGH, OUT and OUT/ are forced
into LOW and HIGH states, respectively. The address is not latched and must remain asserted during
normal operation.
DASH NUMBER SPECIFICATIONS
SERIES SPECIFICATIONS
Part
Number
Incremental Delay
Per Step (ns)
.5 ± .3
Total Delay
Change (ns)
7.5 ± 1.0
15 ± 1.0
30 ± 1.5
45 ± 2.3
60 ± 3.0
75 ± 3.8
150 ± 7.5
225 ± 11.3
300 ± 15.0
450 ± 22.5
600 ± 30.0
750 ± 37.5
1,500 ± 75.0
·
·
·
Total programmed delay tolerance: 5% or 1ns,
whichever is greater
Inherent delay (TD0): 9ns typical (OUT)
8ns typical (OUT/)
Setup time and propagation delay:
Address to input setup (TAIS): 5ns
Disable to output delay (TDISO): 6ns typ. (OUT)
Operating temperature: 0° to 70° C
Temperature coefficient: 100PPM/°C (excludes TD0)
Supply voltage VCC: 5VDC ± 5%
Supply current: ICCH = 74ma
PDU14F-.5
PDU14F-1
PDU14F-2
PDU14F-3
PDU14F-4
PDU14F-5
PDU14F-10
PDU14F-15
PDU14F-20
PDU14F-30
PDU14F-40
PDU14F-50
PDU14F-100
1 ± .5
2 ± .5
3 ± 1.0
4 ± 1.0
5 ± 1.0
10 ± 1.5
15 ± 1.5
20 ± 2.0
30 ± 3.0
40 ± 4.0
50 ± 5.0
100 ± 10.0
·
·
·
·
ICCL = 30ma
Minimum pulse width: 10% of total delay
·
NOTE: Any dash number between .5 and 100 not
shown is also available.
Ó1997 Data Delay Devices
Doc #97002
1/13/97
DATA DELAY DEVICES, INC.
3 Mt. Prospect Ave. Clifton, NJ 07013
1
PDU14F
APPLICATION NOTES
possibility of spurious signals persists until the
required TDISH has elapsed.
ADDRESS UPDATE
The PDU14F is a memory device. As such,
special precautions must be taken when
changing the delay address in order to prevent
spurious output signals. The timing restrictions
are shown in Figure 1.
INPUT RESTRICTIONS
There are three types of restrictions on input
pulse width and period listed in the AC
Characteristics table. The recommended
conditions are those for which the delay
After the last signal edge to be delayed has
appeared on the OUT pin, a minimum time,
TOAX, is required before the address lines can
change. This time is given by the following
relation:
tolerance specifications and monotonicity are
guaranteed. The suggested conditions are
those for which signals will propagate through the
unit without significant distortion. The absolute
conditions are those for which the unit will
produce some type of output for a given input.
TOAX = max { (Ai - A i-1) * TINC , 0 }
where A i-1 and Ai are the old and new address
codes, respectively. Violation of this constraint
may, depending on the history of the input signal,
cause spurious signals to appear on the OUT
pin. The possibility of spurious signals persists
until the required TOAX has elapsed.
When operating the unit between the
recommended and absolute conditions, the
delays may deviate from their values at low
frequency. However, these deviations will
remain constant from pulse to pulse if the input
pulse width and period remain fixed. In other
words, the delay of the unit exhibits frequency
and pulse width dependence when operated
beyond the recommended conditions. Please
consult the technical staff at Data Delay Devices
if your application has specific high-frequency
requirements.
A similar situation occurs when using the EN/
signal to disable the output while IN is active. In
this case, the unit must be held in the disabled
state until the device is able to “clear” itself. This
is achieved by holding the EN/ signal high and
the IN signal low for a time given by:
Please note that the increment tolerances listed
represent a design goal. Although most delay
increments will fall within tolerance, they are not
guaranteed throughout the address range of the
unit. Monotonicity is, however, guaranteed over
all addresses.
TDISH = Ai * TINC
Violation of this constraint may, depending on
the history of the input signal, cause spurious
signals to appear on the OUT pin. The
A3-A0
EN/
A i-1
Ai
TAENS
TOAX
TAIS
TENIS
PWIN
TDISH
IN
TDA
PWOUT
TDISO
OUT
OUT/
TSKEW
Figure 1: Timing Diagram
Doc #97002
1/13/97
DATA DELAY DEVICES, INC.
Tel: 973-773-2299 Fax: 973-773-9672 http://www.datadelay.com
2
PDU14F
DEVICE SPECIFICATIONS
TABLE 1: AC CHARACTERISTICS
PARAMETER
Total Programmable Delay
Inherent Delay
SYMBOL
TDT
MIN
TYP
15
9.0
1.5
6.0
UNITS
TINC
ns
TD0
Output Skew
TSKEW
TDISO
TAENS
TAIS
TENIS
TOAX
TDISH
PERIN
PERIN
PERIN
PWIN
PWIN
PWIN
ns
ns
ns
ns
Disable to Output Low Delay
Address to Enable Setup Time
Address to Input Setup Time
Enable to Input Setup Time
Output to Address Change
Disable Hold Time
2.0
5.0
2.5
ns
See Text
See Text
20
Absolute
% of TDT
% of TDT
% of TDT
% of TDT
% of TDT
% of TDT
Input Period
Suggested
Recommended
Absolute
40
200
10
20
Input Pulse Width
Suggested
Recommended
100
TABLE 2: ABSOLUTE MAXIMUM RATINGS
PARAMETER
DC Supply Voltage
Input Pin Voltage
Storage Temperature
Lead Temperature
SYMBOL
VCC
VIN
TSTRG
TLEAD
MIN
-0.3
-0.3
-55
MAX
7.0
VDD+0.3
150
UNITS NOTES
V
V
C
300
C
10 sec
TABLE 3: DC ELECTRICAL CHARACTERISTICS
(0C to 70C, 4.75V to 5.25V)
PARAMETER
SYMBOL
MIN
TYP
MAX
UNITS
NOTES
High Level Output Voltage
VOH
2.5
3.4
V
VCC = MIN, IOH = MAX
VIH = MIN, VIL = MAX
VCC = MIN, IOL = MAX
VIH = MIN, VIL = MAX
Low Level Output Voltage
VOL
0.35
0.5
V
High Level Output Current
Low Level Output Current
High Level Input Voltage
Low Level Input Voltage
Input Clamp Voltage
Input Current at Maximum
Input Voltage
High Level Input Current
Low Level Input Current
Short-circuit Output Current
Output High Fan-out
IOH
IOL
VIH
VIL
VIK
IIHH
-1.0
20.0
mA
mA
V
V
V
2.0
-60
0.8
-1.2
0.1
VCC = MIN, II = IIK
VCC = MAX, VI = 7.0V
mA
IIH
IIL
IOS
20
-0.6
-150
25
VCC = MAX, VI = 2.7V
VCC = MAX, VI = 0.5V
VCC = MAX
mA
mA
mA
Unit
Load
Output Low Fan-out
12.5
Doc #97002
1/13/97
DATA DELAY DEVICES, INC.
3 Mt. Prospect Ave. Clifton, NJ 07013
3
PDU14F
PACKAGE DIMENSIONS
.020 TYP.
.040 TYP.
.010 TYP.
24 23 22 21 20 19 18 17 16 15 14 13
.270
.430
TYP.
TYP.
1
2
3
4
5
6
7
8
9
10 11 12
.100
24 23 22 21 20 19 18 17 16 15 14 13
Lead Material:
Nickel-Iron alloy 42
TIN PLATE
.110
.300
MAX.
.050
TYP.
1.100
1.290 MAX.
1
2
3
4
5
6
7
8
9 10 11 12
Commercial Gull-Wing (PDU14F-xxA4)
.280
MAX.
1.270
.020 TYP.
.040 TYP.
.050 TYP.
.290
MAX.
24 23 22 21 20 19 18 17 16 15 14 13
.320
TYP.
.270
TYP.
1
2
3
4
5
6
7
8
9
10 11 12
.015 TYP.
.070 MAX.
.010 .002
±
.110
.100
.350
MAX.
.110
TYP.
.018 TYP.
.350
MAX.
1.100
1.100
1.290 MAX.
Commercial DIP (PDU14F-xx)
Commercial J-Lead (PDU14F-xxB4)
24 23 22 21 20
16 15
.410
MAX.
1
2
3
4
6
8
11 12
.020 TYP.
.040 TYP.
.010 .002
±
24 23 22 21 20 19 18 17 16 15 14 13
1.300 TYP.
.882
.710 .590
.005 MAX.
.005
±
±
.300
.007
MAX.
±.005
1
2
3
4
5
6
7
8
9
10 11 12
.100
.130
MIN.
.012 TYP.
.090
.280
MAX.
.050
.018 TYP.
.100 TYP.
.300
TYP.
1.100
1.280±.020
.100
.010
±
1.100 TYP.
Military DIP (PDU14F-xxM)
Military Gull-Wing (PDU14F-xxMC4)
Doc #97002
1/13/97
DATA DELAY DEVICES, INC.
Tel: 973-773-2299 Fax: 973-773-9672 http://www.datadelay.com
4
PDU14F
DELAY LINE AUTOMATED TESTING
TEST CONDITIONS
INPUT:
OUTPUT:
Ambient Temperature: 25oC ± 3oC
Supply Voltage (Vcc): 5.0V ± 0.1V
Load:
Cload
1 FAST-TTL Gate
5pf ± 10%
:
Input Pulse:
High = 3.0V ± 0.1V
Threshold: 1.5V (Rising & Falling)
Low = 0.0V ± 0.1V
Source Impedance:
Rise/Fall Time:
50W Max.
3.0 ns Max. (measured
between 0.6V and 2.4V )
PWIN = 1.5 x Total Delay
PERIN = 4.5 x Total Delay
Pulse Width:
Period:
NOTE: The above conditions are for test only and do not in any way restrict the operation of the device.
PRINTER
COMPUTER
SYSTEM
REF
PULSE
GENERATOR
OUT
IN
OUT
IN
TIME INTERVAL
COUNTER
DEVICE UNDER
TEST (DUT)
TRIG
TRIG
Test Setup
PERIN
PWIN
VIH
TRISE
TFALL
INPUT
SIGNAL
2.4V
1.5V
0.6V
2.4V
1.5V
0.6V
VIL
TDAR
TDAF
OUTPUT
SIGNAL
VOH
1.5V
1.5V
VOL
Timing Diagram For Testing
Doc #97002
1/13/97
DATA DELAY DEVICES, INC.
3 Mt. Prospect Ave. Clifton, NJ 07013
5
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