PEB20571F [ETC]
?DSP Embedded Line and Port Interface Controller ? ; ？ DSP嵌入式线和港口接口控制器？\n
| 型号： | PEB20571F |
| 厂家： | 
ETC |
| 描述： | ?DSP Embedded Line and Port Interface Controller ?
|
| 文件： | 总63页 (文件大小：1518K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Data Sheet, DS4, March 2001
VIP, VIP-8
Versatile ISDN Port
PEB 20590 Version 2.1
PEB 20591 Version 2.1
Wired
Communications
N e v e r s t o p t h i n k i n g .
Edition 2001-03-01
Published by Infineon Technologies AG,
St.-Martin-Strasse 53,
D-81541 München, Germany
© Infineon Technologies AG 2001.
All Rights Reserved.
Attention please!
The information herein is given to describe certain components and shall not be considered as warranted
characteristics.
Terms of delivery and rights to technical change reserved.
We hereby disclaim any and all warranties, including but not limited to warranties of non-infringement, regarding
circuits, descriptions and charts stated herein.
Infineon Technologies is an approved CECC manufacturer.
Information
For further information on technology, delivery terms and conditions and prices please contact your nearest
Infineon Technologies Office in Germany or our Infineon Technologies Representatives worldwide (see address
list).
Warnings
Due to technical requirements components may contain dangerous substances. For information on the types in
question please contact your nearest Infineon Technologies Office.
Infineon Technologies Components may only be used in life-support devices or systems with the express written
approval of Infineon Technologies, if a failure of such components can reasonably be expected to cause the failure
of that life-support device or system, or to affect the safety or effectiveness of that device or system. Life support
devices or systems are intended to be implanted in the human body, or to support and/or maintain and sustain
and/or protect human life. If they fail, it is reasonable to assume that the health of the user or other persons may
be endangered.
Data Sheet, DS4, March 2001
VIP, VIP-8
Versatile ISDN Port
PEB 20590 Version 2.1
PEB 20591 Version 2.1
Wired
Communications
N e v e r s t o p t h i n k i n g .
PEB 20590, PEB 20591
PRELIMINARY
Revision History:
2001-03-01
DS4
Previous Version:
01.00
Page
Subjects (major changes since last revision)
Pull-ups for the signals TMS, TDI, TRST
ID-Code for TAP controller
Page 15
Page 34
Page 29
Page 35
Page 46
Page 46
Maximum wander tolerance
VIP version register
Primary inductance for recommended S/T transformer
External S/T Receiver Circuitry
Page 38-
Electrical Characteristics
Page 45
Note: This revision history is not 100% complete.
For questions on technology, delivery and prices please contact the Infineon
Technologies Offices in Germany or the Infineon Technologies Companies and
Representatives worldwide: see our webpage at http://www.infineon.com
ABM®, AOP®, ARCOFI®, ARCOFI®-BA, ARCOFI®-SP, DigiTape®, EPIC®-1, EPIC®-S, ELIC®, FALC®54, FALC®56,
FALC®-E1, FALC®-LH, IDEC®, IOM®, IOM®-1, IOM®-2, IPAT®-2, ISAC®-P, ISAC®-S, ISAC®-S TE, ISAC®-P TE,
ITAC®, IWE®, MUSAC®-A, OCTAT®-P, QUAT®-S, SICAT®, SICOFI®, SICOFI®-2, SICOFI®-4, SICOFI®-4µC,
SLICOFI® are registered trademarks of Infineon Technologies AG.
ACE™, ASM™, ASP™, POTSWIRE™, QuadFALC™, SCOUT™ are trademarks of Infineon Technologies AG.
PEB 20590
PEB 20591
Table of Contents
Page
1
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
Logic Symbol Diagrams . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Typical Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
1.1
1.2
1.3
2
2.1
2.2
Pin Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Pin Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Pin Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
3
3.1
3.2
Interface Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Overview of Interfaces . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
UPN Line Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Frame Structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
UPN Transceiver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Receive PLL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Receive Signal Oversampling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
S/T Line Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Frame Structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
S/T Transceiver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
Receive Clock Recovery . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
LT-S Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
LT-T Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
Reference Clock Selection in LT-T Mode . . . . . . . . . . . . . . . . . . . . . . . 28
Receive Signal Oversampling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
Elastic Buffer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
IOM-2000 Interface Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
IOM-2000 Frame Structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
Data Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
JTAG Boundary Scan Test Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
TAP Controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
3.2.1
3.2.2
3.2.3
3.2.4
3.3
3.3.1
3.3.2
3.3.3
3.3.3.1
3.3.3.2
3.3.4
3.3.5
3.3.6
3.4
3.4.1
3.4.1.1
3.5
3.5.1
4
Operational Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
General . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
Initialization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
Analog Test Loops . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
Monitoring of Code Violations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
4.1
4.2
4.3
4.4
4.5
5
Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
Operating Range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
DC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
Capacitances . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
Recommended 15.36-MHz Crystal Parameters . . . . . . . . . . . . . . . . . . . . 41
5.1
5.2
5.3
5.4
5.5
Data Sheet
2001-03-01
PEB 20590
PEB 20591
Table of Contents
Page
5.6
5.7
5.8
5.9
5.10
5.11
5.12
AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
REFCLK . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
Upn Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
IOM-2000 Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
JTAG Boundary Scan Test Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
UPN Transmitter Performance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
S/T Transmitter Performance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
6
6.1
6.1.1
6.1.2
6.1.3
6.2
Application Hints . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
VIP External Circuitry . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
Recommended Line Transformers . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
UPN Interface External Circuitry . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
S/T Interface External Circuitry . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
Wiring Configurations in LT-S Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49
Loop Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
6.3
7
8
9
Package Outlines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51
Glossary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52
Index . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53
Data Sheet
2001-03-01
PEB 20590
PEB 20591
List of Figures
Page
Figure 1
Figure 2
Figure 3
Figure 4
Figure 5
Figure 6
Figure 7
Figure 8
Top-Level Block Diagram of the VIP . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
Logic Symbol PEB 20590 (72 of 80 Pins used). . . . . . . . . . . . . . . . . . . 6
Logic Symbol PEB 20591 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
VIP in Mixed S/T and UPN Line Cards (e.g. 8 S/T and 16 UPN). . . . . . . 7
VIP in a Small PBX Solution . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
DELIC-PB and VIP in a PC Card for 8/16 S/T Interfaces . . . . . . . . . . . 8
Pin Diagram, PEB 20590. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Pin Diagram, PEB 20591. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
UPN Interface Frame Structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
AMI Coding on the UPN Interface in VIP . . . . . . . . . . . . . . . . . . . . . . . 19
Transceiver Functional Blocks. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Equalizer Effect . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Receive Signal Oversampling on UPN Interface . . . . . . . . . . . . . . . . . 22
Frame Structure at Reference Points S and T (ITU-T I.430) . . . . . . . . 23
S/T Interface Line Code (without Code Violation) . . . . . . . . . . . . . . . . 24
Receiver Functional Blocks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
Clock Recovery in LT-T Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
LT-T Reference Clock Channel Selection for Cascaded VIPs. . . . . . . 28
Receive Signal Oversampling in S/T Receiver . . . . . . . . . . . . . . . . . . 29
Overview of IOM-2000 Interface Structure (Example with One VIP). . 30
IOM-2000 Data Sequence (1 VIP with 8 Channels) . . . . . . . . . . . . . . 32
IOM-2000 Data Order (3 VIPs with 24 Channels) . . . . . . . . . . . . . . . . 33
Recommended Oscillator Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
Input/Output Wave Form for AC Tests. . . . . . . . . . . . . . . . . . . . . . . . . 42
IOM-2000 Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
JTAG Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
1:1 Transformer Model. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
External Transceiver Circuitry of the VIP in UPN Mode . . . . . . . . . . . . 47
Overview of External Circuitry of the VIP in S/T Mode . . . . . . . . . . . . 47
External S/T Transmitter Circuitry . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
External S/T Receiver Circuitry . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
Wiring Configurations in User Premises (LT-S Mode). . . . . . . . . . . . . 49
Internal and External Loop-Back Modes . . . . . . . . . . . . . . . . . . . . . . . 50
Figure 9
Figure 10
Figure 11
Figure 12
Figure 13
Figure 14
Figure 15
Figure 16
Figure 17
Figure 18
Figure 19
Figure 20
Figure 21
Figure 22
Figure 23
Figure 24
Figure 25
Figure 26
Figure 27
Figure 28
Figure 29
Figure 30
Figure 31
Figure 32
Figure 33
Data Sheet
2001-03-01
PEB 20590
PEB 20591
List of Tables
Page
Table 1
Table 2
Table 3
Table 4
Table 5
Table 6
Table 7
Table 8
Table 9
Table 10
Table 11
Table 12
Table 13
Table 14
Table 15
VIP Product Family . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
PEB 20590: UPN and S/T Line Interface . . . . . . . . . . . . . . . . . . . . . . . 11
PEB 20591: UPN and S/T Line Interface . . . . . . . . . . . . . . . . . . . . . . . 12
IOM-2000 Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Clock Signals and Dedicated Pins. . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Power Supply and Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
JTAG Boundary Scan Test Interface (IEEE 1149.1) . . . . . . . . . . . . . . 15
Control Bits in S/T Mode on DR Line. . . . . . . . . . . . . . . . . . . . . . . . . . 31
Control Bits in S/T Mode on DX Line . . . . . . . . . . . . . . . . . . . . . . . . . . 31
TAP Controller Instruction Codes Overview . . . . . . . . . . . . . . . . . . . . 34
DC Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
I/O Capacitances (except line interfaces and clocks) . . . . . . . . . . . . . 41
Recommended Crystal Parameters. . . . . . . . . . . . . . . . . . . . . . . . . . . 41
IOM-2000 Interface Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
JTAG Boundary Scan Timing Values . . . . . . . . . . . . . . . . . . . . . . . . . 45
Data Sheet
2001-03-01
PEB 20590
PEB 20591
Preface
This document provides reference information on VIP1) (Versatile ISDN Port).
Organization of this Document
This Data Sheet is divided into 9 chapters. It is organized as follows:
• Chapter 1, Introduction
Gives a general description of the VIP, lists the key features, and presents some
typical applications.
• Chapter 2, Pin Description
Lists pin locations with associated signals, categorizes signals according to function,
and describes signals.
• Chapter 3, Interface Description
Describes the VIP external interfaces.
• Chapter 4, Operational Description
Describes the VIP operations reset, initialization, analog test loops and the monitoring
of illegal code violations.
• Chapter 5, Electrical Characteristics
Contains the DC and AC specification and timing diagrams.
• Chapter 6, Application Hints
Provides information on external line interface circuitry in UPN and S/T mode, such as
transformers and line protection.
• Chapter 7, Package Outlines
• Chapter 8, Glossary
• Chapter 9, Index
1)
Throughout this document the name VIP will be used to refer to both chip versions PEB 20590 and PEB 20591.
Data Sheet
1
2001-03-01
PEB 20590
PEB 20591
PRELIMINARY
Your Comments
We welcome your comments on this document. We are continuously trying to improve
our documentation. Please send your remarks and suggestions by e-mail to
sc.docu_comments@infineon.com
Please provide in the subject of your e-mail:
device name (VIP), device number (PEB 20590), device version (Version 2.1),
and in the body of your e-mail:
document type (Data Sheet), issue date (2001-03-01) and document revision number
(DS4).
Related Documentation
• Data Sheet for DELIC Version 2.3 or higher (PEB 20570, PEB 20571)
Data Sheet
2
2001-03-01
PEB 20590
PEB 20591
Introduction
PRELIMINARY
1
Introduction
This chapter gives a general overview of the VIP including a top-level block diagram and
the logic symbol diagram, it lists the key features, and presents some typical
applications.
1.1
Overview
VIP (Versatile ISDN Port) is a highly-integrated multiple layer-1 transceiver IC
connecting to
• UPN subscriber line interfaces (2-wire) and
• S/T subscriber or trunk line interfaces (4-wire).
VIP integrates the complete analog line interface circuitry as well as the transceiver logic
required for eight full-duplex channels.
Typical VIP applications include PBX line cards (UPN, S/T or mixed), and small PBXs.
VIP must be operated in combination with DELIC1), which is required for configuration
and control/activation of VIP’s layer-1 transceivers. The communication path between
the DELIC and the VIP is the serial IOM-2000 interface with a data rate of up to 12.288
Mbit/s. DELIC also processes the signaling information of each VIP channel by providing
a dedicated HDLC controller per subscriber. For more information on DELIC and the
IOM-2000 interface, please refer to the DELIC-LC/-PB Data Sheet.
1)
Infineon Technologies DELIC: DSP Embedded Line and Port Interface Controller. The DELIC is available in
two versions: PEB 20570 and PEB 20571.
Data Sheet
3
2001-03-01
PEB 20590
PEB 20591
Introduction
PRELIMINARY
The VIP is available in two different versions, which differ in the possible interface
combinations:
Table 1
Device
VIP
VIP Product Family
Available Interfaces
PEB 20590 Four channels are programmable to either S/T or UPN mode, and
the other four channels can be operated in UPN mode only.
•
Maximum Number of UPN and S/T channels
UPN
S/T
8
0
7
1
6
2
5
3
4
4
3
4
2
4
1
4
0
4
VIP-8 PEB 20591 All eight channels are programmable to either S/T or UPN mode.
•
Maximum Number of UPN and S/T channels
UPN
S/T
8
0
7
1
6
2
5
3
4
4
3
5
2
6
1
7
0
8
IOM-2000
S/T or
UPN
UPN and S/T
Transceiver
IOM-2000
Interface
Analog Line
Interface
DELIC
Clock
JTAG
Central Biasing
vip_0002_block_diagram
Figure 1
Top-Level Block Diagram of the VIP
Data Sheet
4
2001-03-01
PRELIMINARY
Versatile ISDN Port
VIP, VIP-8
PEB 20590
PEB 20591
Version 2.1
CMOS
1.2
VIP Key Features
VIP is a universal ISDN transceiver IC for different
interface modes (S/T or UPN).
• Eight 2B+D line interfaces with full duplex
transceivers
– S/T interfaces at 192 kbit/s with line transceivers
according to ITU-T I.430, ETSI 300.012 and ANSI
T1.605
P-MQFP-80-1
– UPN interfaces at 384 kbit/s with line transceivers according to ZVEI standard
– Receive timing recovery
– Conversion between pseudo-ternary and binary codes
– Conversion between UPN or S/T frames and IOM-2000 frame structures
– Execution of test loops
– Frame alignment in trunk applications with maximum wander correction of ± 25 µs
– UPN interface compatible to OCTAT-P (PEB 2096)1)
– S/T interface compatible to QUAT-S (PEB 2084)2)
• IOM-2000 interface to DELIC supporting up to three VIPs (24 channels)
– Transceiver initialization and configuration
– Control of layer-1 activation/deactivation
– Exchange of command and status information
• Signaling control for all VIP channels by dedicated HDLC controllers in DELIC
• Single 3.3 V power supply
• JTAG IEEE1149.1-compliant test interface with dedicated reset input
Note: UPN refers to a version of the UP0 interface (meeting the ZVEI standard) with a
reduced loop length of up to 1.3 km, depending on the type of cable.
1)
Infineon Technologies OCTAT-P (PEB 2096): Octal Transceiver for UPN-Interfaces.
Infineon Technologies QUAT-S (PEB 2084): Quadruple Transceiver for S/T-Interface.
2)
Type
Package
PEB 20590, PEB 20591
P-MQFP-80-1
Data Sheet
5
2001-03-01
PEB 20590
PEB 20591
Introduction
PRELIMINARY
1.3
Logic Symbol Diagrams
Power Supply Analog / Digital,
Reset
27
24
S/T and UPN
Line Interface
7
IOM-2000
Interface
VIP
PEB 20590
6
Dedicated
Pins
5
3
Clock
Signals
JTAG
vip_0003_logic_symbol
Test Interface
Figure 2
Logic Symbol PEB 20590 (72 of 80 Pins used)
Power Supply Analog / Digital,
Reset
27
32
S/T and UPN
Line Interface
7
IOM-2000
Interface
VIP-8
PEB 20591
6
Dedicated
Pins
5
3
Clock
Signals
JTAG
vip_0006_8logic_symbol
Test Interface
Figure 3
Logic Symbol PEB 20591
Data Sheet
6
2001-03-01
PEB 20590
PEB 20591
Introduction
PRELIMINARY
1.4
Typical Applications
Typical VIP applications are PBX line cards (UPN, S/T or mixed), and small PBXs.
The following figures illustrate sample configurations in which the VIP shows its
flexibility.
•
up to
4 x
IOM-2000
S/T
VIP
PEB 20590
PCM
4 x
4 x 32 TS
UPN
DELIC
up to
4 x
PEB 20570
(PEB 20571)
S/T
VIP
PEB 20590
4 x
UPN
Signaling
up to 2.048 Mbit/s
8 x
VIP
UPN
PEB 20590
µP
Memory
Infineon
C166
vip_0004_line_card
Figure 4
VIP in Mixed S/T and UPN Line Cards (e.g. 8 S/T and 16 UPN)
•
IOM-2
HV-SLIC
SLICOFI-2
PCM
HV-SLIC
up to 32 TS
32 x t/r
HV-SLIC
HV-SLIC
SLICOFI-2
DELIC-PB
PEB 20571
4 x
UPN
IOM-2000
VIP
2 x S
2 x T
LNC
PEB 20590
Central
Office
2 Mbit/s
for service
µP
Power
Memory
Infineon
C166
Supply
vip_0007_pbx
Figure 5
VIP in a Small PBX Solution
Data Sheet
7
2001-03-01
PEB 20590
PEB 20591
Introduction
PRELIMINARY
•
VIP-8
H.100/
H.110
PCM
8 x S
PEB 20591
(optional)
SWITI
(optional)
DELIC-PB
PEB 20571
6 x S
2 x T
VIP-8
IOM-2000
PEB 20591
Central
Office
PCI
PITA
µP
Memory
Infineon
C166
vip_0008_pc_card
Figure 6
DELIC-PB and VIP in a PC Card for 8/16 S/T Interfaces
Data Sheet
8
2001-03-01
PEB 20590
PEB 20591
Pin Description
PRELIMINARY
2
Pin Description
The VIP is available in an 80-pin Plastic Metric Quad Flat Package (P-MQFP-80-1). This
chapter presents a simple layout of the 80-pin MQFP package with pin and signal
callouts and a table of signal definitions.
2.1
Pin Configuration
(top view)
P-MQFP-80-1
60
61
56
52
48
41
44
40
36
32
28
SR5b/LI5b
SR5a/LI5a
VDDA
SR3b/Ll3b
SR3a/Ll3a
VDDA
VSSA
SX3b
64
68
72
76
80
VSSA
SX5b
SX5a
VDDA
VSSA
n.c.
n.c.
VSSA
VDDA
LI6a
SX3a
VIP_ADD1
VIP_ADD0
n.c.
n.c.
VSSA
VDDA
Ll2a
Ll2b
SR1b/Ll1b
SR1a/Ll1a
VDDA
VSSA
SX1b
VIP
PEB 20590
LI6b
SR7b/LI7b
SR7a/LI7a
VDDA
24
21
VSSA
SX7b
SX7a
SX1a
1
4
8
12
16
20
vip_0001_pinout
Figure 7
Pin Diagram, PEB 20590
Data Sheet
9
2001-03-01
PEB 20590
PEB 20591
Pin Description
PRELIMINARY
(top view)
P-MQFP-80-1
60
61
56
52
48
41
44
40
36
32
28
SR5b/LI5b
SR5a/LI5a
VDDA
SR3b/Ll3b
SR3a/Ll3a
VDDA
VSSA
SX3b
64
68
72
76
80
VSSA
SX5b
SX5a
VDDA
VSSA
SX6a
SX6b
VSSA
SX3a
VIP_ADD1
VIP_ADD0
SX2a
SX2b
VSSA
VIP-8
PEB 20591
VDDA
VDDA
SR6a/LI6a
SR6b/LI6b
SR7b/LI7b
SR7a/LI7a
VDDA
SR2a/Ll2a
SR2b/Ll2b
SR1b/Ll1b
SR1a/Ll1a
VDDA
VSSA
SX1b
SX1a
24
21
VSSA
SX7b
SX7a
1
4
8
12
16
20
vip_0005_vip8_pinout
Figure 8
Pin Diagram, PEB 20591
Data Sheet
10
2001-03-01
PEB 20590
PEB 20591
Pin Description
PRELIMINARY
2.2
Pin Descriptions
Table 2
PEB 20590: UPN and S/T Line Interface
In (I) During Function
Out(O) Reset
Pin Symbol
No.
25
26
39
40
62
61
76
75
SR1a/LI1a
SR1b/LI1b
SR3a/LI3a
SR3b/LI3b
SR5a/LI5a
SR5b/LI5b
SR7a/LI7a
SR7b/LI7b
I / I/O
I/O
O
I
S/T Receive Channel 1, 3, 5, 7
UPN Transmit/Receive Channel 1, 3, 5, 7
/
12
13
28
27
48
47
73
74
LI0a
LI0b
LI2a
LI2b
LI4a
LI4b
LI6a
LI6b
I
UPN Transmit/Receive Channel 0, 2, 4, 6
S/T Transmit Channel 1, 3, 5, 7
not connected
21
22
35
36
66
65
80
79
SX1a
SX1b
SX3a
SX3b
SX5a
SX5b
SX7a
SX7b
O
8, 9, n.c.
31,
-
-
32,
51,
52,
69,
70
Data Sheet
11
2001-03-01
PEB 20590
PEB 20591
Pin Description
PRELIMINARY
Table 3
PEB 20591: UPN and S/T Line Interface
In (I) During Function
Out(O) Reset
Pin Symbol
No.
12
13
25
26
27
28
39
40
48
47
62
61
73
74
76
75
SR0a/LI0a
SR0b/LI0b
SR1a/LI1a
SR1b/LI1b
SR2a/LI2a
SR2b/LI2b
SR3a/LI3a
SR3b/LI3b
SR4a/LI4a
SR4b/LI4b
SR5a/LI5a
SR5b/LI5b
SR6a/LI6a
SR6b/LI6b
SR7a/LI7a
SR7b/LI7b
I / I/O
I
S/T Receive Channel /
UPN Transmit/Receive Channel
8
9
SX0a
SX0b
SX1a
SX1b
SX2a
SX2b
SX3a
SX3b
SX4a
SX4b
SX5a
SX5b
SX6a
SX6b
SX7a
SX7b
O
O
S/T Transmit Channel
21
22
32
31
35
36
52
51
66
65
69
70
80
79
Data Sheet
12
2001-03-01
PEB 20590
PEB 20591
Pin Description
PRELIMINARY
Table 4
IOM-2000 Interface
Pin
No.
Symbol
In (I)
Out (O) Reset
During
Function
18
FSC
I
I
I
I
IOM-2000 Frame SynChronization
8 kHz signal for IOM-2000 frames
19
DCL_2000
IOM-2000 Data CLock
Data Clock from DELIC (3.072, 6.144 or
12.288 MHz in case of 1, 2 or 3 VIPs)
1
DR
O
I
O
I
IOM-2000 Data Receive
Data received on the line interface is
sent to the DELIC
20
2
DX
IOM-2000 Data Transmit
Data to be transmitted on the line
interface is received from the DELIC.
CMD
STAT
REFCLK
I
I
IOM-2000 ComManD
Receives the commands from the
DELIC.
3
O
O
O
O
IOM-2000 STATus
Transmits the VIP status information to
the DELIC.
4
IOM-2000 REFerence CLocK
Provides a 1.536 MHz reference clock
(e.g. derived from Central Office in LT-T
applications) to the DELIC
Data Sheet
13
2001-03-01
PEB 20590
PEB 20591
Pin Description
PRELIMINARY
Table 5
Clock Signals and Dedicated Pins
Pin
No.
Symbol
In (I)
Out (O) Reset
During Function
42
43
CLK15-I
CLK15-O
I
O
I
O
15.36-MHz External Crystal Input
15.36-MHz External Crystal Output
17
INCLK
I
I
I
External Reference CLocK INput
Reference clock from VIP or Central Office
33
34
VIP_ADD0 I
VIP_ADD1
VIP ADDress Pins
Determines the sequential order of up to
3 VIPs in the IOM-2000 frame for the 12-
MHz case:
VIP_ADD(1:0)
’00’ = VIP in 1st quarter of IOM-2000 frame
’01’ = VIP in 2nd quarter of IOM-2000 frame
’10’ = VIP in 3rd quarter of IOM-2000 frame
’11’ = Reserved for future connection of VIP
in 4th quarter of IOM-2000 frame. Currently
only the lower addresses are available.
(refer to IOM-2000 description in DELIC-LC/
-PB Data Sheet)
16
41
IDDQ
I
I
I
I
IDDQ Test Mode
Forces the Line Interface Unit into power
down mode for IDDQ testing.
POWDN
Oscillator POWer DowN
Switches the internal oscillator into power
down mode (in case that 15.36-MHz input
clock is provided by the DELIC)
5
DIR
O
I
O
I
DIRection of Transfer on UPN Line Interface
Indicates the direction of the data transfer
(Tx or Rx) in UPN ping-pong mode (required
for driving electronic transformers).
60
SCANEN
SCAN ENable
If driven to ’1’ during device tests, a full scan
of the VIP is enabled.
Data Sheet
14
2001-03-01
PEB 20590
PEB 20591
Pin Description
PRELIMINARY
Table 6
Power Supply and Reset
Symbol In (I) During Function
Out (O) Reset
Pin
No.
11, 24, V
29, 38,
49, 63,
67, 72,
77
I
I
Power Supply 3.3 V Analog
Used for VIP analog logic
DDA
6, 14,
45, 53
V
I
I
I
I
Power Supply 3.3 V Digital
Used for VIP digital logic
Reference Ground (0 V) Analog
DDD
SSA
10, 23, V
30, 37,
50, 64,
68, 71,
78
7, 15,
46, 54
V
I
I
Reference Ground (0 V) Digital
SSD
44
RESET I
’low’
System Reset
VIP is forced to go into reset state.
Table 7
JTAG Boundary Scan Test Interface (IEEE 1149.1)
Symbol In (I) During Function
Out (O) Reset
Pin
No.
58
TCK
I
I
Test ClocK
Provides a clock for JTAG test logic.
57
TMS
I
I
Test Mode Select (internal pull-up)
A ’0’ to ’1’ transition on this pin is required to step
through the TAP controller state machine.
56
59
55
TDI
I
I
Test Data Input (internal pull-up)
In the appropriate TAP controller state, test data
or a instruction is shifted in via this line.
TDO
TRST
O
I
O
I
Test Data Output
In the appropriate TAP controller state, test data
or a instruction is shifted out via this line.
Test ReSeT (internal pull-up)
Provides an asynchronous reset to the TAP
controller state machine.
Data Sheet
15
2001-03-01
PEB 20590
PEB 20591
Interface Description
PRELIMINARY
3
Interface Description
The VIP provides four types of external interfaces: UPN line interfaces, S/T line
interfaces, an IOM-2000 interface and a JTAG boundary scan test interface. These
interfaces are described in the following sections:
3.1
Overview of Interfaces
The VIP provides the following system interfaces:
• UPN line interfaces
The VIP provides up to 8 independent UPN line interfaces for connection of ISDN
terminals or DECT base stations.
• S/T line interfaces
The PEB 20590 provides up to 4 independent S/T line interfaces (up to 8 for PEB
20591). They can be operated in subscriber mode (LT-S) or trunk mode (LT-T).
• IOM-2000 interface
– Up to three VIPs can be connected to one DELIC via the IOM-2000 interface.
– VIP’s transceivers are initialized and controlled by the DELIC.
• JTAG boundary scan test interface
– The VIP provides a standard test interface according to IEEE 1149.1.
– User-specific instructions are implemented to generate periodic test patterns on the
line.
– The TAP controller has an own reset input.
3.2
UPN Line Interface
The functionality is compatible to OCTAT-P (PEB 2096). 1:1 transformers are required.
3.2.1
Frame Structure
The UPN interface uses a ping-pong technique for 2B+D data transmission over the line.
UPN is always point-to-point.
The frame structure of the data transfer between the exchange (PBX, LT) and the
terminal (TE) is depicted in Figure 9.
• The PBX starts a transmission every 250 µs (burst repetition period).
• A frame transmitted by the exchange (PBX) is received by the terminal (TE) after a
given propagation delay td.
• The terminal waits a minimum guard time (tg = 5.2 µs) while the line clears. Then a
frame is transmitted from the terminal to the PBX.
Data Sheet
16
2001-03-01
PEB 20590
PEB 20591
Interface Description
PRELIMINARY
• The time between the end of reception of a frame from the TE and the beginning of
transmission of the next frame by the LT must be greater than the minimum guard
time. The guard time in TE is always defined with respect to the M-bit.
•
tr
LT
TE/PT
td
tg
td
)
LF
B1
8
B2
8
D
4
B1
8
B2
8
M1 DC 2)
1
1
#Bits
99
µ
s
LF-Framing Bit
1)
CV
T
S
T
CV
T
S
T
CV
M Channel Superframe
ITD00823
CV = Code Violation: for Superframe synchronization
T = Transparent Channel (2 kbit/s)
S = Service Channel (1 kbit/s)
2)
DC balancing bit, only sent after a code violation in the
M-bit position and in special configurations.
Timings: tr = burst repetition period = 250
µs
td = ine delay = 20.8
tg = guard time = 5.2
µ
s maximum
s minimum
µ
Figure 9
UPN Interface Frame Structure
Data Rates
Within a burst, the UPN data rate is 384 kbit/s using a 38-bit frame structure. During the
250-µs burst repetition period, 4 D-bits, 16 B1-bits and 16 B2-bits are transferred in each
direction, resulting in a full-duplex user data rate of 144 kbit/s.
Data Sheet
17
2001-03-01
PEB 20590
PEB 20591
Interface Description
PRELIMINARY
Control and Maintenance Bits
Bit Description
LF Framing Bit
Always logical ‘1’.
M
M-Bit
Final bit of the frame. Four successive M-bits compose a superframe. Three
signals are carried in this superframe:
CV Code Violation Bit
First bit of the superframe. Used for superframe synchronization.
S
Service Bit
Third bit of the superframe. Accessible via DELIC’s command/status interface.
Conveys test loop control information from the PBX to the TE and reports
transmission errors from the TE to the PBX (far-end code violation).
T
T-Bit
2nd and 4th bit of the superframe. Accessible via DELIC’s command/status
interface. Carries the D-channel "available/blocked" information for the terminal
and the DECT synchronization information.
DC DC Balancing Bit
May be added to the burst to decrease DC offset voltage on the line after
transmission of a CV in the M-bit position. VIP issues this DC balancing bit when
transmitting INFO 4 (line activated and synchronized), and when line
characteristics indicate a potential decrease in performance. DELIC is able to
enable or disable this feature (via the DELIC BBC command bit).
UPN Coding
The coding technique used in the VIP transceiver is half-bauded AMI code with a 50 %
pulse width (refer to Figure 10).
•
Binary Value
Logical ‘0’
AMI Code with 50 % Pulse Width
Neutral level
Logical ‘1’
Alternate positive and negative pulses
A Code Violation (CV) is caused by two successive pulses with the same polarity.
Data Sheet
18
2001-03-01
PEB 20590
PEB 20591
Interface Description
PRELIMINARY
•
Figure 10
AMI Coding on the UPN Interface in VIP
Scrambling / Descrambling
B-channel data on the UPN interface is scrambled to ensure that the receiver at the
subscriber terminal gets enough pulses for a reliable clock extraction (flat continuous
power density spectrum), and to avoid periodical patterns on the line. The scrambler/
descrambler polynomial implemented in DELIC complies with ITU-T V.27 and
OCTAT-P.
Data Sheet
19
2001-03-01
PEB 20590
PEB 20591
Interface Description
PRELIMINARY
3.2.2
UPN Transceiver
The receiver input stages consist of an amplifier/equalizer, followed by a peak detector
adaptively controlling the thresholds of the comparators and a digital oversampling unit.
Receive
Data
Receive
Clock
CLK15-I
RxPLL and Oversampling
Comparators
LIa
LIb
Peak
Detector
Up_TRANS.vsd
Transmit
Data
Figure 11
Transceiver Functional Blocks
Amplitude
Cable
Frequency
equi_up.vsd
Figure 12
Equalizer Effect
The equalizer compensates the loss of Amplitude of higher frequencies (see Figure 12).
In order to reach the best performance and range of the UPN transceiver, it is
recommended to use the equalizer with automatic adaptation.
Data Sheet
20
2001-03-01
PEB 20590
PEB 20591
Interface Description
PRELIMINARY
To enable the filter of equalizer inside the VIP, set bit TICCMR:FIL to ’1’ (please refer to
VIP channel config description in DELIC-LC/-PB SW User’s Manual). The adaptive
amplifier control of the equalizer should be set to automatic. Set bit TICCMR:AAC (1:0)
to ’00’ (please refer to VIP channel config description in DELIC-LC/-PB SW User’s
Manual).
3.2.3
Receive PLL
The receive PLL (RxPLL) recovers bit timing from a comparator output signal.
Note: The recommended setting for the receive PLL is integral behaviour. This is
enabled by setting bit TICCMR:PLLINT=’1’ (please refer to VIP channel
config description in DELIC-LC/-PB SW User’s Manual).
Comparator threshold.
The comparator has a threshold of 80 % with respect to the signal stored by the peak
detector.
Phase adjustment.
The RxPLL performs tracking after detecting phase shifts of the same polarity in four
consecutive pulses. A phase adjustment is done by adding or subtracting 65 ns or
32.5 ns (one UPN oscillator period), programmable by the DELIC command bit ’PLLS’
(default TICCMR:PLLS ’0’), to or from the 384 kHz receive data clock.
3.2.4
Receive Signal Oversampling
In order to further reduce the bit error rate in severe conditions, the VIP performs
oversampling of the received signal and uses majority decision logic. The process of
receive signal oversampling is illustrated in Figure 13:
• Each received bit is sampled 6 times at 15.36-MHz clock intervals inside the estimated
bit window.
• The samples obtained are compared to a threshold of 50 % with respect to the signal
stored by the peak detector.
If at least ’n’ samples have an amplitude exceeding the 50 % threshold, a logical ’1’ is
detected; otherwise a logical ’0’ (no signal) is assumed.
The parameter ’n’ is programmed in steps of 2 in bits OWIN(2:0) of IOM-2000 CMD
register.
Note: The recommended setting for signal oversampling is TICCMR:OWIN =’011’.
For detailed description please refer to DELIC-LC/-PB Data Sheet.
Data Sheet
21
2001-03-01
PEB 20590
PEB 20591
Interface Description
PRELIMINARY
.
Figure 13
3.3
Receive Signal Oversampling on UPN Interface
S/T Line Interface
The functionality is compatible with that of QUAT-S (PEB 2084). External protection
circuitry is reduced, and 1:1 transformers are required.
Data Sheet
22
2001-03-01
PEB 20590
PEB 20591
Interface Description
PRELIMINARY
3.3.1
Frame Structure
The S/T interface uses two pairs of copper wires (dedicated to transmit and receive) for
2B+D data transfer. It builds a direct link between the VIP and connected subscriber
terminals or the Central Office. It supports point-to-point or point-to-multipoint modes.
Data and maintenance information is accessible by DELIC via the IOM-2000 interface.
•
Figure 14
Frame Structure at Reference Points S and T (ITU-T I.430)
•
Bit
Description
Framing Bit
F
F = (0b) → code violation, identifies a new frame (always positive pulse)
L.
D
E
DC Balancing Bit
L. = (0b) → number of binary ZEROs sent after the previous L. bit was odd
D-Channel Data
Signaling data specified by user
D-Channel Echo Bit
E = D if D-channel is not blocked, otherwise E = D. (ZEROs always overwrite
ONEs)
FA
Auxiliary Framing Bit
See section 6.3 in ITU I.430
N
N = FA
B1
B1-Channel Data
User data
B2
B2-Channel Data
User data
Data Sheet
23
2001-03-01
PEB 20590
PEB 20591
Interface Description
PRELIMINARY
Bit
Description
A
Activation Bit
A = (0b) → INFO 2 transmitted
A = (1b) → INFO 4 transmitted
S
S-Channel Data Bit
S1 and S2 channel data
M
Multiframing Bit
M = (1b) → Start of new multi-frame
Data Rates
The S/T transmission rate is 192 kbit/s (36 bits user data and 12 bits control and
maintenance). Frames are transmitted with a 2-bit offset in TE/LT-T → LT-S direction.
S/T Coding
The coding technique used on the S/T interface is a full-bauded AMI code with 100 %
pulse width (refer to Figure 15).
•
Binary Value
AMI Code with 100 % Pulse Width
Logical ‘0’
Alternate positive and negative pulses.
There are two exceptions:
• The first binary ’0’ following the first DC balancing bit is
of the same polarity as the DC bit,
• The F-bit is always at positive level (required code
violations).
Logical ‘1’
No line signal (0 V)
•
Figure 15
S/T Interface Line Code (without Code Violation)
Data Sheet
24
2001-03-01
PEB 20590
PEB 20591
Interface Description
PRELIMINARY
3.3.2
S/T Transceiver
Receiver Characteristics
The receiver input stages consist of a differential amplifier, followed by a peak detector
and a set of comparators. Additional noise immunity is achieved by digital oversampling
after the comparators, meaning that the sampling of the received bit is controlled digitally
and dependent on the mode (Command Register).
The peak detector requires at most 2 µs to reach the peak value while storing the peak
level for at least 250 µs. The data detection thresholds are set to 35 % of the peak
voltage to increase the performance in extended passive bus configurations. However,
they are never lower than 85 mV with respect to the line signal level in order to increase
noise immunity.
The level detector monitors the line input signals to detect whether an INFO signal is
present. It is possible to indicate an incoming signal during activated analog loop.
1.65 V
Figure 16
3.3.3
Receiver Functional Blocks
Receive Clock Recovery
The VIP generates the internal clocks with a PLL, that receives a 15.36-MHz signal via
an on-chip oscillator either from an external crystal or from the DELIC.
•
VIP Operating Mode
All Clocks Synchronized to
LT-S or UPN mode
IOM-2000 interface data clock provided by the DELIC on
DCL_2000 pin
LT-T mode
Data Sheet
Data clock provided by the Central Office
25
2001-03-01
PEB 20590
PEB 20591
Interface Description
PRELIMINARY
3.3.3.1 LT-S Mode
In the LT-S mode, the DELIC is the clock master to all terminals connected to the VIP.
In receive direction, two cases are distinguished, depending on the bus configuration:
• Point-to-point or extended passive bus
• Short passive bus.
Point-to-Point or Extended Passive Bus
• Programmed by DELIC IOM-2000 Command bits:
MOSEL(1:0) = ’00’ MODE(2:0) = ’011’
• The 192-kHz receive bit clock is recovered (via PLL) from the receive data stream on
the S interface.
• Shift between receive and transmit frame:
According to ITU-T I.430, the receive frame may be shifted by 2 to 8 bits with respect
to the transmit frame. VIP supports also other frame shifts, including 0.
Note: The recommended setting for point-to-point and extended passive bus in
LT-S mode is TICCMR:OWIN=’101’ and TICCMR:PD=’0’. For detailed
description please refer to VIP channel config command in the DELIC-LC/-
PB SW User’s Manual.
Short Passive Bus
• Programmed by DELIC IOM-2000 Command bits:
MOSEL(1:0) = ’00’, MODE(2:0) = ’111’
• The 192-kHz receive bit clock is identical to the transmit bit clock generated by division
of the incoming IOM-2000 data clock.
• Shift between receive and transmit frame:
The sampling instant for the receive bits is shifted by 4.6 µs with respect to the
transmit bit clock. According to ITU-T I.430, the receive frame must be shifted
(delayed) by two bits with respect to the transmit frame.
Note: If one VIP has channels working in LT-S and UPN mode, then the F-bits appear on
the S interface 6 UPN clocks (nominal case) later than the F-bits on the UPN lines
(within the same sync frame).
Note: The recommended setting for short passive bus in LT-S mode is
TICCMR:OWIN=’001’ and TICCMR:PD=’0’. For detailed description please
refer to VIP channel config command in the DELIC-LC/-PB SW User’s
Manual.
Data Sheet
26
2001-03-01
PEB 20590
PEB 20591
Interface Description
PRELIMINARY
3.3.3.2 LT-T Mode
• Programmed by DELIC IOM-2000 Command bits:
MOSEL (1:0) = ’00’, MODE(2:0) = ’001’
• In LT-T applications, the VIP/DELIC system operates as slave to the central office
clock.
• The 192-kHz receive bit timing is recovered (via RxPLL) from the receive data stream
on the trunk line interface that was selected as clock source.
• The RxPLL also provides a 1.536-MHz clock synchronous to the Central Office clock
(adaptive timing recovery), which in LT-T applications is used to synchronize the
DELIC clock generator via the IOM-2000 REFCLK line; refer to Figure 17.
The RxPLL tracks every 250 µs after detecting the phase between the framing bit
transition (F/L-bit in S/T frame) of the receive signal and the recovered clock. A phase
adjustment is done by adding or subtracting 65 ns or 130 ns to or from the 15.36-MHz
clock depending on ’PLLS’.
• If several VIP or several S/T lines are operated in LT-T mode, only one trunk line may
be selected to deliver the reference clock. The selection of this trunk line is
programmed by the DELIC via IOM-2000 Command bits REFSEL(2:0) and EXREF.
Note: In LT-T mode, the transmit clock is identical to the recovered receive clock.
Note: The recommended setting for short passive bus in LT-T mode is
TICCMR:OWIN=’101’ and TICCMR:PD=’1’. For detailed description please
refer to VIP channel config command in the DELIC-LC/-PB SW User’s
Manual.
15.36 MHz
15.36 MHz
VIP
DELIC
OSC
DCL_2000
3.072/6.144/12.288
MHz
clock = 192 kHz
(up to 4 or 8 ch.)
CO
192 kHz
RxPLL
FIFO
MUX
REFCLK
1.536 MHz
192 kHz
CO
clock = 192 kHz
Data
DR
RxPLL
FIFO
VIP-LTT-Ref.vsd
Figure 17
Clock Recovery in LT-T Mode
Data Sheet
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PEB 20591
Interface Description
PRELIMINARY
Jitter Requirements
In LT-T mode, ITU-T I.430 specifies a maximum jitter in transmit direction of – 7 % to
+ 7 %, resulting in 730 ns peak-to-peak.
This specification will be met by the VIP provided that the master clock source is
accurate within 100 ppm.
3.3.4
Reference Clock Selection in LT-T Mode
In LT-T configurations, the DELIC receives the CO reference clock via the XCLK input
pin, which is connected to VIP’s REFCLK output.
The VIP reference clock channel is programmed by the DELIC. The source may be
either one of the 8 VIP channels operated in LT-T mode or VIP’s INCLK pin, when
several VIP’s are connected to the IOM-2000 interface (see Figure 18).
•
REFCLK
XCLK
Ch_0
CH_7
VIP_0
DELIC
DR
INCLK
VIP_n
REFSEL
REFCLK
VIP_1
Ch_0
Reference Clock
Trunk (LT-T)
Ch_0
EXREF
INCLK
Ch_7
REFCLK
VIP_2
Ch_0
Ch_7
Ch_7
INCLK
Figure 18
LT-T Reference Clock Channel Selection for Cascaded VIPs
Data Sheet
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2001-03-01
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PEB 20591
Interface Description
PRELIMINARY
3.3.5
Receive Signal Oversampling
The receive signal is oversampled within the receive clock period, and a majority logic is
used to reduce the bit error rate in severe conditions.
• As illustrated in Figure 19, each received bit is sampled 29 times at 7.68-MHz clock
intervals inside the estimated bit window.
• The samples obtained are compared against a threshold of 35% with respect to the
signal stored by the peak detector.
If at least a number of ’n’ samples have an amplitude exceeding the threshold, a
logical ’0’ is detected; otherwise a logical ’1’ (no signal) is assumed. The parameter ’n’
is programmed by the OWIN command bits.
Figure 19
3.3.6
Receive Signal Oversampling in S/T Receiver
Elastic Buffer
A buffer in the VIP is designed as a wander-tolerant system, required in LT-T and LT-S
modes. In LT-T mode, the VIP is clock slave to the CO, and the data clocks of the S/T
interface and the IOM-2000 interface have a time dependent phase relationship. The
buffer compensates a maximum phase wander of ± 20 µs.
A slip detector indicates when this limit is exceeded. The ’SLIP’ bit in VIP Status Register
issues a warning to the DELIC when a slip of 20 µs in either direction was detected. The
VIP buffers are reset to their default positions automatically.
Note: In case of frame slip, the phase relationship between the IOM-2000 interface and
the S/T interface is arbitrary. A re-alignment of the wander buffer after a slip may
result in loss of data.
Data Sheet
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Interface Description
PRELIMINARY
3.4
IOM-2000 Interface Overview
The IOM-2000 interface connects up to three VIPs to DELIC.
DELIC as the communication controller performs parts of the layer-1 protocol, which
enables flexible and efficient operation of the VIP.
Note: For detailed description of IOM-2000, including the command and data interface,
please refer to the DELIC Data Sheet.
IOM-2000
Description
Frame synchronization
Data interface
IOM-2000 uses an 8-kHz FSC.
Data is transmitted via DX line from DELIC to VIP with
DCL_2000 rising edge. Data is received via DR line from
VIP to DELIC, sampled with DCL_2000 falling edge.
Command/Status
interface
Configuration and control information of VIP’s layer-1
transceivers is exchanged via CMD and STAT lines.
Data/Command Clock
Data and commands for one VIP are transmitted at
3.072 MHz. When DELIC drives 2 or 3 VIPs, the
transmission rate is increased.
Reference clock
In LT-T mode, the VIP provides a reference clock
synchronized to the exchange. In LT-S or UPN mode,
DELIC is always the clock master to VIP.
•
bit 1 bit 0
data ctrl
Data Transmit / Receive in S/T mode
f=3.072 MHz (2 x 8 x 192 kbit/s)
S/T:
DX / DR:
bit 0
data
Data Transmit / Receive for UPN mode
f=3.072 MHz (8 x 384 kbit/s)
UPN:
FSC
DCL_2000
Channel_0
DX
DR
.
.
.
DELIC
VIP
STAT
CMD
Channel_7
Figure 20
Overview of IOM-2000 Interface Structure (Example with One VIP)
Data Sheet
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Interface Description
PRELIMINARY
3.4.1
IOM-2000 Frame Structure
3.4.1.1 Data Interface
On the ISDN line side of the VIP, data is ternary coded. Since the VIP contains logic to
detect the level of the signal, only the data value is transferred via IOM-2000 to DELIC.
UPN Mode
In UPN mode, only data is sent via the IOM-2000 data interface.
S/T Mode
In S/T mode, data and control information is sent via IOM-2000 data interface. Every
data bit has a control bit associated with it. Thus, for each S/T line signal, 2 bits are
transferred via DX and DR. Bit0 is assigned to the user data, and bit1 carries control
information.
Table 8
Control Bits in S/T Mode on DR Line
ctrl (bit1) data (bit0) Function
0
0
1
1
0
1
0
1
Logical ’0’ received on line interface
Logical ’1’ received on line interface
Received E-bit = inverted transmitted D-bit (E=D) (LT-T only)
F-bit (Framing) received; indicates the start of the S frame
Table 9
Control Bits in S/T Mode on DX Line
ctrl (bit1) data (bit0) Function
0
0
1
1
0
1
0
1
Logical ’0’ transmitted on line interface
Logical ’1’ transmitted on line interface
not used
F-bit (Framing) transmitted; indicates the start of the S frame
Note: ’data’ is always transmitted prior to ’ctrl’ via DX/DR lines (refer to Figure 21).
Data Sheet
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Interface Description
PRELIMINARY
125 µs
FSC
DCL
3.072 MHz
F-bit
data ctrl
data
LT-S mode:
UPN mode:
Ch0 bit0
Ch1 bit0 (data)
Ch2 bit0
Ch7 bit0 (data)
DX/DR
Ch0 bit1
Ch1 bit0 (ctrl)
Ch2 bit1
Ch7 bit0 (ctrl)
Ch0 bit2
Ch1 bit1 (data)
Ch2 bit2
Ch1,3,5,7 in S mode (LT-S)
Ch0,2,4,6 in UPN mode
Ch7 bit1 (data)
last bit of UPN frame
last bit of LT-S frame
Ch6 bit37
Ch7 bit 23 (ctrl)
Figure 21
IOM-2000 Data Sequence (1 VIP with 8 Channels)
Note: 1. Data transfer on IOM-2000 interface always starts with the MSB (related to B
channels), whereas CMD and STAT bits transfer always starts with LSB (bit 0)
of any register
2. All registers follow the Intel structure (LSB=20, MSB=231)
3. Unused bits are don’t care (’x’)
4. The order of reception or transmission of each VIP channel is always
channel 0 to channel 7. A freely programmable channel assignment of multiple
VIPs on IOM-2000 (e.g., ch0 of VIP_0, ch1 of VIP_0, ch0 of VIP_1, ch2 of
VIP_0,...) is not possible.
Data Sheet
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Interface Description
PRELIMINARY
125 µs
FSC
DCL
12.288 MHz
F-bit
Ch0 bit0
Ch23 bit0
Ch24 bit0
not used (don’t care)
DX/DR
Ch31 bit0
Ch0 bit1
Ch23 bit1
Ch24 bit1
not used (don’t care)
Ch31 bit1
Ch0 bit37
(example for 24 channels in UPN mode)
Ch23 bit37
Ch24 bit37
not used
Ch31 bit37
Figure 22
IOM-2000 Data Order (3 VIPs with 24 Channels)
Receive Data Channel Shift
In receive direction (DR), data of all IOM-2000 channels (ch0...7 if one VIP is used,
ch0 ... ch23 if three VIPs are used) is shifted by 2 channels with respect to the
transmitted data channels (DX), assuming a start of transmission of ch0 bit0 with the
FSC signal. DELIC is transmitting ch0, while receiving ch2 via DR the same time, etc.
DX
DR
ch0
ch2
ch1
ch3
ch2
ch4
ch3
ch5
ch4
ch6
ch5
ch7
ch6
ch0
ch7
ch1
ch0
ch2
Data Sheet
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Interface Description
PRELIMINARY
3.5
JTAG Boundary Scan Test Interface
The VIP provides IEEE 1149.1-compatible boundary scan support to allow cost-effective
board testing. It consists of:
• Complete boundary scan test
• Test access port (TAP) controller
• Five dedicated pins: TCK, TMS, TDI, TDO (according to JTAG) and an additional
TRST pin to enable asynchronous resets to the TAP controller
• One 32-bit IDCODE register
• Specific functions for the analog line interface pins LIna, b and SXna, b
3.5.1
TAP Controller
The TAP controller implements the state machine defined in the JTAG standard IEEE
1149.1. Transitions on the pin TMS cause the TAP controller to perform a state change.
The TAP controller supports 7 instructions:
• 5 standard instructions
• 2 additional user-specific instructions for transmitting continuous pulses at the line
interfaces LIna/b (60 kHz) and SXna/b (120 kHz)
Table 10
Code
0000
TAP Controller Instruction Codes Overview
Instruction
EXTEST
Function
External testing
0001
INTEST
Internal testing
0010
SAMPLE/PRELOAD
IDCODE
Snap-shot testing
0011
Reading ID code register
Bypass operation
1111
BYPASS
1000
User specific
User specific
Continuous pulses on LIna and LInb
Continuous pulses on SXna and SXnb
1001
TAP Controller Instructions
EXTEST. EXTEST is used to verify the board interconnections.
When the TAP controller is in the state “update DR”, all output pins are updated with the
falling edge of TCK. When it has entered state “capture DR” the levels of all input pins
are latched with the rising edge of TCK. The in/out shifting of the scan vectors is typically
done using the instruction SAMPLE/PRELOAD.
Data Sheet
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2001-03-01
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PEB 20591
Interface Description
PRELIMINARY
INTEST . INTEST supports internal chip testing.
When the TAP controller is in the state “update DR”, all inputs are updated internally with
the falling edge of TCK. When it has entered state “capture DR” the levels of all outputs
are latched with the rising edge of TCK. The in/out shifting of the scan vectors is typically
done using the instruction SAMPLE/PRELOAD.
Note: 0011 (IDCODE) is the default value of the instruction register.
SAMPLE/PRELOAD. SAMPLE/PRELOAD provides a snap-shot of the pin level during
normal operation or is used to either preload (TDI) or shift out (TDO) the boundary scan
test vector. Both activities are transparent to the system functionality.
Note: The input pin CLK15-I should not be evaluated.
The input frequency (15.36 MHz) is not synchronous with TCK (6.25 MHz); this
may cause unpredictable snap-shots on the pin CLK15-I.
IDCODE. The 32-bit identification register is read out serially via TDO. It contains the
version number (4 bits), the device code (16 bits) and the manufacturer code (11 bits).
The LSB is fixed to ’1’.
The code for VIP version 2.1 is ’0010’.
Version
0010
Device Code
Manufacturer Code
0000 1000 001
Output
0000 0000 0100 1111
1
--> TDO
Note: In the state “test logic reset”, the code “0011” is loaded into the instruction code
register.
BYPASS. A bit entering TDI is shifted to TDO after one TCK clock cycle, e.g. to skip
testing of selected ICs on a printed circuit board.
User-Specific Instructions. Symmetric continuous pulses can be generated at pins
LIna/b (60 kHz) and SXna/b (120 kHz) to test the analog line interfaces.
Note: A 15.36 MHz crystal or an external 15.36 MHz clock signal on CLK15-I is required
for test pulse generation.
Data Sheet
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2001-03-01
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Operational Description
PRELIMINARY
4
Operational Description
After some general remarks on the operation of the DELIC & VIP chipset, the reset and
the initialization procedure are described. The operation of analog test loops as well as
the monitoring of illegal code violations are also part of this chapter.
4.1
General
The DELIC & VIP chipset provides all functionality required for data transmission over
the UPN and the S/T interface, e.g., initialization and configuration, activation and
deactivation, frame and multiframe synchronization.
The UPN and S/T layer-1 state machines run on DELIC’s DSP, performing activation/
deactivation, switching of loops and transmission of test pulse patterns. Such actions
can be initiated by INFO signals on the UPN and S/T lines, or by C/I codes sent by the µP
to DELIC, and transferred to VIP via the IOM-2000 Command and Status interface. All
options and register settings are described in the DELIC Data Sheet.
4.2
Reset
• At power-up, a reset pulse (RESET = low active) of at least 1 µs must be applied to
reset the line interfaces of the VIP.
• The source of the reset can be either the microprocessor, or the DELIC RESIND pin,
which is a delayed reset signal. This assures that the VIP is always reset
simultaneously with the DELIC, and receives stable clock signals by the DELIC after
reset.
4.3
Initialization
After hardware reset, each VIP must be initialized and configured by IOM-2000
commands. The following steps are required to initialize the VIP:
1. DELIC: Hardware Reset (to synchronize the state machines, counters etc.)
2. VIP: Hardware Reset
3. Release resets
4. Read version register from VIP-CMD register (optional) (available from VIP version
V2.1 and higher)
5. Program the VIP if required, e.g. LT-T clock source
6. DELIC: Program VIP channel mode: UPN, LT-S or LT-T, closing test loops
7. DELIC: Configure each VIP receiver if required, e.g. oversampling, D-channel
handling.
Data Sheet
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2001-03-01
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Operational Description
PRELIMINARY
4.4
Analog Test Loops
Different analog test loops may be switched in the VIP near to the S/T or UPN line
interfaces. No external UPN or S/T interface circuitry is required to close these loops:
• Transparent analog loop, data forward path enabled
• Non-transparent analog loop, data forward path blocked
• External transparent analog loop, for board testing.
Initialization of Test Loops
Unlike the LT-T state machine, the LT-S and UPN state machines in the DELIC do not
support loops. Consequently neither the C/I commands nor indications are provided by
the mailbox protocol. A loop can be programmed by setting bits TICCMR:LOOP and
TICCMR:EXLP for the respective channel.
Note: For detailed description please refer also to the Application Note ’Test loops in the
VIP’.
Transparency
In UPN or LT-S mode, the user may output the loop-back data also transparently onto the
line interface. The selection is performed via IOM-2000 TX_EN command. External
analog loops are activated by EXLP Command bit (refer to Chapter 6.3).
Note: In order to guaranty that the loop is closed TX_EN must be set to one for the UPN
Interface
4.5
Monitoring of Code Violations
Any code violation on the S/T interface (according to ANSI T1.605), or code violations at
positions other than the F-bit or M-bit in the UPN frame result in VIP Status bit FECV being
sent to DELIC. The check is performed once in every multiframe (every 20th 4-kHz S/T
frame). To synchronize the checking, DELIC must issue the SH_FSC bit every 40th IOM
frame.
Data Sheet
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2001-03-01
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Electrical Characteristics
PRELIMINARY
5
Electrical Characteristics
This chapter contains the DC and AC specifications (as far as available) and timing
diagrams.
5.1
Absolute Maximum Ratings
Parameter
Symbol
Tstg
Limit Values
– 65 to 150
– 0.3 to 4.6
Unit
°C
V
Storage temperature
IC supply voltage
VDD
VI
DC input voltage (except I/Os)
– 0.3 to 6.0
V
DC output voltage (including I/Os);
output in high or low state
VO
– 0.3 to VDD + 0.3
V
DC output voltage (including I/Os);
output in tri-state
ESD robustness1)
VI, VO
– 0.3 to 6.0
V
V
VESD,HBM 2000
HBM: 1.5 kΩ, 100 pF
1)
According to MIL-Std 883D, method 3015.7 and ESD Ass. Standard EOS/ESD-5.1-1993. The SX pins are not
protected against voltage stress > 1500 V (versus VS or GND).
Note: Stresses above those listed here may cause permanent damage to the
device. Exposure to absolute maximum rating conditions for extended
periods may affect device reliability.
Maximum ratings are absolute ratings; exceeding only one of these values
may cause irreversible damage to the integrated circuit.
5.2
Operating Range
Parameter
Symbol
Limit Values
min. max.
3.47 V
Unit
Power supply voltage ±5%
Ground
VDD
VSS
VIN
TA
3.13
0
0
0
0 V
DD + 0.3 V
70 °C
Voltage applied to input pins
Operating temperature
V
Note: In the operating range the functions given in the circuit description are fulfilled.
Data Sheet
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PEB 20591
Electrical Characteristics
PRELIMINARY
5.3
DC Characteristics
VDD = 3.3 V ± 0.17 V, TA = 0 to 70°C
Table 11
DC Characteristics
Symbol
Parameter
Limit Values
min. max.
Unit Test Condition
All digital pins except LIna,b; SXna,b; SRna,b; CLK15-I,-O
L-input voltage
VIL
VIH
VOL
VOH
ILI
0.8
V
H-input voltage
2.0
2.4
VDD + 0.3
0.45
V
L-output voltage
H-output voltage
Input leakage current
V
Iout = 2mA
Iout = 2 mA
V
± 1
µA
0 V ≤ VIN ≤ VDD;
not specified for pins
DIR and REFCLK.
TDI; TMS; TRST
Input leakage current
high
ILIH
ILIL
1
µA
µA
VIN = VDD
Input leakage current
low
10
300
VIN = 0 V; internal
pull-up resistor
LIna,b
Transmitter output
amplitude
2.24
10
3.08
V
Upn-Transmitter
output amplitude
VX
ZR
Receiver input
impedance
kΩ
Receiver input
impedance,
transmitter inactive
SXna,b
Absolute value of
output pulse amplitude
VX
1.05
1.05
1.16
1.23
V
V
RL = 50 Ω
RL = 400 Ω
(VSXna – VSXnb
)
Data Sheet
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Electrical Characteristics
PRELIMINARY
Table 11
DC Characteristics (cont’d)
Parameter
Symbol
Limit Values
Unit Test Condition
min.
max.
Transmitter output
current
IX
21.0 1)
mA
26.8 2)
RL = 5.6 Ω
Transmitter output
impedance
ZX
acc. to
ITU-T
I.430
kΩ
Inactive or during
binary one,
0 V ≤ VIN ≤ VDD
0
Ω
during binary zero
1) Nominal value determined by fuses
2) Absolute current limit resulting from the S interface specification
CLK15-I
H-input voltage
L-input voltage
VIH
VIL
1.2
2.4
VDD + 0.3
V
V
0.4
CLK15-O
H-output voltage
L-output voltage
VOH
VOL
V
V
f = 0
f = 0
0.45
30
Supply Current
Operational supply
current, Peak value
ICC
mA Peak supply current,
VDD = 3.3 V
+ n × 27.5
+ m × 47.5
n = number of S/T
interfaces activated
m = number of UPN
interfaces activated
Operational supply
current, Mean (typical)
value
ICC
18
mA Mean supply current,
VDD = 3.3 V
+ n × 8.5
+ m × 6.5
n = number of S/T
interfaces activated
m = number of UPN
interfaces activated
Data Sheet
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PEB 20591
Electrical Characteristics
PRELIMINARY
5.4
Capacitances
TA = 25 °C; VDD = 3.3 V ± 0.17 V, VSS = 0 V, fC = 1 MHz, unmeasured pins grounded
Table 12
I/O Capacitances (except line interfaces and clocks)
Parameter
Symbol
Limit Values
Unit Test Condition
min.
max.
Pin capacitance
CI/O
7
pF
5.5
Recommended 15.36-MHz Crystal Parameters
The user has two options to supply the VIP 15.36-MHz input clock:
• via a standard 15.36-MHz crystal or
• via an external source, e.g. connecting the DELIC output pin L1_CLK (duty cycle of
40:60 or better is required). The on-chip oscillator must be powered-down via pin
POWDN.
Note: It is recommended to supply the VIP 15.36-MHz input clock via the DELIC.
In case a crystal (serial resonance) is connected, it should meet the requirements shown
in Table 13.
Table 13
Recommended Crystal Parameters
Symbol Typical Unit Test Condition
Values
20
Parameter
Motional Capacitance
C1
C0
CL
Rr
fF
Shunt Capacitance
7
pF
pF
Ω
External Load Capacitance
Resonance Resistance
Frequency Calibration Tolerance
≤ 30
≤ 65
≤ 100
ppm
CLD
External
Oscillator
Signal
CLK-15
Ι
CLK-15Ι
15.36 MHz
±100 ppm
CLD
N.C.
CLK-15O
CLK-15O
Crystal Oscillator Mode
CLD = 2 CL - CI/O
Driving from External Source
.
ITS11110
Figure 23
Recommended Oscillator Circuit
Data Sheet
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Electrical Characteristics
PRELIMINARY
5.6
AC Characteristics
TA = 0 to 70°C; VDD = 3.3 V ± 0.17 V
Note: Timing measurements are made at 2.0 V for a logical 1’ and at 0.8 V for a
logical ’0’.
50 pF
Figure 24
Input/Output Wave Form for AC Tests
5.7
REFCLK
•
Parameter
Symbol
Limit Values
Unit Comment
min.
max.
High phase of clock
Low phase of clock
Clock period
tWH
40
ns
ns
ns
Delay of falling
edge after falling
edge of INCLK
tWL
40
Delay of rising
edge after rising
edge of INCLK
TP
651
During PLL
adjustment this
value could
change
5.8
Upn Interface
Parameter
Symbol
Limit Values
Unit Comment
min.
max.
DIR delay from DCL_2000 tDIR
60
ns
rising edge
Data Sheet
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PEB 20591
Electrical Characteristics
PRELIMINARY
5.9
IOM-2000 Interface
•
FSC
tFS CS
DC L_2000
DX
tDX S
tDX H
ch2
ch3
ch0
ch1
tDR
DR
ch4
ch2
ch3
ch5
tCM DS
tCM D H
CM D
tS TAT
STAT
IOM_2000.vsd
Figure 25
IOM-2000 Timing
Table 14
IOM-2000 Interface Timing
Parameter
Symbol
Limit Values
min. typ. max.
38
Unit Notes
DR delay from
DCL_2000 rising edge
tDR
ns
ns
ns
ns
STAT delay from
DCL_2000 rising edge
tSTAT
tCMDS
tCMDH
38
CMD setup time to
DCL_2000 falling edge
10
10
CMD hold time to
DCL_2000 falling edge
Data Sheet
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Electrical Characteristics
PRELIMINARY
Table 14
IOM-2000 Interface Timing
Parameter
Symbol
Limit Values
Unit Notes
min. typ. max.
FSC setup time before
DCL_2000 rising edge
tFSCS
tFSCH
tDXS
-2
10
ns
FSC hold time after
DCL_2000 falling edge
70
10
10
ns
ns
ns
not shown in
Figure 25
DX setup time before
DCL_2000 falling edge
DX hold time after
tDXH
DCL_2000 falling edge
5.10
JTAG Boundary Scan Test Interface
Figure 26
JTAG Timing
Data Sheet
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Electrical Characteristics
PRELIMINARY
Table 15
JTAG Boundary Scan Timing Values
Parameter
Symbol
Limit Values
Unit
min.
100
50
max.
Test clock period
tTCP
tTCPL
tTCPH
tMSS
tMSH
tDIS
ns
ns
ns
ns
ns
ns
ns
ns
Test clock period low
Test clock period high
TMS setup time to TCK
TMS hold time from TCK
TDI setup time to TCK
TDI hold time from TCK
TDO valid delay from TCK
50
10
10
10
tDIH
10
tDOD
30
5.11
UPN Transmitter Performance
The VIP fulfills the electrical requirements of the UPN interface for loop lengths,
depending on the cable quality:
•
Adaptive Equalizer Switching is Enabled
AAC(1:0) = ’0x’ and FIL = 1 in DELIC IOM-2000 Command Register
Cable
Loop Length
up to 1 km
J-Y (ST) Y 2 × 2 × 0.6
AWG 26
up to 1.3 km
5.12
S/T Transmitter Performance
•
Cable 0.6 mm, 120 nF/km
Configuration
Condition
Distance TE-TE Distance TE-LT
Point-to-point
no noise
–
–
1000
950
200 / 2000 kHz
100 mVpp
Ext. passive bus
no noise
120m
120m
750m
550m
(Roundtrip < 2 µs) 200 / 2000 kHz
100 mVpp
Data Sheet
45
2001-03-01
PEB 20590
PEB 20591
Application Hints
PRELIMINARY
6
Application Hints
This chapter provides some additional information on how to use the VIP. The first
section describes some external circuitry: Recommended line transformers, resistors
and capacitors. Different wiring configurations in user premises are depicted for the LT-
S mode, and the different loops that can be closed in the VIP via the DELIC are also
presented in the following sections.
6.1
VIP External Circuitry
6.1.1
Recommended Line Transformers
The VIP is connected to the UPN or S/T lines via 1:1 transformers. The line side (primary
side) of the transformer could be center-tapped for the phantom power supply.
Reference model parameters of the transformers are shown below.
UPN Transformer
Primary to secondary transformer ratio:
Primary total DC resistance:
1:1
R ≤ 4..8 Ω
Primary inductance:
Primary inductance with secondary short circuited:
Coupling capacitance:
LM > 2.1 mH ±=20 %
LP < 22 µH
CK < 150 pF
S/T Transformer
Primary to secondary transformer ratio:
Primary total DC resistance:
Primary inductance:
Primary inductance with secondary short circuited:
Coupling capacitance:
1:1
R ≤ 2 Ω=
LM > 30 mH
LP < 6 µH
CK < 80 pF
CK
LP
R
Line Side
LM
1:1
Ideal Transformer
vip-trafo-model.vsd
Figure 27
1:1 Transformer Model
Data Sheet
46
2001-03-01
PEB 20590
PEB 20591
Application Hints
PRELIMINARY
6.1.2
UPN Interface External Circuitry
A transformer, external resistors and two capacitors (100 nF and 0.33 µF) are connected
externally to the line interface pins LIna,b. Voltage overload protection is achieved by
adding clamping diodes (see Figure 28).
1:1
10
Ω
50
Ω
VIP
100 nF
Vdd
UPN
UPN
0.33 F
µ
Transceiver
50
Ω
ext_u_tr.vsd
10
Ω
Figure 28
External Transceiver Circuitry of the VIP in UPN Mode
Note: The resistor values in Figure 28 are optimized for an ideal transformer (RCu = 0).
The 0.33-µF capacitance will be verified during system tests.
6.1.3
S/T Interface External Circuitry
The VIP needs some external circuitry to achieve impedance matching, overvoltage
protection and ElectroMagnetic Compatibility (EMC) for its connection to the 4-wire S/T
interface. The configuration is shown in Figure 29.
Imax= 26.8 mA (Spec.)
Imax= 21 mA (typ.)
1:1
1:1
Zw = 100
Ω
S/T
S/T
External
Circuitry
External
Circuitry
RT = 100 Ω
RT = 100
Ω
0,75 V
±10%
1,1 V
0,75 V
Transmitter
Receiver
ext_s
Figure 29
Overview of External Circuitry of the VIP in S/T Mode
Note: The actual values of the external resistors depend on the transformer selected.
The resistor values are optimal for an ideal transformer (RCu = 0).
Line termination (RT) is usually applied to the NT and last wall outlet on the S bus
only.
Data Sheet
47
2001-03-01
PEB 20590
PEB 20591
Application Hints
PRELIMINARY
Transmitter. Dedicated external resistors (10 … 12.5 Ω) are required for the transmitter
in order to
• Adjust the output voltage to the pulse mask (nominal 750 mV according to ITU-T
I.430),
• Meet the output impedance of a minimum of 20 Ω (transmission of a binary ’0’
according to ITU-T I.430).
10...12.5
VDD
Ω
1:1
SXna
S-Interface
Connector
S/T
Overvoltage
Protection
Transmitter
GND
SXnb
10...12.5
Ω
DC Point
Diodes: 1N4151
EXT_S_TR.vsd
(or similar)
Figure 30
External S/T Transmitter Circuitry
Receiver. At the receiver, 8 kΩ overall resistance is needed in each receive path. It is
recommended to use two resistors per line, as shown in Figure 31. This makes it
possible to place a high resistance between the transformer and the diode protection
circuit (required to pass 96-kHz input impedance test of ITU-T I.430). The remaining
resistor protects the VIP receiver from input current peaks.
1:1
1.2 kΩ
6.8 k
Ω
SRna
*)
*)
S/T
S-Interface
Connector
Overvoltage
Protection
VDD
GND
6.8 k
Receiver
1.2 k
Ω
Ω
SRnb
Diodes: 1N4151
(or similar)
DC Point
*) Up to 47 pF (for additional noise reduction if required)
EXT_S_RE.vsd
Figure 31
External S/T Receiver Circuitry
Data Sheet
48
2001-03-01
PEB 20590
PEB 20591
Application Hints
PRELIMINARY
6.2
Wiring Configurations in LT-S Mode
•
< 1000 m
Point-to-Point
Configurations
VIP
SCOUT-S
TE1
TR
TR
LT-S
< 100-200 m *
TR
TR
VIP
Short Passive Bus
< 10m
LT-S
SCOUT-S
SCOUT-S
...
TE1
TE8
500 m
< 25-50 m *
Extended Passive Bus
TR
TR
VIP
< 10m
LT-S
SCOUT-S
SCOUT-S
...
TE1
TE8
TR: Terminating Resistor
* see ITU I.430
VIP_0009_busconf_lts
Figure 32
Wiring Configurations in User Premises (LT-S Mode)
Data Sheet
49
2001-03-01
PEB 20590
PEB 20591
Application Hints
PRELIMINARY
6.3
Loop Modes
The following figure shows the different loops that can be closed in the VIP. Loops are
programmed by the DELIC using the command bits LOOP, EXLP and TX_EN.
•
VIP
External
Circuitry
Internal analog loop
Analog
Analog
DX
Line
TX
Transmitter
Driver
LOOP
IOM-2000
DR
TX_EN
EXLP
1
0
Analog
Receiver
RX
MUX
Figure 33
Internal and External Loop-Back Modes
Data Sheet
50
2001-03-01
PEB 20590
PEB 20591
Package Outlines
7
Package Outlines
•
P-MQFP-80-1
(Plastic Metric Quad Flat Package)
Sorts of Packing
Package outlines for tubes, trays etc. are contained in our
Data Book “Package Information”.
Dimensions in mm
2001-03-01
SMD = Surface Mounted Device
Data Sheet
51
PEB 20590
PEB 20591
Glossary
PRELIMINARY
8
Glossary
•
AMI
Alternate Mark Inversion
ANSI
CMOS
CO
American National Standardization Institute
Complementary Metal Oxide Semiconductor
Central Office
DC
Direct Current
DECT
DELIC
Digital European Cordless Telecommunication
DSP Embedded Line and Port Interface Controller
(PEB 20570, PEB 20571)
EMC
ETSI
HDLC
IEEE
INFO
I/O
ElectroMagnetic Compatibility
European Telephone Standards Institute
High-level Data Link Control
Institute of Electrical and Electronic Engineers
U- and S-interface signal as specified by ANSI/ETSI
Input/Output
IOM-2
IOM-2000
ISDN
ITU
ISDN-Oriented Modular 2nd generation
Proprietary ISDN inferface for connection of VIP to DELIC
Integrated services Digital Network
International Telecommunications Union
OCTAl Transceiver for UPN-Interfaces (PEB 2096)
Line Termination-Subscriber
OCTAT-P
LT-S
LT-T
Line Termination-Trunk
PLL
Phase-Locked Loop
PBX
Private Branch Exchange
QUAT-S
S/T
QUAdrupleTransceiver for S/T-Interface (PEB 2084)
Two-wire pair interface
TAP
Test Access Port
UPN
Two-wire interface
ZVEI
Zentralverband Elektrotechnik und Elektroindustrie e.V.
Data Sheet
52
2001-03-01
PEB 20590
PEB 20591
Index
PRELIMINARY
42
9
Index
L
A
Logic symbol
PEB 20590 6
PEB 20591 6
Loop modes 50
AC characteristics 42
Analog test loops 37
Application hints 46
Applications
7
O
B
Operating modes 25
Operating range 38
Operational description 36
Oscillator circuit 41
Block diagram 4
C
Capacitances 41
Clock synchronization 25
Crystal parameters 41
P
Package 51
Pin descriptions
9
D
Clock signals and dedicated pins
14
DC characteristics 39
IOM-2000 interface 13
JTAG boundary scan test inter-
face 15
Power supply and reset 15
UPN and S/T line interface 12
UPN and S/T line interface 11
E
Extended passive bus 26
External circuitry 46
F
Features (VIP)
5
Pin diagram
PEB 20590 9
PEB 20591 10
P-MQFP-80-1 51
I
Initialization 36
Interface
Product family (VIP)
4
IOM-2000 interface 30
JTAG boundary scan test inter-
face 34
Overview 16
S/T line interface 22
UPN line interface 16
R
Reference clock selection 28
Reset 36
S
IOM-2000 Frame Structure 31
S/T coding 24
S/T line interface 22
Data rates 24
Elastic buffer 29
External circuitry 47
Frame structure 23
IOM-2000 interface 30
J
Jitter requirements 28
JTAG boundary scan test interface 34
JTAG boundary scan test interface timing
Receive signal oversampling 29
Data Sheet
53
2001-03-01
PEB 20590
PEB 20591
Index
PRELIMINARY
S/T transceiver 25
Receive clock recovery 25
Receiver characteristics 25
S/T transformer 46
S/T transmitter performance 45
Short passive bus 26
System integration 7
T
TAP controller 34
U
UPN coding 18
UPN line interface 16
Control and maintenance bits
18
External circuitry 47
Frame structure 16
UPN scrambling/descrambling 19
UPN transceiver 20
Receive PLL 21
Receive signal oversampling 21
UPN transformer 46
UPN transmitter performance 45
W
Wiring configurations in LT-S mode 49
Data Sheet
54
2001-03-01
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