PEEL22CV10AI-15 [ETC]
CMOS Programmable Electrically Erasable Logic Device; CMOS可编程电可擦除逻辑器件
| 型号： | PEEL22CV10AI-15 |
| 厂家： | 
ETC |
| 描述： | CMOS Programmable Electrically Erasable Logic Device |
| 文件： | 总10页 (文件大小：242K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Commercial/
Industrial
-7/-10/-15/-25
PEEL™ 22CV10A
CMOS Programmable Electrically Erasable Logic Device
Features
■
High Speed/Low Power
■
Architectural Flexibility
- 132 product term X 44 input AND array
- Up to 22 inputs and 10 outputs
- Speeds ranging from 7ns to 25ns
- Power as low as 30mA at 25MHz
- Up to 12 configurations per macrocell
- Synchronous preset, asynchronous clear
- Independent output enables
■
Electrically Erasable Technology
- Superior factory testing
- Reprogrammable in plastic package
- Reduces retrofit and development costs
- 24-pin DIP/SOIC/TSSOP and 28-pin PLCC
■
Application Versatility
- Replaces random logic
- Pin and JEDEC compatible with 22V10
- Enhanced Architecture fits more logic
than ordinary PLDs
■
Development/Programmer Support
- Third party software and programmers
- ICT PLACE Development Software
General Description
The PEEL™22CV10A is a Programmable Electrically Eras-
able Logic (PEEL™) device providing an attractive alterna-
tive to ordinary PLDs. The PEEL™22CV10A offers the
performance, flexibility, ease of design and production
practicality needed by logic designers today. The
PEEL™22CV10A is available in 24-pin DIP, SOIC, TSSOP
and 28-pin PLCC packages (see Figure 1), with speeds
ranging from 7ns to 25ns and with power consumption as
low as 30mA. EE-reprogrammability provides the conve-
nience of instant reprogramming for development and a
reusable production inventory, minimizing the impact of
programming changes or errors. EE-reprogrammability
also improves factory testability, thus ensuring the highest
quality possible. The PEEL™22CV10A is JEDEC file com-
patible with standard 22V10 PLDs. Eight additional configu-
rations per macrocell (a total of 12) are also available by
using the “+” software/programming option (i.e.,
22CV10A+). The additional macrocell configurations allow
more logic to be put into every design. Programming and
development support for the PEEL™22CV10A are pro-
vided by popular third-party programmers and develop-
ment software. ICT also offers free PLACE development
software.
Figure 1. Pin Configuration
Figure 2. Block Diagram
I/CLK
1
24
VCC
I
I
2
3
23
22
I/O
I/O
I
I
4
5
21
20
I/O
I/O
I
I
6
7
19
18
I/O
I/O
I
I
I
8
17
16
15
I/O
I/O
I/O
9
10
I
11
12
14
13
I/O
I
GND
TSSOP
DIP
SOIC
PLCC
*Optional extra ground pin for
-7/I-7 speed grade.
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PEELTM 22CV10A
ASYNCHRONOUS CLEAR
(TO ALL MACROCELLS)
0
2
I/O
I/O
MACRO
CELL
9
I/CLK
10
MACRO
CELL
20
21
I
I/O
I/O
MACRO
CELL
33
34
I
I
MACRO
CELL
48
49
I/O
I/O
I/O
MACRO
CELL
65
66
I
MACRO
CELL
82
83
I
I
MACRO
CELL
97
98
I/O
I/O
MACRO
CELL
110
111
I
I
MACRO
CELL
121
124
I/O
MACRO
CELL
130
131
I
I
SYNCHRONOUS PRESET
(TO ALL MACROCELLS)
I
Figure 3. PEEL™22CV10A Logic Array Diagram
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PEELTM 22CV10A
programming selected connections in the AND array. (Note
that PEEL™ device programmers automatically program
the connections on unused product terms so that they will
have no effect on the output function.)
Function Description
The PEEL™22CV10A implements logic functions as sum-
of-products expressions in a programmable-AND/ fixed-OR
logic array. User-defined functions are created by program-
ming the connections of input signals into the array. User-
configurable output structures in the form of I/O macrocells
further increase logic flexibility.
Variable Product Term Distribution
The PEEL™22CV10A provides 120 product terms to drive
the 10 OR functions. These product terms are distributed
among the outputs in groups of 8, 10, 12, 14 and 16 to form
logical sums (see Figure 3). This distribution allows opti-
mum use of device re-sources.
Architecture Overview
The PEEL™22CV10A architecture is illustrated in the block
diagram of Figure 2. Twelve dedicated inputs and 10 I/Os
provide up to 22 inputs and 10 outputs for creation of logic
functions. At the core of the device is a programmable elec-
trically-erasable AND array which drives a fixed OR array.
With this structure, the PEEL™22CV10A can implement up
to 10 sum-of-products logic expressions.
Programmable I/O Macrocell
The output macrocell provides complete control over the
architecture of each output. The ability to configure each
output independently permits users to tailor the configura-
tion of the PEEL™22CV10A to the precise requirements of
their designs.
Associated with each of the 10 OR functions is an I/O mac-
rocell which can be independently programmed to one of 4
different configurations. The programmable macrocells
allow each I/O to create sequential or combinatorial logic
functions with either active-high or active-low polarity.
Macrocell Architecture
Each I/O macrocell, as shown in Figure 4, consists of a D-
type flip-flop and two signal-select multiplexers. The config-
uration of each macrocell is determined by the two
EEPROM bits controlling these multiplexers (refer to Table
1). These bits determine output polarity and output type
(registered or non-registered). Equivalent circuits for the
four macro-cell configurations are illustrated in Figure 5.
AND/OR Logic Array
The programmable AND array of the PEEL™22CV10A
(shown in Figure 3) is formed by input lines intersecting
product terms. The input lines and product terms are used
as follows:
Output Type
44 Input Lines:
The signal from the OR array can be fed directly to the out-
put pin (combinatorial function) or latched in the D-type flip-
flop (registered function). The D-type flip-flop latches data
on the rising edge of the clock and is controlled by the glo-
bal preset and clear terms. When the synchronous preset
term is satisfied, the Q output of the register will be set
HIGH at the next rising edge of the clock input. Satisfying
the asynchronous clear term will set Q LOW, regardless of
the clock state. If both terms are satisfied simultaneously,
the clear will override the preset.
24 input lines carry the true and complement
of the signals applied to the 12 input pins
20 additional lines carry the true and complement
values of feedback or input signals from
the 10 I/Os
132 product terms:
120 product terms (arranged in 2 groups of 8,
10, 12, 14 and 16) used to form logical sums
10 output enable terms (one for each I/O)
1 global synchronous present term
Output Polarity
Each macrocell can be configured to implement active-high
or active-low logic. Programmable polarity eliminates the
need for external inverters.
1 global asynchronous clear term
At each input-line/product-term intersection there is an
EEPROM memory cell which determines whether or not
there is a logical connection at that intersection. Each prod-
uct term is essentially a 44-input AND gate. A product term
which is connected to both the true and complement of an
input signal will always be FALSE, and thus will not affect
the OR function that it drives. When all the connections on
a product term are opened, a “don’t care” state exists and
that term will always be TRUE. When programming the
PEEL™22CV10A, the device programmer first performs a
bulk erase to remove the previous pattern. The erase cycle
opens every logical connection in the array. The device is
then configured to perform the user-defined function by
Output Enable
The output of each I/O macrocell can be enabled or dis-
abled under the control of its associated programmable
output enable product term. When the logical conditions
programmed on the output enable term are satisfied, the
output signal is propagated to the I/O pin. Otherwise, the
output buffer is driven into the high-impedance state.
Under the control of the output enable term, the I/O pin can
function as a dedicated input, a dedicated output, or a bi-
directional I/O. Opening every connection on the output
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PEELTM 22CV10A
enable term will permanently enable the output buffer and
yield a dedicated output. Conversely, if every connection is
intact, the enable term will always be logically false and the
I/O will function as a dedicated input.
Design Security
The PEEL™22CV10A provides a special EEPROM secu-
rity bit that prevents unauthorized reading or copying of
designs programmed into the device. The security bit is set
by the PLD programmer, either at the conclusion of the pro-
gramming cycle or as a separate step after the device has
been programmed. Once the security bit is set, it is impos-
sible to verify (read) or program the PEEL™ until the entire
device has first been erased with the bulk-erase function.
Input/Feedback Select
When configuring an I/O macrocell to implement a regis-
tered function (configurations 1 and 2 in Figure 5), the Q
output of the flip-flop drives the feedback term. When con-
figuring an I/O macrocell to implement a combinatorial
function (configurations 3 and 4 in Figure 5), the feedback
signal is taken from the I/O pin. In this case, the pin can be
used as a dedicated input or a bi-directional I/O. (Refer
also to Table 1.)
Signature Word
The signature word feature allows a 24-bit code to be pro-
grammed
into
the
PEEL™22CV10A
if
the
PEEL™22CV10A+ software option is used. The code can
be read back even after the security bit has been set. The
signature word can be used to identify the pattern pro-
grammed into the device or to record the design revision,
etc.
Additional Macro Cell Configurations
Besides the standard four-configuration macrocell shown in
Figure 5, each PEEL™22CV10A provides an additional
eight configurations that can be used to increase design
flexibility. The configurations are the same as provided by
the PEEL™18CV8 and PEEL™22CV10AZ. However, to
maintain JEDEC file compatibility with standard 22V10
PLDs the additional configurations can only be utilized by
specifying the PEEL™22CV10A+ for logic assembly and
programming. To reference these additional configurations
please refer to the PEEL™22CV10A+ specifications at the
end of this data sheet.
Figure 4. Block Diagram of the PEEL™ 22CV10A I/O Macrocell.
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PEELTM 22CV10A
Figure 5. Four Configurations of the PEEL™22CV10A I/O Macrocell
Table 1. PEEL™ 22CV10A Macrocell Configuration Bits
Configuration
Input/Feedback Select
Output Select
#
A
B
1
2
3
4
0
1
0
1
0
0
1
1
Active Low
Active High
Active Low
Active High
Register Feedback
Bi-Directional I/O
Register
Combinatorial
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PEELTM 22CV10A
Additional Macrocell Configurations
Besides the standard four-configuration macrocells, each
PEEL™22CV10A provides an additional eight configura-
tions (twelve total) that can be used to increase design flex-
ibility
(see Figure 6 and Table 2). For logic assembly of all twelve
configurations, specify PEEL™22CV10A+. Also, select the
PEEL™22CV10A+ for programming.
Figure 6. Twelve Configurations of the PEEL™22CV10A+ I/O Macrocell
Table 2. PEEL™ 22CV10A+ Macrocell Configuration Bits
Configuration
Input/Feedback Select
Output Select
#
A B C D
1
1
0
1
0
1
0
1
0
1
1
1
0
1
1
0
0
1
1
0
0
1
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
0
0
0
0
Active Low
Active High
Active Low
Active High
Active Low
Active High
Active Low
Active High
Active Low
Active High
Active Low
Active High
Register
Combinatorial
Register
2
Bi-Directional I/O
3
4
5
6
Combinatorial Feedback
7
Combinatorial
Register
8
9
10
11
12
Register Feedback
Combinatorial
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PEELTM 22CV10A
This device has been designed and tested for the recommended
operating conditions. Proper operation outside of these levels is not
guaranteed. Exposure to absolute maximum ratings may cause per-
manent damage.
Table 6. Absolute Maximum Ratings
Symbol
Parameter
Conditions
Ratings
Unit
VCC
Supply Voltage
Relative to Ground
-0.5 to + 7.0
V
2
1
VI, VO
-0.5 to VCC + 0.6
V
Voltage Applied to Any Pin
Output Current
Relative to Ground
Per pin (IOL, IOH)
IO
±25
-65 to + 150
+300
mA
°C
TST
TLT
Storage Temperature
Lead Temperature
Soldering 10 seconds
°C
Table 7. Operating Ranges
Symbol
Parameter
Conditions
Min
Max
Unit
Commercial
4.75
4.5
0
5.25
5.5
+70
+85
20
VCC
Supply Voltage
V
Industrial
Commercial
Industrial
TA
Ambient Temperature
°C
-40
TR
Clock Rise Time
Clock Fall Time
VCC Rise Time
See Note 3
See Note 3
See Note 3
ns
ns
TF
20
TRVCC
250
ms
Table 8. D.C. Electrical Characteristics over the recommended operating conditions
Symbol
Parameter
Conditions
Min
Max
Unit
VOH
Output HIGH Voltage
VCC = Min, IOH = -4.0mA
2.4
V
13
VOHC
VCC = Min, IOH = -10µA
VCC - 0.3
V
Output HIGH Voltage - CMOS
Output LOW Voltage - TTL
VOL
VCC = Min, IOL = 16mA
VCC = Min, IOH = -10µA
0.5
V
V
13
VOLC
0.15
Output LOW Voltage - CMOS
Input HIGH Level
VIH
VIL
IIL
2.0
VCC + 0.3
0.8
V
V
Input LOW Level
-0.3
Input Leakage Current
Output Leakage Current
VCC = Max, VIN = GND ≤ VIN £ VCC
I/O = High-Z, GND ≤ VO ≤ VCC
±10
µA
µA
IOZ
±10
-7/I-7
90/100
90/100
135/145
30/40
6
VIN = 0V or 3V
f = 25MHz
VCC Current
(See CR-1 for typical ICC)
-10/I-10
10
mA
ICC
4
All outputs disabled
-15/I-15
-25/I-25
7
Input Capacitance
Output Capacitance
pF
pF
CIN
TA = 25°C, VCC = 5.0V
@ f = 1 MHz
7
12
COUT
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PEELTM 22CV10A
Over the Operating Range8,11
Table 9. A.C. Electrical Characteristics
-7 / I-7
-10 / I-10
-15 / I-15
-25 / I-25
Unit
Symbol Parameter
Min Max Min Max Min Max Min Max
5
tPD
7.5
7.5
7.5
5.5
10
10
10
6
15
15
15
8
25
25
25
15
ns
ns
ns
ns
Input to non-registered output
5
6
tOE
tOD
tCO1
Input to output enable
6
Input5 to output disable
Clock to Output
Clock to comb. output delay via
internal registered feedback
tCO2
10
12
4
17
5
35
9
ns
tCF
tSC
Clock to Feedback
3.5
ns
ns
5
3
0
3
5
0
4
8
0
6
15
0
Input or Feedback Setup to Clock
5
tHC
ns
ns
Input Hold After Clock
8
tCL, tCH
13
Clock Low Time, Click High Time
tCP
Min Clock Period Ext (tSC + tCO1)
8.5
11
18
30
ns
12
fMAX1
142
111
76.9
41.6
MHz
Internal Feedback (1tSC + tCF)
12
fMAX2
fMAX3
117
166
7.5
90.9
125
10
62.5
83.3
15
33.3
38.4
25
MHz
MHz
External Feedback (1/tCP)
12
No Feedback (1/tCL + tCH)
tAW
tAP
Asynchronous Reset Pulse Width
ns
ns
5
7.5
7.5
10
10
15
15
25
25
Input to Asynchronous Reset
tAR
Asynch. Reset recovery time
ns
µs
Power-on Reset Time for
registers in Clear State
tRESET
5
5
5
5
Switching Waveforms
Inputs, I/O,
Registered Feedback,
Synchronous Preset
Clock
Asynchronous
Reset
Registered
Outputs
Combinatorial
Outputs
8. Test conditions assume: signal transition times of 3ns or less from the
10% and 90% points, timing reference levels of 1.5V (unless otherwise
specified).
9. Test one output at a time for a duration of less than 1sec.
10. ICC for a typical application: This parameter is tested with the device
programmed as an 8-bit Counter.
Notes
1. Minimum DC input is -0.5V, however inputs may undershoot to -2.0V for
periods less than 20ns.
2. VI and VO are not specified for program/verify operation.
3. Test points for Clock and VCC in tR, tF are referenced at 10% and 90%
levels.
11. PEEL™ Device test loads are specified in Section 6 of this Data Book.
12. Parameters are not 100% tested. Specifications are based on initial
characterization and are tested after any design or process modifica-
tion which may affect operational frequency.
4. I/O pins are 0V and 3V.
5. “Input” refers to an Input pin signal.
6. tOE is measured from input transition to VREF ± 0.1V, tOD is measured
from input transition to VOH -0.1V or VOL +0.1V; VREF =VL see test loads
in Section 5 of the Data Book.
13. Available only for 22CV10A -15/I-15/-25/I-25 grades.
7. Capacitances are tested on a sample basis.
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PEELTM 22CV10A
Table 6. Ordering Information
Part Number
Speed
Temperature
Package
PEEL22CV10AP-7
PEEL22CV10API-7
PEEL 22CV10AJ-7
PEEL 22CV10AJI-7
PEEL 22CV10AS-7
PEEL 22CV10ASI-7
PEEL 22CV10AT-7
PEEL 22CV10ATI-7
PEEL 22CV10AP-10
PEEL 22CV10API-10
PEEL 22CV10AJ-10
PEEL 22CV10AJI-10
PEEL 22CV10AS-10
PEEL 22CV10ASI-10
PEEL 22CV10AT-10
PEEL 22CV10ATI-10
PEEL 22CV10AP-15
PEEL 22CV10API-15
PEEL 22CV10AJ-15
PEEL 22CV10AJI-15
PEEL 22CV10AS-15
PEEL 22CV10ASI-15
PEEL 22CV10AT-15
PEEL 22CV10ATI-15
PEEL 22CV10AP-25
PEEL 22CV10API-25
PEEL 22CV10AT-25
PEEL 22CV10ATI-25
PEEL 22CV10AJ-25
PEEL 22CV10AJI-25
PEEL 22CV10AS-25
PEEL 22CV10ASI-25
C
7.5ns
P24
I
C
I
7.5ns
7.5ns
7.5ns
10ns
10ns
10ns
10ns
15ns
15ns
15ns
15ns
25ns
25ns
25ns
25ns
J28
S24
T24
P24
J28
S24
T24
P24
J28
S24
T24
P24
T24
J28
S24
C
I
C
I
C
I
C
I
C
I
C
I
C
I
C
I
C
I
C
I
C
I
C
I
C
I
C
I
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PEELTM 22CV10A
Device
Suffix
Part Number
PEEL™ 22CV10A PI-25
Package
Speed
P = Plastic 300mil DIP
-7 = 7.5ns tpd
-10 = 10ns tpd
-15 = 15ns tpd
J = Plastic (J) Leaded Chip Carrier (PLCC)
S = SOIC
T = TSSOP
-25 = 25ns tpd
Temperature Range and Power Options
(Blank) = Commercial 0 to 70°C
I = Industrial -40 to +85°C
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