PEF82912H [ETC]
?2B1Q Second Generation Modular ISDN NT (Intelligent)? ; ？ 2B1Q第二代模块化ISDN新台币（智能） ？\n
| 型号： | PEF82912H |
| 厂家： | 
ETC |
| 描述： | ?2B1Q Second Generation Modular ISDN NT (Intelligent)?
|
| 文件： | 总240页 (文件大小：3068K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Data Sheet, DS 1, March 2001
Q-SMINT®I
2B1Q Second Gen. Modular ISDN NT
(Intelligent)
PEF 82912/82913 Version 1.3
Wired
Communications
N e v e r s t o p t h i n k i n g .
Edition March 2001
Published by Infineon Technologies AG,
St.-Martin-Strasse 53,
D-81541 München, Germany
© Infineon Technologies AG 2001.
All Rights Reserved.
Attention please!
The information herein is given to describe certain components and shall not be considered as warranted
characteristics.
Terms of delivery and rights to technical change reserved.
We hereby disclaim any and all warranties, including but not limited to warranties of non-infringement, regarding
circuits, descriptions and charts stated herein.
Infineon Technologies is an approved CECC manufacturer.
Information
For further information on technology, delivery terms and conditions and prices please contact your nearest
Infineon Technologies Office in Germany or our Infineon Technologies Representatives worldwide (see address
list).
Warnings
Due to technical requirements components may contain dangerous substances. For information on the types in
question please contact your nearest Infineon Technologies Office.
Infineon Technologies Components may only be used in life-support devices or systems with the express written
approval of Infineon Technologies, if a failure of such components can reasonably be expected to cause the failure
of that life-support device or system, or to affect the safety or effectiveness of that device or system. Life support
devices or systems are intended to be implanted in the human body, or to support and/or maintain and sustain
and/or protect human life. If they fail, it is reasonable to assume that the health of the user or other persons may
be endangered.
Data Sheet, DS 1, March 2001
Q-SMINT®I
2B1Q Second Gen. Modular ISDN NT
(Intelligent)
PEF 82912/82913 Version 1.3
Wired
Communications
N e v e r s t o p t h i n k i n g .
PEF 82912/82913
Revision History:
March 2001
DS 1
Previous Version:
Preliminary Data Sheet 10.00
Page
All
Subjects (major changes since last revision)
Editorial changes, addition of notes for clarification etc.
Table 1,
Introduced new version 82913 with extended performance of the U-interface
Chapter 1.3
Chapter
2.1.1.1
SCI: header description: added to sequences 43H, 41H and 49H: ’Generally, it can
be used for any register access to the address range 20H-7DH.’
Chapter
2.3.2
IOM-2 handler: removed ’U-transceiver (U)’ from listing of functional units with
programmable time slot and data port.
Figure 12
Figure ’Data Access via CDAx0 and CDAx1 register pairs’ corrected: input swap has
influence on the input enable (EN_I0,1), too
Chapter
2.5.5.2
C/I commands: removed ’unconditional command’ from description C/I-command
’DR’
Chapter
2.5.5.3
LT-S state machine: C/I=command AIL removed (no valid input to the LT-S state
machine)
Chapter 4
Detailed register description:
• U-transceiver Mode Evaluation Timing: clarified description
• register ID: reset value of version 1.3 is 01H (not 00H)
• CIX1.CODX1: bits 5-0 of C/I-channel 1 (not 7-2)
• IOM_CR:TIC_DIS: added for clarification: ’This means that the timeslots TIC, A/
B, S/G and BAC are not available any more.’
Chapter 5.1 Refined references for ESD requirements:’ ...(CDM), EIA/JESD22-A114B (HBM) ---’
Chapter 5.2 Input/output leakage current set to 10µA (before: 1µA)
Table 38
U-transceiver characteristics: enhanced S/N+D for 82913 and threshold level for
82912 and 82913 distinguished
Chapter 5.1 Absolute Maximum Ratings: Maximum Voltage on VDD: 4.2V (before: 4.6V)
Chapter
5.6.2
AC-Timing SCI/parallel µC interface: enhanced timing specifications
Chapter
5.6.3
Chapter
5.6.3
Added restriction for control interval tRI
Chapter
5.6.5
Parameters of the UVD/POR Circuit:
defined reduced range of hysteresis: min. 30mV/max. 90mV
relaxed upper limit of Detection Threshold to 2.92V (before: 2.9V)
defined max. rising VDD for power-on
Chapter
7.2.5
Register summary U-transceiver 4B3T:
Reset value of MASKU is FFH (not 00H)
Chapter 7.3 External circuitry for T-SMINT updated
For questions on technology, delivery and prices please contact the Infineon
Technologies Offices in Germany or the Infineon Technologies Companies and
Representatives worldwide: see our webpage at http://www.infineon.com
PEF 82912/82913
Page
Table of Contents
1
Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
References . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2
Features PEF 82912 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
Features PEF 82913 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
Not Supported are ... . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Pin Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Pin Definitions and Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Specific Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
System Integration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
1.1
1.2
1.3
1.4
1.5
1.6
1.7
1.7.1
1.8
2
2.1
2.1.1
2.1.1.1
2.1.2
2.1.3
2.2
2.3
2.3.1
Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Microcontroller Interfaces . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Serial Control Interface (SCI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Programming Sequences . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Parallel Microcontroller Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Microcontroller Clock Generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
Reset Generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
IOM -2 Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
IOM‚-2 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
IOM‚-2 Handler . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
Controller Data Access (CDA) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
Serial Data Strobe Signal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
IOM‚-2 Monitor Channel . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
Handshake Procedure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
Error Treatment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
MONITOR Channel Programming as a Master Device . . . . . . . . . . . 48
MONITOR Channel Programming as a Slave Device . . . . . . . . . . . . 48
Monitor Time-Out Procedure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49
MONITOR Interrupt Logic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49
C/I Channel Handling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
D-Channel Access Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52
Application Examples for D-Channel Access Control . . . . . . . . . . . . 52
TIC Bus Handling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53
Stop/Go Bit Handling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54
D-Channel Arbitration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55
State Machine of the D-Channel Arbiter . . . . . . . . . . . . . . . . . . . . . . 56
Activation/Deactivation of IOM®-2 Interface . . . . . . . . . . . . . . . . . . . . . 59
U-Transceiver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60
2B1Q Frame Structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60
Maintenance Channel . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64
Reporting to the µC Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64
Access from the µC Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64
2.3.2
2.3.2.1
2.3.2.2
2.3.3
2.3.3.1
2.3.3.2
2.3.3.3
2.3.3.4
2.3.3.5
2.3.3.6
2.3.4
2.3.5
2.3.5.1
2.3.5.2
2.3.5.3
2.3.5.4
2.3.5.5
2.3.6
2.4
2.4.1
2.4.2
2.4.2.1
2.4.2.2
Data Sheet
2001-03-30
PEF 82912/82913
Page
Table of Contents
2.4.2.3
2.4.2.4
2.4.3
2.4.3.1
2.4.3.2
2.4.3.3
2.4.3.4
2.4.4
2.4.4.1
2.4.4.2
2.4.4.3
2.4.4.4
2.4.5
Availability of Maintenance Channel Information . . . . . . . . . . . . . . . . 64
M-Bit Register Access Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65
Processing of the EOC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67
EOC Commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67
EOC Processor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69
EOC Operating Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71
Examples for different EOC modes . . . . . . . . . . . . . . . . . . . . . . . . . . 72
Processing of the Overhead Bits M4, M5, M6 . . . . . . . . . . . . . . . . . . . . 75
M4 Bit Reporting to the µC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75
M4 Bit Reporting to State Machine . . . . . . . . . . . . . . . . . . . . . . . . . . 75
M5, M6 Bit Reporting to the µC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75
Summary of M4, M5, M6 Bit Reporting . . . . . . . . . . . . . . . . . . . . . . . 75
M4, M5, M6 Bit Control Mechanisms . . . . . . . . . . . . . . . . . . . . . . . . . . . 77
Cyclic Redundancy Check / FEBE bit . . . . . . . . . . . . . . . . . . . . . . . . . . 79
Block Error Counters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81
Near-End and Far-End Block Error Counter . . . . . . . . . . . . . . . . . . . 81
Testing Block Error Counters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81
Scrambling/ Descrambling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83
C/I Codes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83
State Machines for Line Activation / Deactivation . . . . . . . . . . . . . . . . . 85
Notation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85
Standard NT State Machine (IEC-Q / NTC-Q Compatible) . . . . . . . . 87
Inputs to the U-Transceiver: . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88
Outputs of the U-Transceiver: . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89
Description of the NT-States . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93
Simplified NT State Machine . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95
Metallic Loop Termination . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99
U-Transceiver Interrupt Structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101
S-Transceiver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103
Line Coding, Frame Structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103
S/Q Channels, Multiframing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105
Data Transfer between IOM‚-2 and S0 . . . . . . . . . . . . . . . . . . . . . . . . 106
Loopback 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 106
Control of S-Transceiver / State Machine . . . . . . . . . . . . . . . . . . . . . . 106
C/I Codes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109
State Machine NT Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 111
State Machine LT-S Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 115
S-Transceiver Enable / Disable . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 118
Interrupt Structure S-Transceiver . . . . . . . . . . . . . . . . . . . . . . . . . . . . 119
2.4.6
2.4.7
2.4.7.1
2.4.7.2
2.4.8
2.4.9
2.4.10
2.4.10.1
2.4.10.2
2.4.10.3
2.4.10.4
2.4.10.5
2.4.10.6
2.4.11
2.4.12
2.5
2.5.1
2.5.2
2.5.3
2.5.4
2.5.5
2.5.5.1
2.5.5.2
2.5.5.3
2.5.6
2.5.7
3
3.1
3.1.1
Operational Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 120
Layer 1 Activation/Deactivation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 120
Complete Activation Initiated by Exchange . . . . . . . . . . . . . . . . . . . . . 120
Data Sheet
2001-03-30
PEF 82912/82913
Page
Table of Contents
3.1.2
3.1.3
3.1.4
3.1.5
3.2
3.2.1
3.2.2
3.2.3
3.2.3.1
3.2.3.2
3.2.4
3.3
3.3.1
3.3.2
3.3.3
3.3.4
3.3.5
Complete Activation Initiated by TE . . . . . . . . . . . . . . . . . . . . . . . . . . . 121
Complete Activation Initiated by NT . . . . . . . . . . . . . . . . . . . . . . . . . . . 122
Complete Deactivation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 123
Loop 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 124
Layer 1 Loopbacks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 125
Analog Loopback U-Transceiver (No. 3) . . . . . . . . . . . . . . . . . . . . . . . 125
Analog Loop-Back S-Transceiver . . . . . . . . . . . . . . . . . . . . . . . . . . . . 126
Loopback No.2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 127
Complete Loopback . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 127
Loopback No.2 - Single Channel Loopbacks . . . . . . . . . . . . . . . . . . 128
Local Loopbacks Featured By the LOOP Register . . . . . . . . . . . . . . . 128
External Circuitry . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 130
Power Supply Blocking Recommendation . . . . . . . . . . . . . . . . . . . . . . 130
U-Transceiver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 130
S-Transceiver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 132
Oscillator Circuitry . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 134
General . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 135
4
Register Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 136
Address Space . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 136
Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 137
Register Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 139
Reset of U-Transceiver Functions During Deactivation or with
4.1
4.2
4.3
4.4
C/I-Code RESET 146
4.5
4.6
U-Transceiver Mode Register Evaluation Timing . . . . . . . . . . . . . . . . . . 147
Detailed C/I Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 148
MODEH - Mode Register IOM-2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 148
CIR0 - Command/Indication Receive 0 . . . . . . . . . . . . . . . . . . . . . . . . 148
CIX0 - Command/Indication Transmit 0 . . . . . . . . . . . . . . . . . . . . . . . . 150
CIR1 - Command/Indication Receive 1 . . . . . . . . . . . . . . . . . . . . . . . . 151
CIX1 - Command/Indication Transmit 1 . . . . . . . . . . . . . . . . . . . . . . . . 151
Detailed S-Transceiver Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 152
S_CONF0 - S-Transceiver Configuration Register 0 . . . . . . . . . . . . . . 152
S_CONF2 - S-Transmitter Configuration Register 2 . . . . . . . . . . . . . . 153
S_STA - S-Transceiver Status Register . . . . . . . . . . . . . . . . . . . . . . . 154
S_CMD - S-Transceiver Command Register . . . . . . . . . . . . . . . . . . . . 155
SQRR - S/Q-Channel Receive Register . . . . . . . . . . . . . . . . . . . . . . . 156
SQXR- S/Q-Channel Transmit Register . . . . . . . . . . . . . . . . . . . . . . . 156
ISTAS - Interrupt Status Register S-Transceiver . . . . . . . . . . . . . . . . . 157
MASKS - Mask S-Transceiver Interrupt . . . . . . . . . . . . . . . . . . . . . . . . 158
S_MODE - S-Transceiver Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 159
Interrupt and General Configuration Registers . . . . . . . . . . . . . . . . . . . . 160
ISTA - Interrupt Status Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 160
4.6.1
4.6.2
4.6.3
4.6.4
4.6.5
4.7
4.7.1
4.7.2
4.7.3
4.7.4
4.7.5
4.7.6
4.7.7
4.7.8
4.7.9
4.8
4.8.1
Data Sheet
2001-03-30
PEF 82912/82913
Page
Table of Contents
4.8.2
4.8.3
4.8.4
4.8.5
4.8.6
4.9
4.9.1
4.9.2
4.9.3
4.9.4
4.9.5
4.9.6
4.9.7
4.9.8
4.9.9
4.9.10
4.9.11
4.9.12
4.9.13
4.10
4.10.1
4.10.2
4.10.3
4.10.4
4.10.5
4.10.6
4.11
4.11.1
4.11.2
4.11.3
4.11.4
4.11.5
4.11.6
4.11.7
4.11.8
4.11.9
4.11.10
4.11.11
4.11.12
4.11.13
4.11.14
4.11.15
MASK - Mask Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 161
MODE1 - Mode1 Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 162
MODE2 - Mode2 Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 163
ID - Identification Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 164
SRES - Software Reset Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 165
Detailed IOM®-2 Handler Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 165
CDAxy - Controller Data Access Register xy . . . . . . . . . . . . . . . . . . . . 165
XXX_TSDPxy - Time Slot and Data Port Selection for CHxy . . . . . . . 166
CDAx_CR - Control Register Controller Data Access CH1x . . . . . . . . 167
S_CR - Control Register S-Transceiver Data . . . . . . . . . . . . . . . . . . . 168
CI_CR - Control Register for CI1 Data . . . . . . . . . . . . . . . . . . . . . . . . 169
MON_CR - Control Register Monitor Data . . . . . . . . . . . . . . . . . . . . . 170
SDS1_CR - Control Register Serial Data Strobe 1 . . . . . . . . . . . . . . . 171
SDS2_CR - Control Register Serial Data Strobe 2 . . . . . . . . . . . . . . . 172
IOM_CR - Control Register IOM Data . . . . . . . . . . . . . . . . . . . . . . . . . 173
MCDA - Monitoring CDA Bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 174
STI - Synchronous Transfer Interrupt . . . . . . . . . . . . . . . . . . . . . . . . . 174
ASTI - Acknowledge Synchronous Transfer Interrupt . . . . . . . . . . . . . 175
MSTI - Mask Synchronous Transfer Interrupt . . . . . . . . . . . . . . . . . . . 175
Detailed MONITOR Handler Registers . . . . . . . . . . . . . . . . . . . . . . . . . . 176
MOR - MONITOR Receive Channel . . . . . . . . . . . . . . . . . . . . . . . . . . 176
MOX - MONITOR Transmit Channel . . . . . . . . . . . . . . . . . . . . . . . . . . 176
MOSR - MONITOR Interrupt Status Register . . . . . . . . . . . . . . . . . . . 177
MOCR - MONITOR Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . 177
MSTA - MONITOR Status Register . . . . . . . . . . . . . . . . . . . . . . . . . . . 178
MCONF - MONITOR Configuration Register . . . . . . . . . . . . . . . . . . . . 179
Detailed U-Transceiver Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 179
OPMODE - Operation Mode Register . . . . . . . . . . . . . . . . . . . . . . . . . 179
MFILT - M Bit Filter Options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 180
EOCR - EOC Read Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 181
EOCW - EOC Write Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 182
M4RMASK - M4 Read Mask Register . . . . . . . . . . . . . . . . . . . . . . . . . 183
M4WMASK - M4 Write Mask Register . . . . . . . . . . . . . . . . . . . . . . . . . 183
M4R - M4 Read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 184
M4W - M4 Write Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 185
M56R - M56 Read Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 186
M56W - M56 Write Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 187
UCIR - C/I Code Read Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 187
UCIW - C/I Code Write Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 188
TEST - Test Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 188
LOOP - Loop Back Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 189
FEBE - Far End Block Error Counter Register . . . . . . . . . . . . . . . . . . 190
Data Sheet
2001-03-30
PEF 82912/82913
Page
Table of Contents
4.11.16
4.11.17
4.11.18
4.11.19
NEBE - Near End Block Error Counter Register . . . . . . . . . . . . . . . . . 191
ISTAU - Interrupt Status Register U-Interface . . . . . . . . . . . . . . . . . . . 191
MASKU - Mask Register U-Interface . . . . . . . . . . . . . . . . . . . . . . . . . . 192
FW_VERSION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 193
5
5.1
5.2
5.3
5.4
5.5
5.6
5.6.1
5.6.2
5.6.3
5.6.4
5.6.5
Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 194
Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 194
DC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 195
Capacitances . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 197
Power Consumption . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 197
Supply Voltages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 197
AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 199
IOM®-2 Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 200
Serial µP Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 202
Parallel µP Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 203
Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 206
Undervoltage Detection Characteristics . . . . . . . . . . . . . . . . . . . . . . . 207
6
Package Outlines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 209
7
7.1
7.2
7.2.1
7.2.2
7.2.3
7.2.4
7.2.5
7.3
Appendix: Differences between Q- and T-SMINT‚I . . . . . . . . . . . . . . . 211
Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 211
U-Transceiver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 212
U-Interface Conformity . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 212
U-Transceiver State Machines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 213
Command/Indication Codes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 216
Interrupt Structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 217
Register Summary U-Transceiver . . . . . . . . . . . . . . . . . . . . . . . . . . . . 219
External Circuitry . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 222
8
Index . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 224
Data Sheet
2001-03-30
PEF 82912/82913
Page
List of Figures
Figure 1
Figure 2
Figure 3
Figure 4
Figure 5
Figure 6
Figure 7
Figure 8
Figure 9
Figure 10
Figure 11
Figure 12
Figure 13
Figure 14
Figure 15
Figure 16
Figure 17
Figure 18
Pin Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Application Example Q-SMINT®I: High Feature Intelligent NT . . . . . . 14
Control via µP Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Control via IOM‚-2 Interface. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Serial Control Interface Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Serial Command Structure. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Direct/Indirect Register Address Mode . . . . . . . . . . . . . . . . . . . . . . . . 24
Reset Generation of the Q-SMINT®I . . . . . . . . . . . . . . . . . . . . . . . . . . 25
IOM -2 Frame Structure of the Q-SMINT‚I . . . . . . . . . . . . . . . . . . . . . 28
Architecture of the IOM -2 Handler . . . . . . . . . . . . . . . . . . . . . . . . . . 30
Data Access via CDAx0 and CDAx1 register pairs . . . . . . . . . . . . . . . 32
Examples for Data Access via CDAxy Registers. . . . . . . . . . . . . . . . . 33
Data Access when Looping TSa from DU to DD . . . . . . . . . . . . . . . . . 34
Data Access when Shifting TSa to TSb on DU (DD) . . . . . . . . . . . . . . 35
Example for Monitoring Data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
Interrupt Structure of the Synchronous Data Transfer. . . . . . . . . . . . . 39
Examples for the Synchronous Transfer Interrupt Control with
one STIxy enabled. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
Data Strobe Signal Generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
MONITOR Channel Protocol (IOM®-2) . . . . . . . . . . . . . . . . . . . . . . . . 44
Monitor Channel, Transmission Abort requested by the Receiver. . . . 47
Monitor Channel, Transmission Abort requested by the Transmitter. . 47
Monitor Channel, Normal End of Transmission . . . . . . . . . . . . . . . . . . 47
MONITOR Interrupt Structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
CIC Interrupt Structure. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51
D-Channel Arbitration: µC with HDLC and Direct Access to TIC Bus . 52
D-Channel Arbitration: µC with HDLC and no Access to TIC Bus. . . . 53
Structure of Last Octet of Ch2 on DU . . . . . . . . . . . . . . . . . . . . . . . . . 54
Structure of Last Octet of Ch2 on DD . . . . . . . . . . . . . . . . . . . . . . . . . 55
State Machine of the D-Channel Arbiter (Simplified View). . . . . . . . . . 57
Deactivation of the IOM®-2 Clocks . . . . . . . . . . . . . . . . . . . . . . . . . . . 59
U-Superframe Structure. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60
U-Basic Frame Structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61
U2B1Q Framer - Data Flow Scheme. . . . . . . . . . . . . . . . . . . . . . . . . . 63
U2B1Q Deframer - Data Flow Scheme . . . . . . . . . . . . . . . . . . . . . . . . 63
Write Access Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66
Read Access Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67
EOC Message Reception . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70
EOC Command/Message Transmission . . . . . . . . . . . . . . . . . . . . . . . 70
Maintenance Channel Filtering Options. . . . . . . . . . . . . . . . . . . . . . . . 76
M4 Bit Report Timing (Statemachine vs. µC). . . . . . . . . . . . . . . . . . . . 76
Figure 19
Figure 20
Figure 21
Figure 22
Figure 23
Figure 24
Figure 25
Figure 26
Figure 27
Figure 28
Figure 29
Figure 30
Figure 31
Figure 32
Figure 33
Figure 34
Figure 35
Figure 36
Figure 37
Figure 38
Figure 39
Figure 40
Figure 41
Data Sheet
2001-03-30
PEF 82912/82913
Page
List of Figures
Figure 42
Figure 43
Figure 44
Figure 45
Figure 46
Figure 47
M4, M5, M6 Bit Control in Receive Direction . . . . . . . . . . . . . . . . . . . . 78
M4, M5, M6 Bit Control in Transmit Direction . . . . . . . . . . . . . . . . . . . 78
CRC-Process. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80
Block Error Counter Test . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83
Explanation of State Diagram Notation . . . . . . . . . . . . . . . . . . . . . . . . 86
Standard NT State Machine (IEC-Q / NTC-Q Compatible)
(Footnotes: see “Dependence of Outputs” on Page 92) . . . . . . . . . 87
Simplified NT State Machine . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98
Pulse Streams Selecting Quiet Mode . . . . . . . . . . . . . . . . . . . . . . . . 100
Interrupt Structure U-Transceiver . . . . . . . . . . . . . . . . . . . . . . . . . . . 102
S/T -Interface Line Code . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103
Frame Structure at Reference Points S and T (ITU I.430). . . . . . . . . 104
S-Transceiver Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107
State Diagram Notation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108
State Machine NT Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 111
State Machine LT-S Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 115
Interrupt Structure S-Transceiver. . . . . . . . . . . . . . . . . . . . . . . . . . . . 119
Complete Activation Initiated by Exchange . . . . . . . . . . . . . . . . . . . . 120
Complete Activation Initiated by TE. . . . . . . . . . . . . . . . . . . . . . . . . . 121
Complete Activation Initiated by Q-SMINT®I . . . . . . . . . . . . . . . . . . . 122
Complete Deactivation Initiated by Exchange . . . . . . . . . . . . . . . . . . 123
Loop 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 124
Test Loopbacks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 125
External Loop at the S/T-Interface. . . . . . . . . . . . . . . . . . . . . . . . . . . 126
Complete Loopback Options in NT-Mode . . . . . . . . . . . . . . . . . . . . . 127
Loopbacks Featured by Register LOOP . . . . . . . . . . . . . . . . . . . . . . 129
Power Supply Blocking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 130
External Circuitry U-Transceiver . . . . . . . . . . . . . . . . . . . . . . . . . . . . 131
External Circuitry S-Interface Transmitter . . . . . . . . . . . . . . . . . . . . . 133
External Circuitry S-Interface Receiver . . . . . . . . . . . . . . . . . . . . . . . 134
Crystal Oscillator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 134
Address Space. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 136
Q-SMINT®I Interrupt Status Registers. . . . . . . . . . . . . . . . . . . . . . . . 137
Maximum Sinusoidal Ripple on Supply Voltage . . . . . . . . . . . . . . . 198
Input/Output Waveform for AC Tests. . . . . . . . . . . . . . . . . . . . . . . . . 199
IOM®-2 Interface - Bit Synchronization Timing . . . . . . . . . . . . . . . . . 200
IOM®-2 Interface - Frame Synchronization Timing . . . . . . . . . . . . . . 200
Serial Control Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 202
Microprocessor Read Cycle. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 203
Microprocessor Write Cycle. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 203
Multiplexed Address Timing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 203
Non-Multiplexed Address Timing. . . . . . . . . . . . . . . . . . . . . . . . . . . . 204
Figure 48
Figure 49
Figure 50
Figure 51
Figure 52
Figure 53
Figure 54
Figure 55
Figure 56
Figure 57
Figure 58
Figure 59
Figure 60
Figure 61
Figure 62
Figure 63
Figure 64
Figure 65
Figure 66
Figure 67
Figure 68
Figure 69
Figure 70
Figure 71
Figure 72
Figure 73
Figure 74
Figure 75
Figure 76
Figure 77
Figure 78
Figure 79
Figure 80
Figure 81
Figure 82
Data Sheet
2001-03-30
PEF 82912/82913
Page
List of Figures
Figure 83
Figure 84
Figure 85
Figure 86
Figure 87
Figure 88
Figure 89
Figure 90
Figure 91
Figure 92
Figure 93
Microprocessor Read Timing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 204
Microprocessor Write Cycle. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 204
Non-Multiplexed Address Timing. . . . . . . . . . . . . . . . . . . . . . . . . . . . 205
Reset Input Signal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 206
Undervoltage Control Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 207
INTC-Q Compatible State Machine Q-SMINT®I: 2B1Q. . . . . . . . . . . 213
Simplified State Machine Q-SMINT®I: 2B1Q. . . . . . . . . . . . . . . . . . . 214
IEC-T/NTC-T Compatible State Machine T-SMINT‚I: 4B3T. . . . . . . . 215
Interrupt Structure U-Transceiver Q-SMINT®I: 2B1Q . . . . . . . . . . . . 217
Interrupt Structure U-Transceiver T-SMINT‚I: 4B3T. . . . . . . . . . . . . . 218
External Circuitry Q- and T-SMINT‚I . . . . . . . . . . . . . . . . . . . . . . . . . 222
Data Sheet
2001-03-30
PEF 82912/82913
Page
List of Tables
Table 1
Table 2
Table 3
Table 4
Table 5
Table 6
Table 7
Table 8
NT Products of the 2nd Generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Pin Definitions and Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
ACT States. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Interface Selection for the Q-SMINT‚I . . . . . . . . . . . . . . . . . . . . . . . . . 17
Header Byte Code . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Bus Operation Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
MCLK Frequencies . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
Reset Source Selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
Examples for Synchronous Transfer Interrupts . . . . . . . . . . . . . . . . . . 38
Transmit Direction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
Receive Direction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
Q-SMINT®I Configuration Settings in Intelligent NT Applications . . . . 56
Major Differences D-Channel Arbiter INTC-Q and Q-SMINT®I . . . . . . 57
U-Superframe Format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61
Enabling the Maintenance Channel (Receive Direction) . . . . . . . . . . . 64
Coding of EOC-Commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68
Usage of Supported EOC-Commands. . . . . . . . . . . . . . . . . . . . . . . . . 68
EOC Auto Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73
Transparent mode 6 ms. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74
Transparent mode ’@change’ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74
Transparent mode TLL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74
U - Transceiver C/I Codes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84
Timers Used. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89
U-Interface Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90
Signal Output on Uk0. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92
C/I-Code Output. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92
Changes to achieve Simplified NT State Machine. . . . . . . . . . . . . . . . 96
Appearance of the State Machine to the Software . . . . . . . . . . . . . . . 99
ANSI Maintenance Controller States . . . . . . . . . . . . . . . . . . . . . . . . . 100
S/Q-Bit Position Identification and Multi-Frame Structure . . . . . . . . . 105
U-Transformer Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 131
S-Transformer Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 132
Crystal Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 135
Reset of U-Transceiver Functions During Deactivation or with
Table 9
Table 10
Table 11
Table 12
Table 13
Table 14
Table 15
Table 16
Table 17
Table 18
Table 19
Table 20
Table 21
Table 22
Table 23
Table 24
Table 25
Table 26
Table 27
Table 28
Table 29
Table 30
Table 31
Table 32
Table 33
Table 34
C/I-Code RESET . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 146
Maximum Input Currents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 194
S-Transceiver Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 195
U-Transceiver Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 196
Pin Capacitances. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 197
Reset Input Signal Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . 206
Parameters of the UVD/POR Circuit . . . . . . . . . . . . . . . . . . . . . . . . . 207
Pin Definitions and Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 211
Table 36
Table 37
Table 38
Table 39
Table 40
Table 41
Table 42
Data Sheet
2001-03-30
PEF 82912/82913
Page
List of Tables
Table 43
Table 44
Table 45
Related Documents to the U-Interface. . . . . . . . . . . . . . . . . . . . . . . . 212
C/I Codes. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 216
Dimensions of External Components. . . . . . . . . . . . . . . . . . . . . . . . . 223
Data Shee
2001-03-30
PEF 82912/82913
Overview
1
Overview
The PEF 82912 / 82913 (Q-SMINT®I) offers U-transceiver, S-transceiver and an IOM-
2 interface. A microcontroller interface provides access to both transceivers as well as
the IOM-2 interface.
However, as opposed to its bigger brother Q-SMINT®IX, the Q-SMINT®I does not have
an HDLC controller. Main target applications of the Q-SMINT®I are intelligent NT
applications where the HDLC controller(s) is (are) provided by the microcontroller or
other additional components. An example for such a microcontroller is the Infineon
UTAH chip which features four flexible HDLC controllers.
Table 1 summarizes the 2nd generation NT products.
•
Table 1
NT Products of the 2nd Generation
PEF80912 PEF80913 PEF81912 PEF81913 PEF82912 PEF82913
Q-SMINT®O
Q-SMINT®IX
Q-SMINT®I
Package
P-MQFP-44
P-MQFP-64
P-TQFP-64
P-MQFP-64
P-TQFP-64
Register
access
no
n.a.
no
U+S+HDLC+ IOM-2
U+S+ IOM-2
Access via
parallel (or SCI or
IOM-2)
parallel (or SCI or
IOM-2)
MCLK,
yes
yes
watchdog
timer, SDS,
BCL, D-
channel
arbitration,
IOM-2access
and
manipulation
etc. provided
HDLC
controller
no
yes
no
no
no
NT1 mode
available
yes (only)
Extended U-
Performance
20kft
no
yes
no
yes
no
yes
Data Sheet
1
2001-03-30
PEF 82912/82913
Overview
1.1
References
[1]
TS 102 080, Transmission and Multiplexing ; ISDN basic rate access; Digital
transmission system on metallic local lines, ETSI, November 1998
[2]
T1.601-1998 (Revision of ANSI T1.601-1992), ISDN-Basic Access Interface
for Use on Metallic Loops for Application on the Network Side of the NT
(Layer 1 Specification), ANSI, 1998
[3]
[4]
ST/LAA/ELR/DNP/822, CNET, France
RC7355E, 2B1Q Generic Physical Layer Specification, British
Telecommunications plc., 1997
[5]
FZA TS 0095/01:1997-10, Technische Spezifikationen für
Netzabschlußgeräte für den ISDN Basisanschluß (NT-BA), Post & Telekom
Austria, 1997
[6]
pr ETS 300 012 Draft, ISDN; Basic User Network Interface (UNI), ETSI,
November 1996
[7]
T1.605-1991, ISDN-Basic Access Interface for S and T Reference Points
(Layer 1 Specification), ANSI, 1991
[8]
I.430, ISDN User-Network Interfaces: Layer 1 Recommendations, ITU,
November 1988
[9]
IEC-Q, ISDN Echocancellation Circuit, PEB 2091 V4.3, User’s Manual
02.95, Siemens AG, 1995
[10]
[11]
[12]
SBCX, S/T Bus Interface Circuit Extended, PEB 2081 V3.4, User’s Manual
11.96, Siemens AG, 1996
NTC-Q, Network Termination Controller (2B1Q), PEB / PEF 8091 V1.1, Data
Sheet 10.97, Siemens AG, 1997
INTC-Q, Intelligent Network Termination Controller (2B1Q), PEB / PEF 8191
V1.1, Data Sheet 10.97, Siemens AG, 1997
[13]
[14]
IOM-2 Interface Reference Guide, Siemens AG, 03.91
SCOUT-S(X), Siemens Codec with S/T-Transceiver, PSB 2138x V1.3,
Preliminary Data Sheet 8.99, Infineon Technologies, 1999
[15]
[16]
PITA, PCI Interface for Telephony/Data Applications V0.3, SICAN GmbH,
September 1997
Dual Channel SLICOFI-2, HV-SLIC; DUSLIC; PEB3265, 4265, 4266; Data
Sheet DS2, Infineon Technologies, July 2000.
Data Sheet
2
2001-03-30
PEF 82912/82913
Overview
•
2B1Q Second Gen. Modular ISDN NT (Intelligent)
PEF 82912/82913
Q-SMINT®I
Version 1.3
1.2
Features PEF 82912
Features known from the PEB/PEF 8191
• U-transceiver and S-transceiver on one chip
• Perfectly suited for high-end intelligent NTs that
require multiple HDLC controllers (which are provided
externally)
P-MQFP-64-1,-2
• U-interface (2B1Q) conform to ETSI [1], ANSI [2] and
CNET [3]:
P-MQFP-64
– Meets all transmission requirements on all ETSI,
ANSI and CNET loops with margin
– Conform to British Telecom’s RC7355E [4]
– Compliant with ETSI 10 ms micro interruptions
– MLT input and decode logic (ANSI [2])
• S/T-interface conform to ETSI [6], ANSI [7] and ITU
[8]
– Supports point-to-point and bus configurations
– Meets and exceeds all transmission requirements
• Activation status LED supported
P-TQFP-64
• BCL, SDS1, SDS2, programmable MCLK, watchdog timer,
• Access to IOM-2 C/I and Monitor channels
• Power-down and reset states (e.g. S-transceiver) for individual circuits
• Automatic D-channel arbitration between S-bus and external HDLC controller
• Parallel or serial µP-interface
Type
Package
PEF 82912/82913
PEF 82912/82913
P-MQFP-64
P-TQFP-64
Data Sheet
3
2001-03-30
PEF 82912/82913
Overview
•
New Features
• Reduced number of external components for external U-hybrid required
• Optional use of up to 2x20 Ω resistors on the line side of the transformer (e.g. PTCs)
• Pin Uref and the according external capacitor removed
• Improved ESD (2 kV instead of <850 V)
• Inputs accept 3.3 V and 5 V
• I/O (open drain) accepts pull-up to 3.3 V1)
• LED signal is programmable but can also automatically indicate the activation status
(mode select via 1 bit)
• Pin compatible with T-SMINT®I (2nd Generation)
• Priority setting (8/10) for off-chip HDLC controller
• Enhanced IOM-2 timeslot access and manipulation (SCOUT)
• MCLK can be disabled (SCOUT)
• External Awake (EAW)
• Optional: All registers can be read and written to via new Monitor channel concept
• Optional: Implementation of S-transceiver statemachine in software
• Indirect Addressing (SCOUT)
• Programmable strobes SDS1/2 are more flexible, e.g. active during several timeslots
• Power-on reset and Undervoltage Detection with no external components
• Lowest power consumption due to:
– Low power CMOS technology (0.35µ)
– Newly optimized low-power libraries
– High output swing on U- and S-line interface leads to minimized power
consumption
– Single 3.3 Volt power supply
• 200 mW (INTC-Q: 295 mW) power consumption with random data over ETSI Loop
2 (external loads on the S and U interface only and no additional external loads).
• 15 mW typical power consumption in power down (INTC-Q: 28 mW)
1.3
Features PEF 82913
The Q-SMINT®I PEF 82913 provides all features of the PEF 82912. Additionally, a
significantly enhanced performance of the U-interface as compared to ETSI [1], ANSI
[2] and CNET [3] requirements is guaranteed:
Transparent transmission on 20kft AWG26 with a BER < 10-7 (without noise).
1)
Pull-ups to 5 V must be avoided. A so-called ’hot-electron-effect’ would lead to long term degradation.
Data Sheet
4
2001-03-30
PEF 82912/82913
Overview
1.4
Not Supported are ...
• Integrated U-hybrid
• On-chip HDLC controller
• ’Self test request’ and ’Self test passed’ of U-transceiver
• TE-mode of the S-transceiver
• DECT-link capability
• SRA (capacitive receiver coupling is not suited for S-feeding).
• ’NT-Star’ with star point on the IOM®-2 bus (already not supported in INTC-Q).
• No access to S2-5 channels. Access only to S1 and Q channel as in SCOUT. No
selection between transparent and non-auto mode provided.
• The oscillator architecture was changed with respect to the INTC-Q to reduce power
consumption. As a consequence, the Q-SMINT®I always needs a crystal and pin XIN
can not be connected to an external clock as it was possible for IEC-Q and NTC-Q.
This does not limit the use of the Q-SMINT®I in NTs since all NT designs use crystals
anyway.
Data Sheet
5
2001-03-30
PEF 82912/82913
Overview
1.5
Pin Configuration
•
48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33
49
50
32
/VDDDET
FSC
DCL
VSSD
VDDD
TP2
31
30
29
51
52
53
VDDa_SR
VSSa_SR
A5
A6
Q-SMINT I
AD7 or SDX
28
27
54
55
AD6 or SDR
AD5 or SCLK
AD4
PS1
26
25
PEF 82912/
PEF 82913
56
57
24
23
22
AD3
AD2
AD1
AD0
/EAW
58
59
XOUT
XIN
BOUT
60
61
21
20
19
18
17
VDDa_UX
VSSa_UX
AOUT
62
63
64
MCLK
/ACT
1
2
3
4
5
6
7
8
9
10 11 12 13 14 15 16
pin_2.vsd
Figure 1
Pin Configuration
Data Sheet
6
2001-03-30
PEF 82912/82913
Overview
1.6
Block Diagram
•
VDDDET
XIN
XOUT
RST RSTO
PS1
PS2
MTI
SR1
Clock Generation
POR/UVD
AOUT
BOUT
SR2
SX1
SX2
S-Transceiver
U-Tansceiver
AIN
BIN
D-Channel
Arbitration
to µP IF
to µP IF
M
O
N
C
D
A
W
D
T
C/I
TP1
TP2
Factory
Tests
TIC
LED
ACT
µP Interface
(e.g. Multiplexed Mode)
IOM-2 Interface
FSC DCL BCL DU DD SDS1 SDS2
AD0-AD7
ALE RD WR CS INT MCLK EAW
block diagram.vsd
Figure 2
Block Diagram
Data Sheet
7
2001-03-30
PEF 82912/82913
Overview
1.7
Pin Definitions and Functions
Pin Definitions and Functions
•
Table 2
Pin
Symbol Type
Function
VDDa_UR
2
–
Supply voltage for U-Receiver
(3.3 V ± 5 %)
VSSa_UR
1
–
Analog ground (0 V) U-Receiver
VDDa_UX
62
–
Supply voltage for U-Transmitter
(3.3 V ± 5 %)
VSSa_UX
63
51
–
Analog ground (0 V) U-Transmitter
VDDa_SR
–
Supply voltage for S-Receiver
(3.3 V ± 5 %)
VSSa_SR
52
46
–
Analog ground (0 V) S-Receiver
VDDa_SX
–
Supply voltage for S-Transmitter
(3.3 V ± 5 %)
VSSa_SX
45
29
–
Analog ground (0 V) S-Transmitter
VDDD
–
Supply voltage digital circuits
(3.3 V ± 5 %)
VSSD
30
13
–
Ground (0 V) digital circuits
VDDD
–
Supply voltage digital circuits
(3.3 V ± 5 %)
VSSD
14
–
Ground (0 V) digital circuits
32
31
FSC
DCL
O
O
Frame Sync:
8-kHz frame synchronization signal
Data Clock:
IOM-2 interface clock signal (double clock):
1.536 MHz
35
BCL
O
Bit Clock:
The bit clock is identical to the IOM-2 data rate
(768 kHz)
33
34
DD
DU
I/O
OD
Data Downstream:
Data on the IOM-2 interface
I/O
OD
Data Upstream:
Data on the IOM-2 interface
Data Sheet
8
2001-03-30
PEF 82912/82913
Overview
Table 2
Pin Definitions and Functions (cont’d)
Pin
Symbol Type
Function
8
SDS1
O
Serial Data Strobe1:
Programmable strobe signal for time slot and/
or D-channel indication on IOM-2
7
SDS2
O
Serial Data Strobe2:
Programmable strobe signal for time slot and/
or D-channel indication on IOM-2
12
CS
I
Chip Select:
A low level indicates a microcontroller access to
the Q-SMINTI
26
26
SCLK
AD5
I
Serial Clock:
Clock signal of the SCI interface if a serial
interface is selected
Multiplexed Bus Mode:
Address/data bus
I/O
Address/data line AD5 if the parallel interface is
selected
Non-Multiplexed Bus Mode:
Data bus
Data line D5 if the parallel interface is selected
27
27
SDR
AD6
I
Serial Data Receive:
Receive data line of the SCI interface if a serial
interface is selected
I/O
Multiplexed Bus Mode:
Address/data bus
Address/data line AD6 if the parallel interface is
selected
Non-Multiplexed Bus Mode:
Data bus
Data line D6 if the parallel interface is selected
Data Sheet
9
2001-03-30
PEF 82912/82913
Overview
Table 2
Pin Definitions and Functions (cont’d)
Pin
Symbol Type
Function
28
SDX
AD7
OD,O Serial Data Transmit:
Transmit data line of the SCI interface if a serial
interface is selected
28
I/O
Multiplexed Bus Mode:
Address/data bus
Address/data line AD7 if the parallel interface is
selected
Non-Multiplexed Bus Mode:
Data bus
Data line D7 if the parallel interface is selected
21
22
23
24
25
AD0
AD1
AD2
AD3
AD4
I/O
I/O
I/O
I/O
I/O
Multiplexed Bus Mode:
Address/data bus
Transfers addresses from the microcontroller to
the Q-SMINTI and data between the
microcontroller and the Q-SMINTI.
Non-Multiplexed Bus Mode:
Data bus.
Transfers data between the microcontroller and
the Q-SMINTI (data lines D0-D4).
36
37
38
39
40
53
54
A0
A1
A2
A3
A4
A5
A6
I
I
I
I
I
I
I
Non-Multiplexed Bus Mode:
Address bus transfers addresses from the
microcontroller to the Q-SMINTI. For indirect
address mode only A0 is valid.
Multiplexed Bus Mode
Not used in multiplexed bus mode. In this case
A0-A6 should directly be connected to VDD.
11
RD
I
Read
Indicates a read access to the registers (Intel
bus mode).
DS
I
Data Strobe
The rising edge marks the end of a valid read or
write operation (Motorola bus mode).
Data Sheet
10
2001-03-30
PEF 82912/82913
Overview
Table 2
Pin Definitions and Functions (cont’d)
Pin
Symbol Type
Function
Write
10
WR
I
I
Indicates a write access to the registers (Intel
bus mode).
Read/Write
R/W
A HIGH identifies a valid host access as a read
operation and a LOW identifies a valid host
access as a write operation (Motorola bus
mode).
9
5
ALE
RST
I
I
Address Latch Enable
An address on the external address/data bus
(multiplexed bus type only) is latched with the
falling edge of ALE.
ALE also selects the microcontroller interface
type (multiplexed or non multiplexed).
Reset:
Low active reset input. Schmitt-Trigger input
with hysteresis of typical 360 mV. Tie to ’1’ if not
used.
6
RSTO
INT
OD
OD
Reset Output:
Low active reset output.
15
Interrupt Request:
INT becomes active if the Q-SMINTI requests
an interrupt.
18
MCLK
EAW
O
I
Microcontroller Clock:
Clock output for the microcontroller
19
20
Tie to ‘1‘
External Awake:
A low level on EAW during power down
activates the clock generation of the Q-
SMINTI, i.e. the IOM-2 interface provides
FSC, DCL and BCL for read and write
access.1)
43
44
47
SX1
SX2
SR1
O
O
I
S-Bus Transmitter Output (positive)
S-Bus Transmitter Output (negative)
S-Bus Receiver Input
Data Sheet
11
2001-03-30
PEF 82912/82913
Overview
Table 2
Pin Definitions and Functions (cont’d)
Pin
Symbol Type
Function
48
SR2
I
S-Bus Receiver Input
60
59
XIN
I
Crystal 1:
Connected to a 15.36 MHz crystal
XOUT
O
Crystal 2:
Connected to a 15.36 MHz crystal
64
61
3
AOUT
BOUT
AIN
O
O
I
Differential U-interface Output
Differential U-interface Output
Differential U-interface Input
Differential U-interface Input
4
BIN
I
VDDDET
49
I
VDD Detection:
This pin selects if the VDD detection is active
(’0’) and reset pulses are generated on pin
RSTO or whether it is deactivated (’1’) and an
external reset has to be applied on pin RST.
16
55
MTI
PS1
I
I
Metallic Termination Input.
Input to evaluate Metallic Termination pulses.
Tie to ’1’ if not used.
Power Status (primary).
The pin status is passed to the overhead bit
’PS1’ in the U frame to indicate the status of the
primary power supply (’1’ = ok).
41
PS2
I
Power Status (secondary).
The pin status is passed to the overhead bit
’PS2’ in the U frame to indicate the status of the
secondary power supply (’1’ = ok).
17
42
ACT
TP1
O
I
Activation LED.
Indicates the activation status of U- and S-
transceiver. Can directly drive a LED (4 mA).
Test Pin 1.
Used for factory device test.
Tie to VSS
Data Sheet
12
2001-03-30
PEF 82912/82913
Overview
Table 2
Pin Definitions and Functions (cont’d)
Pin
Symbol Type
TP2
Function
50
I
Test Pin 2.
Used for factory device test.
Tie to VSS
56, 57, res
Reserved
58
1)
This function of pin EAW is different to that defined in Ref. [14]
I: Input
O: Output (Push-Pull)
OD: Output (Open Drain)
1.7.1
Specific Pins
LED Pin ACT
A LED can be connected to pin ACT to display four different states (off, slow flashing,
fast flashing, on). It displays the activation status of the U- and S-transceiver according
to Table 3. or it is programmable via two bits (LED1 and LED2 in register MODE2).
Table 3
Pin ACT
VDD
ACT States
LED
off
U_Deactivated
U_Activated
S_Activated
1
0
0
0
x
0
1
1
x
x
0
1
8Hz
8Hz
1Hz
on
1Hz
GND
with:
U_Deactivated: ’Deactivated State’ as defined in Chapter 2.4.10.5. If the ‘Simplified
State Machine‘ is selected: ’Deactivated State’ and ‘IOM-2 Awaked‘.
U_Activated: ’Synchronized 1’, ’Synchronized 2’, ’Wait for ACT’, ’Transparent’, ’Error S/
T’, ’Pend. Deact. S/T’, ’Pend. Deact. U’ as defined in Chapter 2.4.10.5.
S-Activated: ’Activated State’ as defined in Chapter 2.5.5.
Note: Optionally, pin ACT can drive a second LED with inverse polarity (connect this
additional LED to 3.3 V only).
Data Sheet
13
2001-03-30
PEF 82912/82913
Overview
Test Modes
The test patterns on the S-interface (‘2 kHz Single Pulses‘, ‘96 kHz Continuous Pulses‘)
and on the U-interface (‘Data Through‘, ‘Send Single Pulses‘) are invoked via C/I codes
(TM1, TM2, DT, SSP). Setting SRES.RES_U to ‘1‘ forces the U-transceiver into test
mode ‘Quiet Mode‘ (QM), i.e. the U-transceiver is hardware reset.
1.8
System Integration
•
DC/DC Converter
IDCC
PEB2023
MLT
S/T - Interface
U - Interface
Q-SMINTI
PEF 82912
PEF 82913
S
U
POTS Interface
µP
UTAH
C 165 Core
HV - SLIC
SLICOFI - 2
4x HDLC
IOM-2
IOM-2
USB/
V.24
HV - SLIC
USB / V.24 Interface
HENTappl.vsd
Figure 3
Application Example Q-SMINTI: High Feature Intelligent NT
The U-transceiver, S-transceiver and the IOM-2 channels can be controlled and
monitored via:
a) the parallel or serial microprocessor interface
- Access of on-chip registers via µP interface Address/Data format
- Activation/Deactivation control of U- and S-transceiver via µP interface and C/I
handler
- Q-SMINTI is Monitor channel master
- TIC bus is transparent on IOM-2-interface and is used for D-channel arbitration
between S-transceiver and off-chip HDLC controllers.
Data Sheet
14
2001-03-30
PEF 82912/82913
Overview
•
C/I0
S
C/I1
U
Mon
C/I
Register
MON
IOM -2
µc - Interface
IOM-2 Slave
e.g. SLICOFI-2
µc
iommaster.vsd
Figure 4
Control via µP Interface
Alternatively, the Q-SMINTI can be controlled via
b) the IOM-2 Interface
- Access of on-chip registers via the Monitor channel with Header/Address/Data
format (Device is Monitor slave)
- Activation/Deactivation control of U- and S-transceiver via the C/I channels CI0
and CI1
- TIC bus is transparent on IOM-2-interface and is used for D-channel arbitration
between S-transceiver and off-chip HDLC controllers.
Data Sheet
15
2001-03-30
PEF 82912/82913
Overview
•
S
C/I1
U
C/I0
MON
Register
IOM -2
INT
IOM-2 Master
e.g. UTAH
iomslave.vsd
Figure 5
Control via IOM-2 Interface
Data Sheet
16
2001-03-30
PEF 82912/82913
Functional Description
2
Functional Description
2.1
Microcontroller Interfaces
The Q-SMINTI supports either a serial or a parallel microcontroller interface. For
applications where no controller is connected to the Q-SMINTI microcontroller
interface, register programming is done via the IOM-2 MONITOR channel from a
master device. In such applications the Q-SMINTI operates in the IOM-2 slave mode
(refer to the corresponding chapter of the IOM-2 MONITOR handler).
The interface selections are all done by pinstrapping. The possible interface selections
are listed in Table 4. The selection pins are evaluated when the reset input RST is
released. For the pin levels stated in the tables the following is defined:
’High’:dynamic pin value which must be ’High’ when the pin level is evaluated
VDD, VSS:static ’High’ or ’Low’ level (tied to VDD, VSS)
•
Table 4
PINS
WR RD
Interface Selection for the Q-SMINTI
Serial/Parallel
Interface
PINS
ALE
Interface
Type/Mode
CS
(R/W) (DS)
VDD
VSS
edge
VSS
VSS
Motorola
’High’ ’High’
Parallel
Serial
‘High’
Siemens/Intel Non-Mux
Siemens/Intel Mux
VSS
VSS
’High’
VSS
Serial Control Interface(SCI)
IOM-2 MONITOR Channel
(Slave Mode)
Note: For a selected interface mode which does not require all pins (e.g. address pins)
the unused pins must be tied to VDD.
The microcontroller interface also consists of a microcontroller clock generation at pin
MCLK, an interrupt request at pin INT, a reset input pin RST and a reset output pin
RSTO.
The interrupt request pin INT (open drain output) becomes active if the Q-SMINTI
requests an interrupt.
Data Sheet
17
2001-03-30
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Functional Description
2.1.1
Serial Control Interface (SCI)
The serial control interface (SCI) is compatible to the SPI interface of Motorola and to the
Siemens C510 family of microcontrollers.
The SCI consists of 4 lines: SCLK, SDX, SDR and CS. Data is transferred via the lines
SDR and SDX at the rate given by SCLK. The falling edge of CS indicates the beginning
of a serial access to the registers. The Q-SMINTI latches incoming data at the rising
edge of SCLK and shifts out at the falling edge of SCLK. Each access must be
terminated by a rising edge of CS. Data is transferred in groups of 8 bits with the MSB
first.
Pad mode of SDX can be selected ’open drain’ or ’push-pull’ by programming
MODE2.PPSDX.
Figure 6 shows the timing of a one byte read/write access via the serial control interface.
Data Sheet
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Functional Description
•
Write Access
CS
SCLK
SDR
SDX
Command/Address
Header
Data
7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0
`0`
write
Read Access
CS
SCLK
SDR
SDX
Command/Address
Header
7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0
`1`
read
Data
7 6 5 4 3 2 1 0
SCI_TIM.VSD
Figure 6
Serial Control Interface Timing
Data Sheet
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PEF 82912/82913
Functional Description
2.1.1.1 Programming Sequences
The basic structure of a read/write access to the Q-SMINTI registers via the serial
control interface is shown in Figure 7.
•
write sequence:
write
byte 2
byte 3
header
address (command)
write data
0
SDR
7
0 7
6
0
7
7
0
0
read sequence:
read
byte 2
address (command)
header
1
0 7
SDR
7
6
0
byte 3
SDX
read data
Figure 7
Serial Command Structure
A new programming sequence starts with the transfer of a header byte. The header byte
specifies different programming sequences allowing a flexible and optimized access to
the individual functional blocks of the Q-SMINTI.
The possible sequences are listed in Table 5 and are described after that.
•
Table 5
Header Byte Code
Sequence
Header
Byte
Sequence Type
Access to
40H
48H
43H
41H
49H
Adr-Data-Adr-Data
non-interleaved
interleaved
Address Range 00H-7FH
Adr-Data-Data-Data Read-/Write-only
non-interleaved
Address Range 00H-7FH
interleaved
Data Sheet
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Functional Description
Header 40H: Non-interleaved A-D-A-D Sequences
The non-interleaved A-D-A-D sequences give direct read/write access to the address
range 00H-7FH and can have any length. In this mode SDX and SDR can be connected
together allowing data transmission on one line.
Example for a read/write access with header 40H:
header wradr wrdata rdadr
rdadr
wradr wrdata
SDR
SDX
rddata
rddata
Header 48H: Interleaved A-D-A-D Sequences
The interleaved A-D-A-D sequences give direct read/write access to the address range
00H-7FH and can have any length. This mode allows a time optimized access to the
registers by interleaving the data on SDX and SDR.
Example for a read/write access with header 48H:
header wradr wrdata rdadr
rdadr
wradr wrdata
SDR
SDX
rddata rddata
Header 43H: Read-/Write- only A-D-D-D Sequence
Generally, it can be used for any register access to the address range 20H-7DH. The
sequence can have any length and is terminated by the rising edge of CS.
Example for a write access with header 43H:
header wradr wrdata wrdata wrdata wrdata wrdata wrdata wrdata
SDR
SDX
(wradr)
(wradr)
(wradr)
(wradr)
(wradr)
(wradr)
(wradr)
Example for a read access with header 43H:
header rdadr
SDR
SDX
rddata rddata rddata rddata rddata rddata rddata
(rdadr)
(rdadr)
(rdadr)
(rdadr)
(rdadr)
(rdadr)
(rdadr)
Data Sheet
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PEF 82912/82913
Functional Description
Header 41H: Non-interleaved A-D-D-D Sequence
This sequence (header 41H) allows in front of the A-D-D-D write access a non-
interleaved A-D-A-D read access. Generally, it can be used for any register access to
the address range 20H-7DH.The termination condition of the read access is the reception
of the wradr. The sequence can have any length and is terminated by the rising edge of
CS.
Example for a read/write access with header 41H:
header rdadr
rdadr
wradr wrdata wrdata wrdata
SDR
SDX
(wradr)
(wradr)
(wradr)
rddata
rddata
Header 49H: Interleaved A-D-D-D Sequence
This sequence (header 49H) allows in front of the A-D-D-D write access an interleaved
A-D-A-D read access. Generally, it can be used for any register access to the address
range 20H-7DH.The termination condition of the read access is the reception of the
wradr. The sequence can have any length and is terminated by the rising edge of CS.
Example for a read/write access with header 49H:
header rdadr
rdadr
wradr wrdata wrdata wrdata
SDR
SDX
(wradr)
(wradr)
(wradr)
rddata rddata
2.1.2
Parallel Microcontroller Interface
The 8-bit parallel microcontroller interface with address decoding on chip allows an easy
and fast microcontroller access.
The parallel interface of the Q-SMINTI provides three types of µP busses which are
selected via pin ALE. The bus operation modes with corresponding control pins are listed
in Table 6.
•
Table 6
Bus Operation Modes
Bus Mode
Pin ALE
VDD
Control Pins
CS, R/W, DS
CS, WR, RD
(1) Motorola
(2) Siemens/Intel non-multiplexed
(3) Siemens/Intel multiplexed
VSS
Edge
CS, WR, RD, ALE
The occurrence of an edge on ALE, either positive or negative, at any time during the
operation immediately selects the interface type (3). A return to one of the other interface
types is possible only if a hardware reset is issued.
Data Sheet
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Functional Description
Note: For a selected interface mode which does not require all pins (e.g. address pins)
the unused pins must be tied to VDD.
A read/write access to the Q-SMINTI registers can be done in multiplexed or non-
multiplexed mode.
In non-multiplexed mode the register address must be applied to the address bus (A0-
A6) for the data access via the data bus (D0-D7).
In multiplexed mode the address on the address bus (AD0-AD7) is latched in by ALE
before a read/write access via the address/data bus is performed.
The Q-SMINTI provides two different ways to address the register contents which can
be selected with the AMOD bit in the MODE2 register. The address mode after reset is
the indirect address mode (AMOD = ’0’). Reprogramming into the direct address mode
(AMOD = ’1’) has to take place in the indirect address mode. Figure 8 illustrates both
register addressing modes.
Direct address mode (AMOD = ’1’): The register address to be read or written is directly
set in the way described above.
Indirect address mode (AMOD = ’0’):
• non-muxed: only the LSB of the address bus (A0)
• muxed: only the LSB of the address-data bus (AD0)
gets evaluated to address a virtual ADDRESS (0H) and a virtual DATA (1H) register.
Every access to a target register consists of:
• a write access (muxed or non-muxed) to ADDRESS to store the target register´s
address, as well as
• a read access (muxed or non-muxed) from DATA to read from the target register or
• a write access (muxed or non-muxed) to DATA to write to the target register
Data Sheet
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PEF 82912/82913
Functional Description
•
Direct Address Mode
AMOD = ´1´
Indirect Address Mode
AMOD = ´0´ (default)
D7 - D0
Data
D7 - D0
Data
A6 - A0
7Fh
A0
7Eh
7Dh
7Ch
04h
03h
02h
01h
00h
1h
0h
DATA
ADDRESS
regacces.vsd
Figure 8
2.1.3
Direct/Indirect Register Address Mode
Microcontroller Clock Generation
The microcontroller clock is derived from the unregulated 15.36 MHz clock from the
oscillator and provided by the pin MCLK. Five clock rates are selectable by a
programmable prescaler which is controlled by the bits MODE1.MCLK and
MODE1.CDS corresponding to the following table.
Table 7
MODE1.
MCLK Frequencies
MCLK frequency
MCLK frequency
with
MODE1.CDS = ’1’
MCLK
Bits
with
MODE1.CDS = ’0’
0
0
1
1
0
1
0
1
3.84 MHz
0.96 MHz
7.68 MHz
disabled
7.68 MHz
1.92 MHz
15.36 MHz
disabled
The clock rate is changed after CS becomes inactive.
Data Sheet
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PEF 82912/82913
Functional Description
2.2
Reset Generation
Figure 9 shows the organization of the reset generation of the Q-SMINTI.
•.
RSS1
´0´
´1´
125µs
≤ t ≤ 250µs
C/I0 Code Change
(Exchange Awake)
RSTO
´1,x´
´0,0´
≥1
RSS2,1
RSS2,1
´0,1´= open
t = 125µs
Watchdog
Deacti-
vation
Delay
Reset MODE1
Register
´1´
´0´
Software Reset
Register (SRES)
VDDDET
RES_CI
RES_HDLC
RES_S
POR/UVD
Reset
Functional
Block
´0´
´1´
VDDDET
RES_U
≥1
Internal Reset
of all Registers
RST Pin
RESETGEN.VSD
Figure 9
Reset Generation of the Q-SMINTI1)
Reset Source Selection
The internal reset sources C/I code change and Watchdog timer can be output at the low
active reset pin RSTO. These reset sources can be selected with the RSS2,1 bits in the
MODE1 register according to Table 8.
1)
The ’OR’-gates shall illustrate in a symbolic way, that ’source A active’ or ’source B active’ is forwarded. The
real polarity of the different sources is not considered.
Data Sheet
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Functional Description
The internal reset sources set the MODE1 register to its reset value.
Table 8
Reset Source Selection
RSS2
Bit 1
RSS1
Bit 0
C/I Code
Change
Watchdog
Timer
POR/UVD1) and
RST
0
0
1
0
1
0
1
--
--
x
/RSTO disabled (= high impedance)
x
--
x
x
x
1
--
1)
POR/UVD can be enabled/disabled via pin VDDDET
•
• C/I Code Change (Exchange Awake)
A change in the downstream C/I channel (C/I0) generates a reset pulse of 125 µs ≤ t
≤ 250 µs.
• Watchdog Timer
After the selection of the watchdog timer (RSS = ’11’) an internal timer is reset and
started. During every time period of 128 ms the microcontroller has to program the
WTC1- and WTC2 bits in the following sequence to reset and restart the watchdog timer:
WTC1
WTC2
1.
2.
1
0
0
1
Otherwise the timer expires and a WOV-interrupt (ISTA Register) together with a reset
out pulse on pin RSTO of 125 µs is generated.
Deactivation of the watchdog timer is only possible with a hardware reset (including
expiration of the watchdog timer).
As in the SCOUT-S, the watchdog timer is clocked with the IOM-2 clocks and works
only if the internal IOM-2 clocks are active. Hence, the power consumption is
minimized in state power down.
Software Reset Register (SRES)
Several main functional blocks of the Q-SMINTI can be reset separately by software
setting the corresponding bit in the SRES register. This is equivalent to a hardware reset
of the corresponding functional block. The reset state is activated as long as the bit is set
to ’1’.
Data Sheet
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Functional Description
External Reset Input
At the RST input an external reset can be applied forcing the Q-SMINTI in the reset
state. This external reset signal is additionally fed to the RSTO output.
After release of an external reset, the µC has to wait for min. tµC before it starts read or
write access to the Q-SMINTI (see Table 40).
Reset Ouput
If VDDDET is active, then the deactivation of a reset output on RSTO is delayed by
tDEACT (see Table 41).
Reset Generation
The Q-SMINTI has an on-chip reset generator based on a Power-On Reset (POR) and
Under Voltage Detection (UVD) circuit (see Table 41). The POR/UVD requires no
external components.
The POR/UVD circuit can be disabled via pin VDDDET.
The requirements on VDD ramp-up during power-on reset are described in
Chapter 5.6.5.
Clocks and Data Lines During Reset
During reset the data clock (DCL), the bit clock (BCL), the microcontroller clock1) (MCLK)
and the frame synchronization (FSC) keep running.
During reset DD and DU are high; with the exception of:
• The output C/I code from the U-Transceiver on DD IOM-2 channel 0 is ’DR’ = 0000
(Value after reset of register UCIR = ’00H’)
• The output C/I code from the S-Transceiver on DU IOM-2 channel 1 is ’TIM’ = 0000.
1)
during a Power-On/UVD Reset, the microcontroller clock MCLK is not running, but starts running as soon as
timer t
is started.
DEAC
Data Sheet
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Functional Description
2.3
IOM -2 Interface
The Q-SMINTI supports the IOM-2 interface in terminal mode (DCL=1.536 MHz)
according to the IOM-2 Reference Guide [13].
IOM -2 Functional Description
2.3.1
The IOM-2 interface consists of four lines: FSC, DCL, DD, DU and optionally BCL. The
rising edge of FSC indicates the start of an IOM-2 frame. The DCL and the BCL clock
signals synchronize the data transfer on both data lines DU and DD. The DCL is twice
the bit rate, the BCL rate is equal to the bit rate. The bits are shifted out with the rising
edge of the first DCL clock cycle and sampled at the falling edge of the second clock
cycle. With BCL the bits are shifted out with the rising edge and sampled with the falling
edge of the single clock cycle.
The IOM-2 interface can be enabled/disabled with the DIS_IOM bit in the IOM_CR
register.
The FSC signal is an 8 kHz frame sync signal. The number of PCM timeslots on the
receive and transmit lines is determined by the frequency of the DCL clock (or BCL), with
the 1.536 MHz (BCL=768 kHz) clock 3 channels consisting of 4 timeslots each are
available.
®
IOM -2 Frame Structure of the Q-SMINTI
The frame structure on the IOM-2 data ports (DU,DD) of the Q-SMINTI with a DCL
clock of 1.536 MHz (or BCL=768 kHz) and if TIC bus is not disabled (IOM_CR.TIC_DIS)
is shown in Figure 10.
•
macro_19
Figure 10
IOM -2 Frame Structure of the Q-SMINTI
Data Sheet
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Functional Description
The frame is composed of three channels
• Channel 0 contains 144-kbit/s of user and signaling data (2B + D), a MONITOR
programming channel (MON0) and a command/indication channel (CI0) for control
and programming of e.g. the U-transceiver.
• Channel 1 contains two 64-kbit/s intercommunication channels (IC), a MONITOR
programming channel (MON1) and a command/indication channel (CI1) for control
and programming of e.g. the S-transceiver.
• Channel 2 is used for D-channel access mechanism (TlC-bus, S/G bit). Additionally,
channel 2 supports further IC and MON channels.
IOM -2 Handler
2.3.2
The IOM-2 handler offers a great flexibility for handling the data transfer between the
different functional units of the Q-SMINTI and voice/data devices connected to the
IOM-2 interface. Additionally it provides a microcontroller access to all time slots of the
IOM-2 interface via the four controller data access registers (CDA).
The PCM data of the functional units
• S-transceiver (S) and the
• Controller data access (CDA)
can be configured by programming the time slot and data port selection registers
(TSDP). With the TSS bits (Time Slot Selection) the PCM data of the functional units can
be assigned to each of the 12 PCM time slots of the IOM-2 frame. With the DPS bit
(Data Port Selection) the output of each functional unit is assigned to DU or DD
respectively. The input is assigned vice versa. With the control registers (CR) the access
to the data of the functional units can be controlled by setting the corresponding control
bits (EN, SWAP).
The IOM-2 handler also provides access to the
• U and S transceiver
• MONITOR channel
• C/I channels (CI0,CI1)
• TIC bus (TIC)
The access to these channels is controlled by the registers S_CR, CI_CR and MON_CR.
The IOM-2 interface with the two Serial Data Strobes (SDS1,2) is controlled by the
control registers IOM_CR, SDS1_CR and SDS2_CR.
The following Figure 11 shows the architecture of the IOM-2 handler.
Data Sheet
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Functional Description
•
CDA Data
Monitor Data
DU
DD
FSC
DCL
TIC Bus Data
BCL/SCLK
C/I0 Data
C/I1 Data
SDS1
SDS2
D/B1/B2 Data
C/I0 Data
Figure 11
Architecture of the IOM-2 Handler
Data Sheet
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Functional Description
2.3.2.1 Controller Data Access (CDA)
The four controller data access registers (CDA10, CDA11, CDA20, CDA21) provide
microcontroller access to the 12 IOM-2 time slots and more:
• looping of up to four independent PCM channels from DU to DD or vice versa over the
four CDA registers
• shifting or switching of two independent PCM channels to another two independent
PCM channels on both data ports (DU, DD). Between reading and writing the data can
be manipulated (processed with an algorithm) by the microcontroller. If this is not the
case a switching function is performed.
• monitoring of up to four time slots on the IOM-2 interface simultaneously
• microcontroller read and write access to each PCM channel
The access principle, which is identical for the two channel register pairs CDA10/11 and
CDA20/21, is illustrated in Figure 12. The index variables x,y used in the following
description can be 1 or 2 for x, and 0 or 1 for y. The prefix ’CDA_’ from the register names
has been omitted for simplification.
To each of the four CDAxy data registers a TSDPxy register is assigned by which the
time slot and the data port can be determined. With the TSS (Time Slot Selection) bits a
time slot from 0...11 can be selected. With the DPS (Data Port Selection) bit the output
of the CDAxy register can be assigned to DU or DD respectively. The time slot and data
port for the output of CDAxy is always defined by its own TSDPxy register. The input of
CDAxy depends on the SWAP bit in the control registers CRx.
If the SWAP bit = ’0’ (swap is disabled) the time slot and data port for the input and output
of the CDAxy register is defined by its own TSDPxy register.
If the SWAP bit = ’1’ (swap is enabled) the input port and time slot of the CDAx0 is
defined by the TSDP register of CDAx1 and the input port and time slot of CDAx1 is
defined by the TSDP register of CDAx0. The input definition for time slot and data port
CDAx0 are thus swapped to CDAx1 and for CDAx1 swapped to CDAx0. The output
timeslots are not affected by SWAP.
The input and output of every CDAxy register can be enabled or disabled by setting the
corresponding EN (-able) bit in the control register CDAx_CR. If the input of a register is
disabled the output value in the register is retained.
Usually one input and one output of a functional unit (transceiver, CDA register) is
programmed to a timeslot on IOM-2 (e.g. for B-channel transmission in upstream
direction the S-transceiver writes data onto IOM-2 and the U-transceiver reads data
from IOM-2). For monitoring data in such cases a CDA register is programmed as
described below under “Monitoring Data”. Besides that none of the IOM-2 timeslots
must be assigned more than one input and output of any functional unit.
Data Sheet
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Functional Description
•.
TSa
TSb
DU
Control
Register
CDA_CRx
0
0
1
1
Enable
Enable
Input
Swap
(SWAP)
output
(EN_O1)
input
(EN_I0)
input
(EN_I1)
output
(EN_O0)
1
1
CDAx1
CDAx0
1
1
1
1
1
0
0
1
DD
TSa
IOM_HAND.FM4
TSb
x = 1 or 2; a,b = 0...11
Figure 12
Data Access via CDAx0 and CDAx1 register pairs
Looping and Shifting Data
Figure 13 gives examples for typical configurations with the above explained control and
configuration possibilities with the bits TSS, DPS, EN and SWAP in the registers
TSDPxy or CDAx_CR:
a) looping IOM-2 time slot data from DU to DD or vice versa (SWAP = ’0’)
b) shifting data from TSa to TSb and TSc to TSd in both transmission directions (SWAP
= ’1’)
c) switching data from TSa to TSb and looping from DU to DD or switching TSc to TSd
and looping from DD to DU .
TSa is programmed in TSDP10, TSb in TSDP11, TSc in TSDP20 and TSd in TSDP21.
Data Sheet
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PEF 82912/82913
Functional Description
•
a) Looping Data
TSa
TSb
TSc
TSd
DU
CDA10 CDA11
CDA20 CDA21
DD
DU
.TSS: TSa
.DPS
.SWAP
TSb
’0’
TSc
’1’
TSd
’1’
’0’
’0’
’0’
b) Shifting Data
TSa
TSb
TSd
TSc
CDA10 CDA11
CDA20 CDA21
DD
DU
.TSS: TSa
TSb
’1’
TSc
’0’
TSd
’1’
.DPS
’0’
.SWAP
’1’
’1’
c) Switching Data
TSa
TSb
TSd
TSc
CDA10 CDA11
CDA20 CDA21
DD
.TSS: TSa
TSb
’0’
TSc
’1’
TSd
’1’
.DPS
’0’
.SWAP
’1’
’1’
Figure 13
Examples for Data Access via CDAxy Registers
a) Looping Data
b) Shifting (Switching) Data
c) Switching and Looping Data
Data Sheet
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Functional Description
Figure 14 shows the timing of looping TSa from DU to DD via CDAxy register. TSa is
read in the CDAxy register from DU and is written one frame later on DD.
Figure 15 shows the timing of shifting data from TSa to TSb on DU(DD). In Figure 15a)
shifting is done in one frame because TSa and TSb didn’t succeed directly one another
(a = 0...9 and b ≥ a+2). In Figure 15b) shifting is done from one frame to the following
frame. This is the case when the time slots succeed one other (b = a+1) or b is smaller
than a (b < a).
At looping and shifting the data can be accessed by the controller between the
synchronous transfer interrupt (STI) and the status overflow interrupt (STOV). STI and
STOV are explained in the section ’Synchronous Transfer’. If there is no controller
intervention the looping and shifting is done autonomously.
•.
FSC
DU
TSa
TSa
CDAxy
µC *)
DD
TSa
TSa
*) if access by the µC is required
Figure 14
Data Access when Looping TSa from DU to DD
Data Sheet
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PEF 82912/82913
Functional Description
•
a) Shifting TSa → TSb within one frame
(a,b: 0...11 and b ≥ a+2)
FSC
DU
(DD)
TSa
TSa
TSb
CDAxy
µC *)
b) Shifting TSa → TSb in the next frame
(a,b: 0...11 and (b = a+1 or b <a)
FSC
DU
TSa
TSb
TSa TSb
(DD)
CDAxy
ACK
µC *)
*) if access by the µC is required
Figure 15
Data Access when Shifting TSa to TSb on DU (DD)
Data Sheet
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Functional Description
Monitoring Data
Figure 16 gives an example for monitoring of two IOM-2 time slots each on DU or DD
simultaneously. For monitoring on DU and/or DD the channel registers with even
numbers (CDA10, CDA20) are assigned to time slots with even numbers TS(2n) and the
channel registers with odd numbers (CDA11, CDA21) are assigned to time slots with odd
numbers TS(2n+1). The user has to take care of this restriction by programming the
appropriate time slots.
This mode is only valid if two blocks (e.g. both transceivers) are programmed to these
timeslots and communicating via IOM-2.
However, if only one block is programmed to this timeslot the timeslots for CDAx0 and
CDAx1 can be programmed completely independently.
•.
a) Monitoring Data
EN_O:
EN_I:
DPS: ’0’
TSS: TS(2n)
’0’
’1’
’0’
’1’
CDA_CR1.
’0’
TS(2n+1)
DU
CDA10
CDA20
CDA11
CDA21
DD
TS(2n)
TSS:
TS(2n+1)
DPS: ’1’
’1’
’1’
’0’
CDA_CR2.
’1’
’0’
EN_I:
EN_O:
Figure 16
Example for Monitoring Data
Data Sheet
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Functional Description
Monitoring TIC Bus
Monitoring the TIC bus (TS11) is handled as a special case. The TIC bus can be
monitored with the registers CDAx0 by setting the EN_TBM (Enable TIC Bus Monitoring)
bit in the control registers CRx. The TSDPx0 must be set to 08h for monitoring from DU
or 88h for monitoring from DD. By this it is possible to monitor the TIC bus (TS11) and
the odd numbered D-channel (TS3) simultaneously on DU and DD.
Synchronous Transfer
While looping, shifting and switching the data can be accessed by the controller between
the synchronous transfer interrupt (STI) and the synchronous transfer overflow interrupt
(STOV).
The microcontroller access to each of the CDAxy registers can be synchronized by
means of four programmable synchronous transfer interrupts (STIxy)1) and synchronous
transfer overflow interrupts (STOVxy)2) in the STI register.
Depending on the DPS bit in the corresponding TSDPxy register the STIxy is generated
two (for DPS=’0’) or one (for DPS=’1’) BCL clock after the selected time slot
(CDA_TSDPxy.TSS). One BCL clock is equivalent to two DCL clocks.
In the following description the index xy0 and xy1 are used to refer to two different
interrupt pairs (STI/STOV) out of the four CDA interrupt pairs (STI10/STOV10, STI11/
STOV11, STI20/STOV20, STI21/STOV21).
A STOVxy0 is related to its STIxy0 and is only generated if STIxy0 is enabled and not
acknowledged. However, if STIxy0 is masked, the STOVxy0 is generated for any other
STIxy1 which is enabled and not acknowledged.
Table 9 gives some examples for that. It is assumed that a STOV interrupt is only
generated because a STI interrupt was not acknowledged before.
In example 1 only the STIxy0 is enabled and thus STIxy0 is only generated. If no STI is
enabled, no interrupt will be generated even if STOV is enabled (example 2).
In example 3 STIxy0 is enabled and generated and the corresponding STOVxy0 is
disabled. STIxy1 is disabled but its STOVxy1 is enabled, and therefore STOVxy1 is
generated due to STIxy0. In example 4 additionally the corresponding STOVxy0 is
enabled, so STOVxy0 and STOVxy1 are both generated due to STIxy0.
In example 5 additionally the STIxy1 is enabled with the result that STOVxy0 is only
generated due to STIxy0 and STOVxy1 is only generated due to STIxy1.
Compared to the previous example STOVxy0 is disabled in example 6, so STOVxy0 is
not generated and STOVxy1 is only generated for STIxy1 but not for STIxy0.
1)
In order to enable the STI interrupts the input of the corresponding CDA register has to be enabled. This is also
valid if only a synchronous write access is wanted. The enabling of the output alone does not effect an STI
interrupt.
In order to enable the STOV interrupts the output of the corresponding CDA register has to be enabled. This
2)
is also valid if only a synchronous read access is wanted. The enabling of the input alone does not effect an
interrupt.
Data Sheet
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PEF 82912/82913
Functional Description
•
Table 9
Examples for Synchronous Transfer Interrupts
Enabled Interrupts
(Register MSTI)
Generated Interrupts
(Register STI)
STI
xy0
STOV
-
STI
xy0
-
STOV
-
Example 1
Example 2
Example 3
Example 4
Example 5
-
xy0
-
xy0
xy1
xy0
xy0
xy1
xy0
xy0 ; xy1
xy0 ; xy1
xy0 ; xy1
xy0 ; xy1
xy0
xy1
xy0
xy1
xy0 ; xy1
xy0 ; xy1
xy1
xy0
xy1
-
Example 6
Example 7
xy1
xy0 ; xy1 ; xy2
xy0
xy1
xy0 ; xy2
xy1 ; xy2
Compared to example 5 in example 7 a third STOVxy2 is enabled and thus STOVxy2 is
generated additionally for both STIxy0 and STIxy1.
A STOV interrupt is not generated if all stimulating STI interrupts are acknowledged.
A STIxy must be acknowledged by setting the ACKxy bit in the ASTI register two BCL
clock (for DPS=’0’) or one BCL clocks (for DPS=’1’) before the time slot which is selected
for the appropriate STIxy. The interrupt structure of the synchronous transfer is shown
in Figure 17.
Data Sheet
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2001-03-30
PEF 82912/82913
Functional Description
•.
INT
U
ST
CIC
1
U
STOV21
STOV20
STOV11
STOV10
STI21
STOV21
STOV20
ST
CIC
0
STOV11
STOV10
STI21
WOV
S
ACK21
ACK20
ACK11
ACK10
ASTI
WOV
S
STI20
STI20
MOS
1
MOS
0
STI11
STI10
STI
STI11
STI10
MSTI
MASK
ISTA
Figure 17
Interrupt Structure of the Synchronous Data Transfer
Figure 18 shows some examples based on the timeslot structure. Figure a) shows at
which point in time a STI and STOV interrupt is generated for a specific timeslot. Figure
b) is identical to example 3 above, figure c) corresponds to example 5 and figure d)
shows example 4.
Data Sheet
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Functional Description
•.
: STI interrupt generated
: STOV interrupt generated for a not acknowledged STI interrupt
a) Interrupts for data access to time slot 0 (B1 after reset), MSTI.STI10 and MSTI.STOV10 enabled
xy:
10
11
21
TS5
'1'
20
TS11
'1'
CDA_TDSPxy.TSS:
MSTI.STIxy:
MSTI.STOVxy:
TS0 TS1
'0'
'0'
'1'
'1'
'1'
'1'
TS11 TS0 TS1 TS2 TS3 TS4 TS5 TS6 TS7 TS8 TS9 TS10 TS11 TS0
b) Interrupts for data access to time slot 0 (B1 after reset), STOV interrupt used as flag for "last possible CDA
access"; MSTI.STI10 and MSTI.STOV20 enabled
xy:
10
11
21
TS5
'1'
20
TS11
'1'
CDA_TDSPxy.TSS:
MSTI.STIxy:
MSTI.STOVxy:
TS0 TS1
'0'
'1'
'1'
'1'
'1'
'0'
TS11 TS0 TS1 TS2 TS3 TS4 TS5 TS6 TS7 TS8 TS9 TS10 TS11 TS0
c) Interrupts for data access to time slot 0 and 1 (B1 and B2 after reset), MSTI.STI10, MSTI.STOV10,
MSTI.STI11 and MSTI.STOV11 enabled
xy:
10
11
21
TS5
'1'
20
TS11
'1'
CDA_TDSPxy.TSS:
MSTI.STIxy:
MSTI.STOVxy:
TS0 TS1
'0'
'0'
'0'
'0'
'1'
'1'
TS11 TS0 TS1 TS2 TS3 TS4 TS5 TS6 TS7 TS8 TS9 TS10 TS11 TS0
d) Interrupts for data access to time slot 0 (B1 after reset), STOV20 interrupt used as flag for "last possible CDA
access", STOV10 interrupt used as flag for "CDA access failed"; MSTI.STI10, MSTI.STOV10 and
MSTI.STOV20 enabled
xy:
10
11
21
TS5
'1'
20
TS11
'1'
CDA_TDSPxy.TSS:
MSTI.STIxy:
MSTI.STOVxy:
TS0 TS1
'0'
'0'
'1'
'1'
'1'
'0'
TS11 TS0 TS1 TS2 TS3 TS4 TS5 TS6 TS7 TS8 TS9 TS10 TS11 TS0
sti_stov.vsd
Figure 18
Examples for the Synchronous Transfer Interrupt Control with one
STIxy enabled
•
.
Data Sheet
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2001-03-30
PEF 82912/82913
Functional Description
2.3.2.2 Serial Data Strobe Signal
For time slot oriented standard devices at the IOM-2 interface, the Q-SMINTI provides
two independent data strobe signals SDS1 and SDS2.
The two strobe signals can be generated with every 8-kHz-frame and are controlled by
the registers SDS1/2_CR. By programming the TSS bits and three enable bits
(ENS_TSS, ENS_TSS+1, ENS_TSS+3) a data strobe can be generated for the IOM-2
time slots TS, TS+1 and TS+3 (bit7,6) and the combinations of them.
The data strobes for TS and TS+1 are always 8 bits long (bit7 to bit0) whereas the data
strobe for TS+3 is always 2 bits long (bit7, bit6).
•
FSC
M M
R X
M M
R X
D CI0
CI1
DD,DU
B1
B2 MON0
IC1
IC2 MON1
TS0 TS1 TS2 TS3 TS4 TS5 TS6 TS7 TS8 TS9 TS10 TS11 TS0 TS1
SDS1,2
(Example1)
SDS1,2
(Example2)
SDS1,2
(Example3)
Example 1: TSS
ENS_TSS
= '0H'
= '0'
ENS_TSS+1 = '1'
ENS_TSS+3 = '0'
Example 2: TSS
ENS_TSS
= '5H'
= '1'
ENS_TSS+1 = '1'
ENS_TSS+3 = '0'
Example 3: TSS
ENS_TSS
= '0H'
= '1'
ENS_TSS+1 = '1'
ENS_TSS+3 = '1'
strobe.vsd
Figure 19
Data Strobe Signal Generation
Data Sheet
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2001-03-30
PEF 82912/82913
Functional Description
Figure 19 shows three examples for the generation of a strobe signal. In example 1 the
SDS is active during channel B2 on IOM-2, whereas in the second example during IC2
and MON1. The third example shows a strobe signal for 2B+D channels which is used
e.g. at an IDSL (144 kbit/s) transmission.
IOM -2 Monitor Channel
2.3.3
The IOM-2 MONITOR channel is utilized for information exchange between the Q-
SMINTI and other devices in the MONITOR channel.
The MONTIOR channel data can be controlled by the bits in the MONITOR control
register (MON_CR). For the transmission of the MONITOR data one of the 3 IOM-2
channels can be selected by setting the MONITOR channel selection bits (MCS) in the
MONITOR control register (MON_CR).
The DPS bit in the same register selects between an output on DU or DD respectively
and with EN_MON the MONITOR data can be enabled/disabled. The default value is
MONITOR channel 0 (MON0) enabled and transmission on DD.
The MONITOR channel of the Q-SMINTI can be used in the following applications
(refer also to Figure 4 and Figure 5):
• As a master device the Q-SMINTI can program and control other devices (e.g. PSB
2161) attached to the IOM-2, which therefore, do not need a microcontroller
interface.
• As a slave device the Q-SMINTI is programmed and controlled from a master
device on IOM-2 (e.g. UTAH). This is used in applications where no microcontroller
is connected directly to the Q-SMINTI.
The MONITOR channel operates according to the IOM-2 Reference Guide [13].
Note: In contrast to the INTC-Q, the Q-SMINTI does neither issue nor react on Monitor
commands (MON0,1,2,8). Instead, the Q-SMINTI operated in IOM-2 slave
mode must be programmed via new MONITOR channel concept (see
Chapter 2.3.3.4), which provides full register access. The Monitor time out
procedure is available. Reporting of the Q-SMINTI is performed via interrupts.
2.3.3.1 Handshake Procedure
The MONITOR channel operates on an asynchronous basis. While data transfers on the
bus take place synchronized to frame sync, the flow of data is controlled by a handshake
procedure using the MONITOR Channel Receive (MR) and MONITOR Channel
Transmit (MX) bits. Data is placed onto the MONITOR channel and the MX bit is
activated. This data will be transmitted once per 8-kHz frame until the transfer is
acknowledged via the MR bit.
Data Sheet
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PEF 82912/82913
Functional Description
The MONITOR channel protocol is described In the following section and Figure 22
shall illustrate this. The relevant control and status bits for transmission and reception
are listed in Table 10 and Table 11.
Table 10
Transmit Direction
Control/
Register
Bit
Function
Status Bit
Control
Status
MOCR
MXC
MIE
MX Bit Control
Transmit Interrupt (MDA, MAB, MER) Enable
Data Acknowledged
MOSR
MSTA
MDA
MAB
MAC
Data Abort
Transmission Active
Table 11
Receive Direction
Control/
Register
Bit
Function
Status Bit
Control
Status
MOCR
MRC
MRE
MDR
MER
MR Bit Control
Receive Interrupt (MDR) Enable
Data Received
MOSR
End of Reception
Data Sheet
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2001-03-30
PEF 82912/82913
Functional Description
•
µ
µ
P
P
Transmitter
MON
Receiver
MR
MX
FF
1
1
0
1
1
1
MIE = 1
MOX = ADR
MXC = 1
125
µ
s
FF
ADR
MDR Int.
MAC = 1
RD MOR (=ADR)
MRC = 1
ADR
0
1
0
0
0
0
MDA Int.
MOX = DATA1
DATA1
DATA1
MDR Int.
RD MOR (=DATA1)
DATA1
DATA1
0
0
1
0
MDA Int.
MOX = DATA2
DATA2
DATA2
1
0
0
0
MDR Int.
RD MOR (=DATA2)
DATA2
DATA2
0
0
1
0
MDA Int.
MXC = 0
FF
FF
1
1
0
0
MER Int.
MRC = 0
FF
FF
1
1
1
1
MAC = 0
ITD10032
®
Figure 20
MONITOR Channel Protocol (IOM -2)
Before starting a transmission, the microprocessor should verify that the transmitter is
inactive, i.e. that a possible previous transmission has been terminated. This is indicated
by a ’0’ in the MONITOR Channel Active MAC status bit.
After having written the MONITOR Data Transmit (MOX) register, the microprocessor
sets the MONITOR Transmit Control bit MXC to ’1’. This enables the MX bit to go active
(0), indicating the presence of valid MONITOR data (contents of MOX) in the
corresponding frame. As a result, the receiving device stores the MONITOR byte in its
MONITOR Receive MOR register and generates a MDR interrupt status.
Alerted by the MDR interrupt, the microprocessor reads the MONITOR Receive (MOR)
register. When it is ready to accept data (e.g. based on the value in MOR, which in a
point-to-multipoint application might be the address of the destination device), it sets the
MR control bit MRC to ’1’ to enable the receiver to store succeeding MONITOR channel
bytes and acknowledge them according to the MONITOR channel protocol.
Data Sheet
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PEF 82912/82913
Functional Description
In addition, it enables other MONITOR channel interrupts by setting MONITOR Interrupt
Enable (MIE) to ’1’.
As a result, the first MONITOR byte is acknowledged by the receiving device setting the
MR bit to ’0’. This causes a MONITOR Data Acknowledge MDA interrupt status at the
transmitter.
A new MONITOR data byte can now be written by the microprocessor in MOX. The MX
bit is still in the active (0) state. The transmitter indicates a new byte in the MONITOR
channel by returning the MX bit active after sending it once in the inactive state. As a
result, the receiver stores the MONITOR byte in MOR and generates a new MDR
interrupt status. When the microprocessor has read the MOR register, the receiver
acknowledges the data by returning the MR bit active after sending it once in the inactive
state. This in turn causes the transmitter to generate a MDA interrupt status.
This "MDA interrupt – write data – MDR interrupt – read data – MDA interrupt"
handshake is repeated as long as the transmitter has data to send. Note that the
MONITOR channel protocol imposes no maximum reaction times to the microprocessor.
When the last byte has been acknowledged by the receiver (MDA interrupt status), the
microprocessor sets the MONITOR Transmit Control bit MXC to ’0’. This enforces an
inactive (’1’) state in the MX bit. Two frames of MX inactive signifies the end of a
message. Thus, a MONITOR Channel End of Reception MER interrupt status is
generated by the receiver when the MX bit is received in the inactive state in two
consecutive frames. As a result, the microprocessor sets the MR control bit MRC to 0,
which in turn enforces an inactive state in the MR bit. This marks the end of the
transmission, making the MONITOR Channel Active MAC bit return to ’0’.
During a transmission process, it is possible for the receiver to ask a transmission to be
aborted by sending an inactive MR bit value in two consecutive frames. This is effected
by the microprocessor writing the MR control bit MRC to ’0’. An aborted transmission is
indicated by a MONITOR Channel Data Abort MAB interrupt status at the transmitter.
The MONITOR transfer protocol rules are summarized in the following section
• A pair of MX and MR in the inactive state for two or more consecutive frames indicates
an idle state or an end of transmission.
• A start of a transmission is initiated by the transmitter by setting the MXC bit to ’1’
enabling the internal MX control. The receiver acknowledges the received first byte by
setting the MR control bit to ’1’ enabling the internal MR control.
• The internal MX, MR control indicates or acknowledges a new byte in the MON slot
by toggling MX, MR from the active to the inactive state for one frame.
• Two frames with the MR-bit set to inactive indicate a receiver request for abort.
• The transmitter can delay a transmission sequence by sending the same byte
continuously. In that case the MX-bit remains active in the IOM-2 frame following the
first byte occurrence. Delaying a transmission sequence is only possible while the
receiver MR-bit and the transmitter MX-bit are active.
Data Sheet
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2001-03-30
PEF 82912/82913
Functional Description
• Since a double last-look criterion is implemented the receiver is able to receive the
MON slot data at least twice (in two consecutive frames), the receiver waits for the
acknowledge of the reception of two identical bytes in two successive frames.
• To control this handshake procedure a collision detection mechanism is implemented
in the transmitter. This is done by making a collision check per bit on the transmitted
MONITOR data and the MX bit.
• Monitor data will be transmitted repeatedly until its reception is acknowledged or the
transmission time-out timer expires.
• Two frames with the MX bit in the inactive state indicates the end of a message
(EOM).
• Transmission and reception of monitor messages can be performed simultaneously.
This feature is used by the device to send back the response before the transmission
from the controller is completed (the device does not wait for EOM from controller).
2.3.3.2 Error Treatment
In case the device does not detect identical monitor messages in two successive frames,
transmission is not aborted. Instead the device will wait until two identical bytes are
received in succession.
A transmission is aborted by the device if
• an error in the MR handshaking occurs
• a collision on the IOM-2 bus of the MONITOR data or MX bit occurs
• the transmission time-out timer expires
A reception is aborted by the device if
• an error in the MX handshaking occurs or
• an abort request from the opposite device occurs
MX/MR Treatment in Error Case
In the master mode the MX/MR bits are under control of the microcontroller through MXC
or MRC, respectively. An abort is indicated by an MAB interrupt or MER interrupt,
respectively.
In the slave mode the MX/MR bits are under control of the device. An abort is always
indicated by setting the MX/MR bit inactive for two or more IOM-2 frames. The
controller must react with EOM.
Figure 21 shows an example for an abort requested by the receiver, Figure 22 shows
an example for an abort requested by the transmitter and Figure 23 shows an example
for a successful transmission.
Data Sheet
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PEF 82912/82913
Functional Description
•
IOM -2 Frame No.
1
2
3
4
5
6
7
1
MX (DU)
EOM
0
1
MR (DD)
0
Abort Request from Receiver
mon_rec-abort.vsd
Figure 21
Monitor Channel, Transmission Abort requested by the Receiver
•
IOM -2 Frame No.
1
2
3
4
5
6
7
1
MR (DU)
EOM
0
1
MX (DD)
0
Abort Request from Transmitter
mon_tx-abort.vsd
Figure 22
Monitor Channel, Transmission Abort requested by the Transmitter
•
IOM -2 Frame No.
1
2
3
4
5
6
7
8
1
0
1
0
MR (DU)
MX (DD)
EOM
mon_norm.vsd
Figure 23
Monitor Channel, Normal End of Transmission
Data Sheet
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2001-03-30
PEF 82912/82913
Functional Description
2.3.3.3 MONITOR Channel Programming as a Master Device
The master mode is selected by default if one of the microcontroller interfaces is
selected. The monitor data is written by the microcontroller in the MOX register and
transmitted via IOM-2 DD(DU) line to the programmed/controlled device e.g. ARCOFI-
BA PSB 2161. The transfer of the commands in the MON channel is regulated by the
handshake protocol mechanism with MX, MR.
2.3.3.4 MONITOR Channel Programming as a Slave Device
MONITOR slave mode can be selected by pinstrapping the microcontroller interface pins
according to Table 4. All programming data required by the device is received in the
MONITOR time slot on the IOM-2 and is transferred to the MOR register. The transfer
of the commands in the MON channel is regulated by the handshake protocol
mechanism with MX, MR which is described in the previous Chapter 2.3.3.1.
The first byte of the MONITOR message must contain in the higher nibble the MONITOR
channel address code which is ’1000’ for the Q-SMINTI. The lower nibble distinguishes
between a programming command and an identification command.
Identification Command
In order to be able to identify unambiguously different hardware designs of the Q-
SMINTI by software, the following identification command is used:
DU 1st byte value
DU 2nd byte value
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
The Q-SMINTI responds to this identification sequence by sending a identification
sequence:
DD 1st byte value
DD 2nd byte value
1
0
0
0
0
0
0
0
0
0
DESIGN
<IDENT>
DESIGN: six bit code, specific for each device in order to identify differences in operation
(see “ID - Identification Register” on Page 164).
This identification sequence is usually done once, when the Q-SMINTI is connected for
the first time. This function is used so that the software can distinguish between different
possible hardware configurations. However this sequence is not compulsory.
Programming Sequence
The programming sequence is characterized by a ’1’ being sent in the lower nibble of the
received address code. The data structure after this first byte is equivalent to the
structure of the serial control interface described in chapter Chapter 2.1.1.
Data Sheet
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PEF 82912/82913
Functional Description
•
DU 1st byte value
DU 2nd byte value
DU 3rd byte value
1
0
0
0
0
0
0
1
Header Byte
Command/
R/W
Register Address
DU 4th byte value
Data 1
DU (nth + 3) byte value
Data n
All registers can be read back when setting the R/W bit to ’1’. The Q-SMINTI responds
by sending his IOM-2 specific address byte (81h) followed by the requested data.
Note: Application Hint:
It is not allowed to disable the MX- and MR-control in the programming device at
the same time! First, the MX-control must be disabled, then the µC has to wait for
an End of Reception before the MR-control may be disabled. Otherwise, the Q-
SMINTI does not recognize an End of Reception.
2.3.3.5 Monitor Time-Out Procedure
To prevent lock-up situations in a MONITOR transmission a time-out procedure can be
enabled by setting the time-out bit (TOUT) in the MONITOR configuration register
(MCONF). An internal timer is always started when the transmitter must wait for the reply
of the addressed device or for transmit data from the microcontroller. After 40 IOM-2
frames (5 ms) without reply the timer expires and the transmission will be aborted with
an EOM (End of Message) command by setting the MX bit to ’1’ for two consecutive
IOM-2 frames.
2.3.3.6 MONITOR Interrupt Logic
Figure 24 shows the interrupt structure of the MONITOR handler. The MONITOR Data
Receive interrupt status MDR has two enable bits, MONITOR Receive interrupt Enable
(MRE) and MR bit Control (MRC). The MONITOR channel End of Reception MER,
MONITOR channel Data Acknowledged MDA and MONITOR channel Data Abort MAB
interrupt status bits have a common enable bit MONITOR Interrupt Enable MIE.
MRE set to “0” prevents the occurrence of MDR status, including when the first byte of
a packet is received. When MRE is set to “1” but MRC is set to “0”, the MDR interrupt
status is generated only for the first byte of a receive packet. When both MRE and MRC
are set to “1”, MDR is always generated and all received MONITOR bytes - marked by
a 1-to-0 transition in MX bit - are stored. Additionally, a MRC set to “1” enables the control
of the MR handshake bit according to the MONITOR channel protocol.
Data Sheet
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PEF 82912/82913
Functional Description
•
ISTA
U
MASK
U
ST
ST
CIC
1
CIC
0
WOV
S
WOV
S
MDR
MER
MRE
MOS
0
MOS
1
MIE
MDA
MAB
MOCR
MOSR
INT
Figure 24
2.3.4
MONITOR Interrupt Structure
C/I Channel Handling
The Command/Indication channel carries real-time status information between the Q-
SMINTI and another device connected to the IOM-2.
1) C/I0 channel lies in IOM-2 channel 0 and access may be arbitrated via the TIC bus
access protocol. In this case the arbitration is done in IOM-2 channel 2.
The C/I0 channel is accessed via register CIR0 (received C/I0 data from DD) and
register CIX0 (transmitted C/I0 data to DU). The C/I0 code is four bits long.
In the receive direction, the code from layer-1 is continuously monitored, with an interrupt
being generated any time a change occurs (ISTA.CIC).
C/I0 only: a new code must be found in two consecutive IOM-2 frames to be considered
valid and to trigger a C/I code change interrupt status (double last look criterion).
In the transmit direction, the code written in CIX0 is continuously transmitted in C/I0.
2) A second C/I channel (called C/I1) lies in IOM-2 channel 1 and is used to convey real
time status information of the on-chip S-transceiver or an external device. The C/I1
channel consists of four or six bits in each direction. The width can be changed from 4
bit to 6 bit by setting bit CIX1.CICW.
Data Sheet
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Functional Description
In 4-bit mode 6-bits are written whereby the higher 2 bits must be set to “1” and 6-bits
are read whereby only the 4 LSBs are used for comparison and interrupt generation (i.e.
the higher two bits are ignored).
The C/I1 channel is accessed via registers CIR1 and CIX1. The connection of CIR1 and
CIX1 to DD and DU, respectively, can be selected by setting bit CI_CR.DPS_CI1. A
change in the received C/I1 code is indicated by an interrupt status without double last
look criterion.
CIC Interrupt Logic
Figure 25 shows the CIC interrupt structure.
The two corresponding status bits CIC0 and CIC1 are read in CIR0 register. CIC1 can
be individually disabled by clearing the enable bit CI1E in the CIX1 register. In this case
the occurrence of a code change in CIR1 will not be displayed by CIC1 until the
corresponding enable bit has been set to one.
Bits CIC0 and CIC1 are cleared by a read of CIR0.
An interrupt status is indicated every time a valid new code is loaded in CIR0 or CIR1.
The CIR0 is buffered with a FIFO size of two. If a second code change occurs in the
received C/I channel 0 before the first one has been read, immediately after reading of
CIR0 a new interrupt will be generated and the new code will be stored in CIR0. If several
consecutive codes are detected, only the first and the last code are obtained at the first
and second register read, respectively.
For CIR1 no FIFO is available. The actual code of the received C/I channel 1 is always
stored in CIR1.
•
MASK
U
ISTA
U
ST
CIC
0
ST
CIC
1
CIC0
CIC1
CIR0
CI1E
CIX1
WOV
S
WOV
S
MOS
0
MOS
1
INT
Figure 25
CIC Interrupt Structure
Data Sheet
51
2001-03-30
PEF 82912/82913
Functional Description
2.3.5
D-Channel Access Control
The upstream D-channel is arbitrated between the S-bus and external HDLC controllers
via the TIC bus (S/G, BAC, TBA bits) according to the IOM-2 Reference Guide1).
Further to the implementation in the INTC-Q it is possible, to set the priority (8 or 10) of
all HDLC-controllers connected to IOM-2, which is particularly useful for use of the Q-
SMINTI together with the UTAH.
2.3.5.1 Application Examples for D-Channel Access Control
Figure 26 and Figure 27 show different scenarios for the local D-channel arbitration
between the S-bus and the microcontroller.
•
Q-SMINTI
BAC
E-Bit
Arbitr.
S
U
D
D
S/G
Prio
IOM-2 i/f
µP - i/f
•µC has access to BAC-Bit
and S/G-bit on IOM-2.
•Access to TBA generally not
required if only one local D-channel
source.
BAC
C
HDLC
S/G
µC
e.g. UTAH;
MPC860
IOM-2
Figure 26
D-Channel Arbitration: µC with HDLC and Direct Access to TIC Bus
1)
The A/B-bit is not supported by the U-transceiver
Data Sheet
52
2001-03-30
PEF 82912/82913
Functional Description
•
Q-SMINTI
BAC
S/G
E-Bit
Arbitr.
S
U
BAC
D
D
S/G
CIX0
Prio
C/I Channel
Handler
CIR0
IOM-2 i/f
µP - i/f
.
µC has access to BAC, TBA-Bit
and S/G-bit
•
C
via TIC-Bus Handler
•µC must poll S/G bit until S/G=0,
then transmit D-channel
HDLC
µC
e.g.
MC68302
IOM-2
Figure 27
D-Channel Arbitration: µC with HDLC and no Access to TIC Bus
2.3.5.2 TIC Bus Handling
The TIC bus is implemented to organize the access to the C/I0-channel and to the D-
channel from up to 7 D-channels HDLC controllers. The arbitration mechanism must be
activated by setting MODEH.DIM2-0=00x.
The arbitration mechanism is implemented in the last octet in IOM-2 channel 2 of the
IOM-2 interface (see Figure 28). An access request to the TIC bus may either be
generated by software (µC access to the C/I0-channel via CIX0 register) or by an
external D-channel HDLC controller (transmission of an HDLC frame in the D-channel).
A software access request to the bus is effected by setting the BAC bit in register CIX0
to ’1’ (resulting in BAC = ’0’ on IOM-2).
In the case of an access request by the Q-SMINTI, the Bus Accessed-bit BAC (bit 5 of
last octet of CH2 on DU, see Figure 28) is checked for the status "bus free“, which is
indicated by a logical ’1’. If the bus is free, the Q-SMINTI transmits its individual TIC bus
address TAD programmed in the CIX0 register (CIX0.TBA2-0). While being transmitted
the TIC bus address TAD is compared bit by bit with the value read back on DU. If a sent
bit set to ’1’ is read back as ’0’ because of the access of an external device with a lower
TAD, the Q-SMINTI withdraws immediately from the TIC bus, i.e. the remaining TAD
bits are not transmitted. The TIC bus is occupied by the device which sends and reads
back its address error-free. If more than one device attempt to seize the bus
simultaneously, the one with the lowest address values wins. This one will set BAC=0 on
TIC bus and starts D-channel transmission in the same frame.
Data Sheet
53
2001-03-30
PEF 82912/82913
Functional Description
•
MR
MX
MR
MX
TAD
BAC
B1
B2
MON0
D
CI0
IC1
IC2
MON1
CI1
DU
BAC
TAD
1
ITD02575.vsd
2
0
TIC-BUS Address (TAD 2 - 0)
Bus Accessed ("1" no TIC-BUS Access)
Figure 28
Structure of Last Octet of Ch2 on DU
When the TIC bus is seized by the Q-SMINTI, the bus is identified to other devices as
occupied via the DU Ch2 Bus Accessed-bit state ’0’ until the access request is
withdrawn. After a successful bus access, the Q-SMINTI is automatically set into a
lower priority class, that is, a new bus access cannot be performed until the status "bus
free" is indicated in two successive frames.
If none of the devices connected to the IOM-2 interface request access to the D and C/
I0 channels, the TIC bus address 7 will be present. The device with this address will
therefore have access, by default, to the D and C/I0 channels.
Note: Bit BAC (CIX0 register) should be reset by the µC when access is no more
requested, to grant other devices access to the D and C/I0 channels.
2.3.5.3 Stop/Go Bit Handling
The availability of the DU D channel is indicated in bit 5 "Stop/Go" (S/G) of the last octet
in DD channel 2 (Figure 29). The arbitration mechanism must be activated by setting
MODEH.DIM2-0=0x1.
S/G = 1 : stop
S/G = 0 : go
The Stop/Go bit is available to other layer-2 devices connected to the IOM-2 interface
to determine if they can access the D channel in upstream direction.
Data Sheet
54
2001-03-30
PEF 82912/82913
Functional Description
•
MR
MX
MR
MX
S/G
A/B
MON
0
B1
B2
D
CI0
IC1
IC2
MON1
CI1
DD
S/G A/B
ITD09693.vsd
Stop/Go
Available/Blocked
Figure 29
Structure of Last Octet of Ch2 on DD
2.3.5.4 D-Channel Arbitration
In intelligent NT applications (selected via register S_MODE.MODE2-0) the Q-SMINTI
has to share the upstream D-channel with one or more D-channel controllers on the
IOM-2 interface and with all connected TEs on the S interface.
The S-transceiver incorporates an elaborate state machine for D-channel priority
handling on IOM-2 (Chapter 2.3.5.5). For the access to the D-channel a similar
arbitration mechanism as on the S interface (writing D-bits, reading back E-bits) is
performed for all D-channel sources on IOM-2. Due to this an equal and fair access is
guaranteed for all D-channel sources on both the S interface and the IOM-2 interface.
The access to the upstream D-channel is handled via the S/G bit for the HDLC
controllers and via E-bit for all connected terminals on S (E-bits are inverted to block the
terminals on S). Furthermore, if more than one HDLC source is requesting D-channel
access on IOM-2 the TIC bus mechanism is used (see Chapter 2.3.5.2).
The arbiter permanently counts the “1s” in the upstream D-channel on IOM-2. If the
necessary number of “1s” is counted and an HDLC controller on IOM-2 requests
upstream D-channel access (BAC bit is set to 0), the arbiter allows this D-channel
controller immediate access and blocks other TEs on S (E-bits are inverted). Similar as
on the S-interface the priority for D-channel access on IOM-2 can be configured to 8 or
10 (S_CMD.DPRIO).
The configuration settings of the Q-SMINTI in intelligent NT applications are
summarized in Table 12.
Data Sheet
55
2001-03-30
PEF 82912/82913
Functional Description
•
Table 12
Q-SMINTI Configuration Settings in Intelligent NT Applications
Functional Configuration
Configuration Setting
Block
Description
Layer 1
Select Intelligent
NT mode
S-Transceiver Mode Register:
S_MODE.MODE0 = 0 (NT state machine)
or
S_MODE.MODE0 = 1 (LT-S state machine)
S_MODE.MODE1 = 1
S_MODE.MODE2 = 1
Layer 2
Enable S/G bit and
TIC bus evaluation
D-channel Mode Register:
MODEH.DIM2-0 = 001
Note: For mode selection in the S_MODE register the MODE1/2 bits are used to select
intelligent NT mode, MODE0 selects NT or LT-S state machine.
With the configuration settings shown above the Q-SMINTI in intelligent NT
applications provides for equal access to the D-channel for terminals connected to the
S-interface and for D-channel sources on IOM-2.
2.3.5.5 State Machine of the D-Channel Arbiter
Figure 30 gives a simplified view of the state machine of the D-channel arbiter. CNT is
the number of ’1’ on the IOM-2 D-channel and BAC corresponds to the BAC-bit on
IOM-2. The number n depends on configuration settings (selected priority 8 or 10) and
the condition of the previous transmission, i.e. if an abort was seen (n = 8 or 10,
respectively) or if the last transmission was successful (n = 9 or 11, respectively).
Data Sheet
56
2001-03-30
PEF 82912/82913
Functional Description
•
RST=0, A/B=0, Mode=0xx
IN
BAC
State
S/G
DCI
E
OUT
BAC = 1 & DCI = 0
READY
(CNT
≥ 2 & D=0)
CNT ≥ 6
& [BAC = 1 or (BAC = 0 & CNT
< n)]
S/G = 1
E = D 1)2)
(BAC=1 & DCI=0)
BAC = d.c. DCI = d.c.
LOCAL ACCESS
Transmit / Stop Flag
DCI=1)
(BAC=0 or
& CNT
BAC = d.c. DCI = 0
S ACCESS
≥
n
S/G = 0
E = D
CNT = 6
S/G = 1
E = D1)
BAC = 0 or DCI = 1
LOCAL ACCESS
Wait for Start Flag
1) Setting DCI = 1 causes E = D
2) Setting A/B = 0 causes E = D
S/G = 0
E = D
D-Channel_Arbitration.vsd
Figure 30
State Machine of the D-Channel Arbiter (Simplified View)1)
Table 13 lists the major differences of the D-channel arbiter´s state machine between Q-
SMINTI and INTC-Q [12]
•:
Table 13
Major Differences D-Channel Arbiter INTC-Q and Q-SMINTI
INTC-Q
Q-SMINTI
Automatically entered from Not available, initial state is
State ’IDLE’
(S/G=0, E=D)
state ’READY’ or
’READY’ (S/G=1, E=D)
’S ACCESS’ after CNT=n
BAC-bit
Ignored
Local HDLC must tie BAC =
’0’ to enter state ’LOCAL
ACCESS’
D-channel inhibit
Not possible
S-MODE.DCH_INH
Alternative to BAC-bit to
enter state ’LOCAL
ACCESS’
1)
If the S-transceiver is reset by SRES.RES_S = ’1’ or disabled by S_CONF0.DIS_TR = ’1’, then the D-channel
arbiter is in state Ready (S/G = ’1’), too. The S/G evaluation of the HDLC has to be disabled in this case;
otherwise, the HDLC is not able to send data.
Data Sheet
57
2001-03-30
PEF 82912/82913
Functional Description
1. Local D-Channel Controller Transmits Upstream
In the initial state (’Ready’ state) neither the local D-channel sources nor any of the
terminals connected to the S-bus transmit in the D-channel.
The Q-SMINTI S-transceiver thus receives BAC = “1” (IOM-2 DU line) and transmits
S/G = “1” (IOM-2 DD line). The access will then be established according to the
following procedure:
• Local D-channel source verifies that BAC bit is set to ONE (currently no bus access).
• Local D-channel source issues TIC bus address and verifies that no controller with
higher priority requests transmission (TIC bus access must always be performed even
if no other D-channel sources are connected to IOM-2).
• Local D-channel source issues BAC = “0” to block other sources on IOM-2 and to
announce D-channel access.
• Q-SMINTI S-transceiver pulls S/G bit to ZERO (’Local Access’ state) as soon as
CNT ≥ n (see note) to allow sending D-channel data from the entitled source.
Q-SMINTI S-transceiver transmits inverted echo channel (E bits) on the S-bus to
block all connected S-bus terminals (E = D).
• Local D-channel source commences with D data transmission on IOM-2 as long as
it receives S/G = “0”.
• After D-channel data transmission is completed the controller sets the BAC bit to
ONE.
• Q-SMINTI S-transceiver transmits non-inverted echo (E = D).
• Q-SMINTI S-transceiver pulls S/G bit to ONE (’Ready’ state) to block the D-channel
controller on IOM-2.
Note: If right after D-data transmission the D-channel arbiter goes to state ’Ready’ and
the local D-channel source wants to transmit again, then it may happen that the
leading ’0’ of the start flag is written into the D-channel before the D-channel
source recognizes that the S/G bit is pulled to ’1’ and stops transmission. In order
to prevent unintended transitions to state ’S-Access’, the additional condition CNT
≥ 2 is introduced. As soon as CNT ≥ n, the S/G bit is set to ’0’ and the D-channel
source may start transmission again (if TIC bus is occupied). This allows an equal
access for D-channel sources on IOM-2 and on the S interface.
2. Terminal Transmits D-Channel Data Upstream
The initial state is identical to that described in the last paragraph. When one of the
connected S-bus terminals needs to transmit in the D-channel, access is established
according to the following procedure:
• S-transceiver recognizes that the D-channel on the S-bus is active via D = ’0’.
• S-transceiver transfers S-bus D-channel data transparently through to the upstream
IOM-2 bus.
Data Sheet
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2001-03-30
PEF 82912/82913
Functional Description
2.3.6
Activation/Deactivation of IOM®-2 Interface
The deactivation procedure of the IOM-2 interface is shown in Figure 31. After
detecting the code DI (Deactivation Indication) the Q-SMINTI responds by transmitting
DC (Deactivation Confirmation) during subsequent frames and stops the timing signals
after the fourth frame. The clocks stop at the end of the C/I-code in IOM-2 channel 0.
•
a)
IOM R -2 Interface
deactivated
FSC
DI
DI
DI
DI
DI
DI
DIN
DR
DR
DC
DC
DC
DC
DOUT
Detail see Fig.b
b)
IOM R -2 Interface
deactivated
DCL
DIN
D
C / Ι
C / Ι
C / Ι
C / Ι
ITD10292
Figure 31
Deactivation of the IOM®-2 Clocks
Conditions for Power-Down
If none of the following conditions is true, the IOM-2 interface can be switched off,
reducing power consumption to a minimum.
• S-transceiver is not in state ’Deactivated’
• Signal INFO0 on the S-interface
• Uk0-transceiver is not in state ’Deactivated’
• Pin DU is low (either at the IOM-2 interface or via IOM_CR.SPU)
• External pin EAW External Awake is low
• Bit MODE 1.CFS = ’0’
• Stop on the correct place in the IOM-2 frame. DCL must be low during power down
(stop on falling edge of DCL) (see Figure 31).
Data Sheet
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PEF 82912/82913
Functional Description
A deactivated IOM-2 can be reactivated by one of the following methods:
• Pulling pin DU line low:
– directly at the IOM-2 interface
– via the µP interface with "Software Power Up" (IOM_CR:SPU bit)
• Pulling pin EAW ‘External Awake‘ low
• Setting ‘Configuration Select‘ MODE1:CFS bit = ’0’
• Level detection at the S-interface
• Activation from the U-interface
2.4
U-Transceiver
The state machine of the U-Transceiver is based on the NT state machine in the PEB /
PEF 8191 documentation [12].
Note: ’Self test request’ and ’Self test passed’ are not executed by the U-transceiver
The U-transceiver is configured and controlled via the registers described in
Chapter 4.11. The U-transceiver is always in IOM-2 channel 0. It is possible to select
between a state machine that simplifies programming (see Chapter 2.4.10.6) and the
state machine as known from the PEB / PEF 8091 (see Chapter 2.4.10.2).
2.4.1
2B1Q Frame Structure
Transmission on the U2B1Q-interface is performed at a rate of 80 kbaud. The code used
is reducing two bits to one quaternary symbol (2B1Q).
Data is grouped together into U-superframes of 12 ms each. Each superframe consists
of eight basic frames which begin with a synchronization word and contain 222 bits of
information. The first basic frame of a superframe starts with an inverted synchword
(ISW) compared to the other basic frames (SW). The structure of one U-superframe is
illustrated in Figure 32 and Figure 33.
ISW 1. Basic Frame SW
2. Basic Frame . . .
SW
8. Basic Frame
<---12 ms--->
Figure 32
U-Superframe Structure
Data Sheet
60
2001-03-30
PEF 82912/82913
Functional Description
•
•
(I) SW
12 × 2B + D
M1 – M6
(Inverted) Synch Word
18 Bit (9 Quat)
User Data
216 Bits (108 Quat)
Maintenance Data
6 Bits (3 Quat)
<---1,5 ms--->
Figure 33
U-Basic Frame Structure
Out of the 222 information bits 216 contain 2B + D data from 12 IOM®-frames, the
remaining 6 bits are used to transmit maintenance information. Thus 48 maintenance
bits are available per U-superframe. They are used to transmit two EOC-messages (24
bit), 12 Maintenance (overhead) bits and one checksum (12 bit).
•
Table 14
U-Superframe Format
Fram- 2B + Overhead Bits (M1 – M6)
ing
1 – 9
D
Quat
Position
s
10 – 118 s 118 m 119 s 119 m 120 s 120 m
117
Bit
Position
s
1 – 18 19 – 235
234
236
237
238
239
240
Super
Basic
Sync
Frame # Frame # Word
2B + M1
D
M2
M3
M4
M5
1
M6
1
1
1
2
3
4
5
6
ISW
SW
SW
SW
SW
SW
2B + EOC EOC EOC ACT/
a1 a2 a3 ACT
2B + EOC EOC EOC DEA /
dm i1 i2 PS1
2B + EOC EOC EOC SCO/
i3 i4 i5 PS2
2B + EOC EOC EOC 1/ NTM CRC3 CRC4
i6 i7 i8
2B + EOC EOC EOC 1/ CSO CRC5 CRC6
a1 a2 a3
2B + EOC EOC EOC
dm i1 i2
D
1
FEBE
D
CRC1 CRC2
D
D
D
1
CRC7 CRC8
D
Data Sheet
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PEF 82912/82913
Functional Description
Table 14
U-Superframe Format (cont’d)
Fram- 2B + Overhead Bits (M1 – M6)
ing
D
7
8
SW
2B + EOC EOC EOC UOA /
i3 i4 i5 SAI
2B + EOC EOC EOC AIB /
i6 i7 i8 NIB
CRC9 CRC
10
D
SW
CRC CRC
D
11
12
2,3…
LT- to NT dir. > /
< NT- to LT dir.
– ISW Inverted Synchronization Word (quad):
– SW Synchronization Word (quad):
– CRC Cyclic Redundancy Check
– 3 – 3 + 3 + 3 + 3 – 3 + 3 – 3 – 3
+ 3 + 3 – 3 – 3 – 3 + 3 – 3 + 3 + 3
– EOC Embedded Operation Channel
a
= address bit
d/m = data / message bit
= information (data / message)
i
– ACT Activation bit
– DEA Deactivation bit
– CSO Cold Start Only
– UOA U-Only Activation
– SAI S-Activity Indicator
– FEBE Far-end Block Error
– PS1 Power Status Primary Source
ACT = (1) –> Layer 2 ready for communication
DEA = (0) –> LT informs NT that it will turn off
CSO = (1) –> NT-activation with cold start only
UOA = (0) –> U-only activated
SAI = (0) –> S-interface is deactivated
FEBE = (0) –> Far-end block error occurred
PS1 = (1) –> Primary power supply ok
– PS2 Power Status Secondary Source PS2 = (1) –> Secondary power supply ok
– NTM NT-Test Mode
NTM = (0) –> NT busy in test mode
– AIB Alarm Indication Bit
– NIB Network Indication Bit
– SCO Start on Command only bit
AIB = (0) –> Interruption (according to ANSI)
NIB = (1) –> no function (reserved for network use)
– 1
(currently not defined by ANSI/ETSI)
can be accessed by the system interface for proprietary use
The principle signal flow is depicted in Figure 34 and Figure 35. The data is first
grouped in bits that are covered by the CRC and bits that are not. After the CRC
generation the bits are arranged in the proper sequence according to the 2B1Q frame
format, encoded and finally transmitted.
In receive direction the data is first decoded, descrambled, deframed and handed over
for further processing.
Data Sheet
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PEF 82912/82913
Functional Description
•
U2B1Q-Fram er
(M-bit handling acc. to ETR080)
Tone/Pulse
Patterns
M
U
X
Sync/Inv. Sync
M1,2,3 (EOC)
2B+D, M4
M
U
X
M5,6 except CRC
2B1Q Encoding
Scrambler
M
U
X
M4
M
CRC Generation
U
X
2B+D
Control
uframer.emf
Figure 34
U2B1Q Framer - Data Flow Scheme
•
M1,2,3 (EOC)
U2B1Q-Deframer
(M-bit handling acc. to ETR080)
M5,6 except CRC
D
E
CRC Check
D
E
M
U
X
Descrambler
M
U
X
2B1Q Decoding
M4
D
E
M
U
X
Sync/Inv. Sync
2B+D
Control
udeframer.emf
Figure 35
U2B1Q Deframer - Data Flow Scheme
Data Sheet
63
2001-03-30
PEF 82912/82913
Functional Description
2.4.2
Maintenance Channel
The last three symbols (6 bits) of each basic frame are used as M (Maintenance)-
channel for the exchange of operation and maintenance data between the network and
the NT. Approved M-bit data is first processed and then reported to the µC by interrupt
requests. The verification method is programmed in the MFILT register (see
Chapter 4.11.2).
EOC-data is inserted into the U-frame at the positions M1, M2 and M3 (Table 14)
thereby permitting the transmission of two complete EOC-messages (2× 12 bits) within
one U-superframe (see Chapter 2.4.3).
M4 bits are used to communicate status and maintenance functions between the
transceivers. The meaning of a bit position is dependent upon the direction of
transmission (upstream/downstream) and the operation mode (NT/LT). See Table 14 for
the different meaning of the M4 bits. For details see Chapter 2.4.4.
The M5 and M6 bits contain the FEBE bit and the CRC bits. For details see
Chapter 2.4.6.
2.4.2.1 Reporting to the µC Interface
The maintenance channel information is exchanged with external devices via the
appropriate registers. Received maintenance channel information is reported to the µC
by an interrupt.
2.4.2.2 Access from the µC Interface
The maintenance data to be transmitted can be programmed by writing the internal
EOCW/M4W/M56W registers.
2.4.2.3 Availability of Maintenance Channel Information
Transmission of the Maintenance channel data is only possible if a superframe is
transmitted and the M-bits are transparent (M-Bits are “normal” in Table 24). In other
states all maintenance bits are clamped to high.
Reception of the Maintenance channel data is enabled by the state machine in the
following states:
Table 15
Enabling the Maintenance Channel (Receive Direction)
Synchronized1
Synchronized2
Wait for ACT
Transparent
Error S/T
Data Sheet
64
2001-03-30
PEF 82912/82913
Functional Description
Table 15
Enabling the Maintenance Channel (Receive Direction)
Pend. Deac. S/T
Pend. Deac. U
Analog Loop Back
Reporting and execution of maintenance information is only sensible if the Q-SMINTI
is synchronous. Filters are provided to avoid meaningless reporting.
Reset values are applied to the maintenance bits before the state machine enters one of
the states in Table 15.
2.4.2.4 M-Bit Register Access Timing
Since the maintenance data must be put into and read from the U-frame in time there is
the need for synchronization if M-Bit data is exchanged via the µC-interface. Below the
timing is given for the access to the M-Bit read and write registers.
The write access timing is depicted in Figure 36. Timing references for a write access
are the 6 ms and 12 ms interrupts which are accommodated in the ISTAU register. An
active 6 ms interrupt signals that from this event there is a time frame of 3 basic frames
duration (4.5 ms) for the write access to the EOCW register.
The 12 ms interrupt serves as time reference for the write access to the M4W and M56W
registers. From the point of time the 12 ms interrupt goes active there is a time window
of 7 basic frames to overwrite the register values. The programmed data will be sent out
with the next U-superframe.
Note that the point of time when the 6 ms and 12 ms interrupts are generated within basic
frame #1 and #5 is not fixed and may vary.
Data Sheet
65
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PEF 82912/82913
Functional Description
•
read access to
ISTAU clears 6ms
interrupt
6ms Interrupt
Frame No.
#1
#4
#5
#8
#1
µC write access
time to EOCW
µC write access
time to EOCW
3 Base Frames
(4.5ms)
max. 3 Base Frames
(4.5ms)
1. EOC
2. EOC
read access to
ISTAU clears 12ms
interrupt
12ms Interrupt
Frame No.
#1
#8
#1
µC write access time to M4W, M56W
max. 7 Base Frames
(10.5ms)
wr_acs_timg_QSMINT.emf
Figure 36
Write Access Timing
The read access timing is illustrated in Figure 37. An interrupt source of the same
name is associated with each read register (EOCR, M4R, M56R). An EOC interrupt
indicates that the value of the EOCR register has been changed and updated. So do the
M4 and M56 interrupts. Note that unlike the 6 ms and 12 ms interrupts the ’read’
interrupts are only generated on change of the register value and do not occur
periodically.
The EOC, M4 and M56 interrupt bits are all accommodated in the ISTAU register.
Data Sheet
66
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PEF 82912/82913
Functional Description
•
set active in frame
#1 or #5 if value has
been updated
read access to
ISTAU clears EOC
interrupt
EOC Interrupt
Frame No.
#1
#4
#5
#8
#1
µC read access time
to EOCR
µC read access time
to EOCR
3 Base Frames
(4.5ms)
max. 3 Base Frames
(4.5ms)
1. EOC
2. EOC
read access to
ISTAU clears M4
interrupt
set active in frame
#1 if value has been
updated
M4 Interrupt
Frame No.
#1
#8
#1
µC read access time to M4R
max. 7 Base Frames
(10.5ms)
read access to
ISTAU clears M56
interrupt
set active in frame
#1 if value has been
updated
M56 Interrupt
Frame No.
#1
#8
#1
µC read access time to M56R
max. 7 Base Frames
(10.5ms)
wr_acs_timg_QSMINT.emf
Figure 37
2.4.3
Read Access Timing
Processing of the EOC
2.4.3.1 EOC Commands
The EOC command consists of an address field, a data/message indicator and an eight-
bit information field. With the address field the destination of the transmitted message/
data is defined. Addresses are defined for the NT, 6 repeater stations and broadcasting.
Data Sheet
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PEF 82912/82913
Functional Description
The data/message indicator needs to be set to (1) to indicate that the information field
contains a message. If set to (0), numerical data is transferred to the NT. Currently no
numerical data transfer to or from the NT is required.
•
Table 16
EOC
Coding of EOC-Commands
Address
Field
Data/
Message
Indicator
Information
Message
O (rigin)
D (estination)
a1a2a3
0 0 0
111
d/m
i1 i2 i3 i4 i5 i6 i7 i8
LT
NT
x
x
x
NT
Broadcast
0 01
1 10
Repeater stations
No. 1 – No. 6
0
1
Data
Message
1
1
1
1
1
1
1
1
0 1 0 1 0 0 0 0
0 1 0 1 0 0 0 1
0 1 0 1 0 0 1 0
0 1 0 1 0 0 1 1
0 1 0 1 0 1 0 0
1 1 1 1 1 1 1 1
0 0 0 0 0 0 0 0
1 0 1 0 1 0 1 0
O
D
LBBD
LB1
LB2
RCC
NCC
RTN
H
O
D
O
D
O
D
O
D
O
D
D/O
D
O/D
O
UTC
•
Table 17
Usage of Supported EOC-Commands
Function
Hex-
code
i1-i8 D
U
00
H
H
Hold. Provokes no change. The device issues Hold if no NT or
broadcast address is used or if the d/m indicator is set to (0).
50
LBBD
Close complete loop-back (B1, B2, D). If this command is
detected in NT EOC auto mode the C/I-code ARL is issued by
the Q-SMINTI U-transceiver.
Data Sheet
68
2001-03-30
PEF 82912/82913
Functional Description
Table 17
Usage of Supported EOC-Commands(cont’d)
Hex-
code
Function
i1-i8 D
U
51
52
53
LB1
Closes B1 loop-back in NT. All B1-channel data will be
looped back within the Q-SMINTI U-transceiver. The bits LB1
and U/IOM are set in the register LOOP.
LB2
Closes B2 loop-back in NT. All B2-channel data will be
looped back within the Q-SMINTI U-transceiver. The bits LB2
and U/IOM are set in the register LOOP.
Request corrupt CRC. Upon receipt the Q-SMINTI transmits
corrupted (= inverted) CRCs upstream. This allows to test the
near end block error counter on the LT-side. The far end block
error counter at the Q-SMINTI-side is stopped and Q-
SMINTI-error indications are retained.
RCC
54
NCC
RTN
Notify of corrupt CRC. Upon receipt of NCC the Q-SMINTI-
block error counters (near-end only) are disabled and error
indications are retained. This prevents wrong error counts
while corrupted CRCs are sent.
AA
FF
XX
UTC Unable to comply. Message sent instead of an
acknowledgment if an undefined EOC-command or d/m bit=0
was received by the Q-SMINTI.
Return to normal. With this command all previously sent
EOC-commands will be released. The EOCW register is reset
to its initial state (FFH).
ACK Acknowledge. If a defined and correctly addressed EOC-
command was received by the Q-SMINTI, the Q-SMINTI
replies by echoing back the received command.
2.4.3.2 EOC Processor
The on-chip EOC-processor is responsible for the correct insertion and extraction of
EOC-data on the U-interface. The EOC-processor can be programmed either to auto
mode or to transparent modes (see Chapter 2.4.3.3).
Figure 38 shows the registers and pins that are involved when EOC data is transmitted
and received.
Data Sheet
69
2001-03-30
PEF 82912/82913
Functional Description
•
U Receive Superframe
EOC Message Filtering
MFILT.EOC
Last Verified EOC Message
EOCR Register
EOC
Processor
Interrupt
Controller
Echo
INT
eoc_rx.emf
Figure 38
EOC Message Reception
•
U-Rx Frame
EOC
Processor
µC
EOC AUTO= '1'
Enable
EOCW
EOC Command/ Message
every 6 msec
U Transmit Superframe
eoc_tx.emf
Figure 39
EOC Command/Message Transmission
Data Sheet
70
2001-03-30
PEF 82912/82913
Functional Description
2.4.3.3 EOC Operating Modes
The EOC operating modes are programmable in the MFILT register (see
Chapter 4.11.2)
EOC Auto Mode
– Acknowledgement: All received EOC-frames are echoed back to the exchange
immediately without triple-last-look. If an address other than (000)B or (111)B is
received, a HOLD message with address (000)B is returned. However there is an
exception: The Q-SMINTI will send a ’UTC’ after three consecutive receptions of d/
m = 0 or after an undefined command.
– Latching: All detected EOC-commands, i.e. LBBD, RCC etc., are latched. Multiple
subsequent valid EOC-commands are executed in parallel, as long as they are not
disabled with the EOC ’RTN’ command or a deactivation.
– Reporting: With the triple-last-look criterion fulfilled the new EOC-command will be
reported by an interrupt, independently of the address used and the status of the d/m
indicator. The triple last look criterion implies that the new verified message is different
to the last TLL-verified message.
– Execution: The EOC-commands listed in Table 16 will be executed automatically by
the U-transceiver if they were addressed correctly (000B or 111B) and the d/m bit was
set to message (1). The execution of a command is performed only after the “triple-
last-look” criterion is met.
EOC Transparent Mode 6 ms
– Acknowledgement: There is no automatic acknowledgement in transparent mode.
Therefore the external µC has to perform the EOC-Procedure. 2 msec must be
available for the report and the subsequent access of the transmit EOC data of the
next outgoing EOC-frame.
– Latching: No latching is performed due to no execution.
– Reporting: The received EOC-frame is reported to the µC by an interrupt every 6 ms.
Verification, acknowledgment and execution of the received command have to be
initiated by an external controller. The µC can program back all defined test functions
(close/open loops, send corrupted CRCs). In the transmit direction, the last written
EOC-code from the µC is used.
– Execution: No automatic execution in transparent modes. The appropriate actions
can be programmed by the µC.
Data Sheet
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2001-03-30
PEF 82912/82913
Functional Description
Transparent mode with ’On Change bit’ active
– Acknowledgment: There is no automatic acknowledgement in transparent mode.
For details see above.
– Latching: No latching is performed due to no execution.
– Reporting: This mode is almost identical to the Transparent Mode 6 ms. But a report
to the µC by an interrupt takes place only, if a change in the EOC message has been
detected.
– Execution: No automatic execution in transparent modes. The appropriate actions
can be programmed by the µC.
Transparent mode with TLL active
– Acknowledgement: There is no automatic acknowledgment in transparent mode.
For details see above.
– Latching: No latching is performed due to no execution.
– Reporting: This mode is almost identical to the Transparent Mode 6 ms. But a report
to the µC by an interrupt takes place only, if the new EOC command has been
detected in at least three consecutive EOC messages.
– Execution: No automatic execution in transparent modes. The appropriate actions
can be programmed by the µC.
2.4.3.4 Examples for different EOC modes
General
In the following examples some letters like A,B,C are used to symbolize EOC command.
There are also particular EOC commands mentioned which indicate special system
behavior (e.g. UTC, H). The examples are shown in tables.
Data Sheet
72
2001-03-30
PEF 82912/82913
Functional Description
EOC Automode
Table 18
EOC Auto Mode
remarks
input from µC
EOC TX
Access to EOCW register has direct impact on EOC TX.
A A A B A A A H H H D D A D D
EOC RX
A A A B A A A C C C D D D D A D D D
report to µC
A
C
D
D
• A, B: EOC commands with correct address, d/m bit = 1 and defined command.
• C: EOC command with wrong address. Immediately acknowledged with H.
• D: EOC command which is not defined or d/m bit = 0. Acknowledgement after TLL with
UTC.
Data Sheet
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PEF 82912/82913
Functional Description
Transparent mode 6 ms)
Table 19
Transparent mode 6 ms
remarks
input from µC
EOC TX
A
A
C
C
B
B
C
C
C
D
D
B
B
A
A
A
A
B
B
A
C
C
B
A
A
B
A
A
C
A
A
C
A
A
C
B
B
D
B
B
D
B
B
EOC RX
report to µC
Transparent mode ’@change’
Table 20
Transparent mode ’@change’
remarks
input from µC
EOC TX
A
B
B
C
C
C
A
D
D
B
A
C
A
A
A
A
B
B
A
C
C
B
A
A
B
A
C
A
C
A
C
B
B
D
B
EOC RX
report to µC
Transparent mode TLL
Table 21
Transparent mode TLL
remarks
input from µC
EOC TX
A
B
C
D
A A A A B B B B B C C C C D D D D
C C C C C A A A B A A A B B B B B
EOC RX
report to µC
C
A
A
B
Data Sheet
74
2001-03-30
PEF 82912/82913
Functional Description
2.4.4
Processing of the Overhead Bits M4, M5, M6
2.4.4.1 M4 Bit Reporting to the µC
Four different validation modes can be selected and take effect on a per bit base. Only
if the received M4 bit change has been approved by the programmed filter algorithm a
report to the µC is triggered. The following filter algorithms are provided and can be
programmed in the MFILT register:
• On Change
• Triple-Last-Look (TLL) coverage
• CRC coverage
Note that unlike the M4 bits the M56 bits are not included in the CRC generation!
• CRC and TLL coverage
2.4.4.2 M4 Bit Reporting to State Machine
Some M4 bits, ACT, DEA and UOA, have two destinations, the state machine and the
µC. Regarding these bits Triple-Last-Look (TLL) is applied by default before the changed
status is input to the state machine. Via the MFILT register the user can decide whether
the M4 bits which are input to the state machine shall be approved
• by TLL (default setting, since TLL is a Bellcore requirement) or
• by the same verification mode as selected for reporting to the µC.
The reset values before activation are ACT=0, DEA=1, UOA=0.
2.4.4.3 M5, M6 Bit Reporting to the µC
By default changes in the received spare bits M51, M52, and M61 are reported to the µC
only if no CRC violation has been detected. However the user has the choice to program
one of the following two options in the MFILT register (for details see Chapter 4.11.2):
• Same validation algorithm is applied to M5 and M6 bits as programmed for M4 bits
• On Change
In transmit direction these bits are set by default to ’1’ if they are not explicitly set by an
µC access (via M56W register).
2.4.4.4 Summary of M4, M5, M6 Bit Reporting
Figure 40 summarizes again the various filtering options that are provided for the
several maintenance channel bits.
Data Sheet
75
2001-03-30
PEF 82912/82913
Functional Description
•
M
U
X
State
Machine
TLL
MFILT.M4(Bit5)
M
U
X
&
M4
M4 INT
CRC
On
Change
MFILT.M4(Bit4,3)
TLL
M
U
X
&
M5, M6
CRC
M
U
X
On
Change
M56 INT
MFILT.M56(Bit6)
m456_filter_QSMINT.emf
Figure 40
Maintenance Channel Filtering Options
Figure 41 illustrates the point of time when a detected M4, M5, M6 bit change is reported
to the µC and when it is reported to the state machine:
• towards the µC reports are always sent after one complete U-superframe was
received,
• whereas towards the state machine M4-bit changes (ACT, DEA, UOA, SAI) are
instantly passed on as soon as they were approved. In context of Figure 41 this
means that a verified ACT bit change is already reported at the end of basic frame #1
instead of the end of basic frame #8.
•
n. Super Frame
2. Basic Frame
2B+D
n+1. Super Frame
1. Basic Frame
8. Basic Frame
ISW
2B+D
M1-6
SW
M1-6
SW
2B+D
M1-6 ISW
2B+D
M1-6
M4= ACT
Time
e.g. ACT
bit
INT
validated
reported to
State
Machine
m4tim2sm_QSMINT.emf
Figure 41
M4 Bit Report Timing (Statemachine vs. µC)
Data Sheet
76
2001-03-30
PEF 82912/82913
Functional Description
However, if the same filter is selected towards the state machine as programmed
towards the µC, the user has to be aware that if CRC mode is active, the state machine
is informed at the end of the next U-superframe.
2.4.5
M4, M5, M6 Bit Control Mechanisms
Figure 42 and Figure 43 show the control mechanisms that are provided for M4, M5 and
M6 bit data:
Via the M4WMASK register the user can selectively program which M4 bits are
externally controlled and which are set by the internal state machine or dedicated pins
(PS1, PS2). If one M4WMASK bit is set to ’0’ then the M4 bit value in the U-transmit
frame is determined by the bit value at the corresponding bit position in the M4W register.
Note: By bit 6 in the M4WMASK register it can be selected whether SAI is set by the
state machine or by µC access and whether the value of the received UOA bit is
reported to the state machine or UOA= ’1’ is signalled.
Via the M4RMASK register the user can selectively program which M4 bit changes shall
cause an report to the µC.
The M4W register latches the M4 bits that are sent with the next available U-superframe.
The M4R register contains the last validated M4 bit data.
The default value of M51, M52 and M61 can be overwritten at any time by use of register
M56W. M56R latches the last received and verified M5, M6 bit data.
The control of the FEBE bit is performed by the CRC-Processor, see Chapter 2.4.6.
Data Sheet
77
2001-03-30
PEF 82912/82913
Functional Description
•
U Receive Superframe
M4 Filtering (per bit)
M56 Filtering (per bit)
MFILT.M4
MFILT.M56
M4R Register
M56R Register
UOA DEA ACT
AIB
UOA M46
M45
M44 SCO DEA ACT
0
MS2 MS1 NEBE M61
M52
M51 FEBE
EN/
DIS
EN/
DIS
EN/
DIS
EN/
DIS
EN/
DIS
EN/
DIS
EN/
DIS
EN/
DIS
M4RMASK
'0'= enabled
'1'= disabled
'1'
MUX
M4WMASK.Bit6
Interrupt
Controller
State
Machine
INT
m456_nt_rx_QSMINT.e
Figure 42
M4, M5, M6 Bit Control in Receive Direction
•
Pins
C/I Codes
µC
State
Machine
M4W Register
NIB
SAI
M46 CSO NTM
PS2
PS1
ACT
'1'
'1'
'0'
'1'
MUX
MUX MUX MUX MUX MUX
MUX
MUX
M4WMASK
M4WMASK.Bit6
'1'= M4W Reg.
'0'= SM/ Pin
U Transmit Superframe
MUX
OPMODE.FEBE
M56W Register
1
1
1
1
M61
M52
M51
FEBE
NEBE
Counter
µC
m456_nt_tx_QSMINT.emf
Figure 43
M4, M5, M6 Bit Control in Transmit Direction
Data Sheet
78
2001-03-30
PEF 82912/82913
Functional Description
2.4.6
Cyclic Redundancy Check / FEBE bit
An error monitoring function is implemented covering the 2B + D and M4 data
transmission of a U-superframe by a Cyclic Redundancy Check (CRC).
The computed polynomial is:
G (u) = u12 + u11 + u3 + u2 + u + 1
(+ modulo 2 addition)
The check digits (CRC bits CRC1, CRC2, …, CRC12) generated are transmitted in the
U-superframe. The receiver will compute the CRC of the received 2B + D and M4 data
and compare it with the received CRC-bits generated by the transmitter.
A CRC-error will be indicated to both sides of the U-interface, as a NEBE (Near-end
Block Error) on the side where the error is detected, as a FEBE (Far-end Block Error) on
the remote side. The FEBE-bit will be placed in the next available U-superframe
transmitted to the originator.
Figure 44 illustrates the CRC-process.
Data Sheet
79
2001-03-30
PEF 82912/82913
Functional Description
•
IOM®-2
IOM®-2
NT
LT
U
(2B + D), M4
SFR(n)
DD
DD
G(u)
G(u)
CRC1... CRC12
CRC1... CRC12
SFR(n + 1)
No
=?
Yes
CRCOK=1
FEBE
Error
Counter
SFR(n + 1.0625)*
(MON-8)
FEBE = "1"
CRCOK=0
SFR(n + 1.0625)
INT
FEBE = "0"
NEBE
Error
µC access
Counter
(2B + D), M4
G(u)
SFR(n + 0.0625)
DU
DU
G(u)
CRC 1... CRC 12
CRC 1... CRC 12
SFR(n + 1.0625)
SFR(n + 2)
No
=?
Yes
FEBE
Error
Counter
CRCOK=1
µC access
INT
FEBE = "1"
SFR(n + 2)
CRCOK=0
FEBE = "0"
NEBE
Error
(MON-8)
Counter
*0.0625 of a SFR is the 60 Quats offset of the NT transmit data.
crc_QSMINT.emf
Figure 44
CRC-Process
Data Sheet
80
2001-03-30
PEF 82912/82913
Functional Description
2.4.7
Block Error Counters
The U-transceiver provides internal counters for far-end and near-end block errors. This
allows a comfortable surveillance of the transmission quality at the U-interface. In
addition, the occurrence of near-end errors, far-end errors, and the simultaneous
occurrence of both errors are reported to the µC by an interrupt at the beginning of the
following receive-superframe.
A block error is detected each time when the calculated checksum (CRC) of the received
data does not correspond to the control checksum transmitted in the successive
superframe. One block error thus indicates that one U-superframe has not been
transmitted correctly. No conclusion with respect to the number of bit errors is therefore
possible.
2.4.7.1 Near-End and Far-End Block Error Counter
A near-end block error (NEBE) indicates that the error has been detected in the receive
direction (i.e. NEBE in the NT = LT => NT error). Each detected NEBE-error increments
the 8-bit NEBE-counter. When reaching the maximum count, counting is stopped and
the counter value reads (FFH).
A far-end block error identifies errors in transmission direction (i.e. FEBE in the NT = NT
=> LT-error). FEBE errors are processed in the same manner as NEBE-errors.
The FEBE and NEBE counter values can be read in registers FEBE and NEBE. The
counter is cleared after read. The counters are also reset to 00H in all states except the
states listed in Table 15.
2.4.7.2 Testing Block Error Counters
Figure 45 illustrates how near- and far-end block error counters can be tested.
Transmission errors are simulated with artificially corrupted CRCs. With two commands
the cyclic redundancy checksum can be inverted in the upstream and downstream
direction. A third command offers to invert single FEBE-bits.
• EOC Command NCC:
Requests the Q-SMINTI to notify corrupted CRCs.
The functional behavior of the Q-SMINTI and the NEBE-counter depends on the
mode selected:
– EOC auto mode:
NEBE-detection stopped: no NEBE interrupt generated and NEBE-counter disabled
– EOC transparent mode
NEBE-detection enabled: NEBE interrupt generated and NEBE-counter enabled
Data Sheet
81
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PEF 82912/82913
Functional Description
• EOC Command RCC:
Requests the Q-SMINTI to send corrupt CRCs. After issuing RCC near-end block
errors will be registered on the LT-side.
The functional behavior of the Q-SMINTI and the FEBE-counter depends on the
mode selected:
– EOC auto mode:
The Q-SMINTI will react with a permanently inverted upstream CRC.
FEBE-detection stopped: no FEBE interrupt generated and FEBE-counter disabled
– EOC transparent mode
The external µC must react on RCC by programming TEST.CCRC = ’1’.
FEBE-detection enabled: FEBE interrupt generated and FEBE-counter enabled
• EOC command RTN:
Disables all previously sent EOC commands.
• M56W.FEBE
By setting / resetting M56W.FEBE (M56W.FEBE can only be set and controlled
externally if OPMODE.FEBE is set to ’1’), the FEBE bit of the next available U-frame
can be set / reset . Therefore, it is possible to predict exactly the FEBE-counter value.
Data Sheet
82
2001-03-30
PEF 82912/82913
Functional Description
•
EOC
EOC
U
LT
IOM -2
µC
Interface
Transparent
Auto-Mode
ISTAU.EOC=1
EOCR = 'NCC'
EOC : NCC
(MON-0) NCC
(MON-0) ACK
STOP
ERROR
DETECT
EOC Acknowledge
Start Inverse
CRC Bits
(MON-8) CCRC
FEBE = "0"
ERROR
COUNT
NEBE
ISTAU.FEBE/
NEBE=1
M56R.NEBE = '1'
(MON-8) RBEF
(MON-8) ABEC
ERROR
COUNT
FEBE
End Inverse
CRC Bits
(MON-8) NORM
EOC : RTN
(MON-0) RTN
(MON-0) ACK
ISTAU.EOC=1
EOCR = 'RTN'
FREE
ERROR
DETECT
EOC Acknowledge
ISTAU.EOC=1
EOCR = 'RCC'
STOP
ERROR
DETECT
EOC : RCC
(MON-0) RCC
(MON-0) ACK
EOC Acknowledge
Start Inverse
CRC Bits
TEST.CCRC = '1'
ERROR
COUNT
FEBE
FEBE = "0"
ISTAU.FEBE/
NEBE=1
(MON-8) RBEN
(MON-8) ABEC
ERROR
COUNT
NEBE
M56R.FEBE = '1'
EOC : RTN
(MON-0) RTN
ISTAU.EOC=1
EOCR = 'RTN'
FREE
ERROR
DETECT
EOC Acknowledge
End Inverse
CRC Bits
TEST.CCRC = '0'
ITD04226_QSMINT.emf
Figure 45
2.4.8
Block Error Counter Test
Scrambling/ Descrambling
The scrambling algorithm ensures that no sequences of permanent binary 0s or 1s are
transmitted. The scrambling / descrambling process is controlled fully by the Q-
SMINTI. Hence, no influence can be taken by the user.
2.4.9
C/I Codes
The operational status of the U-transceiver is controlled by the Control/Indicate channel
(C/I-channel).
Data Sheet
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Functional Description
Table 22 presents all defined C/I codes. A new command or indication will be recognized
as valid after it has been detected in two successive IOM®-2-frames (double last-look
criterion).
Note: Unconditional C/I-Commands must be applied for at least 4 IOM-2 frames for
reliable recognition by the U-transceiver.
Commands have to be applied continuously on DU until the command is validated by the
U-transceiver and the desired action has been initiated. Afterwards the command may
be changed.
An indication is issued permanently by the U-transceiver on DD until a new indication
needs to be forwarded. Because a number of states issue identical indications it is not
possible to identify every state individually.
•
Table 22
U - Transceiver C/I Codes
IN
Code
0000
0001
0010
0011
0100
0101
0110
0111
1000
1001
1010
1011
1100
1101
1110
1111
OUT
DR
–
TIM
RES
–
–
–
–
EI1
SSP
DT
–
EI1
–
–
PU
AR
–
AR
–
ARL
–
ARL
–
AI
AI
–
–
–
AIL
DC
DI
AI: Activation Indication
AIL: Activation Indication Loop
AR: Activation Request
ARL: Activation Request Local Loop
Data Sheet
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PEF 82912/82913
Functional Description
DC: Deactivation Confirmation
DI: Deactivation Indication
DR: Deactivation Request
DT: Data Through test mode
EI1: Error Indication 1
PU: Power-Up
RES: Reset
SSP: Send Single Pulses test mode
TIM: Timing request
2.4.10
State Machines for Line Activation / Deactivation
2.4.10.1 Notation
The state machines control the sequence of signals at the U-interface that are generated
during the start-up procedure. The informations contained in the following state diagrams
are:
– State name
– U-signal transmitted
– Overhead bits transmitted
– C/I-code transmitted
– Transition criteria
– Timers
Data Sheet
85
2001-03-30
PEF 82912/82913
Functional Description
Figure 46 shows how to interpret the state diagrams.
•
IN
Signal Transmitted
to U-Interface
(general)
Single Bit
Transmitted
to U-Interface
State Name
Indication Transmitted on C/I-Channel
(DOUT)
ITD04257.vsd
OUT
Figure 46
Explanation of State Diagram Notation
Combinations of transition criteria are possible. Logical “AND” is indicated by “&” (TN &
DC), logical “OR” is written “or” and for a negation “/” is used. The start of a timer is
indicated with “TxS” (“x” being equivalent to the timer number). Timers are always
started when entering the new state. The action resulting after a timer has expired is
indicated by the path labelled “TxE”.
Data Sheet
86
2001-03-30
PEF 82912/82913
Functional Description
2.4.10.2 Standard NT State Machine (IEC-Q / NTC-Q Compatible)
•
T14E
T14S
TL
.
.
SN0
SN0
T14S
AR or TL
Pending Timing
DC
Deactivated
DC
Any State
SSP or
T14S
TIM
DI
.
SP
C/I= 'SSP'
.
SN0
DI
Test
DR
IOM Awaked
PU
AR or TL
T1S, T11S
DI
DI & NT-AUTO
T1S,
T11S
.
.
.
SN0
TN
Alerting 1
DR
T11E
TN
T1S
T11S
Reset
Alerting
Any State
Pin-RST or
C/I= 'RES'
DR
PU
DC
T11E
ARL
T12S
T12S
T12S
.
SN1
.
.
SN1
SN1
EC-Training AL
DC
EC-Training
DC
EC-Training 1
DR
DI
LSEC or T12E
LSEC or T12E
act=0
LSUE
or T1E
.
SN0
SN3
EQ-Training
Wait for SF AL
DC
DC
BBD0 & FD
BBD1 & SFD
T20S
SN2
1) act=1/03)
SN3/SN3T
Pend.Deact. S/T
LSUE
or T1E
.
SN3T
act=0
Analog Loop Back
AR
LOF
DI
Wait for SF
DC
DR
T20E &
dea=0
LSUE
BBD0 & SFD
LOF
SN3/SN3T1)
act=0
dea=0
LSUE
Synchronized 1
DC
uoa=1
uoa=0
LOF
SN3/SN3T1)
act=0
dea=0
LSUE
Synchronized 2
2)
AR/ARL
Al
uoa=0
dea=0
LSUE
LOF
El1
SN3/SN3T 1) act=1
Wait for Act
2)
AR/ARL
act=1
act=0
act=1
Transparent
LOF
El1
uoa=0
dea=0
LSUE
Any State
DT or
C/I='DT'
SN3T
Yes
2)
AI/AIL
No
uoa=1
act=1 & Al
?
dea=0
uoa=0
LSUE
SN3/SN3T 1)
act=0
Error S/T
act=0
2)
AR/ARL
dea=1
SN3/SN3T1) act=1/03)
Pend.Deact. U
LOF
.
SN0
LOF
Pend Receive Res.
T13S
T7S
EI1
DC
LSU
LSU or ( /LOF & T13E )
T7S
.
SN0
Receive Reset
T7E & DI
TL
DR
Figure 47
Standard NT State Machine (IEC-Q / NTC-Q Compatible) (Footnotes:
see “Dependence of Outputs” on Page 92)
Data Sheet
87
2001-03-30
PEF 82912/82913
Functional Description
Note: The test modes ‘Data Through‘ (DT) and ‘Send Single Pulses‘ (SSP) are invoked
via C/I codes ’DT’ and ’SSP’ according to Table 22. Setting SRES.RES_U to ‘1‘
forces the U-transceiver into test mode ‘Quiet Mode‘ (QM), i.e. the U-transceiver
is hardware reset.
If the Metallic Loop Termination is used, then the U-transceiver is forced into the
states ‘Reset‘ and ‘Transparent‘ by valid pulse streams on pin MTI according to
Table 29.
Note: If the state machine is in state ’Deactivated’ and the IOM-2 clocks are not
running, then the transitions to ’IOM-2 Awaked’ or ’Alerting’ can be invoked by
writing directly the corresponding C/I-code to register UCIW via the µC interface.
2.4.10.3 Inputs to the U-Transceiver:
C/I-Commands:
AI
Activation Indication
The downstream device issues this indication to announce that its layer-1 is
available. The U-transceiver informs the LT side by setting the “ACT” bit to “1”.
AR
ARL
Activation Request
The U-transceiver is requested to start the activation process by sending the wake-
up signal TN.
Activation Request Local Loop-back
The U-transceiver is requested to operate an analog loop-back (close to the U-
interface) and to begin the start-up sequence by sending SN1 (without starting timer
T1). This command may be issued only after the U-transceiver has been HW- or SW-
reset. This eases that the EC- and EQ-coefficient updating algorithms converge
correctly. The ARL-command has to be issued continuously as long as the loop-back
is required.
DI
Deactivation Indication
This indication is used during a deactivation procedure to inform the U-transceiver
that it may enter the deactivated (power-down) state.
DT
EI1
Data Through
This unconditional command is used for test purposes only and forces the U-
transceiver into the “Transparent” state.
Error Indication 1
The downstream device indicates an error condition (loss of frame alignment or loss
of incoming signal). The U-transceiver informs the LT-side by setting the ACT-bit to
“0” thus indicating that transparency has been lost.
RES
SSP
Reset
Unconditional command which resets the U-transceiver.
Send Single Pulses
Unconditional command which requests the transmission of single pulses on the
U-interface.
Data Sheet
88
2001-03-30
PEF 82912/82913
Functional Description
TIM
Timing
The U-transceiver is requested to enter state ’IOM -2 Awaked’.
U-Interface Events:
ACT = 0/1
ACT-bit received from LT-side.
– ACT = 1 requests the U-transceiver to transmit transparently in both directions. In
the case of loop-backs, however, transparency in both directions of transmission is
established when the receiver is synchronized.
– ACT = 0 indicates that layer-2 functionality is not available.
DEA = 0/1
DEA-bit received from the LT-side
– DEA = 0 informs the U-transceiver that a deactivation procedure has been started
by the LT-side.
– DEA = 1 reflects the case when DEA = 0 was detected by faults due to e.g.
transmission errors and allows the U-transceiver to recover from this situation.
UOA = 0/1
UOA-bit received from network side
– UOA = 0 informs the U-transceiver that only the U-interface is to be activated. The
S/T-interface must be deactivated.
– UOA = 1 requests the S/T-interface (if present) to activate.
Timers
The start of timers is indicated by TxS, the expiry by TxE. Table 23 shows which timers
are used:
•
Table 23
Timer
Timers Used
Duration
(ms)
Function
State
T1
15000
40
Supervisor for start-up
Hold time
T7
Receive reset
Alerting
T11
T12
T13
9
TN-transmission
5500
15000
Supervisor EC-converge
Frame synchronization
EC-training
Pend. receive
reset
T14
T20
0.5
10
Hold time
Hold time
Pend. timing
Wait for SF
2.4.10.4 Outputs of the U-Transceiver:
The following signals and indications are issued on IOM®-2 (C/I-indications) and on the
U-interface (predefined U-signals):
Data Sheet
89
2001-03-30
PEF 82912/82913
Functional Description
C/I-Indications
AI
Activation Indication
The U-transceiver has established transparency of transmission. The downstream
device is requested to establish layer-1 functionality.
AIL
Activation Indication Loopback
The U-transceiver has established transparency of transmission. The downstream
device is requested to establish a loopback #2.
AR
Activation Request
The downstream device is requested to start the activation procedure.
ARL
Activation Request Loop-back
The U-transceiver has detected a loop-back 2 command in the EOC-channel and has
®
established transparency of transmission in the direction IOM -2 to U-interface. The
downstream device is requested to start the activation procedure and to establish a
loopback #2.
DC
DR
Deactivation Confirmation
Idle code on the IOM -2-interface.
®
Deactivation Request
The U-transceiver has detected a deactivation request command from the LT-side for
a complete deactivation or a S/T only deactivation. The downstream device is
requested to start the deactivation procedure.
EI1
Error Indication 1
The U-transceiver has entered a failure condition caused by loss of framing on the
U-interface or expiry of timer T1.
Signals on U-Interface
The signals SNx, TN and SP transmitted on the U-interface are defined in Table 24.
•
Table 24
Signal
U-Interface Signals
Synch. Word
(SW)
Superframe
(ISW)
2B + D
M-Bits
TN 1)
SN0
± 3
± 3
± 3
± 3
no signal
present
present
present
present
no signal
absent
absent
present
present
no signal
no signal
1
SN1
1
SN2
1
1
SN3
1
normal
normal
SN3T
Test Mode
SP 2)
normal
test signal
test signal
90
test signal
test signal
Data Sheet
2001-03-30
PEF 82912/82913
Functional Description
1)
Note: Alternating ± 3 symbols at 10 kHz.
Note: 2) 4 Options for the test signal can be selected by register TEST:
A 40 kHz signal composed by alternating +/-3 or +/-1 transmit pulses.
A series of single pulses spaced at intervals of 1.5 ms; Either alternating +/-1 or
+/-3 pulses can be selected.
Input Signals of the State Machine and related U-Signals
The table below summarizes the input signals that control the NT state machine and that
are extracted from the U-interface signal sequences.
•
LOF
Loss of framing
This condition is fulfilled if framing is lost for 573 ms.
LSEC
LSU
Loss of signal behind echo canceller
Internal Signal which indicates that the echo canceller has converged
Loss of Signal on U-Interface
This signal indicates that a loss of signal level for a duration of 3 ms has
been detected on the U-interface. This short response time is relevant in
all cases where the NT waits for a response (no signal level) from the LT-
side.
LSUE
Loss of Signal on U-Interface - Error condition
After a loss of signal has been noticed, a 588 ms timer is started. When
it has elapsed , the LSUE-criterion is fulfilled. This long response time
(see also LSU) is valid in all cases where the NT is not prepared to lose
signal level i.e. the LT has stopped transmission because of loss of
framing, an unsuccessful activation, or the transmission line is
interrupted.
FD
Frame Detected
SFD
Super Frame Detected
BBD0 /
BBD1
BBD0/1 Detected
These signals are set if either ’1' (BBD1) or ’0' (BBD0) were detected in
4 subsequent basic frames. It is used as a criterion that the receiver has
acquired frame synchronization and both its EC- and EQ-coefficients
have converged. BBD0 corresponds to the received signal SL2 in case
of a normal activation, BBD1 corresponds to the internally received
signal SN3 in case of analog loop back.
TL
Awake tone detected
The U-transceiver is requested to start an activation procedure.
Data Sheet
91
2001-03-30
PEF 82912/82913
Functional Description
Signals on IOM-2
The Data (B+B+D) is set to all ’1’s in all states besides the states listed in Table 15.
Dependence of Outputs
• Outputs denoted with 1) in Figure 47:
Signal output on Uk0 depends on the received EOC command and on the history of
the state machine according to Table 25:
•
Table 25
Signal Output on Uk0
EOC Command
History of the State Machine
Signal output on Uk0
received ’LBBD’
no influence
SN3T
SN3
received no ’LBBD’ or ’RTN’ state ’Transparent’ has not been
after an ’LBBD’
reached previously during this
activation procedure
state ’Transparent’ has been
reached previously during this
activation procedure
SN3T
• Outputs denoted with 2) in Figure 47:
C/I-code output depends on received EOC-command ’LBBD’ according to Table 26:
•
Table 26
C/I-Code Output
EOC Command
Synchroni Wait for Act Transparent Error S/T
zed 2
received no ’LBBD’ or
’RTN’ after an ’LBBD’
AR
AR
AI
AR
received ’LBBD’
ARL
ARL
AIL
ARL
• Outputs denoted with 3) in Figure 47:
In States ’Pend. Deact. S/T’ and ’Pend. Deact. U’ the ACT-bit output depends on its
value in the previous state.
• The value of the issued SAI-bit depends on the received C/I-code: DI and TIM lead to
SAI = 0, any other C/I-code sets the SAI-bit to 1 indicating activity of the downstream
device.
• If state Alerting is entered from state Deactivated, then C/I-code ’PU’ is issued, else
C/I-code ’DC’ is issued.
Data Sheet
92
2001-03-30
PEF 82912/82913
Functional Description
2.4.10.5 Description of the NT-States
The following states are used:
Alerting
The wake-up signal TN is transmitted for a period of T11 either in response to a received
wake-up signal TL or to start an activation procedure on the LT-side.
Alerting 1
“Alerting 1” state is entered when a wake-up tone was received in the “Receive Reset”
state and the deactivation procedure on the NT-side was not yet finished. The
transmission of wake-up tone TN is started.
Analog Loop-Back
Transparency is achieved in both directions of transmission. This state can be left by
making use of any unconditional command.
Deactivated
Only in state Deactivated the device may enter the power-down mode.
EC Training
The signal SN1 is transmitted on the U-interface to allow the NT-receiver to update the
EC-coefficients. The automatic gain control (AGC), the timing recovery and the EQ
updating algorithm are disabled.
EC-Training 1
The “EC-Training 1” state is entered if transmission of signal SN1 has to be started and
the deactivation procedure on the NT-side is not yet finished.
EC-Training AL
The signal SN1 is transmitted on the U-interface to allow the NT-receiver to update the
EC-coefficients. The automatic gain control (AGC), the timing recovery and the EQ
updating algorithm are disabled.
EQ-Training
The receiver waits for signal SL1 or SL2 to be able to update the AGC, to recover the
timing phase, to detect the synch-word (SW), and to update the EQ-coefficients.
Data Sheet
93
2001-03-30
PEF 82912/82913
Functional Description
Error S/T
The downstream device is in an error condition (EI1). The LT-side is informed by setting
the ACT-bit to “0” (loss of transparency on the NT-side).
IOM-2-Awaked
The U-transceiver is deactivated, but may not enter the power-down mode.
Pending Deactivation of S/T
The U-transceiver has received the UOA-bit at zero after a complete activation of the S/
T-interface. The U-transceiver requests the downstream device to deactivate by issuing
DR.
Pending Deactivation of U-Interface
The U-transceiver waits for the receive signal level to be turned off (LSU) to start the
deactivation procedure.
Pending Receive Reset
The “Pending Receive Reset” state is entered upon detection of loss of framing on the
U-interface or expiry of timer T1. This failure condition is signalled to the LT-side by
turning off the transmit level (SN0). The U-transceiver then waits for a response (no
signal level LSU) from the LT-side.
Pending Timing
In the NT-mode the pending timing state assures that the C/I-channel code DC is issued
four times before entering the ’Deactivated’ state.
Receive Reset
In state ’Receive Reset’ a reset of the Uk0-receiver is performed, except in case that
state ’Receive Reset’ was entered from state ’Pend. Deact. U’. Timer T7 assures that no
activation procedure is started from the NT-side for a minimum period of time of T7. This
gives the LT a chance to activate the NT.
Reset
In state ’Reset’ a software-reset is performed.
Synchronized 1
State ’Synchronized 1’ is the fully active state of the U-transceiver, while the downstream
device is deactivated.
Data Sheet
94
2001-03-30
PEF 82912/82913
Functional Description
Synchronized 2
In this state the U-transceiver has received UOA = 1. This is a request to activate the
downstream device.
Test
The test signal SP is issued as long as C/I=SSP is applied. For further details see
Table 24.
Transparent
This state is entered upon the detection of ACT = 1 received from the LT-side and
corresponds to the fully active state.
Wait for ACT
Upon the receipt of AI, the NT waits for a response (ACT = 1) from the LT-side.
Wait for SF
The signal SN2 is sent on the U-interface and the receiver waits for detection of the
superframe.
Wait for SF AL
This state is entered in the case of an analog loop-back and allows the receiver to update
the AGC, to recover the timing phase, and to update the EQ-coefficients.
2.4.10.6 Simplified NT State Machine
As an alternative to the activation/deactivation state machine of the U-transceiver known
from the IEC-Q [9], a more software friendly state machine can be selected.
In the early days of ISDN, the activation and deactivation procedure in a NT was
completely determined by the U- and S-transceiver state machines without a
microcontroller being necessary. Intelligent NTs or U-terminals require a microcontroller
and software. In this case the software controls both the S-and the U-transceiver state
machine.
The simplified U-transceiver state machine was developed to better address the needs
and requirements of software running on the microcontroller. The simplified state
machine offers the following advantages:
– the software can tell whether the IOM-2 clocks are active or powered down via the
received C/I code
– From the received C/I code the software always knows, what it is expected to do and
what options it has. The software does not have to backtrack older C/I codes.
Data Sheet
95
2001-03-30
PEF 82912/82913
Functional Description
– unnecessary C/I changes at irrelevant state transitions are omitted, hence the number
of interrupts is reduced.
All advantages can be offered by the following minor changes to the existing state
machine:
•
Table 27
Change
Changes to achieve Simplified NT State Machine
State Standard NT
State Machine State Machine
Simplified NT
Change of Transmitted C/I -Code
Alerting
DC/PU
DC
PU
PU
PU
PU
PU
DR
EC-Training
EQ-Training
Wait for SF
DC
DC
Synchronized 1 DC
Pend. Receive
Res.
EI1
Pend. Deact. U. DC
Wait for SF AL DC
EC-Training AL DC
all other States no changes
DR
DR
DR
Changed State Transition Criteria
Alerting 1 to
Alerting
DI
DI or TIM
DI or TIM
DI or TIM
EC-Training 1 to DI
EC-Training
Pend.Deact.S/T DI
to Synchron. 1
all other
transition
criterias
no changes
New State Transitions
ReceiveResetto none
IOM-2 Awaked
Reset to IOM®-2 none
Awaked
T7E & TIM
TIM
Data Sheet
96
2001-03-30
PEF 82912/82913
Functional Description
Table 27
Change
Changes to achieve Simplified NT State Machine(cont’d)
State Standard NT Simplified NT
State Machine State Machine
Test to IOM-2 none
Awaked
TIM
Not Supported State Transitions
Reset to Alerting DI & NTAUTO
all other no changes
transitions
none
Data Sheet
97
2001-03-30
PEF 82912/82913
Functional Description
•
T14E
T14S
TL
.
.
SN0
SN0
T14S
AR or TL
Pending Timing
DC
Deactivated
DC
Any State
SSP or
T14S
TIM
DI
.
SP
C/I= 'SSP'
.
SN0
DI
Test
IOM Awaked
PU
DR
TIM
AR or TL
T1S, T11S
TN
DI
T1S,
T11S
.
.
.
SN0
TN
T1S
Reset
Alerting 1
Alerting
PU
T11S
DR
Any State
Pin-RST or
C/I= 'RES'
DR
T11E
T11E
ARL
T12S
T12S
T12S
.
SN1
.
.
SN1
SN1
EC-Training AL
DR
EC-Training
PU
EC-Training 1
DR
DI or TIM
LSEC or T12E
LSEC or T12E
LSUE
or T1E
.
SN0
act=0
SN3
EQ-Training
Wait for SF AL
DR
PU
BBD0 & FD
BBD1 & SFD
T20S
SN2
1) act=1/03)
SN3/SN3T
LSUE
or T1E
.
SN3T
act=0
Analog Loop Back
AR
LOF
Pend.Deact. S/T
Wait for SF
PU
DR
T20E &
dea=0
or
LSUE
DI
BBD0 & SFD
TIM
LOF
SN3/SN3T1)
act=0
dea=0
Synchronized 1
LSUE
PU
uoa=1
uoa=0
LOF
SN3/SN3T1)
act=0
dea=0
LSUE
Synchronized 2
2)
AR/ARL
Al
uoa=0
dea=0
LSUE
LOF
El1
SN3/SN3T 1) act=1
Wait for Act
2)
AR/ARL
act=1
act=0
act=1
Transparent
LOF
El1
uoa=0
dea=0
LSUE
Any State
DT or
C/I='DT'
SN3T
Yes
2)
AI/AIL
No
uoa=1
act=1 & Al
?
dea=0
uoa=0
LSUE
SN3/SN3T 1)
act=0
Error S/T
act=0
2)
AR/ARL
dea=1
SN3/SN3T1) act=1/03)
Pend.Deact. U
LOF
.
SN0
LOF
Pend Receive Res.
T13S
T7S
DR
DR
LSU
LSU or ( /LOF & T13E )
T7S
.
SN0
T7E & TIM
T7E & DI
Receive Reset
TL
DR
Figure 48
Simplified NT State Machine
Data Sheet
98
2001-03-30
PEF 82912/82913
Functional Description
•
Table 28
Appearance of the State Machine to the Software
C/I ind. Meaning
Options
U-
transp
arent
DR
DC
LT has decided to deactivate or DI
activation was lost:
– after an activation or
– after an activation attempt or TIM
– after reset
Acknowledge and give no
permission to turn off
the clocks
Acknowledge, clocks
will stay active
four IOM®-2 frames with C/I
code DC are issued before
TIM
AR
turn on clocks
no
start U-activation
no action, permission to
turn off the clocks will be
given
permission to turn off the clocks any
other
C/I-
code
PU
AR
clocks are on;
any
C/I-
code
no action, clocks will
remain on
no
no
U-interface is not transparent
but may be synchronous (e.g.
U-only activation)
used during activation. U-
interface is synchronous and is
waiting for an ok from the
downstream device
AI
accept that activation
can continue, layer 2 of
the downstream device
is ready. Then wait for
CI/ indication AI
AI
U-interface transparent
--
no action, transmit data yes
report problem on
downstream device
EI1 or
act=0
2.4.11
Metallic Loop Termination
For North American applications a maintenance controller according to ANSI T1.601
section 6.5 is implemented. The maintenance pulse stream from the U-interface Metallic
Loop Termination circuit (MLT) is fed to pin MTI, usually via an optocoupler. It is digitally
filtered for 20 ms and decoded independently on the polarity by the maintenance
controller according to Table 29. Therefore, the maintenance controller is capable of
detecting the DC and AC signaling format. The Q-SMINTI automatically sets the U-
transceiver in the proper state and issues an interrupt. The state selected by the MLT is
indicated via two bits.
The Q-SMINTI reacts on a valid pulse stream independently of the current U-
transceiver state. This includes the power-down state.
Data Sheet
99
2001-03-30
PEF 82912/82913
Functional Description
A test mode is valid for 75 seconds. If during the 75 seconds a valid pulse sequence is
detected the 75 s timer starts again. After expiry of the 75 s timer the MLT maintenance
controller goes back to normal operation.
•
Table 29
ANSI Maintenance Controller States
ANSI maintenance U-transceiver State Machine
Number of
counted pulses controller state
<= 5
6
ignored
no impact
Quiet Mode
transition to state ’Reset’
start timer 75s
7
8
ignored
no impact
Insertion Loss Measurement transition to state ’Transparent’
start timer 75s
9
ignored
no impact
10
normal operation
ignored
transition to state ’Reset’
no impact
>= 11
Figure 49 shows examples for pulse streams with inverse polarity selecting Quiet Mode.
•
20 ms < tHIGH < 500 ms
4 ms < tLOW < 500 ms
1
Pin
1
2
3
4
5
6
MTI 0
≥
500 ms
≥500 ms
20 ms < tLOW < 500 ms
4 ms < tHIGH < 500 ms
1
Pin
1
2
3
4
5
6
MTI 0
≥
500 ms
≥
500 ms
mlt.vsd
Figure 49
Pulse Streams Selecting Quiet Mode
Data Sheet
100
2001-03-30
PEF 82912/82913
Functional Description
2.4.12
U-Transceiver Interrupt Structure
The U-Interrupt Status register (ISTAU) contains the interrupt sources of the U-
Transceiver (Figure 50). Each source can be masked by setting the corresponding bit
of the U-Interrupt Mask register (MASKU) to ’1’. Such masked interrupt status bits are
not indicated when ISTAU is read and do not generate an interrupt request.
The ISTAU register is cleared on read access. The interrupt sources of the ISTAU
register (UCIR, EOCR, M4R, M56R) need not be evaluated.
When at time t1 an interrupt source generates an interrupt, all further interrupts are
collected. Reading the ISTAU register clears all interrupts set before t1, even if masked.
All interrupts, which are flagged after t1 remain active. After the ISTAU read access, the
next unmasked interrupt will generate the next interrupt at time t2. After t2 it is possible
to reprogram the MASKU register, so that all interrupts, which arrived between t1 and t2
are accessible.
Data Sheet
101
2001-03-30
PEF 82912/82913
Functional Description
•
M56R
0
7
OPMODE.MLT
MFILT
MS2
MS1
NEBE
M61
+
CRC,
TLL,
no
M52
Filtering
M51
0
7
FEBE
+
M4R
MFILT
M4RMASK
UCIR
7
AIB
UOA
M46
M45
M44
SCO
DEA
ACT
CRC,
TLL,
no
C/I
Filtering
C/I
C/I
C/I
0
0
EOCR
MFILT
15
TLL,
CHG,
no
ISTAU
MLT
MASKU
MLT
7
a1
a2
11
0
Filtering
CI
CI
FEBE/
NEBE
FEBE/
NEBE
M56
M56
i8
M4
M4
EOC
6ms
12ms
EOC
6ms
12ms
0
ISTA
MASK
7
U
interr_U_Q2.vsd
0
INT
Figure 50
Interrupt Structure U-Transceiver
Data Sheet
102
2001-03-30
PEF 82912/82913
Functional Description
2.5
S-Transceiver
The S-Transceiver offers the NT and LT-S mode state machines described in the User’s
Manual V3.4 [10].
The S-transceiver lies in IOM-2 channel 1 (default) and is configured and controlled
via the registers described in Chapter 4.7. The state machine is set to NT mode (default)
but can be set to LT-S mode via register programming.
The TE mode (S-transceiver TE mode, U-transceiver disabled) is not supported.
2.5.1
Line Coding, Frame Structure
Line Coding
The following figure illustrates the line code. A binary ONE is represented by no line
signal. Binary ZEROs are coded with alternating positive and negative pulses with two
exceptions:
For the required frame structure a code violation is indicated by two consecutive pulses
of the same polarity. These two pulses can be adjacent or separated by binary ONEs.
In bus configurations a binary ZERO always overwrites a binary ONE.
•
0 1 1
code violation
Figure 51
S/T -Interface Line Code
Frame Structure
Each S/T frame consists of 48 bits at a nominal bit rate of 192 kbit/s. For user data
(B1+B2+D) the frame structure applies to a data rate of 144 kbit/s (see Figure 51).
In the direction TE → NT the frame is transmitted with a two bit offset. For details on the
framing rules please refer to ITU I.430 section 6.3. The following figure illustrates the
standard frame structure for both directions (NT → TE and TE → NT) with all framing
and maintenance bits.
Data Sheet
103
2001-03-30
PEF 82912/82913
Functional Description
•
Figure 52
Frame Structure at Reference Points S and T (ITU I.430)
– F
Framing Bit
F = (0b) → identifies new frame (always
positive pulse, always code violation)
– L.
D.C. Balancing Bit
L. = (0b) → number of binary ZEROs sent
after the last L. bit was odd
– D
– E
D-Channel Data Bit
D-Channel Echo Bit
Signaling data specified by user
E = D → received E-bit is equal to transmitted
D-bit
– FA
– N
Auxiliary Framing Bit
See section 6.3 in ITU I.430
FA
N =
– B1
– B2
– A
B1-Channel Data Bit
B2-Channel Data Bit
Activation Bit
User data
User data
A = (0b) → INFO 2 transmitted
A = (1b) → INFO 4 transmitted
– S
– M
S-Channel Data Bit
Multiframing Bit
S1 channel data (see note below)
M = (1b) → Start of new multi-frame
Note: The ITU I.430 standard specifies S1 - S5 for optional use.
Data Sheet
104
2001-03-30
PEF 82912/82913
Functional Description
2.5.2
S/Q Channels, Multiframing
According to ITU recommendation I.430 a multi-frame provides extra layer-1 capacity in
the TE-to-NT direction through the use of an extra channel between the TE and NT (Q-
channel). The Q bits are defined to be the bits in the FA bit position.
In the NT-to-TE direction the S-channel bits are used for information transmission.
The S- and Q-channels are accessed via µC by reading/writing the SQR or SQX bits in
the S/Q channel registers (SQRR, SQXR).
Table 30 shows the S and Q bit positions within the multi-frame.
Table 30
S/Q-Bit Position Identification and Multi-Frame Structure
Frame Number NT-to-TE NT-to-TE
FA Bit Position M Bit
NT-to-TE
S Bit
TE-to-NT
FA Bit Position
1
2
3
4
5
ONE
ONE
S11
S21
S31
S41
S51
Q1
ZERO
ZERO
ZERO
ZERO
ZERO
ZERO
ZERO
ZERO
ZERO
ZERO
ZERO
ZERO
6
7
8
9
ONE
ZERO
ZERO
ZERO
ZERO
ZERO
S12
S22
S32
S42
S52
Q2
ZERO
ZERO
ZERO
ZERO
ZERO
ZERO
ZERO
ZERO
10
11
12
13
14
15
ONE
ZERO
ZERO
ZERO
ZERO
ZERO
S13
S23
S33
S43
S53
Q3
ZERO
ZERO
ZERO
ZERO
ZERO
ZERO
ZERO
ZERO
16
17
18
19
20
ONE
ZERO
ZERO
ZERO
ZERO
ZERO
S14
S24
S34
S44
S54
Q4
ZERO
ZERO
ZERO
ZERO
ZERO
ZERO
ZERO
ZERO
1
2
ONE
ZERO
ONE
ZERO
S11
S21
Q1
ZERO
Data Sheet
105
2001-03-30
PEF 82912/82913
Functional Description
The S-transceiver starts multiframing if SQXR1.MFEN is set.
After multi-frame synchronization has been established in the TE, the Q data will be
inserted at the upstream (TE → NT) FA bit position by the TE in each 5th S/T frame, the
S data will be inserted at the downstream (NT → TE) S bit position in each 5th S/T frame
(see Table 30). Access to S2-S5-channel is not supported.
Interrupt Handling for Multi-Framing
To trigger the microcontroller for a multi-frame access an interrupt can be generated
once per multi-frame (SQW) or if the received Q-channel have changed (SQC).
In both cases the microcontroller has access to the multiframe within the duration of one
multiframe (5 ms).
The start of a multiframe can not be synchronized to an external signal.
Data Transfer between IOM -2 and S0
2.5.3
In the state G3 (Activated) or if the internal layer-1 statemachine is disabled and XINF of
register S_CMD is programmed to ’011’ the B1, B2 and D bits are transferred
transparently from the S/T to the IOM-2 interface and vice versa. In all other states ’1’s
are transmitted to the IOM-2 interface.
Note: In intelligent NT or intelligent LT-S mode the D-channel access can be blocked by
the IOM-2 D-channel handler.
2.5.4
Loopback 2
C/I commands ARL and AIL close the analog loop as close to the S-interface as possible.
ETSI refers to this loop under ’loopback 2’. ETSI requires, that B1, B2 and D channels
have the same propagation delay when being looped back.
The D-channel Echo bit is set to bin. 0 during an analog loopback (i.e. loopback 2). The
loop is transparent.
Note: After C/I-code AIL has been recognized by the S-transceiver, zeros are looped
back in the B and D-channels (DU) for four frames.
2.5.5
Control of S-Transceiver / State Machine
The S-transceiver activation/ deactivation can be controlled by an internal statemachine
via the IOM-2 C/I-channel or by software via the µC interface directly. In the default
state the internal layer-1 statemachine of the S-transceiver is used. By setting the L1SW
bit in the S_CONF0 register the internal statemachine can be disabled and the layer-1
transmit commands, which are normally generated by the internal statemachine can be
written directly into the S_CMD register or the received status read out from the S_STA
register, respectively. The S-transceiver layer-1 control flow is shown in Figure 53.
Data Sheet
106
2001-03-30
PEF 82912/82913
Functional Description
•
Disable internal
Statemachine
(S_CONF.L1SW)
C/I
Command
Transmit
INFO
Command Register
for Transmitter
(S_CMD)
Transmitter
Receiver
Layer-1
State
Machine
C/I
Indication
IOM-2
Receive
INFO
Status Register
of Receiver
(S_STA)
Layer-1 Control
µ
C-Interface
macro_14
Figure 53
S-Transceiver Control
The state diagram notation is given in Figure 54.
The information contained in the state diagrams are:
– state name
– Signal received from the line interface (INFO)
– Signal transmitted to the line interface (INFO)
– C/I code received (commands)
– C/I code transmitted (indications)
– transition criteria
The transition criteria are grouped into:
– C/I commands
– Signals received from the line interface (INFOs)
– Reset
Data Sheet
107
2001-03-30
PEF 82912/82913
Functional Description
•
OUT
IN
Unconditional
Transition
IOM-2 Interface
C/I code
Ind. Cmd.
State
S/T Interface
INFO
ir
ix
macro_17.vsd
Figure 54
State Diagram Notation
As can be seen from the transition criteria, combinations of multiple conditions are
possible as well. A “ ” stands for a logical AND combination. And a “+” indicates a logical
OR combination.
Test Signals
• 2 kHz Single Pulses (TM1)
One pulse with a width of one bit period per frame with alternating polarity.
• 96 kHz Continuous Pulses (TM2)
Continuous pulses with a pulse width of one bit period.
Note: The test signals TM1 and TM2 are invoked via C/I codes ‘TM1‘ and ‘TM2‘
according to Chapter 2.5.5.1.
External Layer-1 Statemachine
Instead of using the integrated layer-1 statemachine it is also possible to implement the
layer-1 statemachine completely in software.
The internal layer-1 statemachine can be disabled by setting the L1SW bit in the
S_CONF0 register to ’1’.
The transmitter is completely under control of the microcontroller via register S_CMD.
The status of the receiver is stored in register S_STA and has to be evaluated by the
microcontroller. This register is updated continuously. If not masked a RIC interrupt is
generated by any change of the register contents. The interrupt is cleared after a read
access to this register.
Reset States
After an active signal on the reset pin RST the S-transceiver state machine is in the reset
state.
Data Sheet
108
2001-03-30
PEF 82912/82913
Functional Description
C/I Codes in Reset State
In the reset state the C/I code 0000 (TIM) is issued. This state is entered either after a
hardware reset (RST) or with the C/I code RES.
C/I Codes in Deactivated State
If the S-transceiver is in state ‘Deactivated‘ and receives i0, the C/I code 0000 (TIM) is
issued until expiration of the 8 ms timer. Otherwise, the C/I code 1111 (DI) is issued.
2.5.5.1 C/I Codes
The table below presents all defined C/I0 codes. A command needs to be applied
continuously until the desired action has been initiated. Indications are strictly state
orientated. Refer to the state diagrams in the following sections for commands and
indications applicable in various states.
•
LT-S
Cmd
DR
RES
TM1
TM2
–
NT
Cmd
DR
RES
TM1
TM2
RSY
–
Code
Ind
TIM
–
Ind
TIM
–
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
–
–
–
–
RSY
–
RSY
–
–
–
–
–
–
–
–
–
–
AR
–
AR
–
AR
–
AR
–
ARL
–
–
ARL
–
–
CVR
AI
–
CVR
AI
–
–
AI
–
–
–
–
AIL
DC
–
DC
DI
DI
Data Sheet
109
2001-03-30
PEF 82912/82913
Functional Description
Receive Infos on S/T
I0
I0
I3
I3
INFO 0 detected
Level detected (signal different to I0)
INFO 3 detected
Any INFO other than INFO 3
Transmit Infos on S/T
I0
I2
I4
It
INFO 0
INFO 2
INFO 4
Send Single Pulses (TM1).
Send Continuous Pulses (TM2).
Data Sheet
110
2001-03-30
PEF 82912/82913
Functional Description
2.5.5.2 State Machine NT Mode
•
RST
TM1
TM2
RES
DR
G4 Pend. Deact.
TIM
i0
TIM
TIM
DR
DR
Reset
Test Mode i
it
ARD1)
*
i0
i0
*
(i0*16ms)+32ms
DC
RES
DC
TM1
TM2
Any
State
DR
DI
Any
State
ARD1)
G4 Wait for DR
i0
*
DC
DR
DI
TIM
DC
G1 Deactivated
ARD1)
i0
i0
(i0*8ms)
DC
AR
DR
G1 i0 Detected
i0
*
ARD1)
AR ARD
DR
G2 Pend. Act
i2
i3
i3
i3*ARD
AID
ARD
RSY
AI
ARD
i3*ARD1)
i3*AID2)
DR
G2 Lost
Framing S/T
G2 Wait for AID
RSY
i2
i3
i2
i3
AID2)
RSY
DR
ARD1)
AID2)
ARD1)
i3*AID2)
RSY
AID
RSY
AI
DR
G3 Lost
Framing U
G3 Activated
i4
i3
RSY
i2
*
1): ARD = AR or ARL
2): AID =AI or AIL
statem_nt_s.vsd
Figure 55
State Machine NT Mode
Note: State ’Test Mode’ can be entered from any state except from state ’Test Mode’
itself, i.e. C/I-code ’TMi’ must not be followed by C/I-code ’TMj’ directly.
Data Sheet
111
2001-03-30
PEF 82912/82913
Functional Description
G1 Deactivated
The S-transceiver is not transmitting. There is no signal detected on the S/T-interface,
and no activation command is received in the C/I channel. Activation is possible from the
S/T interface and from the IOM-2 interface.
G1 I0 Detected
An INFO 0 is detected on the S/T-interface, translated to an “Activation Request”
indication in the C/I channel. The S-transceiver is waiting for an AR command, which
normally indicates that the transmission line upstream is synchronized.
G2 Pending Activation
As a result of the ARD command, an INFO 2 is sent on the S/T-interface. INFO 3 is not
yet received. In case of ARL command, loop 2 is closed.
G2 wait for AID
INFO 3 was received, INFO 2 continues to be transmitted while the S-transceiver waits
for a “switch-through” command AID from the device upstream.
G3 Activated
INFO 4 is sent on the S/T-interface as a result of the “switch through” command AID: the
B and D-channels are transparent. On the command AIL, loop 2 is closed.
G2 Lost Framing S/T
This state is reached when the transceiver has lost synchronism in the state G3
activated.
G3 Lost Framing U
On receiving an RSY command which usually indicates that synchronization has been
lost on the transmission line, the S-transceiver transmits INFO 2.
G4 Pending Deactivation
This state is triggered by a deactivation request DR, and is an unstable state. Indication
DI (state “G4 wait for DR”) is issued by the transceiver when:
either INFO0 is received for a duration of 16 ms
or an internal timer of 32 ms expires.
Data Sheet
112
2001-03-30
PEF 82912/82913
Functional Description
G4 wait for DR
Final state after a deactivation request. The S-transceiver remains in this state until DC
is issued.
Unconditional States
Test Mode TM1
Send Single Pulses
Test Mode TM2
Send Continuous Pulses
C/I Commands
•
Command
Abbr. Code
Remark
Deactivation Request DR
0000
Deactivation Request. Initiates a complete
deactivation by transmitting INFO 0.
Reset
RES
0001
Reset of state machine. Transmission of
Info0. No reaction to incoming infos. RES is
an unconditional command.
Send Single Pulses
TM1
TM2
0010
0011
Send Single Pulses.
Send Continuous
Pulses
Send Continuous Pulses.
Receiver not
Synchronous
RSY
AR
0100
1000
1010
Receiver is not synchronous
Activation Request
Activation Request. This command is used to
start an activation.
Activation Request
Loop
ARL
Activation request loop. The transceiver is
requested to operate an analog loop-back
close to the S/T-interface.
Activation Indication
AI
1100
Activation Indication. Synchronous receiver,
i.e. activation completed.
Data Sheet
113
2001-03-30
PEF 82912/82913
Functional Description
Command
Abbr. Code
Remark
Activation Indication
Loop
AIL
1110
Activation Indication Loop
Deactivation
Confirmation
DC
1111
Deactivation Confirmation. Transfers the
transceiver into a deactivated state in which
it can be activated from a terminal (detection
of INFO 0 enabled).
Indication
Abbr. Code
Remark
Timing
TIM
RSY
AR
0000
0100
1000
1011
1100
1111
Interim indication during deactivation
procedure.
Receiver not
Synchronous
Receiver is not synchronous.
Activation Request
INFO 0 received from terminal. Activation
proceeds.
Illegal Code Ciolation CVR
Illegal code violation received. This function
has to be enabled in S_CONF0.EN_ICV.
Activation Indication
AI
DI
Synchronous receiver, i.e. activation
completed.
Deactivation
Indication
Timer (32 ms) expired or INFO 0 received for
a duration of 16 ms after deactivation
request.
Data Sheet
114
2001-03-30
PEF 82912/82913
Functional Description
2.5.5.3 State Machine LT-S Mode
•
RST
TM1
TM2
RES
DR
G4 Pend. Deact.
TIM
i0
TIM
TIM
DR
DR
Reset
Test Mode i
it
ARD1)
*
i0
i0
*
DC
TM1
TM2
RES
DC
(i0*16ms)+32ms
DR
Any
State
Any
State
DI
ARD1)
G4 Wait for DR
i0
*
DC
DR
DI
TIM
DC
G1 Deactivated
i0
i0
(i0*8ms)+ARD1)
DC
ARD
DR
AR
G2 Pend. Act.
i2
i3
i3
i3
DC
DC
RSY
AI
ARD
ARD
i3
DR
G2 Lost
Framing S/T
G3 Activated
i4
i3
i2
i3
DR
1): ARD = AR or ARL
statem_lts_s.vsd
Figure 56
State Machine LT-S Mode
Note: State ’Test Mode’ can be entered from any state except from state ’Test Mode’
itself, i.e. C/I-code ’TMi’ must not be followed by C/I-code ’TMj ’directly.
Data Sheet
115
2001-03-30
PEF 82912/82913
Functional Description
G1 deactivated
The S-transceiver is not transmitting. There is no signal detected on the S/T-interface,
and no activation command is received in the C/I channel. Activation is possible from the
S/T interface and from the IOM-2 interface.
G2 pending activation
As a result of an INFO 0 detected on the S/T line or an ARD command, the S-transceiver
begins transmitting INFO 2 and waits for reception of INFO 3. The timer to supervise
reception of INFO 3 is to be implemented in software. In case of an ARL command, loop
2 is closed.
G3 activated
Normal state where INFO 4 is transmitted to the S/T-interface. The transceiver remains
in this state as long as neither a deactivation nor a test mode is requested, nor the
receiver looses synchronism.
When receiver synchronism is lost, INFO 2 is sent automatically. After reception of
INFO 3, the transmitter keeps on sending INFO 4.
G2 lost framing
This state is reached when the S-transceiver has lost synchronism in the state G3
activated.
G4 pending deactivation
This state is triggered by a deactivation request DR. It is an unstable state: indication DI
(state “G4 wait for DR.”) is issued by the S-transceiver when:
either INFO0 is received for a duration of 16 ms,
or an internal timer of 32 ms expires.
G4 wait for DR
Final state after a deactivation request. The transceiver remains in this state until DC is
issued.
Unconditional States
Test mode - TM1
Single alternating pulses are sent on the S/T-interface.
Data Sheet
116
2001-03-30
PEF 82912/82913
Functional Description
Test mode - TM2
Continuous alternating pulses are sent on the S/T-interface.
•
Command
Abbr. Code
Remark
Deactivation Request DR
0000
DR - Deactivation Request. Initiates a
complete deactivation by transmitting INFO
0.
Reset
RES
0001
Reset of state machine. Transmission of
Info0. No reaction to incoming infos. RES is
an unconditional command.
Send Single Pulses
TM1
TM2
0010
0011
Send Single Pulses.
Send Continuous
Pulses
Send Continuous Pulses.
Activation Request
AR
1000
1010
Activation Request. This command is used to
start an activation.
Activation Request
Loop
ARL
Activation request loop. The transceiver is
requested to operate an analog loop-back
close to the S/T-interface.
Deactivation
Confirmation
DC
1111
Deactivation Confirmation. Transfers the
transceiver into a deactivated state in which
it can be activated from a terminal (detection
of INFO 0 enabled).
Indication
Abbr. Code
Remark
Timing
TIM
RSY
AR
0000
0100
1000
1011
1100
1111
Interim indication during activation
procedure in G1.
Receiver not
Synchronous
Receiver is not synchronous
Activation Request
INFO 0 received from terminal. Activation
proceeds.
Illegal Code Ciolation CVR
Illegal code violation received. This function
has to be enabled in S_CONF0.EN_ICV.
Activation Indication
AI
DI
Synchronous receiver, i.e. activation
completed.
Deactivation
Indication
Timer (32 ms) expired or INFO 0 received for
a duration of 16 ms after deactivation request
Data Sheet
117
2001-03-30
PEF 82912/82913
Functional Description
2.5.6
S-Transceiver Enable / Disable
The layer-1 part of the S-transceiver can be enabled/disabled with the two bits
S_CONF0.DIS_TR and S_CONF2.DIS_TX.
If DIS_TX=’1’ the transmit buffers are disabled. The receiver will monitor for incoming
data in this configuration. By default the transmitter is disabled (DIS_TX = ’1’).
If the transceiver is disabled (DIS_TR = ’1’, DIS_TX = don’t care) all layer-1 functions are
disabled including the level detection circuit of the receiver. In this case the power
consumption of the S-transceiver is reduced to a minimum.
Data Sheet
118
2001-03-30
PEF 82912/82913
Functional Description
2.5.7
Interrupt Structure S-Transceiver
•
Level Detect
S_STA
7
RINF
0
FECV
0
FSYN
0
0
7
LD
SQRR
MSYN
MFEN
0
0
SQR1
SQR2
SQR3
SQR4
0
7
SQXR
0
ISTAS
0
MASKS
MFEN
0
7
1
1
0
0
0
1
SQX1
SQX2
SQX3
SQX4
MASK
ISTA
7
0
1
LD
RIC
SQC
SQW
LD
RIC
SQC
SQW
0
0
S
0
INT
interr.vsd
Figure 57
Interrupt Structure S-Transceiver
Data Sheet
119
2001-03-30
PEF 82912/82913
Operational Description
3
Operational Description
3.1
Layer 1 Activation/Deactivation
3.1.1
Complete Activation Initiated by Exchange
Figure 58 depicts the procedure if activation has been initiated by the exchange side
(LT).
•
NT
IOM -2
IOM -2
TE
S/T-Reference Point
U-Reference Point
LT
INFO 0
INFO 0
S0
DC
DI
µC
Uk0
SL0
SN0
DC
DI
DC
DC
DI
DI
AR
TL
SL0
TN
PU
AR
DC1)
SN1
SN0
SL1
SL2 (act = 0, dea = 1, uoa = 1)
ARM
UAI
SN2
AR
SN3 (act = 0, sai = 0)
AR
AR
AR2)
INFO 2
INFO 3
SN3 (act = 0, sai = 1)
SL3T (act = 0, dea = 1, uoa = 1)
SN3 (act = 1, sai = 1)
AI
AI
AR
AI
AI
SL3T (act = 1, dea = 1, uoa = 1)
AI
SN3T
INFO 4
AI
AR8/10
SBCX-X or
IPAC-X
DFE-Q
Q-SMINTI
1)C/I-Code DC is not issued in case of simplified state machine is selected
2)C/I-Code AR is optional
ITD08687.vsd
Figure 58
Complete Activation Initiated by Exchange
Data Sheet
120
2001-03-30
PEF 82912/82913
Operational Description
3.1.2
Complete Activation Initiated by TE
Figure 59 depicts the procedure if activation has been initiated by the terminal side (TE).
•
IOM -2
IOM -2
TE
S/T-Reference Point
NT
µC
U-Reference Point
LT
S0
Uk0
INFO 0
INFO 0
DC
DI
DC
DI
SL0
SN0
DC
DI
DC
DI
TIM
PU
AR
INFO 1
TIM
AR
TIM
8ms
PU
AR
TN
AR
DC1)
SN1
SN0
SL1
SL2 (act = 0, dea = 1, uoa = 0)
ARM
UAI
SN2
SN3 (act = 0, sai = 1)
SL3T (uoa = 1)
AR
AR
INFO 2
INFO 0
INFO 3
RSY
AR
AI
AI
AI
AI
SN3 (act = 1, sai = 1)
SL3T (act = 1, dea = 1, uoa = 1)
SN3T
AI
INFO 4
AI
SBCX-X or
IPAC-X
Q-SMINTI
DFE-Q
1)C/I-Code DC is not issued in case of simplified state machine is selected
ITD08688.vsd
Figure 59
Complete Activation Initiated by TE
Data Sheet
121
2001-03-30
PEF 82912/82913
Operational Description
3.1.3
Complete Activation Initiated by NT
Figure 60 depicts the procedure if activation has been initiated by the Q-SMINTI itself
(e.g. after hook-off of a local analog phone).
•
NT
IOM -2
IOM -2
TE
S/T-Reference Point
U-Reference Point
LT
S0
Uk0
INFO 0
INFO 0
DC
DI
µC
DC
DI
SL0
SN0
DC
DI
DC
DI
TIM
PU
AR
TN
AR
ARM
UAI
DC1)
SN1
SN0
SL1
SL2 (act = 0, dea = 1, uoa = 0)
SN2
SN3 (act = 0, sai = 1)
SL3T (uoa = 1)
AR
AR
AR
INFO 2
INFO 3
AR
AI
AI
AI
AI
SN3 (act = 1, sai = 1)
SL3T (act = 1, dea = 1, uoa = 1)
SN3T
AI
INFO 4
AI
SBCX-X or
IPAC-X
DFE-Q
Q-SMINTI
ITD08689.vsd
1)C/I-Code DC is not issued in case of simplified state machine is selected
Figure 60
Complete Activation Initiated by Q-SMINTI
Data Sheet
122
2001-03-30
PEF 82912/82913
Operational Description
3.1.4
Complete Deactivation
Figure 61 depicts the procedure if deactivation has been initiated. Deactivation of layer
1 is always initiated by the exchange.
•
IOM -2
IOM -2
TE
S/T-Reference Point
NT
µC
U-Reference Point
LT
INFO 4
INFO 3
S0
AI
AI
AI
AI
SL3T (act = 1, dea = 1, uoa = 1)
SN3T (act = 1, dea = 1)
Uk0
AI
AR
AI
(AR)
DR
SL3T (act = 0, dea = 0)
DEAC
DC1) 2)
DR
40 ms
SL0
SL0
3 ms
DR
INFO 0
INFO 0
TIM
RSY
DR
DI
DI
DC
DI
DC
DI
&
DC
DC
SBCX-X or
IPAC-X
DFE-Q
Q-SMINTI
1)C/I-Code DR is issued in case of simplified state machine is selected
2)C/I-Code AR might be issued before C/I-Code DC in case of M4
ITD08690.vsd
Validation Algorithm TLL, CRC&TLL or On Change is selected
Figure 61
Complete Deactivation Initiated by Exchange
Data Sheet
123
2001-03-30
PEF 82912/82913
Operational Description
3.1.5
Loop 2
Figure 62 depicts the procedure if loop 2 is closed and opened.
•
IOM -2
S/T-Reference Point
NT
µC
U-Reference Point
LT
IOM -2
TE
S0
Uk0
AI
AI
INFO 4
AI
AI
SL3T (act = 1, dea = 1, uoa = 1)
SN3T (act = 1, dea = 1)
AR
AI
AI
AR8/10
INFO 3
2B+D
MON0:LBBD
MON0:RTN
EOC: LBBD: act = 1
EOC: RTN: act = 1
AIL
AIL
ISTAU.EOC=1
2B+D
AI
AI
ISTAU.EOC=1
2B+D
Q-SMINTI
SBCX-X or
IPAC-X
DFE-Q
ITD10034.vsd
Figure 62
Loop 2
Data Sheet
124
2001-03-30
PEF 82912/82913
Operational Description
3.2
Layer 1 Loopbacks
Test loopbacks are specified by the national PTTs in order to facilitate the location of
defect systems. Four different loopbacks are defined. The position of each loopback is
illustrated in Figure 63.
•
U
U
IOM®-2
S-BUS
Loop 2
Loop 2
S-Transceiver
U-Transceiver
IOM®-2
Loop 1 A
IOM®-2
NT
U-Transceiver
U-Transceiver
Loop 1
IOM®-2
U-Transceiver
Repeater (optional)
Loop 2
Layer-1 Controller
Layer-1 Controller
Exchange
U-Transceiver
IOM-2
Loop 3
U-Transceiver
PBX or TE
loop_2b1q.emf
Figure 63
Test Loopbacks
Loopbacks #1, #1A and #2 are controlled by the exchange. Loopback #3 is controlled
locally on the remote side. All four loopback types are transparent. This means all bits
that are looped back will also be passed onwards in the normal manner. Only the data
looped back internally is processed; signals on the receive pins are ignored. The
propagation delay of actually looped B and D channels data must be identical in all
loopbacks.
Besides the remote controlled loopback stimulation via the EOC channel, the Q-
SMINTI features also direct loopback control via its register set.
3.2.1
Analog Loopback U-Transceiver (No. 3)
Loopback #3 is closed by the U-transceiver as near to the U-interface as possible, i.e.
the loop is closed in the analog part by short circuiting the output to the input. The signal
on the line is ignored in this state. For this reason it is also called analog loopback. All
analog signals will still be passed on to the U-interface.
Before an analog loopback is closed by the appropriate C/I-command ARL (activation
request loopback 3), the U-transceiver shall have been reset.
Data Sheet
125
2001-03-30
PEF 82912/82913
Operational Description
In order to open an analog loopback correctly, force the U-transceiver into the RESET
state. This ensures that the echo coefficients and equalizer coefficients will converge
correctly when activating anew.
3.2.2
Analog Loop-Back S-Transceiver
The Q-SMINTI provides test and diagnostic functions for the S/T interface:
The internal local loop (internal Loop A) is activated by a C/I command ARL or by
setting the bit LP_A (Loop Analog) in the S_CMD register if the layer-1 statemachine is
disabled.
The transmit data of the transmitter is looped back internally to the receiver. The data of
the IOM-2 input B- and D-channels are looped back to the output B- and D-channels.
The S/T interface level detector is enabled, i.e. if a level is detected this will be reported
by the Resynchronization Indication (RSY) but the loop function is not affected.
Depending on the DIS_TX bit in the S_CONF2 register the internal local loop can be
transparent or non transparent to the S/T line.
The external local loop (external Loop A) is activated in the same way as the internal
local loop described above. Additionally the EXLP bit in the S_CONF0 register has to be
programmed and the loop has to be closed externally as described in Figure 64.
The S/T interface level detector is disabled.
•
SX1
100
Ω
SX2
SR1
SR2
100
Ω
Figure 64
External Loop at the S/T-Interface
Data Sheet
126
2001-03-30
PEF 82912/82913
Operational Description
3.2.3
Loopback No.2
For loopback #2 several alternatives exist. Both the type of loopback and the location
may vary. The following loopback types belong to the loopback-#2 category:
• complete loopback (B1,B2,D), in the U-transceiver
• complete loopback (B1,B2,D), in a downstream device
• B1-channel loopback, always performed in the U-transceiver
• B2-channel loopback, always performed in the U-transceiver
All loop variations performed by the U-transceiver are closed as near to the internal
IOM-2 interface as possible.
Normally loopback #2 is controlled by the exchange. The maintenance channel is used
for this purpose. All loopback functions are latched. This allows channel B1 and channel
B2 to be looped back simultaneously.
3.2.3.1 Complete Loopback
When receiving the request for a complete loopback, the U transceiver passes it on to
the downstream device, e.g. the S-bus transceiver. This is achieved by issuing the C/I-
code AIL in the “Transparent” state or C/I = ARL in states different than “Transparent”
(note: this holds true only for the EOC automode). The U transceiver may be
commanded to close the complete loopback itself.
Figure 65 illustrates the two options.
•
S-Transceiver
2B+D
U-Transceiver
2 B+D
loop request
U
loop command
Controller
loop command
lp2bymon8.vsd
Figure 65
Complete Loopback Options in NT-Mode
The complete loopback is either opened under control of the exchange via the
maintenance channel or locally controlled via the µC. No reset is required for loopback
#2. The line stays active and is ready for data transmission.
Data Sheet
127
2001-03-30
PEF 82912/82913
Operational Description
3.2.3.2 Loopback No.2 - Single Channel Loopbacks
Single channel loopbacks are always performed directly in the U-Transceiver. No
difference between the B1-channel and the B2-channel loopback control procedure
exists.
3.2.4
Local Loopbacks Featured By the LOOP Register
Besides the standardized remote loopbacks the U-transceiver features additional local
loopbacks for enhanced test and debugging facilities. The local loopbacks that are
featured by register LOOP are shown in Figure 66. They are closed in the U-transceiver
itself and can be activated regardless of the current operational status.
By the LOOP register it can be configured whether the loopback is closed only for the B1
and/or B2 or for 2B+D channels and whether the loopback is closed towards the internal
IOM-2 interface or towards the U-Interface.
By default the loopbacks are set to transparent mode. In transparent mode the data is
both passed on and looped back. In non-transparent mode the data is not forwarded but
substituted by 1s (idle code).
Besides the loopbacks in the system interface an additional digital loopback (DLB), the
Framer/ Deframer loopback, is featured. It allows to test most digital functions of the U-
transceiver besides the signal processing blocks.
Data Sheet
128
2001-03-30
PEF 82912/82913
Operational Description
•
LOOP.LB1=1
LOOP.LB1=1
LOOP.LB2=1
LOOP.LBBD= 1
&
LOOP.LB2=1
LOOP.LBBD= 1
&
LOOP.U/IOM=
0
LOOP.U/IOM=
1
Analog Part Digital Part
Line Interface
Unit
U-
Framing
DAC
Scrambler
2B1Q
2B1Q
Echo
Canceller
Tx-FIFO
Rx-FIFO
IOM-2
Interface
A
G
C
De-
Scrambler
U-De-
Framing
Σ∆
PDM
Filter
Equalizer
+
ADC
Timing
Recovery
Activation/ Deactivation
Controller
U-Transceiver
Bandgap,
Bias, Refer.
LOOP.DLB= 1
Digital Part
Analog Part
Line Interface
Unit
Tx-FIFO
Rx-FIFO
U-
Scrambler
DAC
2B1Q
2B1Q
Framing
Echo
Canceller
IOM-2
Interface
A
De-
U-De-
Σ∆
PDM
Filter
G
+
Equalizer
Scrambler
Framing
ADC
C
Timing
Recovery
Activation/ Deactivation
Controller
U-Transceiver
Bandgap,
Bias, Refer.
loopreg.emf
Figure 66
Loopbacks Featured by Register LOOP
Data Sheet
129
2001-03-30
PEF 82912/82913
Operational Description
3.3
External Circuitry
3.3.1
Power Supply Blocking Recommendation
The following blocking circuitry is suggested.
•
VDDa_UR
VDDa_UX
VDDa_SR
VDDa_SX
VDDD
3.3V
VDDD
1)
1)
1)
1)
1)
1)
100nF
100nF
100nF
100nF
100nF
100nF
1µF
VSSD
VSSD
GND
VSSa_SX
VSSa_SR
VSSa_UX
VSSa_UR
1) These capacitors should be located as near to the pins as possible
blocking_caps_Smint.vsd
Figure 67
3.3.2
Power Supply Blocking
U-Transceiver
The Q-SMINTI is connected to the twisted pair via a transformer. Figure 68 shows the
recommended external circuitry. The recommended protection circuitry is not displayed.
Note: The integrated hybrid as specified for Version 1.1 is no more available in Version
1.3 and an external hybrid is required.
Data Sheet
130
2001-03-30
PEF 82912/82913
Operational Description
•.
RT
R4
R4
RT
AOUT
n
RCOMP
RPTC
BIN
AIN
>1µ
C
Loop
RCOMP
RPTC
extcirc_U_Q2_exthybrid.emf
BOUT
Figure 68
External Circuitry U-Transceiver
U-Transformer Parameters
The following Table 31 lists parameters of typical U-transformers:
Table 31
U-Transformer Parameters
U-Transformer Parameters
Symbol Value
Unit
U-Transformer ratio;
n
1 : 2
Device side : Line side
Main inductance of windings on the line side
LH
14.5
<75
100
mH
µH
pF
Leakage inductance of windings on the line side LS
Coupling capacitance between the windings on CK
the device side and the windings on the line side
DC resistance of the windings on device side
DC resistance of the windings on line side
1)RB / RL according to equation[2]
RB
RL
2.51)
51)
Ω
Ω
Data Sheet
131
2001-03-30
PEF 82912/82913
Operational Description
Resistors of the External Hybrid R3, R4 and RT
R3 = 1.3 kΩ
R4 = 1.0 kΩ
RT = 9.5 Ω
Resistors on the Line Side RPTC / Chip Side RT
Optional use of up to 2x20 Ω resistors (2xRPTC) on the line side of the transformer
requires compensation resistors RCOMP depending on RPTC
:
2RPTC + 8RCOMP = 40 Ω
(1)
(2)
2RPTC + 4(2RCOMP + 2RT + ROUT + RB) + RL = 135 Ω
RB, RL : see Table 31
ROUT : see Table 38
27 nF Capacitor C
To achieve optimum performance the 27 nF capacitor should be MKT. A Ceramic
capacitor is not recommended.
Tolerances
• Rs: ±1%
• C=27 nF: ±10-20%
• L=14.5 mH: ±10%
3.3.3
S-Transceiver
In order to comply to the physical requirements of ITU recommendation I.430 and
considering the national requirements concerning overvoltage protection and
electromagnetic compatibility (EMC), the S-transceiver needs some additional circuitry.
S-Transformer Parameters
The following Table 32 lists parameters of a typical S-transformer:
Table 32
S-Transformer Parameters
Transformer Parameters
Symbol Value
Unit
Transformer ratio;
n
2 : 1
Device side : Line side
Main inductance of windings on the line side
LH
typ. 30
typ. <3
mH
µH
Leakage inductance of windings on the line side LS
Data Sheet
132
2001-03-30
PEF 82912/82913
Operational Description
Transformer Parameters
Symbol Value
Unit
Coupling capacitance between the windings on CK
the device side and the windings on the line side
typ. <100
pF
DC resistance of the windings on device side
DC resistance of the windings on line side
RB
RL
typ. 2.4
typ. 1.4
Ω
Ω
Transmitter
The transmitter requires external resistors Rstx = 47Ω in order to adjust the output
voltage to the pulse mask (nominal 750 mV according to ITU I.430, to be tested with the
test mode “TM1”) on the one hand and in order to meet the output impedance of
minimum 20 Ω on the other hand (to be tested with the testmode ’Continuous Pulses’)
on the other hand.
Note: The resistance of the S-transformer must be taken into account when
dimensioning the external resistors Rstx. If the transmit path contains additional
components (e.g. a choke), then the resistance of these additional components
must be taken into account, too.
•
47
2 : 1
SX1
SX2
VDD
GND
47
DC Point
extcirc_S.vsd
Figure 69
External Circuitry S-Interface Transmitter
Data Sheet
133
2001-03-30
PEF 82912/82913
Operational Description
Receiver
The receiver of the S-transceiver is symmetrical. 10 kΩ overall resistance are
recommended in each receive path. It is preferable to split the resistance into two
resistors for each line. This allows to place a high resistance between the transformer
and the diode protection circuit (required to pass 96 kHz input impedance test of
ITU I.430 [8] and ETS 300012-1). The remaining resistance (1.8 kΩ) protects the S-
transceiver itself from input current peaks.
•
1k8
8k2
2 : 1
SR1
SR2
VDD
GND
1k8
8k2
DC Point
extcirc_S.vsd
Figure 70
3.3.4
External Circuitry S-Interface Receiver
Oscillator Circuitry
Figure 71 illustrates the recommended oscillator circuit.
•
CLD
XOUT
15.36 MHz
CLD
XIN
Figure 71
Crystal Oscillator
Data Sheet
134
2001-03-30
PEF 82912/82913
Operational Description
Table 33
Crystal Parameters
Parameter
Symbol
Limit Values
Unit
MHz
ppm
pF
Frequency
f
15.36
Frequency calibration tolerance
Load capacitance
+/-60
CL
R1
C0
20
Max. resonance resistance
Max. shunt capacitance
Oscillator mode
20
Ω
7
pF
fundamental
External Components and Parasitics
The load capacitance CL is computed from the external capacitances CLD, the parasitic
capacitances CPar (pin and PCB capacitances to ground and VDD) and the stray
capacitance CIO between XIN and XOUT:
(CLD + CPar) × (CLD + CPar
CL = ------------------------------------------------------------------------ + C IO
(CLD + CPar) + (CLD + CPar
)
)
For a specific crystal the total load capacitance is predefined, so the equation must be
solved for the external capacitances CLD, which is usually the only variable to be
determined by the circuit designer. Typical values for the capacitances CLD connected
to the crystal are 22 - 33 pF.
3.3.5
General
• low power LEDs
• MLT input supports
– APC13112
– AT&T LH1465AB
– discrete as proposed by Infineon
Data Sheet
135
2001-03-30
PEF 82912/82913
Register Description
4
Register Description
4.1
Address Space
7D
H
U-Transceiver
60
H
Monitor Handler
5C
H
IOM-2 Handler
(CDA, TSDP, CR, STI)
40
H
Interrupt, Global Registers
3C
H
S-Transceiver
CI-Register
30
H
2E
22
H
MODEH-Register
reserved
H
H
00
Figure 72
Address Space
Data Sheet
136
2001-03-30
PEF 82912/82913
Register Description
4.2
Interrupts
Special events in the Q-SMINTI are indicated by means of a single interrupt output,
which requests the host to read status information from the Q-SMINTI or transfer data
from/to the Q-SMINTI.
Since only one INT request output is provided, the cause of an interrupt must be
determined by the host reading the interrupt status registers of the Q-SMINTI.
The structure of the interrupt status registers is shown in Figure 73.
MASKU ISTAU
MLT
CI
MLT
CI
MSTI
STOV21
STOV20
STOV11
STOV10
STI21
STI
STOV21
ASTI
FE/NEBE
FE/NEBE
M56
M4
STOV20
STOV11
STOV10
STI21
M56
M4
EOC
6ms
EOC
6ms
12ms
ACK21
ACK20
ACK11
ACK10
STI20
STI20
12ms
STI11
STI11
STI10
STI10
MASK
U
ISTA
U
ISTAS
LD
MASKS
LD
ST
ST
CIC
1
CIC0
CIC1
CIR0
CIC
0
RIC
RIC
CI1E
CIX1
SQC
SQW
SQC
SQW
WOV
S
WOV
S
MOS
0
MOS
1
MRE
MDR
MER
MDA
MIE
MAB
MOCR
MOSR
INT
Figure 73
Q-SMINTI Interrupt Status Registers
Data Sheet
137
2001-03-30
PEF 82912/82913
Register Description
After the Q-SMINTI has requested an interrupt by setting its INT pin to low, the host
must read first the Q-SMINTI interrupt status register (ISTA) in the associated interrupt
service routine. The INT pin of the Q-SMINTI remains active until all interrupt sources
are cleared. Therefore, it is possible that the INT pin is still active when the interrupt
service routine is finished.
Each interrupt indication of the interrupt status registers can selectively be masked by
setting the respective bit in the MASK register.
For some interrupt controllers or hosts it might be necessary to generate a new edge on
the interrupt line to recognize pending interrupts. This can be done by masking all
interrupts at the end of the interrupt service routine (writing FFH into the MASK register)
and writing back the old mask to the MASK register.
Data Sheet
138
2001-03-30
PEF 82912/82913
Register Description
4.3
Register Summary
r(0) = reserved, implemented as zero.
CI Handler
Name
7
1
6
1
5
0
4
3
2
1
0
ADDR R/W RES
reserved
00H
-21H
MODEH
r(0)
0
DIM2 DIM1 DIM0
22H R/W C0H
reserved
23H-
2DH
CIR0
CIX0
CIR1
CIX1
CODR0
CODX0
CIC0
CIC1
S/G
BAS
2EH
2EH
2FH
2FH
R
F3H
W FEH
FEH
TBA2 TBA1 TBA0 BAC
CICW CI1E
CODR1
CODX1
R
CICW CI1E
W FEH
Data Sheet
139
2001-03-30
PEF 82912/82913
Register Description
S-Transceiver
Name
7
6
5
4
0
3
2
0
1
0
0
ADDR R/W RES
30H R/W 40H
S_
CONF0
DIS_
TR
BUS
EN_
ICV
L1SW
EXLP
reserved
31H
S_
CONF2
DIS_
TX
0
0
0
0
0
0
0
0
32H R/W 80H
S_STA
S_CMD
SQRR
SQXR
RINF
XINF
MSYN MFEN
ICV
0
1
FSYN
PD
0
LD
0
33H
R
00H
DPRIO
LP_A
34H R/W 08H
0
0
0
0
SQR1 SQR2 SQR3 SQR4
SQX1 SQX2 SQX3 SQX4
35H
35H
R
00H
00H
0
MFEN
W
reserved
36H-37H
38H
ISTAS
0
1
0
x
1
0
x
1
0
x
1
0
LD
LD
RIC
RIC
SQC
SQC
SQW
SQW
R
00H
MASKS
39H R/W FFH
3AH R/W 02H
S_
DCH_
INH
MODE2-0
MODE
reserved
3BH
Data Sheet
140
2001-03-30
PEF 82912/82913
Register Description
Interrupt, General Configuration
Name
ISTA
7
U
U
6
5
4
0
1
3
2
S
S
1
0
0
1
ADDR R/W RES
ST
ST
CIC
CIC
CDS
WOV
WOV
MOS
MOS
3CH
3CH
R
00H
FFH
MASK
MODE1
W
MCLK
WTC1 WTC2 CFS
RSS2 RSS1
AMOD PPSDX 3EH R/W 00H
3DH R/W 04H
MODE2 LED2 LED1 LEDC
0
0
0
ID
0
0
0
0
DESIGN
3FH
3FH
R
01H
00H
SRES
RES_
0
0
0
RES_ RES_
W
CI/TIC
S
U
Data Sheet
141
2001-03-30
PEF 82912/82913
Register Description
IOM Handler (Timeslot, Data Port Selection,
CDA Data and CDA Control Register)
Name
7
6
5
4
3
2
1
0
ADDR R/W RES
40H R/W FFH
41H R/W FFH
42H R/W FFH
43H R/W FFH
44H R/W 00H
CDA10
CDA11
CDA20
CDA21
Controller Data Access Register
Controller Data Access Register
Controller Data Access Register
Controller Data Access Register
CDA_
TSDP10
DPS
DPS
DPS
DPS
0
0
0
0
0
0
0
0
0
0
0
0
TSS
TSS
TSS
TSS
CDA_
TSDP11
45H R/W 01H
46H R/W 80H
47H R/W 81H
CDA_
TSDP20
CDA_
TSDP21
reserved
48H-
4BH
S_
TSDP_
B1
DPS
DPS
0
0
0
0
0
0
TSS
TSS
4CH R/W 84H
S_
4DH R/W 85H
TSDP_
B2
CDA1_
CR
0
0
0
0
EN_ EN_I1 EN_I0 EN_O1 EN_O0 SWAP 4EH R/W 00H
TBM
CDA2_
CR
EN_ EN_I1 EN_I0 EN_O1 EN_O0 SWAP 4FH R/W 00H
TBM
Data Sheet
142
2001-03-30
PEF 82912/82913
Register Description
IOM Handler (Control Registers, Synchronous Transfer Interrupt
Control)
Name
7
1
6
5
4
3
2
1
0
ADDR R/W RES
50H
reserved
S_CR
CI_CS EN_
D
EN_
B2R
EN_
B1R
EN_
B2X
EN_ D_CS 51H R/W FFH
B1X
CI_CR
DPS_
CI1
EN_
CI1
0
0
0
1
0
52H R/W 04H
53H R/W 40H
54H R/W 00H
55H R/W 00H
56H R/W 08H
MON_
CR
DPS
EN_
MON
0
0
0
0
0
0
MCS
SDS1_
CR
ENS_ ENS_ ENS_
TSS TSS+1 TSS+3
TSS
TSS
SDS2_
CR
ENS_ ENS_ ENS_
TSS TSS+1 TSS+3
IOM_CR
SPU
0
0
TIC_
DIS
EN_
BCL
0
DIS_ DIS_
OD
IOM
MCDA
STI
MCDA21
MCDA20
MCDA11
MCDA10
57H
58H
R
R
FFH
00H
STOV STOV STOV STOV
STI
21
STI
20
STI
11
STI
10
21
0
20
0
11
0
10
0
ASTI
MSTI
ACK
21
ACK
20
ACK
11
ACK
10
58H
W
00H
STOV STOV STOV STOV
21 20 11 10
STI
21
STI
20
STI
11
STI
10
59H R/W FFH
reserved
5AH-
5BH
Data Sheet
143
2001-03-30
PEF 82912/82913
Register Description
MONITOR Handler
Name
MOR
7
6
5
4
3
2
1
0
ADDR R/W RES
MONITOR Receive Data
MONITOR Transmit Data
5CH
5CH
5DH
R
W
R
FFH
FFH
00H
MOX
MOSR
MOCR
MSTA
MCONF
MDR
MRE
0
MER
MRC
0
MDA
MIE
0
MAB
MXC
0
0
0
0
0
0
0
0
0
0
0
0
0
5EH R/W 00H
MAC
0
TOUT 5FH
TOUT 5FH
R
00H
00H
0
0
0
0
W
Data Sheet
144
2001-03-30
PEF 82912/82913
Register Description
Register Summary U-Transceiver
Name
7
0
6
5
4
3
0
2
1
0
0
0
ADDR R/W RES
60H R*/W 14H
OPMODE
UCI FEBE MLT
CI_
SEL
MFILT
EOCR
EOCW
M56 FILTER
M4 FILTER
EOC FILTER
61H R*/W 14H
62H
reserved
0
i1
0
0
i2
0
0
i3
0
0
i4
0
a1
i5
a2
i6
a3
i7
d/m
i8
63H
64H
65H
66H
R
0FH
FFH
01H
00H
a1
i5
a2
i6
a3
i7
d/m
i8
W
i1
i2
i3
i4
M4RMASK
M4WMASK
M4R
M4 Read Mask Bits
M4 Write Mask Bits
67H R*/W 00H
68H R*/W A8H
verified M4 bit data of last received superframe
M4 bit data to be send with next superframe
69H
R
BEH
M4W
6AH R*/W BEH
M56R
0
1
0
0
0
MS2
MS1 NEBE M61
M52
M52
M51 FEBE 6BH
M51 FEBE 6CH
R
W
R
1FH
FFH
00H
01H
M56W
UCIR
1
0
0
0
1
0
0
0
1
0
0
0
M61
C/I code output
C/I code input
6DH
6EH
UCIW
W
TEST
CCRC +-1
Tones
0
40
6FH R*/W 00H
KHz
LOOP
FEBE
NEBE
0
DLB TRANS U/IOM
1
LBBD LB2
LB1
70H R*/W 08H
FEBE Counter Value
NEBE Counter Value
reserved
71H
72H
R
R
00H
00H
73H-
79H
Data Sheet
145
2001-03-30
PEF 82912/82913
Register Description
ISTAU
MLT
MLT
CI
CI
FEBE/ M56
NEBE
M4
M4
EOC
EOC
6ms 12ms 7AH
R
00H
MASKU
FEBE/ M56
NEBE
6ms 12ms 7BH R*/W FFH
reserved
7CH
FW_
VERSION
R
6x
H
FW Version Number
reserved
7DH
7EH-
7FH
*) read back function for test use
Note: Registers, which are denoted as ‘reserved‘, may not be accessed by the µC,
neither for read nor for write operations.
4.4
Reset of U-Transceiver Functions During Deactivation or with
C/I-Code RESET
The following U-transceiver registers are reset during deactivation or with software reset:
Table 34
Reset of U-Transceiver Functions During Deactivation or with C/I-
Code RESET
Register
EOCR
EOCW
M4R
Reset to
0FFFH
0100H
BEH
Affected Bits
all bits
all bits
all bits
M4W
BEH
all bits
M56R
M56W
TEST
1FH
all bits are reset besides MS2 and MS1
all bits
FFH
only bit CCRC is reset
LOOP
only the bits LBBD, LB2 and LB1 are reset
Data Sheet
146
2001-03-30
PEF 82912/82913
Register Description
4.5
U-Transceiver Mode Register Evaluation Timing
The point of time when mode settings are detected and executed differs with the mode
register type. Two different behaviors can be classified:
• evaluation and execution after SW-reset (C/I= RES) or upon transition out of state
’Deactivated’
Note: Write access to these registers/bits is allowed only, while the state machine is
in state Reset or Deactivated.
• immediate evaluation and execution
Below the mode registers are listed and grouped according to the different evaluation
times as stated above.
Table 35
Register
U-Transceiver Mode Register Evaluation Timing
Affected Bits
Registers Evaluated After SW-Reset or Upon Transition Out of State Deactivated
OPMODE
MFILT
bit UCI, MLT
complete register
Immediate Evaluation and Execution
OPMODE
M4RMASK
M4WMASK
TEST
bit FEBE, CI_SEL
complete register
complete register
complete register
complete register
complete register
LOOP
MASKU
Data Sheet
147
2001-03-30
PEF 82912/82913
Register Description
4.6
Detailed C/I Registers
4.6.1
MODEH - Mode Register IOM-2
MODEH
read/write
Address:
DIM1
22H
Value after reset: C0H
7
0
1
1
0
r(0)
0
DIM2
DIM0
DIM2-0
Digital Interface Modes
These bits define the characteristics of the IOM Data Ports (DU, DD). The
DIM0 bit enables/disables the stop/go bit (S/G) evaluation. The DIM1 bit
enables/disables the TIC bus access. The effect of the individual DIM bits is
as follows:
0-0 = Stop/go bit evaluation is disabled
0-1 = Stop/go bit evaluation is enabled
00- = TIC bus access is enabled
01- = TIC bus access is disabled
1xx = Reserved
4.6.2
CIR0
CIR0 - Command/Indication Receive 0
read
Address:
2EH
Value after reset: F3H
7
0
CODR0
CIC0
CIC1
S/G
BAS
Data Sheet
148
2001-03-30
PEF 82912/82913
Register Description
CODR0
CIC0
C/I0 Code Receive
Value of the received Command/Indication code. A C/I-code is loaded in
CODR0 only after being the same in two consecutive IOM-frames and the
previous code has been read from CIR0.
C/I0 Code Change
0 = No change in the received Command/Indication code has been
recognized
1 = A change in the received Command/Indication code has been
recognized. This bit is set only when a new code is detected in two
consecutive IOM-frames. It is reset by a read of CIR0.
CIC1
C/I1 Code Change
0 = No change in the received Command/Indication code has been
recognized
1 = A change in the received Command/Indication code in IOM-channel 1
has been recognized. This bit is set when a new code is detected in
one IOM-frame. It is reset by a read of CIR0.
S/G
Stop/Go Bit Monitoring
Indicates the availability of the upstream D-channel;
0 = Go
1 = Stop
BAS
Bus Access Status
Indicates the state of the TIC-bus:
0 = the Q-SMINTI itself occupies the D- and C/I-channel
1 = another device occupies the D- and C/I-channel
Note: The CODR0 bits are updated every time a new C/I-code is detected in two
consecutive IOM-frames. If several consecutive valid new codes are detected and
CIR0 is not read, only the first and the last C/I code are made available in CIR0 at
the first and second read of that register.
Data Sheet
149
2001-03-30
PEF 82912/82913
Register Description
4.6.3
CIX0
CIX0 - Command/Indication Transmit 0
write
Address:
TBA0
2EH
Value after reset: FEH
7
0
CODX0
TBA2
TBA1
BAC
CODX0
TBA2-0
C/I0-Code Transmit
Code to be transmitted in the C/I-channel 0. The code is only transmitted if
the TIC bus is occupied, otherwise “1s” are transmitted.
TIC Bus Address
Defines the individual address for the Q-SMINTI on the IOM bus.
This address is used to access the C/I- and D-channel on the IOM interface.
Note: If only one device is liable to transmit in the C/I- and D-channels of the
IOM it should always be given the address value ‘7’.
BAC
Bus Access Control
Only valid if the TIC-bus feature is enabled (MODE:DIM2-0).
0 =
1 =
inactive
The Q-SMINTI will try to access the TIC-bus to occupy the C/I-
channel even if no D-channel frame has to be transmitted. It should
be reset when the access has been completed to grant a similar
access to other devices transmitting in that IOM-channel.
Note: Access is always granted by default to the Q-SMINTI with TIC-Bus
Address (TBA2-0, CIX0 register) ‘7’, which has the lowest priority in a
bus configuration.
Data Sheet
150
2001-03-30
PEF 82912/82913
Register Description
4.6.4
CIR1
CIR1 - Command/Indication Receive 1
read
Address:
CICW
2FH
Value after reset: FEH
7
0
CODR1
CI1E
CODR1
CICW
C/I1-Code Receive
C/I-Channel Width
Contains the read back value from CIX1 register (see below)
0 =
1 =
4 bit C/I1 channel width
6 bit C/I1 channel width
CI1E
C/I1-channel Interrupt Enable
Contains the read back value from CIX1 register (see below)
0 =
1 =
Interrupt generation ISTA.CIC of CIR0.CIC1is masked
Interrupt generation ISTA.CIC of CIR0.CIC1 is enabled
4.6.5
CIX1
CIX1 - Command/Indication Transmit 1
write
Address:
CICW
2FH
Value after reset: FEH
7
0
CODX1
CI1E
CODX1
CICW
C/I1-Code Transmit
Bits 5-0 of C/I-channel 1
C/I-Channel Width
0 = 4 bit C/I1 channel width
Data Sheet
151
2001-03-30
PEF 82912/82913
Register Description
1 =
6 bit C/I1 channel width
The C/I1 handler always reads and writes 6-bit values but if 4-bit is selected,
the higher two bits are ignored for interrupt generation. However, in write
direction the full CODX1 code is transmitted, i.e. the host must write the
higher two bits to “1”.
CI1E
C/I1-channel Interrupt Enable
0 =
1 =
Interrupt generation ISTA.CIC of CIR0.CIC1is masked
Interrupt generation ISTA.CIC of CIR0.CIC1 is enabled
4.7
Detailed S-Transceiver Registers
4.7.1
S_CONF0 - S-Transceiver Configuration Register 0
S_ CONF0
read/write
Address:
30H
Value after reset: 40H
7
0
0
DIS_TR
BUS
EN_
ICV
0
L1SW
0
EXLP
DIS_TR
BUS
Disable Transceiver
0 =
1 =
All S-transceiver functions are enabled.
All S-transceiver functions are disabled and powered down (analog
and digital parts).
Point-to-Point / Bus Selection
0 =
1 =
Adaptive Timing (Point-to-Point, extended passive bus).
Fixed Timing (Short passive bus), directly derived from transmit
clock.
EN_ICV Enable Far End Code Violation
0 = normal operation.
Data Sheet
152
2001-03-30
PEF 82912/82913
Register Description
1 =
ICV enabled. The receipt of at least one illegal code violation within
one multi-frame according to ANSI T1.605 is indicated by the C/I
indication ‘1011’ (CVR) in two consecutive IOM frames.
L1SW
Enable Layer 1 State Machine in Software
0 =
1 =
Layer 1 state machine of the Q-SMINTI is used.
Layer 1 state machine is disabled. The functionality must be
realized in software.
The commands are written to register S_CMD and the status read
in the S_STA.
EXLP
External Loop
In case the analog loopback is activated with C/I = ARL or with the LP_A bit
in the S_CMD register the loop is a
0 =
1 =
internal loop next to the line pins
external loop which has to be closed between SR1/SR2 and SX1/
SX2
Note: For the external loop the transmitter must be enabled (S_CONF2:DIS_TX = 0).
4.7.2
S_CONF2 - S-Transmitter Configuration Register 2
S_ CONF2
read/write
Address:
32H
Value after reset: 80H
7
0
0
DIS_TX
0
0
0
0
0
0
DIS_TX
Disable Line Driver
0 =
1 =
Transmitter is enabled
Transmitter is disabled
Data Sheet
153
2001-03-30
PEF 82912/82913
Register Description
4.7.3
S_STA - S-Transceiver Status Register
S_ STA
read
Address:
33H
Value after reset: 00H
7
0
RINF
0
ICV
0
FSYN
0
LD
Important: This register is used only if the Layer 1 state machine of the device is disabled
(S_CONF0:L1SW = 1) and implemented in software! With the layer 1 state machine
enabled, the signals from this register are automatically evaluated.
RINF
Receiver INFO
00 =
01 =
10 =
11 =
Received INFO 0 (no signal)
Received any signal except INFO 0 or INFO 3
reserved
Received INFO 3
ICV
Illegal Code Violation
0 =
1 =
No illegal code violation is detected.
Illegal code violation (ANSI T1.605) in data stream is detected.
FSYN
LD
Frame Synchronization State
0 =
1 =
The S/T receiver is not synchronized.
The S/T receiver has synchronized to the framing bit F.
Level Detection
0 =
1 =
No receive signal has been detected on the line.
Any receive signal has been detected on the line.
Data Sheet
154
2001-03-30
PEF 82912/82913
Register Description
4.7.4
S_CMD - S-Transceiver Command Register
S_ CMD
read/write
Address:
34H
Value after reset: 08H
7
0
0
XINF
DPRIO
1
PD
LP_A
Important: This register - except bit DPRIO - is writable only if the Layer 1 state machine
of the device is disabled (S_CONF0.L1SW = 1) and implemented in software! With the
device layer 1 state machine enabled, the signals from this register are automatically
generated. DPRIO can also be written in intelligent NT mode.
XINF
Transmit INFO
000 = Transmit INFO 0
001 = reserved
010 = Transmit INFO 2
011 =
Transmit INFO 4
100 = Send continuous pulses at 192 kbit/s alternating or 96 kHz
rectangular, respectively (TM2)
101 = Send single pulses at 4 kbit/s with alternating polarity
corresponding to 2 kHz fundamental mode (TM1)
11x = reserved
DPRIO
PD
D-Channel Priority
0 =
1 =
Priority class 1 for D channel access on IOM
Priority class 2 for D channel access on IOM
Power Down
0 =
1 =
The transceiver is set to operational mode
The transceiver is set to power down mode
LP_A
Loop Analog
The setting of this bit corresponds to the C/I command ARL.
Data Sheet
155
2001-03-30
PEF 82912/82913
Register Description
0 =
1 =
Analog loop is open
Analog loop is closed internally or externally according to the EXLP
bit in the S_CONF0 register
4.7.5
SQRR - S/Q-Channel Receive Register
SQRR
read
Address:
SQR3
35H
Value after reset: 00H
7
0
MSYN
MFEN
0
0
SQR1
SQR2
SQR4
MSYN
MFEN
Multi-frame Synchronization State
0 =
The S/T receiver has not synchronized to the received F and M
A
bits
1 =
The S/T receiver has synchronized to the received F and M bits
A
Multiframe Enable
Read-back of the MFEN bit of the SQXR register
0 =
1 =
S/T multiframe is disabled
S/T multiframe is enabled
SQR1-4 Received S/Q Bits
Received Q bits in frames 1, 6, 11 and 16
4.7.6
SQXR- S/Q-Channel Transmit Register
SQXR
write
Address:
SQX3
35H
Value after reset: 00H
7
0
0
MFEN
0
0
SQX1
SQX2
SQX4
Data Sheet
156
2001-03-30
PEF 82912/82913
Register Description
MFEN
Multiframe Enable
Used to enable or disable the multiframe structure.
0 =
1 =
S/T multiframe is disabled
S/T multiframe is enabled
SQX1-4
Transmitted S/Q Bits
Transmitted S bits in frames 1, 6, 11 and 16
4.7.7
ISTAS - Interrupt Status Register S-Transceiver
ISTAS
read
Address:
SQC
38H
Value after reset: 00H
7
0
x
x
x
x
LD
RIC
SQW
These bits are set if an interrupt status occurs and an interrupt signal is activated if the
corresponding mask bit is set to “0”. If the mask bit is set to “1” no interrupt is generated,
however the interrupt status bit is set in ISTAS. RIC, SQC and SQW are cleared by
reading the corresponding source register S_STA, SQRR or writing SQXR,
respectively.
x
Reserved
LD
Level Detection
0 =
1 =
inactive
Any receive signal has been detected on the line. This bit is set to
“1” (i.e. an interrupt is generated if not masked) as long as any
receive signal is detected on the line.
RIC
Receiver INFO Change
0 =
1 =
inactive
RIC is activated if one of the S_STA bits RINF or ICV has changed.
Data Sheet
157
2001-03-30
PEF 82912/82913
Register Description
SQC
S/Q-Channel Change
0 =
1 =
inactive
A change in the received 4-bit Q-channel has been detected. The
new code can be read from the SQRx bits of registers SQRR within
the next multiframe1). This bit is reset by a read access to the
SQRR register.
SQW
S/Q-Channel Writable
0 =
1 =
inactive
The S channel data for the next multiframe is writable.
The register for the S bits to be transmitted has to be written within
the next multiframe. This bit is reset by writing register SQXR.
This timing signal is indicated with the start of every multiframe.
Data which is written right after SQW-indication will be transmitted
with the start of the following multiframe. Data which is written
before SQW-indication is transmitted in the multiframe which is
indicated by SQW.
SQW and SQC could be generated at the same time.
1)
Register SQRR stays valid as long as no code change has been received.
4.7.8
MASKS - Mask S-Transceiver Interrupt
MASKS
read/write
Address:
SQC
39H
Value after reset: FFH
7
0
1
1
1
1
LD
RIC
SQW
Bit 3..0
Mask bits
0 = The transceiver interrupts LD, RIC, SQC and SQW are enabled
1 = The transceiver interrupts LD, RIC, SQC and SQW are masked
Data Sheet
158
2001-03-30
PEF 82912/82913
Register Description
4.7.9
S_MODE - S-Transceiver Mode
S_ MODE
read/write
Address:
MODE
3AH
Value after reset: 02H
7
0
0
0
0
0
DCH_INH
DCH_
INH
D-Channel Inhibit
0 =
1 =
inactive
The S-transceiver blocks the access to the D-channel on S by
inverting the E-bits.
MODE
Mode Selection
000 = reserved
001 = reserved
010 = NT (without D-channel handler)
011 = LT-S (without D-channel handler)
110
Intelligent NT mode (with NT state machine and with D-channel
handler)
111
Intelligent NT mode (with LT-S state machine and with D-channel
handler)
100
101
reserved
reserved
Data Sheet
159
2001-03-30
PEF 82912/82913
Register Description
4.8
Interrupt and General Configuration Registers
4.8.1
ISTA
ISTA - Interrupt Status Register
read
Address:
MOS
3CH
Value after reset: 00H
7
0
0
U
ST
CIC
0
WOV
S
U
U-Transceiver Interrupt
0 =
1 =
inactive
An interrupt was generated by the U-transceiver. Read the ISTAU
register.
ST
CIC
Synchronous Transfer
0 =
1 =
inactive
This interrupt enables the microcontroller to lock on to the IOM®-2
timing, for synchronous transfers.
C/I Channel Change
0 =
1 =
inactive
A change in C/I0 channel or C/I1 channel has been recognized.
The actual value can be read from CIR0 or CIR1.
0 =
inactive
WOV
Watchdog Timer Overflow
0 =
1 =
inactive
Signals the expiration of the watchdog timer, which means that the
microcontroller has failed to set the watchdog timer control bits
WTC1 and WTC2 (MODE1 register) in the correct manner. A reset
out pulse on pin RSTO has been generated by the Q-SMINTI.
S
S-Transceiver Interrupt
Data Sheet
160
2001-03-30
PEF 82912/82913
Register Description
0 =
1 =
inactive
An interrupt was generated by the S-transceiver. Read the ISTAS
register.
MOS
MONITOR Status
0 =
1 =
0 =
inactive
A change in the MONITOR Status Register (MOSR) has occurred.
inactive
Note: A read of the ISTA register clears only the WOV interrupt. The other interrupts are
cleared by reading the corresponding status register.
4.8.2
MASK - Mask Register
MASK
write
Address:
MOS
3CH
Value after reset: FFH
7
0
1
U
ST
CIC
1
WOV
S
Bit 7..0
Mask bits
0 =
1 =
Interrupt is not masked
Interrupt is masked
Each interrupt source in the ISTA register can be selectively masked by setting the
corresponding bit in MASK to ‘1’. Masked interrupt status bits are not indicated when
ISTA is read. Instead, they remain internally stored and pending, until the mask bit is
reset to ‘0’.
Note: In the event of a C/I channel change, CIC is set in ISTA even if the corresponding
mask bit in MASK is active, but no interrupt is generated.
Data Sheet
161
2001-03-30
PEF 82912/82913
Register Description
4.8.3
MODE1 - Mode1 Register
MODE1
read/write
Address:
RSS2
3DH
Value after reset: 04H
7
0
MCLK
CDS
WTC1
WTC2
CFS
RSS1
MCLK
Master Clock Frequency
The Master Clock Frequency bits control the microcontroller clock output
depending on MODE1.CDS = ’0’ or ’1’ (Table Table 2.1.3).
MODE1.CDS = ’0’
3.84 MHz
MODE1.CDS = ’1’
7.68 MHz
00 =
01 =
10 =
11 =
0.96 MHz
1.92 MHz
7.68 MHz
15.36 MHz
disabled
disabled
CDS
Clock Divider Selection
0 =
The 15.36 MHz oscillator clock divided by two is input to the MCLK
prescaler
1 =
The 15.36 MHz oscillator clock is input to the MCLK prescaler.
WTC1, 2 Watchdog Timer Control 1, 2
After the watchdog timer mode has been selected (RSS = ‘11’) the
watchdog timer is started. During every time period of 128 ms the
microcontroller has to program the WTC1 and WTC2 bit in the following
sequence (Chapter 2.2):
10
01
first step
second step
to reset and restart the watchdog timer.
If not, the timer expires and a WOV-interrupt (ISTA Register) together with
a reset out pulse on pin RSTO is generated.
The watchdog timer runs only when the internal IOM®-2 clocks are active,
i.e. the watchdog timer is dead when bit CFS = 1 and the U and S-
transceivers are in state power down.
Data Sheet
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PEF 82912/82913
Register Description
CFS
Configuration Select
0 =
The IOM®-2 interface clock and frame signals are always active,
“Deactivated State” of the U-transceiver and the S-transceiver
included.
1 =
The IOM®-2 interface clocks and frame signals are inactive in the
“Deactivated State” of the U-transceiver and the S-transceiver.
RSS2,
RSS1
Reset Source Selection 2,1
The Q-SMINTI reset sources can be selected according to the table below.
C/I Code Change
--
Watchdog Timer
--
POR/UVD and RST
x
00 =
01 =
10 =
11 =
RSTO disabled (high impedance)
x
--
x
x
x
--
4.8.4
MODE2 - Mode2 Register
MODE2
read/write
Address:
3EH
Value after reset: 00H
7
0
LED2
LED1
LEDC
0
0
0
AMOD PPSDX
LED2,1
LED Control on pin ACT
00 =
01 =
10 =
11 =
High
flashing at 8 Hz
flashing at 1 Hz
Low
LEDC
LED Control Enable
0 =
1 =
LED is controlled by the state machines as defined in Table 3.
LED is controlled via bits LED2,1.
Data Sheet
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PEF 82912/82913
Register Description
AMOD
Address Mode
Selects between direct and indirect register access of the parallel
microcontroller interface.
0 =
Indirect address mode is selected. The address line A0 is used to
select between address (A0 = ‘0’) and data (A0 = ‘1’) register
1 =
Direct address mode is selected. The address is applied to the
address bus (A0-A6)
PPSDX
Push/Pull Output for SDX
0 =
1 =
The SDX pin has open drain characteristic
The SDX pin has push/pull characteristic
4.8.5
ID
ID - Identification Register
read
Address:
3FH
Value after reset: 01H
7
0
0
0
DESIGN
DESIGN Design Number
The design number (DESIGN) allows to identify different hardware
designs1) of the Q-SMINTI by software.
000000: Version 1.1
000001: Version 1.2
000001: Version 1.3
1)
Distinction of different firmware versions is also possible by reading register (7D) in the address space of the
H
U-transceiver (see Chapter 4.11.19).
Data Sheet
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Register Description
4.8.6
SRES - Software Reset Register
SRES
write
Address:
3FH
Value after reset: 00H
7
0
0
0
RES_
0
0
0
RES_S RES_U
CI/TIC
RES_xx Reset_xx
0 = Deactivates the reset of the functional block xx
1 = Activates the reset of the functional block xx.
The reset state is activated as long as the bit is set to ‘1’
Detailed IOM®-2 Handler Registers
4.9
4.9.1
CDAxy - Controller Data Access Register xy
These registers are used for microcontroller access to the IOM®-2 timeslots as well as
for timeslot manipulations. (e.g. loops, shifts, ... see also “Controller Data Access
(CDA)” on Page 31).
CDAxy
read/write
Address: 40-43H
0
7
Controller Data Access Register
Data register CDAxy which can be accessed by the controller.
Register Value after Reset Register Address
CDA10
CDA11
CDA20
CDA21
FFH
FFH
FFH
FFH
40H
41H
42H
43H
Data Sheet
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PEF 82912/82913
Register Description
4.9.2
XXX_TSDPxy - Time Slot and Data Port Selection for CHxy
XXX_TSDPxy
read/write
Address: 44-4DH
0
7
DPS
0
0
0
TSS
Register
Value after Reset
Register Address
CDA_TSDP10
CDA_TSDP11
CDA_TSDP20
CDA_TSDP21
00H (= output on B1-DD)
01H (= output on B2-DD)
80H (= output on B1-DU)
81H (= output on B2-DU)
reserved
44H
45H
46H
47H
48-4BH
S_TSDP_B1
S_TSDP_B2
84H (= output on TS4-DU) 4CH
85H (= output on TS5-DU) 4DH
This register determines the time slots and the data ports on the IOM®-2 Interface for the
data channels xy of the functional units XXX (Controller Data Access (CDA) and S-
transceiver (S)).
Note: The U-transceiver is always in IOM-2 channel 0.
DPS
Data Port Selection
0 =
The data channel xy of the functional unit XXX is output on DD.
The data channel xy of the functional unit XXX is input from DU.
1 =
The data channel xy of the functional unit XXX is output on DU.
The data channel xy of the functional unit XXX is input from DD.
Note: For the CDA (controller data access) data the input is determined by the
CDAx_CR.SWAP bit. If SWAP = ‘0’ the input for the CDAxy data is vice versa to
the output setting for CDAxy. If the SWAP = ‘1’ the input from CDAx0 is vice
versa to the output setting of CDAx1 and the input from CDAx1 is vice versa to
the output setting of CDAx0.
TSS
Timeslot Selection
Selects one of the 12 timeslots from 0...11 on the IOM®-2 interface for the
data channels.
Data Sheet
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PEF 82912/82913
Register Description
4.9.3
CDAx_CR - Control Register Controller Data Access CH1x
CDAx_CR
read/write
Address: 4E-4FH
7
0
0
0
EN_TBM EN_I1
EN_I0
EN_O1 EN_O0 SWAP
Register
Value after Reset Register Address
CDA1_CR 00H
CDA2_CR 00H
4EH
4FH
EN_TBM Enable TIC Bus Monitoring
0 =
1 =
The TIC bus monitoring is disabled
The TIC bus monitoring with the CDAx0 register is enabled. The
TSDPx0 register must be set to 08H for monitoring from DU, or 88H
for monitoring from DD.
EN_I1,
EN_I0
Enable Input CDAx1, CDAx0
0 =
1 =
The input of the CDAx1, CDAx0 register is disabled
The input of the CDAx1, CDAx0 register is enabled
EN_O1,
EN_O0
Enable Output CDAx1, CDAx0
0 =
1 =
The output of the CDAx1, CDAx0 register is disabled
The output of the CDAx1, CDAx0 register is enabled
Data Sheet
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PEF 82912/82913
Register Description
SWAP
Swap Inputs
0 =
The time slot and data port for the input of the CDAxy register is
defined by its own TSDPxy register. The data port for the CDAxy
input is vice versa to the output setting for CDAxy.
1 =
The input (time slot and data port) of the CDAx0 is defined by the
TSDP register of CDAx1 and the input of CDAx1 is defined by the
TSDP register of CDAx0. The data port for the CDAx0 input is vice
versa to the output setting for CDAx1. The data port for the CDAx1
input is vice versa to the output setting for CDAx0. The input
definition for time slot and data port CDAx0 are thus swapped to
CDAx1 and for CDAx1 to CDAx0. The outputs are not affected by
the SWAP bit.
4.9.4
S_CR
S_CR - Control Register S-Transceiver Data
read/write
Address:
51H
Value after reset: FFH
7
0
1
CI_CS
EN_D EN_B2R EN_B1R EN_B2X EN_B1X D_CS
CI_CS
EN_D
C/I Channel Selection
This bit is used to select the IOM channel to which the S-transceiver C/I-
channel is related to.
0 =
1 =
C/I-channel in IOM-channel 0
C/I-channel in IOM-channel 1
Enable Transceiver D-Channel Data
0 =
1 =
The corresponding data path to the transceiver is disabled
The corresponding data path to the transceiver is enabled.
EN_B2R Enable Transceiver B2 Receive Data (transmitter receives from IOM)
0 = The corresponding data path to the transceiver is disabled
Data Sheet
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Register Description
1 =
The corresponding data path to the transceiver is enabled.
EN_B1R Enable Transceiver B1 Receive Data (transmitter receives from IOM)
0 =
1 =
The corresponding data path to the transceiver is disabled
The corresponding data path to the transceiver is enabled.
EN_B2X Enable Transceiver B2 Transmit Data (transmitter transmits to IOM)
0 =
1 =
The corresponding data path to the transceiver is disabled
The corresponding data path to the transceiver is enabled.
EN_B1X Enable Transceiver B1 Transmit Data (transmitter transmits to IOM)
0 =
1 =
The corresponding data path to the transceiver is disabled
The corresponding data path to the transceiver is enabled.
These bits are used to individually enable/disable the D-channel and the
receive/transmit paths for the B-channels for the S-transceiver.
D_CS
D Channel Selection
This bit is used to select the IOM channel to which the S-transceiver D-
channel is related to.
0 =
1 =
D-channel in IOM-channel 0
D-channel in IOM-channel 1
4.9.5
CI_CR - Control Register for CI1 Data
CI_CR
read/write
Address:
52H
Value after reset: 04H
7
0
DPS_CI1 EN_CI1
0
0
0
1
0
DPS_CI1 Data Port Selection CI1 Handler
0 =
1 =
The CI1 data is output on DD and input from DU
The CI1 data is output on DU and input from DD
Data Sheet
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PEF 82912/82913
Register Description
EN_CI1
Enable CI1 Handler
0 =
1 =
CI1 data access is disabled
CI1 data access is enabled
Note: The timeslot for the C/I1 handler cannot be programmed but is fixed
to IOM channel 1.
4.9.6
MON_CR - Control Register Monitor Data
MON_CR
read/write
Address:
53H
Value after reset: 40H
7
0
DPS EN_MON
0
0
0
0
MCS
DPS
Data Port Selection
0 = The Monitor data is output on DD and input from DU
1 = The Monitor data is output on DU and input from DD
EN_MON Enable Output
0 = The Monitor data input and output is disabled
1 = The Monitor data input and output is enabled
MCS
MONITOR Channel Selection
00 = The MONITOR data is output on MON0
01 = The MONITOR data is output on MON1
10 = The MONITOR data is output on MON2
11 = Not defined
Data Sheet
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Register Description
4.9.7
SDS1_CR - Control Register Serial Data Strobe 1
SDS1_CR
read/write
Address:
54H
Value after reset: 00H
7
0
ENS_
TSS
ENS_
TSS+1 TSS+3
ENS_
0
TSS
This register is used to select position and length of the strobe signal 1. The length can
be any combination of two 8-bit timeslot (ENS_TSS, ENS_TSS+1) and one 2-bit timeslot
(ENS_TSS+3).
ENS_
TSS
Enable Serial Data Strobe of timeslot TSS
0 =
1 =
The serial data strobe signal SDS1 is inactive during TSS
The serial data strobe signal SDS1 is active during TSS
ENS_
Enable Serial Data Strobe of timeslot TSS+1
TSS+1
0 =
1 =
The serial data strobe signal SDS1 is inactive during TSS+1
The serial data strobe signal SDS1 is active during TSS+1
ENS_
Enable Serial Data Strobe of timeslot TSS+3 (D-Channel)
TSS+3
0 =
1 =
The serial data strobe signal SDS1 is inactive during the D-channel
(bit7, 6) of TSS+3
The serial data strobe signal SDS1 is active during the D-channel
(bit7, 6) of TSS+3
TSS
Timeslot Selection
Selects one of 12 timeslots on the IOM®-2 interface (with respect to FSC)
during which SDS1 is active high. The data strobe signal allows standard
data devices to access a programmable channel.
Data Sheet
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2001-03-30
PEF 82912/82913
Register Description
4.9.8
SDS2_CR - Control Register Serial Data Strobe 2
SDS2_CR
read/write
Address:
55H
Value after reset: 00H
7
0
ENS_
TSS
ENS_
TSS+1 TSS+3
ENS_
0
TSS
This register is used to select position and length of the strobe signal 2. The length can
be any combination of two 8-bit timeslot (ENS_TSS, ENS_TSS+1) and one 2-bit timeslot
(ENS_TSS+3).
ENS_
TSS
Enable Serial Data Strobe of timeslot TSS
0 =
1 =
The serial data strobe signal SDS2 is inactive during TSS
The serial data strobe signal SDS2 is active during TSS
ENS_
Enable Serial Data Strobe of timeslot TSS+1
TSS+1
0 =
1 =
The serial data strobe signal SDS2 is inactive during TSS+1
The serial data strobe signal SDS2 is active during TSS+1
ENS_
Enable Serial Data Strobe of timeslot TSS+3 (D-Channel)
TSS+3
0 =
1 =
The serial data strobe signal SDS2 is inactive during the D-channel
(bit7, 6) of TSS+3
The serial data strobe signal SDS2 is active during the D-channel
(bit7, 6) of TSS+3
TSS
Timeslot Selection
Selects one of 12 timeslots on the IOM®-2 interface (with respect to FSC)
during which SDS2 is active high. The data strobe signal allows standard
data devices to access a programmable channel.
Data Sheet
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Register Description
4.9.9
IOM_CR - Control Register IOM Data
IOM_CR
read/write
Address:
56H
Value after reset: 08H
7
0
SPU
0
0
TIC_DIS EN_BCL
0
DIS_OD DIS_IOM
SPU
Software Power UP
0 =
1 =
The DU line is normally used for transmitting data.
Setting this bit to ‘1’ will pull the DU line to low. This will enforce the
Q-SMINTI and other connected layer 1 devices to deliver IOM-
clocking.
TIC_DIS TIC Bus Disable
0 =
1 =
The last octet of the last IOM time slot (TS 11) is used as TIC bus.
The TIC bus is disabled. The last octet of the last IOM time slot
(TS 11) can be used like any other time slot. This means that the
timeslots TIC, A/B, S/G and BAC are not available any more.
EN_BCL Enable Bit Clock BCL
0 =
1 =
The BCL clock is disabled (output is high impedant)
The BCL clock is enabled
DIS_OD Disable Open Drain
0 =
1 =
IOM outputs are open drain driver
IOM outputs are push pull driver
DIS_IOM Disable IOM
DIS_IOM should be set to ‘1’ if external devices connected to the IOM
interface should be “disconnected” e.g. for power saving purposes.
However, the Q-SMINTI internal operation is independent of the DIS_IOM
bit.
Data Sheet
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Register Description
0 =
1 =
The IOM interface is enabled
The IOM interface is disabled (FSC, DCL, clock outputs have high
impedance; DU, DD data line inputs are switched off and outputs
are high impedant)
4.9.10
MCDA
MCDA - Monitoring CDA Bits
read
Address:
57H
Value after reset: FFH
7
0
MCDA21
MCDA20
Bit7 Bit6
MCDA11
Bit7 Bit6
MCDA10
Bit7 Bit6
Bit7
Bit6
MCDAxy Monitoring CDAxy Bits
Bit 7 and Bit 6 of the CDAxy registers are mapped into the MCDA register.
This can be used for monitoring the D-channel bits on DU and DD and the
“Echo bits” on the TIC bus with the same register.
4.9.11
STI - Synchronous Transfer Interrupt
STI
read
Address:
STI11
58H
Value after reset: 00H
7
0
STOV21 STOV20 STOV11 STOV10 STI21
STI20
STI10
For all interrupts in the STI register the following logical states are applied
0 =
1 =
Interrupt has not occurred
Interrupt has occurred
STOVxy Synchronous Transfer Overflow Interrupt
Data Sheet
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2001-03-30
PEF 82912/82913
Register Description
Enabled STOV interrupts for a certain STIxy interrupt are generated when
the STIxy has not been acknowledged in time via the ACKxy bit in the ASTI
register. This must be one (for DPS = ‘0’) or zero (for DPS = ‘1’) BCL clock
cycles before the time slot which is selected for the STOV.
STIxy
Synchronous Transfer Interrupt
Depending on the DPS bit in the corresponding TSDPxy register the
Synchronous Transfer Interrupt STIxy is generated two (for DPS = ‘0’) or
one (for DPS = ‘1’) BCL clock cycles after the selected time slot
(TSDPxy.TSS).
Note: ST0Vxy and ACKxy are useful for synchronizing microcontroller accesses and
receive/transmit operations. One BCL clock is equivalent to two DCL clocks.
4.9.12
ASTI - Acknowledge Synchronous Transfer Interrupt
ASTI
write
Address:
58H
Value after reset: 00H
7
0
0
0
0
0
ACK21 ACK20 ACK11 ACK10
ACKxy
Acknowledge Synchronous Transfer Interrupt
After a STIxy interrupt the microcontroller has to acknowledge the interrupt
by setting the corresponding ACKxy bit.
0 = No activity is initiated
1 = Sets the acknowledge bit ACKxy for a STIxy interrupt
4.9.13
MSTI
MSTI - Mask Synchronous Transfer Interrupt
read/write
Address:
59H
Value after reset: FFH
7
0
STOV21 STOV20 STOV11 STOV10 STI21
STI20
STI11
STI10
Data Sheet
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PEF 82912/82913
Register Description
For the MSTI register the following logical states are applied:
0 =
1 =
Interrupt is not masked
Interrupt is masked
STOVxy Mask Synchronous Transfer Overflow xy
Mask bits for the corresponding STOVxy interrupt bits.
STIxy
4.10
Synchronous Transfer Interrupt xy
Mask bits for the corresponding STIxy interrupt bits.
Detailed MONITOR Handler Registers
4.10.1
MOR
MOR - MONITOR Receive Channel
read
Address:
5CH
Value after reset: FFH
7
0
Contains the MONITOR data received in the IOM®-2 MONITOR channel according to
the MONITOR channel protocol. The MONITOR channel (0,1,2) can be selected by
setting the monitor channel select bit MON_CR.MCS.
4.10.2
MOX
MOX - MONITOR Transmit Channel
write
Address:
5CH
Value after reset: FFH
7
0
Contains the MONITOR data to be transmitted in IOM®-2 MONITOR channel according
to the MONITOR channel protocol. The MONITOR channel (0,1,2) can be selected by
setting the monitor channel select bit MON_CR.MCS
Data Sheet
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PEF 82912/82913
Register Description
4.10.3
MOSR
MOSR - MONITOR Interrupt Status Register
read
Address:
5DH
Value after reset: 00H
7
0
0
MDR
MER
MDA
MAB
0
0
0
MDR
MER
MDA
MONITOR channel Data Received
0 =
1 =
inactive
MONITOR channel Data Received
MONITOR channel End of Reception
0 =
1 =
inactive
MONITOR channel End of Reception
MONITOR channel Data Acknowledged
The remote end has acknowledged the MONITOR byte being transmitted.
0 =
1 =
inactive
MONITOR channel Data Acknowledged
MAB
MONITOR channel Data Abort
0 =
1 =
inactive
MONITOR channel Data Abort
4.10.4
MOCR
MOCR - MONITOR Control Register
read/write
Address:
5EH
Value after reset: 00H
7
0
0
MRE
MRC
MIE
MXC
0
0
0
Data Sheet
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PEF 82912/82913
Register Description
MRE
MRC
MONITOR Receive Interrupt Enable
0 =
1 =
MONITOR interrupt status MDR generation is masked.
MONITOR interrupt status MDR generation is enabled.
MR Bit Control
Determines the value of the MR bit:
0 =
MR is always ‘1’. In addition, the MDR interrupt is blocked, except
for the first byte of a packet (if MRE = 1).
1 =
MR is internally controlled by the Q-SMINTI according to
MONITOR channel protocol. In addition, the MDR interrupt is
enabled for all received bytes according to the MONITOR channel
protocol (if MRE = 1).
MIE
MONITOR Interrupt Enable
0 =
1 =
MONITOR interrupt status MER, MDA, MAB generation is masked
MONITOR interrupt status MER, MDA, MAB generation is enabled
MXC
MX Bit Control
Determines the value of the MX bit:
0 =
1 =
The MX bit is always ‘1’.
The MX bit is internally controlled by the Q-SMINTI according to
MONITOR channel protocol.
4.10.5
MSTA
MSTA - MONITOR Status Register
read
Address:
5FH
Value after reset: 00H
7
0
0
0
0
0
0
MAC
0
TOUT
Data Sheet
178
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PEF 82912/82913
Register Description
MAC
MONITOR Transmit Channel Active
0 =
1 =
No data transmission in the MONITOR channel
The data transmission in the MONITOR channel is in progress.
TOUT
Time-Out
Read-back value of the TOUT bit
0 =
1 =
The monitor time-out function is disabled
The monitor time-out function is enabled
4.10.6
MCONF - MONITOR Configuration Register
MCONF
write
Address:
5FH
Value after reset: 00H
7
0
0
0
0
0
0
0
0
TOUT
TOUT
Time-Out
0 =
1 =
The monitor time-out function is disabled
The monitor time-out function is enabled
4.11
Detailed U-Transceiver Registers
OPMODE - Operation Mode Register
4.11.1
The Operation Mode register determines the operating mode of the U-transceiver.
OPMODE
read*)/write
Address: 60H
Reset Value:
14H
7
0
6
5
4
3
0
2
1
0
0
0
UCI
FEBE
MLT
CI_SEL
Data Sheet
179
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PEF 82912/82913
Register Description
UCI
Enable/Disable µC Control of C/I Codes
0 =
µC control disabled - C/I codes are exchanged via IOM®-2
Read access to register UCIR by the µP is still possible
1 =
µC control enabled - C/I codes are exchanged via UCIR and UCIW
registers
In this case, the according C/I-channel on IOM®-2 is idle ‘1111‘
FEBE
Enable/Disable External Write Access to FEBE Bit in Register M56W
0 =
external access to FEBE bit disabled - FEBE bit is controlled by
internal FEBE counter
1 =
external access to FEBE bit enabled - FEBE bit is controlled by
external microprocessor
MLT
Enable/Disable Metallic Loop Termination Function
MLT status is reflected in bit MS2 and MS1 in register M56R
0 =
1 =
MLT disabled
MLT enabled
CI_SEL
C/I Code Output Selection
by CI_SEL the user can switch:
– between the standard C/I indications of the NT state machine as
implemented in today’s IEC-Q versions or
– newly defined C/I code indications which facilitates control and debugging
0 =
1 =
Standard NT state machine
compliant to NT state machine of today’s IEC-Q V4.3-V5.3
Simplified NT state machine
output of newly defined C/I code indications for enhanced
activation/deactivation control and debugging facilities
4.11.2
MFILT - M Bit Filter Options
The M Bit Filter register defines the validation algorithm received Maintenance channel
bits (EOC, M4, M56) of the U-interface have to undergo before they are approved and
passed on to the µC.
MFILT
read*)/write
Address: 61H
Reset Value:
14H
Data Sheet
180
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PEF 82912/82913
Register Description
7
6
5
4
3
2
1
0
M56 FILTER
M4 FILTER
EOC FILTER
M56
FILTER
controls the validation mode of the spare bits (M51, M52, M61) on a per bit
base (see Chapter 2.4.4.3).
X0 =
Apply same filter to M5 and M6 bit data as programmed for M4 bit
data.
X1 =
On Change
M4
Filter
3-bit field which controls the validation mode of the M4 bits on a per bit
base (see Chapter 2.4.4.1).
x00 = On Change
x01 = TLL coverage of M4 bit data
x10 = CRC coverage of M4 bit data
x11 = CRC and TLL coverage of M4 bit data
0xx = M4 bits towards state machine are covered by TLL.
1xx = M4 bits towards state machine are checked by the same
validation algorithm as programmed for the reporting to the system
interface (see Chapter 2.4.4.2).
EOC
3-bit field which controls the processing of EOC messages and its
FILTER
verification algorithm (see Chapter 2.4.3.3).
100 = EOC automatic mode
001 = EOC transparent mode without any filtering
010 = EOC transparent mode with ‘on change’ filtering
011 = EOC transparent mode with Triple-Last-Look (TLL) Filtering
4.11.3
EOCR - EOC Read Register
The EOC Read register contains the last verified EOC message (M1-M3 bits) according
to the verification criterion selected in MFILT.EOC FILTER.
EOCR
read
Address: 63H
2001-03-30
Reset Value: 0FFFH
Data Sheet
181
PEF 82912/82913
Register Description
15
0
14
0
13
0
12
0
11
a1
10
a2
9
8
a3
d/m
7
6
5
4
3
2
1
0
i1
i2
i3
i4
i5
i6
i7
i8
EOC
Embedded Operations Channel (see Chapter 2.4.3)
address field
a1 .. a3
d/m
data/ message indicator
i1 .. i8
4.11.4
information field,
EOCW - EOC Write Register
Via the EOC Write register, the EOC message (M1-M3 bits) of the next available U
superframe can be sent and it will be repeated until a new value is written to EOCW, or
the line is deactivated.
Access to the EOCW register is reasonably only if the EOC channel is operated in
‘Transparent mode’, otherwise conflicts with the internal EOC processor may occur.
EOCW
write
Address: 65H
Reset Value: 0100H
15
0
14
0
13
0
12
11
a1
10
a2
9
8
0
a3
d/m
7
6
5
4
3
2
1
0
i1
i2
i3
i4
i5
i6
i7
i8
Data Sheet
182
2001-03-30
PEF 82912/82913
Register Description
a1 .. a3
d/m
address field
data/ message indicator
i1 .. i8
information field (8 codes are reserved by ANSI/ETSI for diagnostic and
loopback functions)
4.11.5
M4RMASK - M4 Read Mask Register
Via the M4 Read Mask register, the user can selectively control which M4 bit changes
are reported via interrupt requests.
M4RMASK
read*)/write
Address: 67H
Reset Value:
00H
6
7
5
4
3
2
1
0
M4 Read Mask Bits
Bit 0..7
0 =
1 =
M4 bit change indication by interrupt active
M4 bit change indication by interrupt masked
4.11.6
M4WMASK - M4 Write Mask Register
Access to the M4 Write Mask register (M4W) is controlled by the M4WMASK register.
By means of the M4WMASK register the user can control on a per bit base which M4
bits are controlled by the user and which are controlled by the state machine.
M4WMASK
read*)/write
Address: 68H
Reset Value:
A8H
6
7
5
4
3
2
1
0
M4 Write Mask Bits
Data Sheet
183
2001-03-30
PEF 82912/82913
Register Description
Bit 0..7
Bit 6
0 =
1 =
M4 bit is controlled by state machine/ external pins (PS1,2)
M4 bit is controlled by µC
Partial Activation Control External/Automatic,
function corresponds to the MON-8 commands PACE and PACA
0 =
1 =
SAI bit is controlled and UOA bit is evaluated by state machine
SAI bit is controlled via the µC, UOA=1 is reported to the state
machine
4.11.7
M4R - M4 Read
The Read M4 bit register contains the last received and verified M4 bit data.
M4R
read
Address: 69H
Reset Value:
BEH
7
6
5
4
3
2
1
0
AIB
UOA
M46
M45
M44
SCO
DEA
ACT
AIB
Interruption (according to ANSI)
0 =
1 =
indicates interruption
inactive
UOA
SCO
U Activation Only
0 =
1 =
indicates that only U is activated
inactive
Start-on-Command Only Bit
indicates whether the DLC network will deactivate the loop between calls
(defined in Bellcore TR-NWT000397)
0 =
Start-on-Command-Only mode active,
in LULT mode the U-transceiver shall initiate the start-up procedure
only upon command from the network (‘AR’ primitive)
Data Sheet
184
2001-03-30
PEF 82912/82913
Register Description
1 =
normal mode,
if the U-transceiver is operated within a DCL configuration as LULT
it shall start operation as soon as power is applied
DEA
Deactivation Bit
0 =
1 =
LT informs NT that it will turn off
inactive
ACT
Activation Bit
0 =
1 =
layer 2 not established
signals layer 2 ready for communication
4.11.8
M4W - M4 Write Register
Via the M4 bit Write register the M4 bits of the next available U-superframe and
subsequent ones can be controlled. The value is latched and transmitted until a new
value is set.
M4W
write
Address: 6AH
Reset Value:
BEH
7
6
5
4
3
2
1
0
NIB
SAI
M46
CSO
NTM
PS2
PS1
ACT
NIB
SAI
Network Indication Bit
0 =
1 =
no function (reserved for network use)
no function (reserved for network use)
S Activity Indicator
0 =
1 =
S-interface is deactivated
S-interface is activated
CSO
Cold Start Only
0 =
1 =
NT is capable to perform warm starts
NT activation with cold start only
Data Sheet
185
2001-03-30
PEF 82912/82913
Register Description
NTM
PS2
NT Test Mode
0 =
1 =
NT busy in test mode
inactive
Power Status Secondary Source
0 =
1 =
secondary power supply failed
secondary power supply ok
PS1
Power Status Primary Source
0 =
1 =
primary power supply failed
primary power supply ok
ACT
4.11.9
Activation Bit
0 =
1 =
layer 2 not established
signals layer 2 ready for communication
M56R - M56 Read Register
Bits 1 to 3 of the M5, M6 bit Read register contain the last verified M5, M6 bit information.
Bits 5 and 6 reflect the current MLT state (MS2,1). The FEBE/NEBE error indication bits
are accommodated at bit positions 0 and 4. They signal that a FEBE and/or NEBE error
have/has occurred.
M56R
read
Address: 6BH
Reset Value:
1FH
7
0
6
5
4
3
2
1
0
MS2
MS1
NEBE
M61
M52
M51
FEBE
MS1,2
MLT Status
00 =
01 =
10 =
11 =
Normal Mode
Insertion Loss
Quiet Mode
Reserved
Data Sheet
186
2001-03-30
PEF 82912/82913
Register Description
NEBE
M61,
Near-End Block Error
0 =
1 =
Near-End Block Error has occurred
no Near-End Block Error has occurred
Received Spare Bits of last U superframe (M51, M52 and M61 have no
M52, M51 effect on the Q-SMINTI ).
FEBE Far-End Block Error
0 =
1 =
Far-End Block Error has occurred
no Far-End Block Error has occurred
4.11.10 M56W - M56 Write Register
Via the M56 bit Write register, the M5 and M6 bits of the next available superframe can
be set. The value is latched and transmitted as long as a new value is set or the function
is disabled. The FEBE bit can only be set and controlled externally if OPMODE.FEBE is
set to ‘1’.
M56W
write
Address: 6CH
Reset Value:
FFH
7
1
6
1
5
1
4
3
2
1
0
1
M61
M52
M51
FEBE
M61,
Transmitted Spare Bits to next U superframe (M51, M52 and M61 have no
M52, M51 effect on the Q-SMINTI.
FEBE
Far-End Block Error
0 =
1 =
Far-End Block Error has occurred
no Far-End Block Error has occurred
4.11.11 UCIR - C/I Code Read Register
Via the U-transceiver C/I code Read register a microcontroller can access the C/I code
that is output from the state machine.
Data Sheet
187
2001-03-30
PEF 82912/82913
Register Description
UCIR
read
Address: 6DH
Reset Value:
00H
7
0
6
0
5
0
4
3
2
1
0
0
C/I code output
4.11.12 UCIW - C/I Code Write Register
The U-transceiver C/I code Write register allows a microcontroller to control the state of
the U-transceiver. To enable this function bit UCI in register OPMODE must be set to ‘1’
before.
UCIW
write
Address: 6EH
Reset Value:
01H
7
0
6
0
5
0
4
3
2
1
0
0
C/I code input
4.11.13 TEST - Test Register
The Test register sets the U-transceiver in the desired test mode.
TEST
read*)/write
Address: 6FH
Reset Value:
00H
7
0
6
0
5
0
4
3
2
1
0
0
0
CCRC
+-1
40kHz
tones
CCRC
Send Corrupt CRC
0 =
1 =
inactive
send corrupt (inverted) CRCs
+-1 tones Send +/-1 Pulses Instead of +/-3
0 = issues +/-3 pulses during 40 kHz tone generation or in SSP mode
Data Sheet
188
2001-03-30
PEF 82912/82913
Register Description
1 =
issues +/-1 pulses
40kHz
40 kHz Test Signal
0 =
1 =
issues single pulses in state ’Test’
issues a 40 kHz test signal in state ’Test’
4.11.14 LOOP - Loop Back Register
The Loop register controls the digital loopbacks of the U-transceiver. The analog
loopback (No. 3) is closed by C/I= ‘ARL’.
Note: If the EOC automatic mode is selected (MFILT.EOC Filter = ’100’), then register
LOOP is accessed by the internal EOC processor:
EOC-command ’LB1’ (’LB2’) sets LOOP.U/IOM and LOOP.LB1 (LOOP.LB2)
EOC-command ’RTN’ resets LOOP.LB1, LOOP.LB2 and LOOP.LBBD
LOOP
read*)/write
Address: 70H
Reset Value:
08H
7
0
6
5
4
3
1
2
1
0
DLB
TRANS U/IOM
LBBD
LB2
LB1
DLB
Close Framer/Deframer Loopback
– the loopback is closed at the analog/digital interface
– prerequisite is that LB1, LB2, LBBD and U/IOM® are set to ‘0’
– only user data is looped and no maintenance data is looped back1)
0 =
1 =
Framer/Deframer loopback open
Framer/Deframer loopback closed
TRANS
Transparent/ Non-Transparent Loopback
– in transparent mode user data is both passed on and looped back,
whereas in non-transparent mode data is not forwarded but substituted
by ’1’s (idle code) and just looped back2)
®
– if LBBD, LB2, LB1 is closed towards the IOM interface and bit TRANS is
set to ’0’ then the state machine has to be put into state ’Transparent’ first
(e.g. by C/I = DT) before data is output on the U-interface
– bit TRANS has no effect on DLB and the analog loopback (ARL operates
always in transparent mode)
Data Sheet
189
2001-03-30
PEF 82912/82913
Register Description
0 =
1 =
sets transparent loop mode for LBBD, LB2, LB1
sets non-transparent mode for LBBD, LB2, LB1
®
’1’s are sent on the IOM -2/PCM interface in the corresponding
time-slot
®
U/IOM
Close LBBD, LB2, LB1 Towards U or Towards IOM
– Switch that selects whether loopback LB1, LB2 or LBBD is closed
®
towards U or towards IOM -2
– the setting affects all test loops, LBBD, LB2 and LB1
– an individual selection for LBBD, LB2, LB1 is not possible
®
®
0 =
1 =
LB1, LB2, LBBD loops are closed from IOM -2 to IOM -2
LB1, LB2, LBBD loops are closed from U to U
LBBD
LB2
Close Complete Loop (B1, B2, D) Near the System Interface
the direction towards the loop is closed is determined by bit ‘U/IOM’
0 =
1 =
complete loopback open
complete loopback closed
Close Loop B2 Near the System Interface
the direction towards the loop is closed is determined by bit ‘U/IOM’
0 =
1 =
loopback B2 open
loopback B2 closed
LB1
Close Loop B1 Near the System Interface
the direction towards the loop is closed is determined by bit ‘U/IOM’
0 =
1 =
loopback B1 open
loopback B1 closed
1)
If in state Transparent the DLB-loopback is closed from IOM- to IOM, then C/I-code
®
’DC’ instead of ’AI’ is issued on the IOM -2-interface.
2)
If in state Transparent the non-transparent LBBD-loopback is closed from U- to U,
®
then C/I-code ’DC’ instead of ’AI’ is issued on the IOM -2-interface. However, the
correct C/I-code ’AI’ can be read from register UCIR.
4.11.15 FEBE - Far End Block Error Counter Register
The Far End Block Error Counter Register contains the FEBE value. If the register is
read out it is automatically reset to ‘0’.
Data Sheet
190
2001-03-30
PEF 82912/82913
Register Description
FEBE
read
Address: 71H
Reset Value:
00H
6
7
5
4
3
2
1
0
FEBE Counter Value
4.11.16 NEBE - Near End Block Error Counter Register
The Near End Block Error Counter Register contains the NEBE value. If the register is
read out it is automatically reset to ‘0’.
NEBE
read
Address: 72H
Reset Value:
00H
6
7
5
4
3
2
1
0
NEBE Counter Value
4.11.17 ISTAU - Interrupt Status Register U-Interface
The Interrupt Status register U-interface generates an interrupt for the unmasked
interrupt flags. Refer to Chapter 2.4.12 for details on masking and clearing of interrupt
flags. For the timing of the interrupt flags ISTAU(3:0) refer to Chapter 2.4.2.4.
ISTAU
read
Address: 7AH
Reset Value:
00H
7
6
5
4
3
2
1
0
MLT
CI
FEBE/
NEBE
M56
M4
EOC
6ms
12ms
MLT
MLT interrupt indication
0 =
1 =
inactive
MLT interrupt has occurred
Data Sheet
191
2001-03-30
PEF 82912/82913
Register Description
CI
C/I code indication
the CI interrupt is generated independently on OPMODE.UCI
0 =
1 =
inactive
CI code change has occurred
FEBE/
NEBE
Far End/Near End Block Error indication
register M56R notifies whether a FEBE or NEBE has been detected
0 =
1 =
inactive
FEBE/NEBE occurred
M56
M4
Validated new M56 bit data received from U-interface
0 =
1 =
inactive
change of any M5, M6 bit has been detected in receive direction
Validated new M4 bit data received from U-interface
0 =
1 =
inactive
change of any M4 bit has been detected in receive direction
EOC
Validated new EOC data received from U-interface
0 =
1 =
inactive
new EOC message has been received and acknowledged from U
6 ms
6 ms timer for the transmission of EOC commands on U
0 =
1 =
inactive
indicates when a EOC command is going to be issued on U
12 ms
Superframe marker (each 12 ms) is going to be issued on U in transmit
direction
Bellcore test requirement: SR-NWT-002397
0 =
1 =
inactive
indicates when a SF marker is going to be transmitted on U
4.11.18 MASKU - Mask Register U-Interface
The Interrupt Mask register U-Interface selectively masks each interrupt source in the
ISTAU register by setting the corresponding bit to ‘1’.
Data Sheet
192
2001-03-30
PEF 82912/82913
Register Description
MASKU
read*)/write
Address: 7BH
Reset Value:
FFH
6
7
5
4
3
2
1
0
MASKU Value
Bit 0..7
Mask bits
0 =
1 =
interrupt active
interrupt masked
4.11.19 FW_VERSION
FW_VERSION Register contains the Firmware Version number
FW_VERSION
read
Address: 7DH
Reset value: 6xH
7
6
5
4
3
2
1
0
Firmware Version Number
Version 1.2 : 6DH
Version 1.3 : 6CH
Data Sheet
193
2001-03-30
PEF 82912/82913
Electrical Characteristics
5
Electrical Characteristics
5.1
Absolute Maximum Ratings
•
Parameter
Symbol Limit Values
Unit
°C
°C
V
Ambient temperature under bias
Storage temperature
TA
-40 to 85
– 65 to 150
4.2
TSTG
VDD
Maximum Voltage on VDD
Maximum Voltage on any pin with respect to VS
ground
-0.3 to VDD + 3.3
(max. < 5.5)
V
ESD integrity (according EIA/JESD22-A114B (HBM)): 2 kV
Note: Stress above those listed here may cause permanent damage to the device.
Exposure to absolute maximum ratings conditions for extended periods may affect
device reliability.
Line Overload Protection
The Q-SMINTI is compliant to ESD tests according to ANSI / EOS / ESD-S 5.1-1993
(CDM), EIA/JESD22-A114B (HBM) and to Latch-up tests according to JEDEC EIA /
JESD78. From these tests the following max. input currents are derived (Table 36):
•
Table 36
Test
Maximum Input Currents
Pulse Width Current
Remarks
ESD
100 ns
5 ms
--
1.3 A
3 repetitions
Latch-up
DC
+/-200 mA
10 mA
2 repetitions, respectively
Data Sheet
194
2001-03-30
PEF 82912/82913
Electrical Characteristics
5.2
DC Characteristics
•
VDD/VDDA = 3.3 V +/- 5% ; VSS/VSSA = 0 V; TA = -40 to 85 °C
Digital
Pins
Parameter
Symbol Limit Values Unit Test
Condition
min. max.
All
Input low voltage
Input high voltage
VIL
-0.3
2.0
0.8
V
V
V
VIH
5.25
0.45
All except Output low voltage
DD/DU
VOL1
IOL1 = 3.0 mA
IOH1 = 3.0 mA
IOL2 = 4.0 mA
IOH2 = 4.0 mA
ACT,LP2I
MCLK
Output high voltage
VOH1
VOL2
VOH2
ILI
2.4
2.4
V
V
V
DD/DU
ACT,LP2I
MCLK
Output low voltage
0.45
Output high voltage
(DD/DU push-pull)
All
Input leakage current
10
10
µA
µA
0 V ≤ VIN ≤ VDD
0 V ≤ VIN ≤ VDD
Output leakage current ILO
Analog
Pins
AIN, BIN Input leakage current
ILI
70
µA
0 V ≤ VIN ≤ VD
D
Table 37
S-Transceiver Characteristics
Pin
Parameter
Symbol Limit Values
min. typ.
Unit Test
Condition
max.
SX1,2 Absolute value of
output pulse
VX
2.03 2.2
2.31
V
RL = 50 Ω
amplitude
(VSX2 - VSX1
)
SX1,2 S-Transmitter
output impedance
ZX
ZR
10
34
kΩ
see 1)
see 2)3)
0
SR1,2 S-Receiver input
impedance
10
100
kΩ
Ω
VDD = 3.3 V
VDD = 0 V
1)
Requirement ITU-T I.430, chapter 8.5.1.1a): ’At all times except when transmitting a binary zero, the output
impedance , in the frequency range of 2kHz to 1 MHz, shall exceed the impedance indicated by the template
in Figure 11. The requirement is applicable with an applied sinusoidal voltage of 100 mV (r.m.s value)’
Data Sheet
195
2001-03-30
PEF 82912/82913
Electrical Characteristics
2)
3)
Requirement ITU-T I.430, chapter 8.5.1.1b): ’When transmitting a binary zero, the output impedance shall be
> 20 Ω.’: Must be met by external circuitry.
Requirement ITU-T I.430, chapter 8.5.1.1b), Note: ’The output impedance limit shall apply for a nominal load
impedance (resistive) of 50 Ω. The output impedance for each nominal load shall be defined by determining
the peak pulse amplitude for loads equal to the nominal value +/- 10%. The peak amplitude shall be defined
as the the amplitude at the midpoint of a pulse. The limitation applies for pulses of both polarities.’
Table 38
U-Transceiver Characteristics
Limit Values
Unit
min.
typ.
max.
Receive Path
Signal / (noise + total harmonic distortion)1) 652)
dB
3)
DC-level at AD-output
45
4
50
5
55
%
Threshold of level detect
16 (PEF mV
(measured between AIN and BIN with
respect to zero signal)
82912)
peak
9 (PEF
82913)
Input impedance AIN/BIN
80
kΩ
Transmit Path
Signal / (noise + total harmonic distortion)4) 70
dB
V
Common mode DC-level
1.61
1.65
2.5
1.69
35
Offset between AOUT and BOUT
mV
V
Absolute peak voltage for a single +3 or -3 2.42
pulse measured between AOUT and
BOUT5)
2.58
Output impedance AOUT/BOUT:
Power-up
Power-down
0.8
3
1.5
6
Ω
Ω
1)
Test conditions: 1.4 Vpp differential sine wave as input on AIN/BIN with long range (low, critical range).
Versions PEF 8x913 with enhanced performance of the U-interface are tested with tightened limit values
The percentage of the "1 "-values in the PDM-signal.
2)
3)
4)
Interpretation and test conditions: The sum of noise and total harmonic distortion, weighted with a low pass
filter 0 to 80 kHz, is at least 70 dB below the signal for an evenly distributed but otherwise random sequence
of +3, +1, -1, -3.
5)
The signal amplitude measured over a period of 1 min. varies less than 1%.
Data Sheet
196
2001-03-30
PEF 82912/82913
Electrical Characteristics
5.3
Capacitances
TA = 25 °C, 3.3 V ± 5 % VSSA = 0 V, VSSD = 0 V, fc = 1 MHz, unmeasured pins grounded.
•
Table 39 Pin Capacitances
Parameter
Symbol Limit Values Unit Remarks
min. max.
Digital pads:
Input Capacitance
I/O Capacitance
CIN
CI/O
7
7
pF
pF
Analog pads:
Load Capacitance
CL
3
pF
pin AIN, BIN
5.4
Power Consumption
•
Power Consumption
VDD=3.3 V, VSS=0 V, Inputs at VSS/VDD, no LED connected, 50% bin. zeros, no output
loads except SX1,2 (50 Ω1))
Parameter
Limit Values
min. typ. max.
Unit Test Condition
Operational
U and S enabled, IOM-2 off
235
200
mW U: ETSI loop 1 (0 m)
mW U: ETSI Loop 2.(typical
line)
Power Down
15
mW
1)
50 Ω (2 x TR) on the S-bus.
5.5
Supply Voltages
VDD = + Vdd ± 5%
D
VDD = + Vdd ± 5%
A
The maximum sinusoidal ripple on VDD is specified in the following figure:
Data Sheet
197
2001-03-30
PEF 82912/82913
Electrical Characteristics
•
mV
(peak)
200
100
10
60
Frequency Ripple
80 100
Frequency / kHz
ITD04269.vsd
Figure 74
Maximum Sinusoidal Ripple on Supply Voltage
Data Sheet
198
2001-03-30
PEF 82912/82913
Electrical Characteristics
5.6
AC Characteristics
TA = -40 to 85 °C, VDD = 3.3 V ± 5%
Inputs are driven to 2.4 V for a logical "1" and to 0.4 V for a logical "0". Timing
measurements are made at 2.0 V for a logical "1" and 0.8 V for a logical "0". The AC
testing input/output waveforms are shown in Figure 75.
•
2.4
2.0
0.8
2.0
0.8
Device
Under
Test
Test Points
0.45
CLoad=50 pF
ITS00621.vsd
Figure 75
Input/Output Waveform for AC Tests
Symbol
Parameter
Limit values
Min Max
Unit
All Output Pins
Fall time
30
30
ns
ns
Rise time
Data Sheet
199
2001-03-30
PEF 82912/82913
Electrical Characteristics
5.6.1
IOM®-2 Interface
•
DCL
t4
t5
Data valid
t7
DU/DD
(Input)
t6
DU/DD
(Output)
last bit
first bit
t8
DU/DD
(Output)
bit n
bit n+1
t18
SDS1,2
IOM-Timing.vsd
Figure 76
IOM®-2 Interface - Bit Synchronization Timing
•
t
9
FSC
DCL
t
10
t
t
3
2
t
1
BCL
t
t
12
11
t
t
13
14
®
Figure 77
IOM -2 Interface - Frame Synchronization Timing
Data Sheet
200
2001-03-30
PEF 82912/82913
Electrical Characteristics
•
Parameter
Symbol Limit values
Unit
IOM®-2 Interface
Min
565
200
200
20
Typ
651
310
310
Max
735
420
420
DCL period
DCL high
t1
t2
t3
t4
t5
ns
ns
ns
ns
ns
ns
DCL low
Input data setup
Input data hold
20
Output data from high impedance to t6
active
100
(FSC high or other than first timeslot)
Output data from active to high
impedance
t7
100
80
ns
Output data delay from clock
FSC high
t8
t9
ns
ns
50% of
FSC
cycle
time
FSC advance to DCL
BCL high
t10
t11
t12
t13
t14
t15
65
130
651
651
1302
130
195
735
735
1470
195
30
ns
ns
ns
ns
ns
ns
ns
565
565
1130
65
BCL low
BCL period
FSC advance to BCL
DCL, FSC rise/fall
Data out fall (C = 50 pF, R = 2 kΩ to t16
200
L
V , open drain)
DD
Data out rise/fall
t17
t18
150
120
ns
ns
(C = 50 pF, tristate)
L
Strobe Signal Delay
Note: At the start and end of a reset period, a frame jump may occur. This results in a
DCL, BCL and FSC high time of min. 130 ns after this specific event.
Data Sheet
201
2001-03-30
PEF 82912/82913
Electrical Characteristics
5.6.2
Serial µP Interface
•
t1
t5
t4
t2
t3
CS
SCLK
SDR
t11
t6
t7
t9
t8
SDX
t10
SCI_timing.vsd
Figure 78
Serial Control Interface
•
Parameter
Symbol
Limit values
Unit
SCI Interface
Min
200
80
Max
SCLK cycle time
SCLK high time
SCLK low time
t1
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
t2
t3
80
CS setup time
t4
20
CS hold time
t5
10
SDR setup time
SDR hold time
t6
15
t7
15
SDX data out delay
CS high to SDX tristate
SCLK to SDX active
CS high to SCLK
t8
60
40
60
t9
t10
t11
10
Data Sheet
202
2001-03-30
PEF 82912/82913
Electrical Characteristics
5.6.3
Parallel µP Interface
Siemens/Intel Bus Mode
•
tRR
tRI
RD x CS
tDF
tDH
tRD
AD0 - AD7
Data
Itt00712.vsd
Figure 79
Microprocessor Read Cycle
•
tWW
tWI
WR x CS
tDW
tWD
AD0 - AD7
Data
Itt00713.vsd
Figure 80
Microprocessor Write Cycle
•
tAA
tAD
ALE
WR x CS or
RD x CS
tALS
tLA
tAL
AD0 - AD7
Address
Itt00714.vsd
Figure 81
Multiplexed Address Timing
Data Sheet
203
2001-03-30
PEF 82912/82913
Electrical Characteristics
•
WR x CS or
RD x CS
tAS
tAH
A0 - A6
Address
Itt009661.vsd
Figure 82
Non-Multiplexed Address Timing
Motorola Bus Mode
•
R / W
tRWD
tDSD
tRR
tRI
CS x DS
tDF
tDH
tRD
D0 - D7
Data
Itt00716.vsd
Figure 83
Microprocessor Read Timing
•
R / W
tRWD
tDSD
tWI
tWW
CS x DS
tWD
tDW
D0 - D7
Data
Itt09679.vsd
Figure 84
Microprocessor Write Cycle
Data Sheet
204
2001-03-30
PEF 82912/82913
Electrical Characteristics
•
CS x DS
A0 - A6
tAS
tAH
Address
Itt09662.vsd
Figure 85
Non-Multiplexed Address Timing
Microprocessor Interface Timing
•
Parameter
Symbol
Limit Values Unit
min.
20
10
10
10
10
10
10
10
80
max.
ALE pulse width
tAA
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Address setup time to ALE
Address hold time from ALE
Address latch setup time to WR, RD
Address setup time
tAL
tLA
tALS
tAS
Address hold time
tAH
tAD
tDSD
tRR
tRD
tDH
tDF
ALE guard time
DS delay after R/W setup
RD pulse width
Data output delay from RD
Data hold from RD
80
25
0
Data float from RD
RD control interval1)
tRI
70
60
10
10
70
10
W pulse width
tWW
tDW
tWD
tWI
Data setup time to W x CS
Data hold time W x CS
W control interval
R/W hold from CS x DS inactive
tRWD
1)
control interval: t ' is minimal 70ns for all registers except ISTAU, FEBE and NEBE. However, the time
RI
between two consecutive read accesses to one of the registers ISTAU, FEBE or NEBE, respectively, must be
longer than 330ns. This does not limit t of read sequences, which involve intermediate read access to other
RI
registers, as for instance: ISTAU -(t )- ISTA -(t )- ISTAH -(t )- ISTAU.
RI
RI
RI
Data Sheet
205
2001-03-30
PEF 82912/82913
Electrical Characteristics
5.6.4
Reset
Table 40
Reset Input Signal Characteristics
Symbol Limit Values
Parameter
Unit Test Conditions
min.
typ.
max.
Length of active tRST
low state
4
ms
Power On
the 4 ms are assumed to
be long enough for the
oscillator to run correctly
2 x
After Power On
DCL
clock
cycles
+ 400
ns
DelaytimeforµC tµC
accessafterRST
rising edge
500
ns
•
t
µC
RST
tRST
ITD09823.vsd
Figure 86
Reset Input Signal
Data Sheet
206
2001-03-30
PEF 82912/82913
Electrical Characteristics
5.6.5
Undervoltage Detection Characteristics
•
VDD
VHYS
VDET
VDDmin
t
RSTO
tACT
tACT
t
tDEACT
tDEACT
VDDDET.VSD
Figure 87
Table 41
Undervoltage Control Timing
Parameters of the UVD/POR Circuit
VDD= 3.3 V ± 5 %; VSS= 0 V; TA = -40 to 85 °C
Parameter
Symbol
Limit Values
Unit Test Condition
min.
2.7
30
typ.
max.
Detection Threshold1)
Hysteresis
VDET
VHys
2.8
2.92
90
V
VDD = 3.3 V ± 5 %
mV
V/µs
Max. rising/falling VDD dVDD/dt
edge for activation/
0.1
deactivation of UVD
Max. rising VDD for
power-on2)
0.1
V/
ms
Min. operating voltage VDDmin 1.5
V
Data Sheet
207
2001-03-30
PEF 82912/82913
Electrical Characteristics
Unit Test Condition
VDD= 3.3 V ± 5 %; VSS= 0 V; TA = -40 to 85 °C
Parameter
Symbol
Limit Values
min.
typ.
max.
10
Delay for activation
of RSTO
tACT
µs
Delay for deactivation
of RSTO
tDEACT
64
ms
1)
The Detection Threshold V
is far below the specified supply voltage range of analog and digital parts of the
DET
®
Q-SMINT I. Therefore, the board designer must take into account that a range of voltages is existing, where
neither performance and functionality of the Q-SMINT I are guaranteed, nor a reset is generated.
®
2)
If the integrated Power-On Reset of the Q-SMINTI is selected (VDDDET = ’0’) and the supply voltage V is
DD
ramped up from 0V to 3.3V +/- 5%, then the Q-SMINTI is kept in reset during V
< V < V
+ V
.
DDmin
DD
DET
Hys
V
must be ramped up so slowly that the Q-SMINTI leaves the reset state after the oscillator circuit has
DD
already finished start-up. The start-up time of the oscillator circuit is typically in the range between 3ms and
12ms.
Data Sheet
208
2001-03-30
PEF 82912/82913
Package Outlines
6
Package Outlines
•
Plastic Package, P-MQFP-64
(Metric Quad Flat Package)
Data Sheet
209
2001-03-30
PEF 82912/82913
Package Outlines
•
Plastic Package, P-TQFP-64
(Thin Quad Flat Package)
Data Sheet
210
2001-03-30
PEF 82912/82913
Appendix: Differences between Q- and T-SMINT‚I
7
Appendix: Differences between Q- and T-SMINTI
The Q- and T-SMINTI have been designed to be as compatible as possible. However,
some differences between them are unavoidable due to the different line codes 2B1Q
and 4B3T used for data transmission on the Uk0 line.
Especially the pin compatibility between Q- and T-SMINTI allows for one single PCB
design for both series with only some mounting differences. The µC software can
distinguish between the Q- and T-series by reading the identification register via the
IOM-2 (MONITOR channel identification command) or the µC interface (register
ID.DESIGN), respectively.
The following chapter summarizes the main differences between the Q- and T-SMINTI.
7.1
Pinning
Table 42
Pin Definitions and Functions
Pin
Q-SMINTI: 2B1Q
T-SMINTI: 4B3T
T/MQFP-64
16
55
41
Metallic Termination Input Tie to ‘1‘
(MTI)
Power Status (primary)
(PS1)
Tie to ‘1‘
Power Status (secondary) Tie to ‘1‘
(PS2)
Data Sheet
211
2001-03-30
PEF 82912/82913
Appendix: Differences between Q- and T-SMINT‚I
7.2
U-Transceiver
7.2.1
U-Interface Conformity
•
Table 43
Related Documents to the U-Interface
Q-SMINTI: 2B1Q
T-SMINTI: 4B3T
ETSI: TS 102 080
conform to annex A
compliant to 10 ms
interruptions
conform to annex B
ANSI: T1.601-1998
(Revision of ANSI T1.601- MLT input and decode logic
1992)
conform
not required
not required
CNET: ST/LAA/ELR/DNP/ conform
822
RC7355E
conform
not required
conform
FTZ-Richtlinie 1 TR 220
not required
Data Sheet
212
2001-03-30
PEF 82912/82913
Appendix: Differences between Q- and T-SMINT‚I
7.2.2
U-Transceiver State Machines
•
T14E
T14S
TL
.
.
SN0
SN0
T14S
AR or TL
Pending Timing
DC
Deactivated
DC
Any State
SSP or
T14S
TIM
DI
.
SP
C/I= 'SSP'
.
SN0
DI
Test
DR
IOM Awaked
PU
AR or TL
T1S, T11S
DI
DI & NT-AUTO
T1S,
T11S
.
.
.
SN0
TN
Alerting 1
DR
T11E
TN
T1S
T11S
Reset
Alerting
Any State
Pin-RST or
C/I= 'RES'
DR
PU
DC
T11E
ARL
T12S
T12S
T12S
.
SN1
.
.
SN1
SN1
EC-Training AL
DC
EC-Training
DC
EC-Training 1
DR
DI
LSEC or T12E
LSEC or T12E
act=0
LSUE
or T1E
.
SN0
SN3
EQ-Training
Wait for SF AL
DC
DC
BBD0 & FD
BBD1 & SFD
T20S
SN2
1) act=1/03)
SN3/SN3T
Pend.Deact. S/T
LSUE
or T1E
.
SN3T
act=0
Analog Loop Back
AR
LOF
DI
Wait for SF
DC
DR
T20E &
dea=0
LSUE
BBD0 & SFD
LOF
SN3/SN3T1)
act=0
dea=0
LSUE
Synchronized 1
DC
uoa=1
uoa=0
LOF
SN3/SN3T1)
act=0
dea=0
LSUE
Synchronized 2
2)
AR/ARL
Al
uoa=0
dea=0
LSUE
LOF
El1
SN3/SN3T 1) act=1
Wait for Act
2)
AR/ARL
act=1
act=0
act=1
Transparent
LOF
El1
uoa=0
dea=0
LSUE
Any State
DT or
C/I='DT'
SN3T
Yes
2)
AI/AIL
No
uoa=1
act=1 & Al
?
dea=0
uoa=0
LSUE
SN3/SN3T 1)
act=0
Error S/T
act=0
2)
AR/ARL
dea=1
SN3/SN3T1) act=1/03)
Pend.Deact. U
LOF
.
SN0
LOF
Pend Receive Res.
T13S
T7S
EI1
DC
LSU
LSU or ( /LOF & T13E )
T7S
.
SN0
Receive Reset
T7E & DI
TL
DR
Figure 88
INTC-Q Compatible State Machine Q-SMINTI: 2B1Q
Data Sheet
213
2001-03-30
PEF 82912/82913
Appendix: Differences between Q- and T-SMINT‚I
•
T14E
.
.
SN0
SN0
T14S
AR or TL
T14S
TL
Pending Timing
DC
Deactivated
DC
Any State
SSP or
T14S
TIM
DI
.
SP
C/I= 'SSP'
.
SN0
DI
Test
IOM Awaked
PU
DR
TIM
AR or TL
T1S, T11S
TN
DI
T1S,
T11S
.
.
.
SN0
TN
Alerting 1
DR
T11E
T1S
T11S
Reset
Alerting
PU
Any State
Pin-RST or
C/I= 'RES'
DR
T11E
ARL
T12S
T12S
T12S
.
SN1
.
.
SN1
SN1
EC-Training AL
DR
EC-Training
PU
EC-Training 1
DR
DI or TIM
LSEC or T12E
LSEC or T12E
LSUE
or T1E
.
SN0
act=0
SN3
EQ-Training
Wait for SF AL
DR
PU
BBD0 & FD
BBD1 & SFD
T20S
SN2
1) act=1/03)
SN3/SN3T
LSUE
or T1E
.
SN3T
act=0
Analog Loop Back
AR
LOF
Pend.Deact. S/T
Wait for SF
PU
DR
T20E &
dea=0
DI or
TIM
LSUE
BBD0 & SFD
LOF
SN3/SN3T1)
act=0
dea=0
Synchronized 1
LSUE
PU
uoa=1
uoa=0
LOF
SN3/SN3T1)
act=0
dea=0
LSUE
Synchronized 2
2)
AR/ARL
Al
uoa=0
dea=0
LSUE
LOF
El1
SN3/SN3T 1) act=1
Wait for Act
2)
AR/ARL
act=1
act=0
act=1
Transparent
LOF
El1
uoa=0
dea=0
LSUE
Any State
DT or
C/I='DT'
SN3T
Yes
2)
AI/AIL
No
uoa=1
act=1 & Al
?
dea=0
uoa=0
LSUE
SN3/SN3T 1)
act=0
Error S/T
act=0
2)
AR/ARL
dea=1
SN3/SN3T1) act=1/03)
LOF
.
SN0
LOF
Pend Receive Res.
Pend.Deact. U
T13S
T7S
DR
DR
LSU
LSU or ( /LOF & T13E )
T7S
.
SN0
T7E & TIM
T7E & DI
Receive Reset
TL
DR
Figure 89
Simplified State Machine Q-SMINTI: 2B1Q
Data Sheet
214
2001-03-30
PEF 82912/82913
Appendix: Differences between Q- and T-SMINT‚I
•
AWR
TIM
AR
U0
IOM Awaked
DC
U0
AWR
AWR
Deactivated
DC
DI
AR
T6S
T05E
U1W
Start Awaking Uk0
RSY
T6S
T05S
T05S
U0
Deactivating
DC
AWT
T6S
T6E
U0
Awake Signal Sent
RSY
AWR
T13S
U0
Ack. Sent / Received
RSY
AWT
T13S
U1W
Sending Awake-Ack.
RSY
T13E
AWR
T13S
(DI & T05E)
U0
T12S
U1A
(U0 & T12E)
T05S
SP / U0
Test
DI
Synchronizing
RSY
Pend. Deactivation
DR
DR
U2
T05S
SSP
ANY STATE
RES
DT
DI
U1
U0
SBC Synchronizing
AR / ARL
LOF
AI
U0
Reset
DR
U3
U0
Wait for Info U4H
AR / ARL
LOF
U4H
U0
U0
U5
U0
Transparent
AI / AIL
LOF
Loss of Framing
RSY
NT_SM_4B3T_cust.emf
Figure 90
IEC-T/NTC-T Compatible State Machine T-SMINTI: 4B3T
Both the Q- and the T-SMINTI U-transceiver can be controlled via state machines,
which are compatible to those defined for the old NT generation INTC-Q and NTC-T.
Additionally, the Q-SMINTI possesses a newly defined, so called ‘simplified‘ state
machine. This simplified state machine can be used optionally instead of the INTC-Q
compatible state machine and eases the U-transceiver control by software. Such a
simplified state machine is not available for the T-SMINTI.
Data Sheet
215
2001-03-30
PEF 82912/82913
Appendix: Differences between Q- and T-SMINT‚I
7.2.3
Command/Indication Codes
Table 44
Code
C/I Codes
Q-SMINTI: 2B1Q
T-SMINTI: 4B3T
IN
TIM
RES
–
OUT
DR
–
IN
OUT
DR
–
0000
0001
0010
0011
0100
0101
0110
0111
1000
1001
1010
1011
1100
1101
1110
1111
TIM
–
–
–
–
–
–
–
–
EI1
SSP
DT
–
EI1
–
–
RSY
–
SSP
DT
–
–
–
PU
AR
–
–
AR
–
AR
–
AR
–
ARL
–
ARL
–
–
ARL
–
–
AI
AI
AI
RES
–
AI
–
–
–
–
AIL
DC
AIL
DC
DI
DI
Data Sheet
216
2001-03-30
PEF 82912/82913
Appendix: Differences between Q- and T-SMINT‚I
7.2.4
Interrupt Structure
•
M56R
7
0
OPMODE.MLT
MFILT
MS2
MS1
NEBE
M61
M52
M51
FEBE
+
CRC,
TLL,
no
Filtering
0
7
+
M4R
MFILT
M4RMASK
UCIR
7
AIB
UOA
M46
M45
M44
SCO
DEA
ACT
CRC,
TLL,
no
C/I
C/I
C/I
Filtering
0
0
C/I
EOCR
MFILT
15
TLL,
CHG,
no
ISTAU
MLT
MASKU
MLT
7
a1
a2
11
0
Filtering
CI
CI
FEBE/
NEBE
FEBE/
NEBE
M56
M56
i8
M4
M4
EOC
6ms
12ms
EOC
6ms
12ms
0
ISTA
MASK
7
U
interr_U_Q2.vsd
0
INT
Figure 91
Interrupt Structure U-Transceiver Q-SMINTI: 2B1Q
Data Sheet
217
2001-03-30
PEF 82912/82913
Appendix: Differences between Q- and T-SMINT‚I
•
UCIR
7
0
0
0
0
C/I
C/I
C/I
C/I
0
ISTAU
MASKU
7
0
CI
RDS
0
1
CI
RDS
1
0
1
0
1
0
1
1ms
1ms
0
ISTA
MASK
U
S
...
...
...
...
...
...
intstruct_4b3t.emf
INT
Figure 92
Interrupt Structure U-Transceiver T-SMINTI: 4B3T
Data Sheet
218
2001-03-30
PEF 82912/82913
Appendix: Differences between Q- and T-SMINT‚I
7.2.5
Register Summary U-Transceiver
U-Interface Registers Q-SMINTI: 2B1Q
Name
7
0
6
5
4
3
0
2
1
0
0
0
ADDR R/W RES
60H R*/W 14H
OPMODE
UCI FEBE MLT
CI_
SEL
MFILT
EOCR
EOCW
M56 FILTER
M4 FILTER
EOC FILTER
61H R*/W 14H
62H
reserved
0
i1
0
0
i2
0
0
i3
0
0
i4
0
a1
i5
a2
i6
a3
i7
d/m
i8
63H
64H
65H
66H
R
0F
FFH
01H
00H
a1
i5
a2
i6
a3
i7
d/m
i8
W
i1
i2
i3
i4
M4RMASK
M4WMASK
M4R
M4 Read Mask Bits
M4 Write Mask Bits
67H R*/W 00H
68H R*/W A8H
verified M4 bit data of last received superframe
M4 bit data to be send with next superframe
69H
R
BEH
M4W
6AH R*/W BEH
M56R
0
1
0
0
0
MS2
MS1 NEBE M61
M52
M52
M51 FEBE 6BH
M51 FEBE 6CH
R
W
R
1FH
FFH
00H
01H
M56W
UCIR
1
0
0
0
1
0
0
0
1
0
0
0
M61
C/I code output
C/I code input
6DH
6EH
UCIW
W
TEST
CCRC +-1
Tones
0
40 KHz 6FH R*/W 00H
LOOP
FEBE
NEBE
0
DLB TRANS U/IOM
1
LBBD LB2
LB1
70H R*/W 08H
FEBE Counter Value
NEBE Counter Value
reserved
71H
72H
R
R
00H
00H
73H-
79H
Data Sheet
219
2001-03-30
PEF 82912/82913
Appendix: Differences between Q- and T-SMINT‚I
Name
7
6
5
4
3
2
1
0
ADDR R/W RES
ISTAU
MLT
CI
FEBE/ M56
NEBE
M4
EOC
6ms 12ms 7AH 00H
R
MASKU
MLT
CI
FEBE/ M56
NEBE
M4
EOC
6ms 12ms 7BH R*/W FFH
reserved
7CH
FW_
FW Version Number
7DH
R
6xH
VERSION
reserved
7EH-
7FH
Data Sheet
220
2001-03-30
PEF 82912/82913
Appendix: Differences between Q- and T-SMINT‚I
U-Interface Registers T-SMINTI: 4B3T
Name
7
0
6
5
0
4
0
3
0
2
0
1
0
0
0
ADDR R/W RES
60H R*/W 00H
OPMODE
UCI
reserved
61H-
6CH
UCIR
UCIW
0
0
0
0
0
0
0
C/I code output
C/I code input
6DH
6EH
6FH
R
00H
01H
0
W
reserved
LOOP
RDS
0
DLB TRANSU/IOM
1
LBBD LB2
LB1
70H R*/W 08H
71H
reserved
Block Error Counter Value
reserved
72H
R
00H
73H-
79H
ISTAU
0
1
CI
CI
RDS
RDS
0
1
0
1
0
1
0
1
1 ms
1 ms
7AH
R
00H
MASKU
7BH R*/W FFH
7CH
reserved
FW_
FW Version Number
7DH
R
3xH
VERSION
reserved
7EH-
7FH
Data Sheet
221
2001-03-30
PEF 82912/82913
Appendix: Differences between Q- and T-SMINT‚I
7.3
External Circuitry
The external circuitry of the Q- and T-SMINTI is equivalent; however, some external
components of the U-transceiver hybrid must be dimensioned different for 2B1Q and
4B3T. All information on the external circuitry is preliminary and may be changed in
future documents.
•
RT
AOUT
n
R4
R4
RT
RCOMP
RPTC
BIN
AIN
>1µ
C
Loop
RCOMP
RPTC
extcirc_U_Q2_exthybrid.emf
BOUT
Figure 93
Note: the necessary protection circuitry is not displayed in Figure 93.
External Circuitry Q- and T-SMINTI
Data Sheet
222
2001-03-30
PEF 82912/82913
Appendix: Differences between Q- and T-SMINT‚I
Table 45
Dimensions of External Components
Q-SMINTI: 2B1Q
Component
T-SMINTI: 4B3T
Transformer:
Ratio
1:2
1:1.6
Main Inductivity
14.5 mH
7.5 mH
Resistance R3
Resistance R4
Resistance RT
Capacitor C
1.3 kΩ
1.75 kΩ
1.0 kΩ
25 Ω
1.0 kΩ
9.5 Ω
27 nF
15 nF
RPTC and RComp
2RPTC + 8RComp = 40 Ω
n2 × (2RCOMP + RB) + RL =
20Ω
Data Sheet
223
2001-03-30
PEF 82912/82913
Index
AC Characteristics 200
8
Index
Activation/Deactivation 59
Detailed Registers 165
Frame Structure 28
A
Absolute Maximum Ratings 194
Address Space 136
Functional Description 28
L
B
Layer 1
Activation/Deactivation 120
Loopbacks 125
LED Pins 13
Block Diagram 7
Block Error Counters 81
C
Line Overload Protection 194
C/I Channel
Detailed Registers 148
Functional Description 50
C/I Codes
S-Transceiver 109
U-Transceiver 83
Controller Data Access (CDA) 31
Cyclic Redundancy Check 79
M
Maintenance Channel 64
Metallic Loop Termination 99
Microcontroller Clock Generation 24
Microcontroller Interfaces
Interface Selection 17
Parallel Microcontroller Interface 22
Serial Control Interface (SCI) 18
Monitor Channel
D
DC Characteristics 195
D-Channel Access Control
Functional Description 52
State Machine 56
Detailed Registers 176
Error Treatment 46
Functional Description 42
Handshake Procedure 42
Interrupt Logic 49
Differences between Q- and T-SMINT 211
Time-Out Procedure 49
E
EOC 67
O
External Circuitry
S-Transceiver 132
U-Transceiver 130
Oscillator Circuitry 134
Overhead Bits 75
P
F
Package Outlines 209
Parallel Microcontroller Interface
AC-Characteristics 203
Functional Description 22
Pin Configuration 6
Pin Definitions and Functions 8
Power Consumption 197
Power Supply Blocking 130
Power-On Reset 27, 207
Features 3
I
Identification
via Monitor Channel 48
via Register Access 164
Interrupts 137
IOM®-2 Interface
Data Sheet
224
2001-03-30
PEF 82912/82913
Index
R
Register Summary 139
Reset
Generation 25
Input Signal Characteristics 206
Power-On Reset 27, 207
Under Voltage Detection 27, 207
S
S/Q Channels 105
Scrambling/ Descrambling 83
Serial Control Interface (SCI)
AC-Characteristics 202
Functional Description 18
Serial Data Strobe Signal 41
Stop/Go Bit Handling 54
S-Transceiver
Detailed Registers 152
Functional Description 103
State Machine, LT-S 115
State Machine, NT 111
Supply Voltages 197
Synchronous Transfer 37
System Integration 14
T
Test Modes 14
TIC Bus Handling 53
U
U-Interface Hybrid 130
Under Voltage Detection 27, 207
U-Transceiver
Detailed Registers 179
Functional Description 60
State Machine, Simplified NT 95
State Machine, Standard NT 87
W
Watchdog Timer 26
Data Sheet
225
2001-03-30
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