PFM21030_技术文档

PRELIMINARY

PFM21030 SPECIFICATION

2110-2170 MHz, 30W, 2-Stage Power Module

Enhancement-Mode Lateral MOSFETs

This versatile UMTS module provides excellent linearity and efficiency in

a low-cost surface mount package. The PFM21030 includes two stages

of amplification, along with internal sense FETs that are on the same

silicon die as the RF devices. These thermally coupled sense FETs

simplify the task of bias temperature compensation of the overall amplifier.

The module includes RF input, interstage, and output matching elements.

The source and load impedances required for optimum operation of the

module are much higher (and simpler to realize) than for unmatched Si

LDMOS transistors of similar performance.

Package Type: Surface Mount

PN: PFM21030SM

The surface mount package base is typically soldered to a conventional

PCB pad with an array of via holes for grounding and thermal sinking

of the module. Optimized internal construction supports low FET

channel temperature for reliable operation.

Package Type: Flange

PN: PFM21030F

• 27 dB Gain

• WCDMA Performance

5 Watts Average Output Level

18% Power Added Efficiency

–45 dBc ACPR

• 30 Watts Peak Output Power

• Internal Tracking FETs

(for improved bias control)

Module Schematic Diagram

Module Substrate

Q2 Die Carrier

Q1 Die Carrier

Drain 2

Q2

RF OUT

Q1

Gate 1

RF IN

Input

Match

Output

Match

Lead

Input

Match

Output

Match

Lead

S2

S1

Lead

Sense S1

Gate 2

Sense S2

Lead

D1

Note: Additionally, there are 250K Ohm resistors connected in shunt with all leads, to enhance ESD protection.

Page 1 of 13 Specifications subject to change without notice. US Patent No.6,822,321

Rev. 3

http://www.cree.com/

PFM21030

Electrical Specification

Parameter

Min

Limits

Typ

Units

Comments

Max

1

2

Operating Frequency

2110

-

2170

MHz

dB

Gain

25

26.7

30

Note 1.

Pulsed CW compression measurement

(12 µsec pulse, 120 µsec period, 10%

duty cycle).

Gain Compression at

Pout =30 Watts

3

4

5

-

1.3

2.0

dB

°

Gain Flatness over any

30 MHz bandwidth

Deviation from Linear

Phase over any 30

MHz bandwidth

± 0.1

± 1.0

± 0.3

± 2.0

Includes delay of test fixture (~0.6

nanoseconds).

Note 3. Refer to applications data for

performance with other protocols.

6

7

8

Group Delay

-

3.5

-44

3.8

-

nanosec

dBc

ACPR with WCDMA

Pave = 5 W

Efficiency under

WCDMA Protocol,

Pave = 5 W

-40

17

19

-

%

Note 3.

Efficiency @ 30W

CW Output

DC Drain Supply

Voltage

9

40

27

-

%

Testing for conformance with RF

specifications is at +27 V.

10

24

-40

-

30

Volts

Operating

Testing for conformance with RF

specification is at +25 °C.

11 Temperature Range

(base temperature)

-

-0.033

-

+115

-

°C

Gain Variation versus

Temperature

12

Bias quiescent currents held constant.

dB/°C

VSWR 10:1, all phase angles. No

degradation in output power before &

after test.

Output Mismatch

Stress

Watts

CW

13

-

30

14 Stability

-60

-

dBc

0<Pout<44.8 dBm CW, 3:1 VSWR

Theta jc is for output device. Verified

with IR scan. Note 2.

15 Theta jc (channel)

2.1

°C/W

Quiescent Currents

16 a) Q1

These DC quiescent currents are typical

of the levels that produce optimum

linearity for CDMA protocol.

80

240

mA

b) Q2

Tracking FET

Periphery Ratio

Ratio of sense FET current, relative to RF

FET current. Ratios are: Stg 1: 33:1;

Stg 2: 58:1 Gates of sense & RF FETs

are DC connected. Measured with no RF

signal present.

17

18

a) Stg 1 Track

b) Stg 2 Track

3.0

1.7

%

ESD Protection

a) Human Body Model

b) Machine Model

a) 2000V, 100 pF, 1500 Ohms

b) 400V, 200 pF, zero Ohms

Mil STD 883E, Method 3015 for Human

Body Model and for Machine Model.

Class 1

Class M3

Page 2 of 13 Specifications subject to change without notice. U.S. Patent No.6,822,321

Rev. 2

http://www.cree.com/

PFM21030

Electrical Specification (Continued)

MAXIMUM RATINGS

Rating

Symbol

Value

Units

DC Drain Supply

a) Drain-to-Source Voltage, (V_GS=0), D1 & D2

& Track D1 & Track D2

b) Normal Operation (Class AB operation)

V_DS

+50

+30

Volts DC

19

V_{D_SUPPLY}

DC Gate Supply

20

a) Gate-to-source Voltage (V_DS=0)

Normal Operation (Class AB operation)

V_GS

V_{G_SUPPLY}

-0.5<V_GS<+15

0<V_GS<+6

Volts DC

21

22

RF Input Power

P_IN

+25

dBm

P_TOTAL

65

-0.7

Watts

Watts/°C

Maximum Power Dissipation (T ≤ +85 °C)

a) Derate above +85 °C base temperature.

23

24

Maximum Channel Operating Temperature

Storage Temperature Range

T_CH

T_STG

+200

-40 to +150

°C

RECOMMENDED SOURCE AND LOAD IMPEDANCES

Impedance Units

Comments

Nominal Source

Impedance for

Optimum Operation

Matched for optimum linearity and gain flatness. Impedance

is looking from the module input lead into the input matching

circuit. Reference plane is 0.105 inches from input end of

module.

Matched for optimum efficiency under WCDMA protocol.

Impedance is from the module output lead looking into the

output matching circuit. Reference plane is 0.105 inches from

output end of module.

18.3 – j0.1

23.7 + j3.8

Ohms

Nominal Load

Impedance for

Optimum Operation

Specification Notes:

1) The module is mounted in a test fixture with external matching elements for all testing. Quiescent current bias

conditions are those appropriate for minimum ACPR under CDMA protocol. Supply voltage for all tests is

+27 volts DC. Testing is at +25 °C unless otherwise specified.

2) Theta jc is measured with a package mounting (base) temp of +85 °C, and with 10 Watts CW output.

3) Pout=5 Watts average; WCDMA protocol: (3GPP Test Model 1, 64 DPCH.).

ACPR conditions: 5.00 MHz offset, 3.84 MHz BW (crest factor = 11 dB).

4) Sense FETs are scaled versions of the main RF FETs, formed from electrically isolated cells at end of the RF

structure. Current scales according to periphery (threshold voltages offset is less than ±150 millivolts between

adjacent devices). RF & Sense FET gates and sources are DC connected. Drains are DC isolated. Leads S1 & S2

are DC connected to drains of sense FETs 1 & 2. Sources are connected to package base. Sense FETs are

electrically isolated from the RF signals.

Page 3 of 13 Specifications subject to change without notice. U.S. Patent No.6,822,321

Rev. 2

http://www.cree.com/

PFM21030

Typical Module Performance

T=+25 °C, unless otherwise noted. Data is for module in a test fixture with external matching elements. See following

page for test fixture details.

Typical CW 2-Tone Intermods vs. Output Power

Typical Small-Signal Gain vs. Frequency

-10

IM3L

IM3U

IM5L

IM5U

IM7L

IM7U

28

27

26

25

24

23

-20

-30

-40

-50

-60

-70

1990

2050

2110

2170

2230

2290

2350

27

29

31

33

35

37

39

41

43

Frequency (MHz)

Average Output Power (dBm)

Typical Gain & Efficiency vs CW Output Power

Typical Input & Output Return Loss vs Freq.

0

- 2

- 4

- 6

- 8

28

27

26

25

24

23

22

21

45

40

35

30

25

20

15

10

GAIN

OUTPUT

INPUT

- 1

0

2

4

6

EFFICIENCY

- 1

32 33 34 35 36 37 38 39 40 41 42 43 44 45 46

2

0

5

0

2

0

8

0

2

1

0

2

1

4

0

2

1

7

0

2

0

2 2 3 0

Output Power (dBm)

Frequency (MHz)

Note: The above data is for initial prototype units. Consult the factory for latest data.

Page 4 of 13 Specifications subject to change without notice. U.S. Patent No.6,822,321

Rev. 2

http://www.cree.com/

PFM21030

PFM21030SM Package Outline

PFM21030F Package Outline

Page 5 of 13 Specifications subject to change without notice. U.S. Patent No.6,822,321

Rev. 2

http://www.cree.com/

PFM21030

Module Application Notes

The PFM21030 was designed to provide a versatile low cost solution for a wide variety of wireless applications

requiring 30 Watt peak output levels. This hybrid module contains two stages of Si LDMOS FET amplification:

a nominally 5 Watt input stage driving a 30 Watt output stage. The module is optimized for efficient, linear operation

with WCDMA signals. The input and output of this module are partially matched, and require source and load

impedances of nominally 19 and 21 Ohms (much higher than typically required by unmatched Si LDMOS FETs).

These source and load impedances can be achieved with compact conventional external PCB circuitry.

Performance for particular signal protocols can be improved slightly by small adjustments in quiescent currents and

load impedances presented to the module. The data presented in the previous pages was taken at one set of quiescent

currents and in a fixture with source and load impedances that were fixed for all measurements. The data presented is

generally representative of the performance– benefits from further optimization in quiescent current are small.

In addition to the two RF gain stages, there are Sense FET (thermally tracking) devices that serve as optional DC circuit

elements. The Sense FETs are fabricated on the same epi material with nominally identical physical characteristics (but

smaller gate periphery) as the RF devices. The sense devices can be applied as temperature compensation elements in

conjunction with external bias circuitry. Alternatively, the two-stage amplifier can be operated with the Sense FETs

unused (S1 and S2 leads floating).

The base of the module is high conductivity copper of 40 mil thickness. It is well matched to typical PCB material, and

it serves as a heat spreader for the device when mounted as a surface-mount component. The module thermal

characteristics were measured with the unit soldered to a 20 mil thick PCB material with an array of plated via holes for

electrical grounding and thermal sinking. IR scans of this configuration demonstrated maximum die channel

temperatures of 142 degrees C with a PCB base temperature of +95 degrees C, and 10 Watts CW output power.

These modules can be provided in tape-and-reel configuration for high volume application

Typical PCB Mounting Pattern

The module outline is indicated by dashed line (0.60 X 1.00 inches). The ground pad is 1.030 X 0.630 inches. Ground

vias in this example are 28 mil diameter on 35 mil (or 70 mil) centers. Thermal resistance is proportional to the

thickness of the PC board (height of vias), and inversely proportional to the total ground hole array periphery (and

thickness of plating in the holes). The densely spaced vias in this layout (on 35 mil spaces) are located in areas of

maximum heat generation. The gap between the lead pads and the ground pad is 25 mils. Note that the underside of

the PCB must be connected to a thermal heat sink and ground.

The above hole pattern is an example of one that maximizes thermal transfer. There are numerous alternative

approaches. Depending on the application (signal protocol, thermal environment, etc.), the number of via holes can be

reduced. High average power applications require the most extensive thermal sinking.

Page 6 of 13 Specifications subject to change without notice. U.S. Patent No.6,822,321

Rev. 2

http://www.cree.com/

PFM21030

Recommended Passive Bias Circuit

This schematic demonstrates a method of applying the Sense FETs internal to the module that uses passive

external circuitry. The circuit maintains a constant current through the Sense FETS, independent of

temperature of the die. The Sense FETs are configured in this case as diodes. The temperature dependence

of the Vf of the diode is very similar to that of the RF FET gate voltage, and therefore the quiescent current

remains nearly constant over a wide temperature range. The advantage of this circuit is its simplicity and

stability (avoidance of operational amplifiers) under all layout conditions. The main limitation of the circuit

is that quiescent currents must be adjusted for each individual module (they are not easily pre-set with

precision).

+10 to

+20 V

Gate

GND

+27 V

Note: Typical Q1 diode bias = 1.4 mA (VG1 ~ 3.96V)

Typical Q2 diode bias = 2.7 mA (VG2 ~ 4.21V)

(based on 6/4/04 measurements)

J1

8

7

6

5

4

3

2

1

C29

S1

S2

C28

C27

C12 C11 C10

R6

R5

C24

C23

R2

C22

C20

C21

C19

C9

C18 C17 C16 C15

C8

Drain 1

C7

Sense D2

Gate 2

C2

R3

C6

R1

Sense D1

PFM21030

RF

OUT

RF

Out

RF IN

RF

C1

Input

C4

C5

C3

Page 7 of 13 Specifications subject to change without notice. U.S. Patent No.6,822,321

Rev. 2

http://www.cree.com/

PFM21030

Alternate Passive Bias Circuit Parts List

Designator

Description

Qty

C1

C2

C3

C5

1

2

3

4

1

CAP, 10 PF±0.5 pF, 0603, ATC 600S

CAP, 0.8 PF±0.1 pF, 0603, ATC 600S

CAP, 1.5 PF±0.1 pF, 0603, ATC 600S

CAP, 1.0 PF±0.1 pF, 0603, ATC 600S

CAP, 3.3 PF±0.1 pF, 0603, ATC 600S

CAP, 24 PF±5%, 0603, ATC 600S

CAP, 24 PF±5%, 100V (min), 0603, any vendor.

CAP, 470 PF ±10%,100 V, 0603, any vendor.

CAP, 3300 PF±10%, 100 V, 0603, Murata GRM39X7R332K100??, or

equivalent.

C4, C6

C7, C19, C20

C10, C13, C14, C15,

C8, C11, C16, C21

C22

C23, C9, C17, C12

C24, C18

4

2

CAP, 15000 PF±10%, 100 V, 0805, MurataGRM40X7R153K100??,

or equivalent.

CAP, 150000 1206, 50V, X7R, 10%

Suggest Murata GRM42-6-X7R-154-K-050-A-L or equivalent.

R5

RES, potentiometer, 10K ohms, Digikey SM4W103-ND

1

R6

RES, potentiometer, 5K ohms, Digikey SM4W502-ND

RES, 1/16W, 0603, 1000 ohms

R1

R3

RES, 1/16W, 0603, 42 ohms

C27

C29

C28

S1, S2

CAP, 2.2uf SMT TANTALUM, 50V (240097)

CAP, 10uf 16V SMT TANTALUM (240096)

CAP, 47UF, 50V, ELECTR SMT (240087)

SPST Switch, Digikey PN CKN1100CT-ND

1

2

Page 8 of 13 Specifications subject to change without notice. U.S. Patent No.6,822,321

Rev. 2

http://www.cree.com/

PFM21030

A metal backed PCB with clamps for securing module is used for module electrical testing and for product

demonstration. The fixture is supplied mounted to a finned heat sink. A fixture schematic is provided on the

following page.

Test Fixture

This test fixture uses an active bias circuit, which sets the bias circuit through the Sense FETs (configured as

FETs) and applies the derived gate voltage to the associated RF FETs. This assures particular quiescent bias

currents, with accuracy determined by the Sense FET-to-RF FET current ratios.

Page 9 of 13 Specifications subject to change without notice. U.S. Patent No.6,822,321

Rev. 2

http://www.cree.com/

PFM21030

Test Fixture (with active bias circuit) Schematic

+27 V

OpAmp

+27 V

GND

J2 Not Used for Demo Fixture

J1

J2

8

7

6

5

4

3

2

1

8

7

6

5

4

3

2

1

RZ_FS1

RZ_FS2

C31

C37

C34

R33

C36

R36

R12

C32

4

R32

R31

R11

R16

U2

5

4

-

₅U1

R13

C43

LM8261

-

+

C42

LM8261

3

R34

C35

2

C41

+

1

3

R14

C33

C40

2

R39

R37

R40

R19

R35

R20

R15

R38

R17

S2

D2

R18

S1

D1

C28

C27

C26

C12 C11 C10

C25

C24

C22

C23

C21

C14

C9

C8

C7

C20

C19

C18 C17 C16 C15

Drain 1

Sense D2

Gate 2

C2

R2

C6

R1

Sense D1

PFM21030

RF

OUT

RF

Out

RF

Input

RF IN

C1

C4

C5

C3

See the following pages for the parts list and a description of the principle of operation. Note that an

alternative, less complex bias scheme is provided on page 10. The advantage of the above active bias design

is that bias currents are set by the RF-to-Sense FET ratios, and once the optimum bias circuit resistor

(potentiometer) values are established, the circuit can stay fixed for multiple modules (thus eliminating

Page 10 of 13 Specifications subject to change without notice. U.S. Patent No.6,822,321

Rev. 2

http://www.cree.com/

PFM21030

module-specific bias alignment). Additionally, aging effects are minimized because of the similar bias

conditions for Sense and RF FETs. The disadvantage of this design is its relative complexity and the

incorporation of operational amplifiers, for which stability is potentially circuit layout dependent.

Parts List for Cree Microwave Test Fixture

Designator

Description

CAP, 10 PF±0.5 pF, 0603, ATC 600S

Qty

1

C1

C2

C3

C5

1

CAP, 0.8 PF±0.1 pF, 0603, ATC 600S

CAP, 1.5 PF±0.1 pF, 0603, ATC 600S

CAP, 1.0 PF±0.1 pF, 0603, ATC 600S

1

C4, C6

2

CAP, 3.3 PF±0.1 pF, 0603, ATC 600S

C7

1

CAP, 24 PF±5%, 0603, ATC 600S

C19, C20

2

CAP, 24 PF±5%, 0603, ATC 600S

C10, C13, C14, C15,

C8, C11, C16, C21

C22

4

CAP, 24 PF±5%, 100V (min), 0603, any vendor.

CAP, 470 PF ±10%,100 V, 0603, any vendor.

CAP, 3300 PF±10%, 100 V, 0603, Murata GRM39X7R332K100

4

1

C9, C23, C17, C12

4

CAP, 15000 PF±10%, 100 V, 0805, MurataGRM40X7R153K100

CAP, 150000 1206, 50V, X7R, 10%

Murata GRM42-6-X7R-154-K-050-A-L

C18, C24, C25, C26,

C31, C34

6

C27, C37

C28

CAP, 2.2uf SMT TANTALUM, 50V

CAP, 47UF, 50V, ELECTR SMT

2

1

2

4

1

2

4

2

1

2

C33, C35

C32, C36

C40, C41, C42, C43

R1

CAP, 18,000 PF ±10%,100 V, 0603

CAP, 33,000 PF ±10%,100 V, 0603

CAP, 1000 PF ±10%,100 V, 0603.

RES, 1/16W, 0603, 1000 ohms, 5%

R2

RES, 1/16W, 0805, 42 Ohms, 5%

RES, 1/16W, 0603, 332 Ohms, 1%

R11, R12

R31, R32

R13, R14, R33, R34

R16, R15, R35, R36

R19, R39

R18

RES, 1/16W, 0603, 147 Ohms, 1%

RES, 1/16W, 0603, 2370 Ohms, 1%

RES, 1/16W, 0603, 511 KOhms, 1%

RES, 1/16W, 0603, 100 KOhms, 5%

RES, 1/16W, 0603, 3320 Ohms, 5%

RES, 1/16W, 0603, 2000 Ohms, 5%

R38

R20, R40

R17, R37

RZ_FS1, RZ_FS2

D1, D2

RES, 1/8W, 1206, 1000 Ohms, 5%

RES, potentiometer, 10 Kohms, Digikey SM4W103-ND, 11T

RES, 1/16W, 0805, 0 Ohms (used as jumpers, demo fixture only)

Zener diode, 6.2 V, Digikey PN BZT52C6V27DICT-ND

SPST Switch, Digikey PN CKN1100CT-ND

Op Amp, High Output, LM8261M5 (5 pin, SOT23 package)

S1, S2

U1, U2

It is also possible to bias the two stages in a conventional manner, with the two tracking FET drains left

unused (floating or grounded). The above bias circuits are just two of several possibilities.

Page 11 of 13 Specifications subject to change without notice. U.S. Patent No.6,822,321

Rev. 2

http://www.cree.com/

PFM21030

Test Fixture Active Bias Circuit Principles of Operation

The active bias circuit test fixture operates off of a single voltage supply. It contains two switches and two

potentiometers. The switches provide for independent on/off for the input and output devices of the module.

The potentiometers allow adjustment of quiescent current level of each stage. The adjustments should be

made with no RF applied to the module.

Q1 Die Carrier

Q1

Output

Match

Input

Match

Vsupply

S1

Vsupply

R1 <<Rbias

R1

-

Differental Amp

+

Ids_sense

Ireference

Rbias

Principal of Operation of Bias Circuitry

The principal of operation of the fixture bias circuit is demonstrated in the above Figure. The potentiometer

establishes a reference current, and the operational amplifier adjusts gate voltage to maintain that current in

the sense device. The same DC gate voltage is also applied to the main (RF) device. Sense devices are

scaled versions of the main (RF) devices, on the same die (to facilitate temperature tracking). As the

temperature of the die changes due to RF drive (or ambient temperature changes), the operational amplifier

maintains constant current through the Sense FET, and thus constant quiescent bias for the main (RF) FET.

No RF signal is applied to the Sense FET.

There is a separate independent bias circuit for the input (Q1) device and for the output device (Q2) of the

module.

Experience has shown this bias circuit to be a reliable method of maintaining tight control of quiescent

current over operating temperature, and for minimizing the impact of device aging effects on amplifier

performance. However, there are some precautions regarding use of this circuit. The principle of the circuit

is for the differential amplifier (op amp) to adjust gate voltage until the desired current is achieved through

the sense FETs. If the current path is interrupted (thereby not allowing I_ds__senseto flow), the operational

amplifier will increase gate bias in an attempt to increase current, with the possibility that the quiescent bias

current in the RF FET may increase beyond a safe limit (the device may be destroyed). The zener diodes in

the test fixture circuit (D1 and D2, test fixture schematic) are safeguards for prohibiting excessive gate

voltage to be applied to the transistors.

Page 12 of 13 Specifications subject to change without notice. U.S. Patent No.6,822,321

Rev. 2

http://www.cree.com/

PFM21030

Disclaimer: Specifications are subject to change without notice. Cree Microwave, Inc. believes the

information contained within this data sheet to be accurate and reliable. However, no responsibility is

assumed by Cree Microwave for any infringement of patents or other rights of third parties, which may

result from its use. No license is granted by implication or otherwise under any patent or patent rights of

Cree Microwave. Cree Microwave makes no warranty, representation or guarantee regarding the

suitability of its products for any particular purpose. “Typical” parameters are the average values

expected by Cree Microwave in large quantities and are provided for information purposes only. These

values can and do vary in different applications, and actual performance can vary over time. All

operating parameters should be validated by customer’s technical experts for each application. Cree

Microwave products are not designed, intended, or authorized for use as components in applications

intended for surgical implant into the body or to support or sustain life, in applications in which the

failure of the Cree product could result in personal injury or death, or in applications for planning,

construction, maintenance or direct operation of a nuclear facility. Cree Microwave is a trademark and

Cree and the Cree logo are registered trademarks of Cree, Inc.

Contact Information:

Cree Microwave, Inc.

160 Gibraltar Court

Sunnyvale, CA 94089-1319

Sheryle Henson (Cree Microwave—Marketing Manager) 408-962-7783

Tom Dekker (Cree Microwave—Sales Director) 919-313-5639

Page 13 of 13 Specifications subject to change without notice. U.S. Patent No.6,822,321

Rev. 2

http://www.cree.com/


型号：	PFM21030
厂家：	ETC
描述：	2110-2170 MHz, 30W, 2-Stage Power Module Enhancement-Mode Lateral MOSFETs 2110至70年兆赫， 30W ， 2级功率模块，增强模式横向的MOSFET
文件：	总13页 (文件大小：423K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

PFM21030 [ETC]

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