PI6C102-16BH_技术文档

PI6C102-16

Spread Spectrum Clock Synthesizer

for Mobile Pentium II

Features

Description

· 100 MHz or 66.6 MHz operation

PericomSemiconductor’sPI6Cclockseriesareproducedusingthe

company’s advanced submicron CMOS technology, achieving

industry leading speed.

· Two copies of CPU clock with V of 2.5V

DD

· High drive option to support modular mobile CPUs

PI6C102-16isahigh-speed, low-noise, clockgeneratorthatworks

with Pericom’s PI6C18x clock buffer to meet all clock needs for

Mobile Intel Architecture platforms. CPU and chipset clock fre-

quencies of 66.6 MHz and 100 MHz are supported.

· Six copies of PCI clock, (synchronous with CPU clock) 3.3V

· One copy of Ref. Clock @ 14.31818 MHz (3.3V

· One copy of 48 MHz Clock (3.3V)

)

TTL

· Low cost 14.31818 MHz crystal oscillator input

· Power management control

Split supplies of 3.3V and 2.5V are used. The 3.3V power supply

powersaportionoftheI/Oandthecore. The2.5Vis usedto power

the remaining outputs. 2.5V signaling follows JEDEC standard

8-X. Power sequencing of the 3.3V and 2.5V supplies is not

required.

· Isolated core V , V pins for noise reduction

DD SS

· Down spread (–16) or center spread spectrum (–16B) options

· 28-pin SSOP package (H)

AnasynchronousPWRDWN#signalmaybeusedtoorderlypower

down (or up) the system.

PI6C102-16 is –0.6% down spread, where as PI6C102-16B is

±0.75% center spread.

PI6C102-16D is the high drive version of PI6C102-16

Block Diagram

Pin Configuration

28-Pin

H

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PI6C102-16

Spread Spectrum Clock Synthesizer

for Mobile Pentium II

Pin Description

Signal Name

XTAL_IN

Type

Qty.

1

Description

1

I

14.318 MHz crystal input

14.318 MHz crystal output

Free running PCI clock output

2

XTAL_OUT

PCICLK_F

PCICLK[1:5]

SEL100/66#

48MHz

O

1

4

O

1

5,7,8,10,11

O

5

PCI clock outputs, TTL compatible

Select 100 MHz or 66 MHz. H = 100 MHz , L = 66 MHz

48 MHz output

15

I

1

16

O

1

17

PWRDWN#

CPUSTOP#

PCISTOP#

I

1

Powers down device when held LOW (Internal Pull up)

Stops CPU clocks LOW if held LOW (Internal Pull up)

Stops PCI clocks LOW if held LOW (Internal Pull up)

Ground for CPU outputs, 2.5V

18

1

19

I

1

22

23,24

V

SS2

ground

O

1

CPUCLK[0:1]

2

CPU and Host clock outputs, 2.5V

Power for CPU outputs, 2.5V

25

V

DD2

power

O

1

26

REF

1

14.318 MHz clock output

6,9,13,21,27

3,12,14,20,28

V

power

ground

5

3.3V Power

DD

V

5

3.3V Ground

SS

SelectFunctions

SEL100/66#

CPUCLK[0:1]

66 MHz

0

1

100 MHz

Clock Enable Configuration

CPUCLK

PCICLK

[1:5]

Other

Clocks

CPU_STOP# PCI_STOP# PWR_DWN#

PCICLK_F

Crystal VCO's 48MHz

off off off

[0:1]

X

0

1

X

0

1

0

1

0

1

low

stopped

running

low

33MHz

running running running

low

33MHz

low

100/66MHz

33MHz

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PI6C102-16

Spread Spectrum Clock Synthesizer

for Mobile Pentium II

Power Management Timing

Latency

Signal

Signal State

No. of rising edges of free running PCICLK

CPU_STOP#

0 (disabled)

1 (enabled)

1

PCI_STOP#

PWR_DWN#

0 (disabled)

1

1 (enabled)

1

1 (normal operation)

0 (power down)

3ms

2 max.

Notes:

1. Clock on/off latency is defined as the number of rising edges of free running PCICLKs

between when the clock disable goes low/high to when the first valid clock comes out of

the device.

2. Power-up latency is from when PWR_DWN# goes inactive (HIGH) to when the first valid

clocks are driven from the device.

CPU_STOP# Timing Diagram

Notes:

1. All timing is referenced to the CPUCLK.

2. The Internal label means inside the chip and is a reference only.

3 CPU_STOP# is an input signal that must be made synchronous to the free running PCI_F.

4. ON/OFF latency shown in the diagram is 2 CPU clocks.

5. All other clocks continue to run undisturbed.

6. PWR_DWN# and PCI_STOP# are shown in a HIGH state.

7. Diagrams shown with respect to 66 MHz. Similar operation as CPU = 100 MHz.

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PI6C102-16

Spread Spectrum Clock Synthesizer

for Mobile Pentium II

PCI_STOP# is an input signal used to turn off PCI clocks for low startedwithaguaranteedfullhighpulsewidth. ThereisONLYone

power operation. PCI clocks are stopped in the LOW state and rising edge of external PCICLK after the clock control logic.

PCI_STOP# Timing Diagram

Notes:

1. All timing is referenced to the CPUCLK.

2. PCI_STOP# signal is an input signal which must be made synchronous to PCI_F output.

3 Internal means inside the chip.

4. All other clocks continue to run undisturbed.

5. PWR_DWN# and CPU_STOP# are shown in a high state.

6. Diagrams shown with respect to 66MHz. Similar operation as CPU = 100 MHz.

PWR_DWN# Timing Diagram

Notes:

1. All timing is referenced to the CPUCLK.

2. The Internal label means inside the chip and is a reference only.

3. PWR_DWN# is an asynchronous input and metastable conditions could exist. The signal is synchronized inside the part.

4. The shaded sections on the VCO and the Crystal signals indicate an active clock.

5. Diagrams shown wth respect to 66 MHz. Similar operation as CPU = 100 MHz.

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PI6C102-16

Spread Spectrum Clock Synthesizer

for Mobile Pentium II

CPU_STOP# is an input signal used to turn off the CPU clocks for The PWR_DWN# is used to place the device in a very low power

low power operation. CPU_STOP# is asserted asynchronously by state. PWR_DWN# is an asynchronous active low input. Internal

the external clock control logic with the rising edge of free running clocksarestoppedafterthedeviceisputinpower-downmode.The

PCIclockandisinternallysynchronizedtotheexternalPCICLK_F power-on latency is less than 3ms. PCI_STOP# and CPU_STOP#

output. All other clocks continue to run while the CPU clocks are are “don’t cares” during the power-down operations. The REF

disabled. The CPU clocks are always stopped in a LOW state and clock is stopped in the LOW state as soon as possible.

started guaranteeing that the high pulse width is a full pulse. CPU

clock on latency is 2 or 3 CPU clocks and CPU clock off latency

is 2 or 3 CPU clocks.

Maximum Ratings

(Above which the useful life may be impaired. For user guidelines, not tested.)

Storage Temperature ............................................................ –65°C to +150°C

Ambient Temperature with Power Applied .............................. –0°C to +70°C

3.3V Supply Voltage to Ground Potential .............................. –0.5V to +4.6V

2.5V Supply Voltage to Ground Potential .............................. –0.5V to +3.6V

DC Input Voltage .................................................................... –0.5V to +4.6V

Note:

StressesgreaterthanthoselistedunderMAXIMUMRATINGSmaycauseperma-

nent damage to the device. This is a stress rating only and functional operation

of the device at these or any other conditions above those indicated in the

operational sections of this specification is not implied. Exposure to absolute

maximum rating conditions for extended periods may affect reliability.

DC Electrical Characteristics(V = +3.3V ±5%, V

= +2.5V ± 5%, T = 0°C to +70°C)

DD

DD2

A

Max. 2.5V Supply Consumption

Max. 3.3V Supply Consumption

Max. discrete cap loads,

PI6C102-16

Condition

Max. discrete cap loads,

= 2.625V

V

DD2

V

DD

= 3.465V

All static inputs = V

or V

All static inputs = V or V

DD SS

DD

SS

Powerdown Mode

(PWRDWN# =0)

100mA

500mA

Active 66MHz

SEL 100/66# = 0

72mA

170mA

Active 100MHz

SEL 100/66# = 1

100mA

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PI6C102-16

Spread Spectrum Clock Synthesizer

for Mobile Pentium II

DC Operating Specifications

Symbol

Parameters

Conditions

Min.

Max.

Units

V

DD

= 3.3V ± 5%

V

Input high voltage

Input low voltage

V

DD

2.0

V

+0.3

IH

DD

V

-0.3

0.8

IL

SS

I

Input leakage current

0 < V < V

DD

-5

+5

0.4

mA

IL

IN

V

= 2.5V ± 5%

DD

V

OH2

Output high voltage

Output low voltage

I

OH

= -1mA

2.0

2.4

V

OL2

I

OL

= 1mA

= 3.3V ± 5%

DD

V

OH

Output high voltage

Output low voltage

I

= -1mA

= 1mA

OH

V

OL

I

OL

V

DD

= 3.3V ± 5%

V

PCI Bus output high voltage

PCI Bus output low voltage

I

= -1mA

= 1mA

OL

2.4

POH

OH

V

I

0.55

POL

C

Input pin capacitance

Xtal pins capacitance

Output pin capacitance

Pin Inductance

5

22.5

6

IN

pF

C

13.5

18.0

0

XTAL

C

OUT

L

7

nH

°C

T

Ambient Temperature

No airflow

70

A

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PI6C102-16

Spread Spectrum Clock Synthesizer

for Mobile Pentium II

BufferSpecifications

Buffer Name

CPU

V

Range(V)

Impedance (W)

13.5 - 45

20 - 60

Buffer Type

Type 1

DD

2.375 -2.625

3.135 - 3.465

REF, 48 MHz

PCI

Type 3

12 - 55

Type 5

Type 1: CPU Clock Buffers (2.5V) for PI6C102-16 and PI6C102-16B

Symbol

Parameters

Pull-up current

Conditions

= 1.0V

OUT

Min.

Typ.

Max.

Units

I

V

-27

OHMIN

I

Pull-up current

V

= 2.375V

= 1.2V

OUT

-27

OHMAX

OUT

mA

I

Pull-down current

V

27

OLMIN

I

V

OUT

= 0.3V

30

4

OLMAX

t

RH

2.5V Type 1 output rise edge rate 2.5V ± 5% @ 0.4V-2.0V

2.5V Type 1 output fall edge rate 2.5V ± 5% @ 2.0V-0.4V

1

V/ns

t

FH

4

Type 1H: CPU Clock Buffers (2.5V) for PI6C102-16D

Symbol

Parameters

Pull-up current

Conditions

= 1.0V

OUT

Min.

Typ.

Max.

Units

I

V

54

OHMIN

I

Pull-up current

V

= 2.375V

= 1.2V

OUT

54

OHMAX

OUT

mA

I

Pull-down current

V

54

OLMIN

I

V

OUT

= 0.3V

60

4

OLMAX

t

RH

2.5V Type 1H output rise edge rate 2.5V ± 5% @ 0.4V-2.0V

2.5V Type 1H output fall edge rate 2.5V ± 5% @ 2.0V-0.4V

1

V/ns

t

FH

4

Type 3: REF, 48MHz Buffers (3.3V)

Symbol

Parameters

Pull-up current

Conditions

= 1.0V

OUT

Min.

Typ.

Max.

Units

I

V

-29

OHMIN

I

Pull-up current

V

= 2.375V

= 1.2V

OUT

-23

OHMAX

OUT

mA

I

Pull-down current

V

29

OLMIN

I

V

OUT

= 0.3V

27

2

OLMAX

t

3.3V Type 3 output rise edge rate 3.3V ± 5% @ 0.4V-2.4V

3.3V Type 3 output fall edge rate 3.3V ± 5% @ 2.4V-0.4V

0.5

RH

V/ns

t

FH

2

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PI6C102-16

Spread Spectrum Clock Synthesizer

for Mobile Pentium II

Type 5: PCI Clock Buffers (3.3V)

Symbol

Parameters

Pull-up current

Conditions

= 1.0V

OUT

Min.

Typ.

Max.

Units

I

V

-33

OHMIN

I

Pull-up current

V

= 3.135V

= 1.95V

= 0.4V

-33

OHMAX

OUT

mA

I

Pull-down current

V

OUT

30

OLMIN

I

V

OUT

38

4

OLMAX

t

3.3V Type 5 output rise edge rate 3.3V ± 5% @ 0.4V-2.4V

3.3V Type 5 output fall edge rate 3.3V ± 5% @ 2.4V-0.4V

1

RH

V/ns

t

FH

4

AC Timing

66 MHz

Min. Max.

100 MHz

Figure 1. Host Clock

to PCI CLK Offset

Parameters

Host CLK period

Units

Min.

Max.

t

(2.5V)

15.0

5.2

5.0

0.4

15.5

10.0

3.0

2.8

0.4

10.5

HKP

t

Host CLK high time

HKH

ns

t

Host CLK low time

HKL

t

(2.5V)

Host CLK rise time

1.6

250

55

1.6

250

55

HRISE

t

Host CLK fall time

HFALL

t

Host CLK Jitter

ps

%

ps

JITTER

Duty Cycle (2.5V)

(2.5V)

Measured at 1.25V

45

t

Host Bus CLK Skew

Output enable delay

175

8.0

3

175

8.0

3

HSKW

t

, t

1.0

PZL PZH

ns

t

, t

Output disable delay

Host CLK Stabilization from power-up

PCI CLK period

PLZ PHZ

t

ms

ns

HSTB

t

30.0

µ

30.0

µ

PKP

t

PCI CLK period stability

PCI CLK high time

500

ps

PKPS

tPKH

12.0

ns

t

PCI CLK low time

PKL

t

PCI Bus CLK Skew

Host to PCI Clock Offset

PCI CLK Stabilization from power-up

500

4.0

3

500

4.0

3

ps

ns

PSKW

t

1.5

HPOFFSET

t

ms

PSTB

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PI6C102-16

Spread Spectrum Clock Synthesizer

for Mobile Pentium II

Host Clock and PCI CLK Timing

Clock Output Waveforms

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PI6C102-16

Spread Spectrum Clock Synthesizer

for Mobile Pentium II

Minimum and Maximum Expected Capacitive Loads

Clock

Min. Load Max. Load

Units

Notes

CPU Clocks (HCLK)

PCI Clocks (PCLK)

10

30

10

20

30

20

1 device load, possible 2 loads

Meets PCI 2.1 requirements

1 device load

pF

REF, 48MHz

Notes:

1. Maximum rise/fall times are guaranteed at maximum specified load for each type of output buffer.

2. Minimum rise/fall times are guaranteed at minimum specified load for each type of output buffer.

3. Rise/fall times are specified with pure capacitive load as shown. Testing is done with an

additional 500Ω resistor in parallel.

Design Guidelines to Reduce EMI

1. Place series resistors and CI capacitors as close as possible to the respective clock pins. Typical value

for CI is 10pF. Series resistor value can be increased to reduce EMI provided that the rise and fall time

are still within the specified values.

2. Minimize the number of “vias” of the clock traces.

3. Route clock traces over a continuous ground plane or over a continuous power plane. Avoid routing

clock traces from plane to plane (refer to rule #2).

4. Position clock signals away from signals that go to any cables or any external connectors.

Ω

P8399-1

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PI6C102-16

Spread Spectrum Clock Synthesizer

for Mobile Pentium II

PCB Layout Suggestion

µ

Note:

This is only a suggested layout. There may be alternate solutions Recommended capacitor values:

depending on actual PCB design and layout.

C2-C7 ..................... 0.1µF,ceramic

As a general rule, C2-C7 should be placed as close as possible to C1,C8 ..................... 22µF

their respective V_DD.

P8399-1

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PI6C102-16

Spread Spectrum Clock Synthesizer

for Mobile Pentium II

28-Pin SSOP Package Data

OrderingInformation

P/N

Description

PI6C102-16H

PI6C102-16BH

PI6C102-16DH

28-pin SSOP Package

Pericom Semiconductor Corporation

2380 Bering Drive • San Jose, CA 95131 • 1-800-435-2336 • Fax (408) 435-1100 • http://www.pericom.com

P8399-1

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型号：	PI6C102-16BH
厂家：	ETC
描述：	CPU System Clock Generator CPU的系统时钟发生器\n 时钟发生器
文件：	总12页 (文件大小：575K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

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