PI6C9930S [ETC]
Eight Distributed-Output Clock Driver ; 八分布式输出时钟驱动器\n
| 型号： | PI6C9930S |
| 厂家： | 
ETC |
| 描述： | Eight Distributed-Output Clock Driver
|
| 文件： | 总5页 (文件大小：353K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
PI6C9930
3.3V Zero-Delay Clock Buffer
Features
ProductDescription
The PI6C9930 Clock Buffer offers zero-delay, low-skew system
clockdistribution.Thesemultipleoutputclockdriversoptimizethe
timing of high-performance computer systems. Each of eight
individual drivers can drive series-terminated transmission lines
with impedances as low as 50Ω while delivering minimal output
skews and full-swing logic levels.
• Near zero input to output delay
• Seven copies of the REF/2 or
Six copies of REF plus one REF × 2
• 25 100 MHz output
• 50% duty cycle
ConnectingQ0toFBprovidesREF/2outputsonQ1-Q7.Connecting
any of Q1 - Q7 output to FB produces six copies of the REF input
plus one REF x 2 on Q0.
• Lowskew
• Lowjitter(<250pscycle-to-cycle)
• Low noise balanced drive outputs
• V =3.3V±0.3V, T =0°to70°
CC
A
Test Mode
• 24-pin209milwideSSOP(H)
• 24-pin150milwideQSOP(Q)
• 24-pin300milwideSOIC(S)
In normal system operation, this pin is connected to ground. For
testing purposes, the TEST pin can have a removable jumper to
ground,orbetiedLOWthrougha100Ωresistor.Thiswillallowdrive
by an external tester. If the TEST input is forced HIGH, the device
will operate with its internal phase-locked loop disconnected, and
input levels supplied to REF will directly control all outputs.
Relativeoutputtooutputfunctionsarethesameasinnormalmode.
Applications
• PCI 66 MHz or 33 MHz systems
Block Diagram
Pinout
24-Pin
H, Q, S
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PI6C9930
3.3V Zero-Delay Clock Buffer
Maximum Ratings
(Above which the useful life may be impaired. For user guidelines, not tested.)
Storage Temperature ............................................................ 65°C to +150°C
Ambient Temperature with Power Applied ......................... 55°C to +125°C
Supply Voltage to Ground Potential ...................................... 0.5V to +7.0V
DC Input Voltage ................................................................... 0.5V to +7.0V
Output Current into Outputs (LOW) ...................................................... 64mA
Note:
Stresses greater than those listed under MAXIMUM RATINGS may cause
permanent damage to the device. This is a stress rating only and functional
operation of the device at these or any other conditions above those indicated in
the operational sections of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect reliability.
Operating Range
Range
Ambient Temperature
V
CC
Commercial
0°C to +70°C
3.3V ± 0.3V
Pin Description
Pin Name
I/O
Functional Description
Reference Frequency Input. This input supplies the frequency and
timing against which all functional variation is measured
REF
I
FB
FS
I
I
PLL feedback input (typically connected to one of eight outputs)
Two-level frequency range select. Internal Pull-up
Two-level select. See Test Mode section. Internal Pull-up
Clock Output, no divider
TEST
I
Q
O
O
O
Q1 - Q7
Clock outputs with internal divide by 2
V
PWR Power supply for output drivers
PWR Power supply for internal circuitry
PWR Ground
CCN
V
CCQ
GND
NC
No Connection
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PI6C9930
3.3V Zero-Delay Clock Buffer
Electrical Characteristics Over Operating Range
Symbol
Parameters
Output HIGH Voltage
Test Conditions
= Min., I = -24 mA
Min. Max. Units
V
OH
V
2.4
0.4
CC
OH
V
OL
Output LOW Voltage
V
= Min., I = +24 mA
CC OL
Input HIGH Voltage
(REF and FB inputs only)
V
IH
2.0
V
CC
V
Input LOW Voltage
(REF and FB inputs only)
V
-0.5
0.8
10
IL
Input HIGH Leakage Current
(REF, Test, FS, and FB inputs only)
I
IH
V
= Max., V = Max.
CC IN
mA
Input LOW Leakage Current
(REF, Test, FS, and FB inputs only)
I
IL
V
CC
= Max., V = 0.4V
-500
IN
(2)
I
Output Short Circuit Current
V
= Max., V = GND (25°C only)
OUT
-250
85
OS
CC
Operating Current
Used by Internal Circuitry
V
CCN
= V
= Max.,
CCQ
I
CCQ
All Inputs Select Open
mA
V
= V = Max., I
= 0 mA
= 0 mA
CCN
CCQ
OUT
OUT
(3)
I
Output Buffer Current per Output Pair
14
78
CCN
Inputs Selects Open, fmax
V
CCN
= V = Max., I
CCQ
(4)
PD
Power Dissipation per Output Pair
mW
Inputs Selects Open, f
MAX
Notes:
1. If these inputs, which are normally wired to V , GND, are switched, the function
CC
and timing of the outputs may glitch and the PLL may require an additional t
time before all datasheet limits are achieved.
LOCK
2. Tested one output at a time, output shorted for less than one second, less than l0% duty
cycle. Room temperature only.
3. (TBD) Total output current per output pair is approximated by the following expression that
includes device current plus load current.
I
= [(4 + 0.11F) + [((835 - 3F)/Z) + (.0022FC)]N1] x 1.1
CCN
Where: F = frequency in MHz
Z = line impedance in ohms
C = capacitive load in pF
FC = F × C
N = number of loaded outputs: 0, l, or 2
4. (TBD) Total power dissipation per output pair can be approximated by the following expression that
includes device power dissipation plus power dissipation due to the load circuit:
PD = [(22 + 0.61F) + [((1550 - 2.7F)/Z) + (0.125FC)]N] × 1.1 (See note 3 for variable definition)
5. TBD
6. Applies to REF and FB inputs only. Tested initially and after any design or process
changes that may affect these parameters.
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PI6C9930
3.3V Zero-Delay Clock Buffer
Capacitance(1,6) (T = 25°C, f = 1 MHz, V = 0V, V
= 0V)
A
IN
OUT
Parameter
Description
Input Capacitance
Test Conditions
Max. Units
C
T = 25C, f = 1 MHz, V = 3.3V
10
pF
IN
A
CC
AC Test Load and Waveform
3.3V
T_cyc
3.3 Volt Clock
T_high
0.6Vcc
T_low
R1
R2
R1 = 100Ω
R2 = 100Ω
CL = 20pF
(Includes fixture and
probe capacitance)
0.5Vcc
0.4Vcc
0.3Vcc
0.5Vcc
0.4Vcc
0.4Vcc
0.3Vcc
p-to-p
0.3Vcc
(minimum)
0.2Vcc
CL
AC Test Load
Clock Waveforms
AC Timing Diagram
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PI6C9930
3.3V Zero-Delay Clock Buffer
Switching Characteristics Over Operating Range(14)
(Commercial: TA = 0°C to 70°C, VCC = 3.3V ± 10%)
Symbol
Description
Min. Typ. Max. Units
FS = LOW
25
50
50
Operation Clock
Frequency in MHz
f
MHz
NOM
FS = HIGH or Floating
100
t
REF Pulse Width HIGH
5.0
5.0
RPWH
t
REF Pulse Width LOW
RPWL
(7,8)
t
Zero Output Skew (All Outputs)
0.3
0.6
1.2
+0.5
55
ns
SKEW
(9,10)
t
Device-to-Device Skew
DEV
t
PD
Propagation delay, REF Rise to FB Rise
Output Duty Cycle, Target Spec @ 66MHz
-0.5
45
1
0.0
50
t
%
V/ns
ms
CYC
(11,12)
s
Slew Rate
1.5
4
RATE
(13)
t
PLL Lock Time
0.5
325
LOCK
t
JR
Cycle-to-Cycle Output Jitter
ps
Notes:
7. Skew is defined as the time between the earliest and the latest output transition among all
outputs with AC Test Load.
8.
9.
t
t
is defined as the skew between outputs.
is the output-to-output skew between any two outputs on separate devices operating
SKEW
DEV
under the same conditions (V , ambient temperature, air flow, etc.).
CC
10. Tested initially and after any design or process changes that may affect these parameters.
11. Specified with outputs loaded without 20pF in AC Test Load.
12. Slew Rate (s
) measured between 0.3V and 0.5V (0.99V and 1.65V).
RATE
CC CC
13. t
is the time that is required before synchronization is achieved. This specification is
LOCK
validonlyafterV isstableandwithinnormaloperatinglimits.Thisparameterismeasured
CC
from the application of a new signal or frequency at REF or FB until t is within specified
PD
limits.
14. Test measurement levels for the PI6C9930 are PCI levels (0.4V
to 0.4V ). Test
CC
CC
conditions assume signal transition times of 2ns or less and output loading as shown in the
AC Test Loads and Waveforms unless otherwise specified.
Ordering Information
P/N
Description
PI6C9930H
PI6C9930Q
PI6C9930S
24 pin SSOP Package
24 pin QSOP Package
24 pin SOIC Package
Pericom Semiconductor Corporation
2380 Bering Drive San Jose, CA 95131 1-800-435-2336 Fax (408) 435-1100 http://www.pericom.com
PS8096B
01/25/99
181
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