PI74ALVCH32501NB [ETC]
18-Bit Bus Transceiver ; 18位总线收发器\n
| 型号： | PI74ALVCH32501NB |
| 厂家： | 
ETC |
| 描述： | 18-Bit Bus Transceiver
|
| 文件： | 总8页 (文件大小：572K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
PI74ALVCH32501
36-Bit Universal Bus Transceiver
with 3-State Outputs
Product Features
ProductDescription
Pericom Semiconductors PI74ALVCH series of logic circuits are
produced using the Companys advanced 0.5 micron CMOS
technology, achieving industry leading speed.
· PI74ALVCH32501 is designed for low voltage operation,
Vcc = 1.65 to 3.6V
· Bus Hold on data inputs eliminates the need for external
pullup resistors
The36-bitPI74ALVCH32501universalbustransceiver isdesigned
for1.65Vto3.6VV operation.
CC
· Industrial operation at 40ºC to 85ºC
· Packages available:
This device can be used as two 18-bit transceivers or one 36-bit
transceiver. Data flow in each direction is controlled by output-
enable (OEAB and OEBA), latch-enable (LEAB and LEBA), and
clock(CLKABandCLKBA)inputs.ForA-to-Bdataflow,thedevice
operatesinthetransparentmodewhen LEABishigh. WhenLEAB
is low, the A-data is latched if CLKAB is held at a
high or low logic level. If LEAB is low, the A data is stored in the
latch/flip-flop on the low-to-high transition of CLKAB.
WhenOEABishigh,theoutputsareactive.WhenOEABislow,the
outputs are in the high-impedance state.
114 Ball, 16mm x 5.5mm x 1.4mm Low Profile
Fine Pitch Ball GridArray,
LFBGA(NB114)
Logic Block Diagram (Positive Logic), Two Sets
DataflowforBtoAissimilar tothatofAtoBbutusesOEBA,LEBA,
and CLKBA. The output enables are complementary (OEAB is
active high and OEBA is active low).
To ensure the high-impedance state during power up or power
down, OEBA should be tied to V through a pullup resistor and
CC
OEAB should be tied to GND through a pulldown resistor; the
minimumvalue of the resistor is determined by the current-sinking
capability of the driver.
Active bus-hold circuitry is provided to hold unused or floating
data inputs at a logic level.
The PI74ALVCH32501 is characterized for operation from
40°C to 85°C.
PS8405A
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PI74ALVCH32501
36-Bit Universal Bus Transceiver
TruthTable(1)
ProductPinDescription
PinName
OE
Description
Inputs
LEAB
Output
Output Enable Input (Active HIGH)
OEAB
CLKAB
A
X
L
B
Z
LE
Latch Enable (Active HIGH)
CLK
Ax
Clock Input (Active HIGH)
L
H
H
H
H
H
X
H
H
L
X
Data I/O
Data I/O
Ground
Power
X
L
Bx
X
H
L
H
GND
VCC
↑
↑
L
L
H
X
H
L
L or H
B0
Notes:
A-to-B data flow is shown; B-toA flow is similar
butusesOEBA, LEBA, andCLKBA.
Output level before the indicated steady state input
conditions were established, provided that CLKAB is
high before LEAB goes low.
NB PACKAGE
Top View
6
5
4
3
2
1
A B C D E F G H J K L M N P R T U V W
TerminalAssignments
6
5
4
3
2
1
1B2
1B4
1B6 1B8 1B10 1B12 1B14 1B15
1B17
1B18
NC
2B2
2B1
2B4 2B6 2B8 2B10 2B12 2B14
2B3 2B5 2B7 2B9 2B11 2B13
2B15
2B16
2B17
2B18
GND
1B1
1B3
1B5 1B7 1B9 1B11 1B13 1B16
2CLKAB
GND
1CLKAB GND
GND VCC GND GND VCC GND 1CLKBA
GND
GND VCC GND GND VCC GND 2CLKBA
1LEAB 1OEAB GND VCC GND GND VCC GND 1OEBA
1LEBA 2OEAB GND VCC GND GND VCC GND 2OEBA 2LEBA
1A1
1A2
A
1A3
1A4
B
1A5 1A7
1A9
1A11 1A13 1A16
1A18
1A17
J
2LEAB
NC
2A1
2A2
L
2A3 2A5 2A7
2A9 2A11 2A13
2A16
2A15
V
2A18
2A17
W
1A6 1A8 1A10 1A12 1A14 1A15
2A4 2A6 2A8 2A10 2A12 2A14
C
D
E
F
G
H
K
M
N
P
R
T
U
PS8405A
09/15/99
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PI74ALVCH32501
36-Bit Universal Bus Transceiver
MaximumRatings
(Above which the useful life may be impaired. For user guidelines, not tested.)
Note:
Stresses greater than those listed under MAXIMUM
RATINGS may cause permanent damage to the device.
This is a stress rating only and functional operation of the
device at these or any other conditions above those indi-
cated in the operational sections of this specification is not
implied. Exposure to absolute maximum rating conditions
for extended periods may affect reliability.
Supply Voltage Range,V
...............................................................0.5V to 4.6V
CC
(1)
Input Voltage Range, V : Except I/O ports
..............................0.5V to 4.6V
........................... 0.5V to V + 0.5V
CC
I
(1,2)
I/O ports
(1,2)
Output Voltage Range, V
............................................ 0.5V to V +0.5V
CC
O
Input Clamp Current, I (V <0) ........................................................ 50mA
IK
I
Output Clamp Current, I (V <0) .................................................. 50mA
Continuous Output Current, I ................................................................... ±50mA
OK
O
O
Continuous Current through each V or GND ............................... ±100mA
CC
(3)
PackageThermalImpedance,θ
Storage Temperature Range, T
............................................................ 39ºC/W
............................................... 65ºC to 150ºC
JA
STG
Note:
1. The input negative voltage and output voltage ratings may be exceeded if the input and output current ratings are observed.
2. This value is limited to 4.6V maximum.
3. The package thermal impedance is calculated in accordance with JESD 51.
Recommended Operating Conditions(1)
Parameters
Description
Supply Voltage
Test Conditions
Min.
Max.
Units
V
CC
1.65
3.6
V
CC
= 1.65V to 1.95V 0.65 x V
CC
V
HIGH Level Input Voltage
LOW Level Input Voltage
V
= 2.3V to 2.7V
= 2.7V to 3.6V
1.7
2
IH
CC
V
CC
V
CC
= 1.65V to 1.95V
0.35 x V
0.7
V
CC
V
V
CC
= 2.3V to 2.7V
= 2.7V to 3.6V
IL
V
CC
0.8
V
Input Voltage
0
0
V
CC
I
V
O
Output Voltage
V
CC
V
= 1.65V
= 2.3V
= 2.7V
= 3.0V
= 1.65V
= 2.3V
= 2.7V
= 3.0V
4
CC
V
12
12
24
4
CC
I
High-level Output Current
Low-level Output Current
OH
V
CC
V
CC
mA
V
CC
V
12
CC
I
OL
V
12
CC
V
24
CC
∆t/∆v
Input Transition rise or fall time
Operating Free-Air Temperature
0
10
ns/V
°C
T
A
-40
85
Note:
1. Unused control inputs must be held at V or G to ensure proper device operation.
CC
ND
PS8405A
09/15/99
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PI74ALVCH32501
36-Bit Universal Bus Transceiver
DC Electrical Characteristics (Over the Operating Range, TA = 40°C to +85°C, VCC = 3.3V ±10%)
(1)
Parameters
Test Conditions
= 100µA
V
Min.
-0.2
Typ.
Max. Units
CC
I
1.65V to 3.6V
1.65V
2.3V
V
CC
OH
I
OH
= 4mA
= 6mA
1.2
I
OH
2.0
1.7
2.2
2.4
2.0
V
OH
2.3V
I
OH
= 12mA
2.7V
3.0V
I
OH
= 24mA
= 100µA
= 4mA
3.0V
V
I
OL
1.65V to 3.6V
1.65V
2.3V
0.2
I
OL
0.45
0.4
I
OL
= 6mA
V
OL
2.3V
0.7
I
OL
= 12mA
= 24mA
2.7V
0.4
I
OL
3V
0.55
±5
I
I
V = V or GND
3.6V
I
CC
V = 0.58V
TBD
TBD
45
I
1.65V
2.3V
3V
V = 1.07V
I
V = 0.7V
I
I (Hold)
I
V = 1.7V
I
45
75
V = 0.8V
I
µA
V = 2V
I
75
(2)
V = 0 to 3.6V
3.6V
3.6V
3.6V
±500
±10
20
I
(3)
I
OZ
V = V or GND
O CC
I
CC
V = V or GND,
I = 0
O
I
CC
One input at V
Other inputs at V or GND
0.6V,
CC
CC
3V to 3.6V
750
∆I
CC
CI Control Inputs V = V or GND
3.3V
3.3V
4
8
I
CC
pF
CIO A or B ports V = V or GND
O
CC
Notes:
1. All typical values are at V = 3.3V, T = 25ºC.
CC
A
2. This is the bus-hold maximum dynamic current. It is the minimum overdrive current required to
switch the input from one state to another.
3. For I/O ports, the I includes the input leakage current.
OZ
PS8405A
09/15/99
4
PI74ALVCH32501
36-Bit Universal Bus Transceiver
Timing Requirements over Operating Range, Figures 1,2,3
V
CC
= 1.8V ±0.15V V = 2.5V ±0.2V
V
= 2.7V
V
= 3.3V ±0.3V
CC
CC
CC
(1)
Parameters
Description
Conditions
Units
Min.
Max.
Min.
Max.
Min. Max.
Min.
Max.
f
Clock frequency
LE high
150
150
150
MHz
CLOCK
3.3
3.3
2.2
1.9
1.3
0.6
1.4
3.3
3.3
2.1
1.6
1.1
0.6
1.7
3.3
3.3
1.7
1.5
1
t
Pulse
W,
Duration
CLK high or low
Data before CLK ↑
C = 50pF
R = 500Ω
L
L
TBD
t
Setup
time
SU,
Data before LE ↓, CLK high
Data before LE ↓, CLK low
Data after CLK ↑
ns
0.7
1.4
t
Hold time
H
Data after LE ↓ CLK high or low
Switching Characteristics Over Operating Range, Figures 1,2,3
V
= 1.8V ±0.15V
V
= 2.5V ±0.2V
V
= 2.7V
V
= 3.3V ±0.V
CC
CC
CC
CC
From
(Input) (Output)
To
Parameters
Conditions
Units
Min.
Max.
Min.
150
1.0
1.1
1.2
1.0
1.5
1.3
1.3
Max.
Min. Max. Min.
Max.
f
150
150
1.0
1.3
1.4
1.0
1.4
1.1
1.3
MHz
MAX
A or B B or A
4.8
5.7
6.1
5.8
6.2
6.3
5.3
4.5
5.3
5.6
5.3
5.7
6.0
4.6
3.9
4.6
4.9
4.6
5.0
5.0
4.2
t
PD
LE
A or B
CLK
A or B
C = 50pF
L
R = 500Ω
L
t
EN
OEAB
OEAB
OEBA
OEBA
B
B
A
A
TBD
ns
t
DIS
t
EN
t
DIS
OperatingCharacteristics,T =25ºC
A
V
CC
= 1.8V
V
CC
= 2.5V
V
CC
= 3.3V
Parameter
Test Conditions
Units
Typ.
Typ.
Typ.
Outputs Enabled
Outputs Disabled
44
6
54
6
C
Power Dissipation
Capacitance
PD
C = 0, f = 10 MHz
L
TBD
pF
PS8405A
09/15/99
5
PI74ALVCH32501
36-Bit Universal Bus Transceiver
ParameterMeasurement Information
= 1.8V ±0.15V
V
CC
LoadCircuit
Test
S1
Ω
t
pd
Open
t
t
2 x V
CC
PLZ/ PZL
Ω
t
t
Open
PHZ/ PZH
VoltageWaveformsSetup andHoldtimes
VoltageWaveformsPulseDuration
VoltageWaveformsEnableand DisableTimes
VoltageWaveformsPropagationDelayTimes
Figure1. LoadCircuitandVoltageWaveforms
Notes:
A. CL includes probe and jig capacitance.
B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control.
C. All inputs pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, Z = 50Ω, t ≤ 2ns, t ≤ 2ns.
O
r
f
D. The outputs are measured one at a time with one transition per measurement.
E. t
F. t
and t
and t
are the same as t .
PLZ
PHZ
dis
are the same as t
.
ten
PZL
PZH
G. t
and t are the same as t .
PHL pd
PLH
.
PS8405A
09/15/99
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PI74ALVCH32501
36-Bit Universal Bus Transceiver
ParameterMeasurement Information
= 2.5V ±0.2V
V
CC
LoadCircuit
Test
S1
Ω
t
pd
Open
Ω
t
t
2 x V
CC
PLZ/ PZL
t
t
GND
PHZ/ PZH
VoltageWaveformsSetup andHoldTimes
VoltageWaveformsPulseDuration
VoltageWaveformsEnableand DisableTimes
VoltageWaveformsPropagationDelayTimes
Figure2. LoadCircuitandVoltageWaveforms
Notes:
A. CL includes probe and jig capacitance.
B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control.
C. All inputs pulses are supplied by generators having the following characteristics: PRR ≤10 MHz, Z = 50Ω, t ≤ 2ns, t ≤ 2ns.
O
r
f
D. The outputs are measured one at a time with one transition per measurement.
E. t
F. t
and t
and t
are the same as t .
PLZ
PHZ
dis
are the same as t
.
ten
PZL
PZH
G. t
and t are the same as t .
PHL pd
PLH
.
PS8405A
09/15/99
7
PI74ALVCH32501
36-Bit Universal Bus Transceiver
ParameterMeasurement Information
= 2.7V and 3.3V ±0.3V
V
CC
LoadCircuit
Test
S1
Ω
t
Open
6V
pd
Ω
t
t
PLZ/ PZL
t
t
GND
PHZ/ PZH
VoltageWaveformsSetup andHoldTimes
VoltageWaveformsPulseDuration
VoltageWaveformsEnableand DisableTimes
VoltageWaveformsPropagationDelayTimes
Figure3. LoadCircuitandVoltageWaveforms
Notes:
A. CL includes probe and jig capacitance.
B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control.
C. All inputs pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, Z = 50Ω, t ≤ 2 ns, t ≤ 2 ns.
O
r
f
D. The outputs are measured one at a time with one transition per measurement.
E. t
F. t
and t
and t
are the same as t .
PLZ
PHZ
dis
are the same as t
.
ten
PZL
PZH
G. t
and t are the same as t .
PHL pd
PLH
.
Pericom Semiconductor Corporation
2380 Bering Drive • San Jose, CA 95131 • 1-800-435-2336 • Fax (408) 435-1100 • http://www.pericom.com
PS8405A
09/15/99
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