PI74ALVCHR16269 [ETC]
Logic | 12/24-Bit Registered Bus Transceiver ; 逻辑| 12 / 24-位寄存总线收发器\n
| 型号： | PI74ALVCHR16269 |
| 厂家： | 
ETC |
| 描述： | Logic | 12/24-Bit Registered Bus Transceiver
|
| 文件： | 总5页 (文件大小：264K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
PI74ALVCHR16269
12-Bit to 24-Bit Registered Bus Exchanger
With 3-STATE Outputs
Product Description
Product Features
Pericom Semiconductor’s PI74ALVCH series of logic circuits are
producedintheCompany’sadvanced0.5micronCMOStechnology,
achieving industry leading speed.
• PI74ALVCHR16269 is designed for low voltage operation
• V = 2.3V to 3.6V
CC
• Hysteresis on all inputs
The PI7ALVCHR16269isusedinapplicationsinwhichtwoseparate
ports must be multiplexed onto, or demultiplexed from, a single port.
ItisparticularlysuitableasaninterfacebetweensynchronousDRAM’s
and high-speed microprocessors.
• Typical V
(Output Ground Bounce)
OLP
< 0.8V at V = 3.3V, T = 25°C
CC
A
• Typical V
(Output V Undershoot)
OH
OHV
< 2.0V at V = 3.3V, T = 25°C
CC
A
Data is stored on the internal B-port registers on the low-to-high
transitionoftheclock(CLK)inputwhentheappropriateclock-enable
(CLKENA) inputs are low. Proper control of these inputs allows two
sequential12-bitwordstobepresentedasa24-bitwordontheB-port.
For data transfer in the B-to-A direction, a single storage register is
provided.Theselect(SEL)lineselects1Bor2BdatafortheAoutputs.
The register on the A output permits the fastest possible data transfer,
thusextendingtheperiodduringwhichthedataisvalidonthebus.The
controlterminalsareregisteredsothatalltransactionsaresynchronous
with CLK. Data flow is controlled by the active-low output enables
(OEA, OEB1, and OEB2).
• All output ports have equivalent 26Ω series resistors,
no external resistors are required
• Bus Hold retains last active bus state during 3-STATE,
eliminating the need for external pullup resistors
• Industrial operation at 40°C to +85°C
• Packages available:
56-pin 240 mil wide plastic TSSOP (A)
56-pin 300 mil wide plastic SSOP (V)
To ensure the high-impedance state during power up or power
down, a clock pulse should be applied as soon as possible and OE
Logic Block Diagram
should be tied to V through a pullup resistor; the minimum value
CC
of the resistor is determined by the current-sinking capability of the
driver. Due to OE being routed through a register, the active state
of the outputs cannot be determined prior to the arrival of the first
clock pulse.
Active bus-hold circuitry is provided to hold unused or floating
data inputs at a valid logic level.
All outputs are designed to sink up to 12mA and include 26Ω
resistors to reduce overshoot and undershoot.
PS8372
01/28/99
1
PI74ALVCHR16269
12-Bit To 24-Bit Registered Bus Exchanger with 3-State Outputs
Product Pin Description
Truth Tables(1)
Pin Name
OE
Description
Inputs
Outputs
1B,2B
Output Enable Input (Active LOW)
Clock
CLK
OEA
H
OEB
H
A
Z
CLK
SEL
Select (Active Low)
Clock Enable (Active Low)
3-State Outputs
Ground
Z
CLKEN
A,1B,2B
GND
H
L
Z
Active
Z
L
H
Active
Active
VCC
Power
L
L
Active
Product Pin Configuration
A to B STORAGE (OEB = L)
INPUTS
OUTPUTS
OEA
OEB1
2B3
OEB2
CLKENA2
2B4
1
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
CLKENA1 CLKENA2 CLK
A
L
1B
2B
2
(2)
L
L
H
H
L
L
L
L
H
X
L
2B
0
3
GND
2B2
GND
4
(2)
H
L
H
L
2B
0
2B5
5
2B1
2B6
6
L
L
V
CC
V
CC
7
56-PIN
A56
V56
L
H
L
H
H
L
A1
A2
2B7
8
2B8
9
(2)
(2)
(2)
H
H
H
1B
0
A3
2B9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
GND
A4
GND
2B10
2B11
2B12
1B12
1B11
1B10
GND
1B9
H
X
1B
H
0
(2)
1B
2B
0
0
A5
A6
B to A STORAGE (OEA = L)
A7
A8
Inputs
Outputs
A
A9
GND
A10
A11
A12
CLK
X
X
↑
SEL
H
1B
X
X
L
2B
X
X
X
X
L
1B8
A0(2)
A0(2)
L
1B7
V
CC
V
CC
1B6
L
1B1
1B2
GND
1B3
NC
1B5
H
GND
1B4
H
H
↑
Η
X
X
CLKENA1
CLK
SEL
L
L
↑
L
H
H
↑
Notes:
1. H = High Signal Level
L = Low Signal Level
X = Irrelevant
Z = High Impedance
↑ = Transition, Low to High
2. Output level before indicated steady state input conditions established
PS8372
01/28/99
2
PI74ALVCHR16269
12-Bit To 24-Bit Registered Bus Exchanger with 3-State Outputs
Maximum Ratings
(Above which the useful life may be impaired. For user guidelines, not tested.)
Storage Temperature ................................................ 65°C to +150°C
Supply Voltage Range, V ................................................. 0.5V to 4.6V
Note:
CC
Stresses greater than those listed under MAXIMUM
RATINGS may cause permanent damage to the device.
Thisisastressratingonlyandfunctionaloperationofthe
device at these or any other conditions above those
indicated in the operational sections of this specification
is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect reliability.
Input Voltage Range,V : Except
I
(1)
I/O ports ................................................................................ 0.5V to 4.6V
(1,2)
I/O ports
............................................................... 0.5V to V
+ 0.5V
CC
(1,2)
Output Voltage Range, V
.............................. 0.5V to V + 0.5V
CC
O
Input Clamp current, I (V < 0) ............................................ 50mA
IK
I
Output Clamp current, I (V < 0) ....................................... 50mA
OK
O
Continous Output Current, I .................................................. ±50mA
O
Continous Current through each V or GND ...................... ±100mA
CC
Maximum Power Dissipation:
A package ........................................................................................1W
V package .....................................................................................1.4W
Notes:
1. The input and output negative-voltage ratings maybe exceeded if the input and
outputclamp-current ratings are observed.
2. This value is limited to 4.6V maximum.
DC Electrical Characteristics (Over the Operating Range, TA = –40°C to +85°C, VCC = 3.3V ± 10%)
Parameters
Description
Supply Voltage
Test Conditions
Min.
2.3
Typ.
Max. Units
V
CC
3.6
V
= 2.3V to 2.7V
= 2.7V to 3.6V
= 2.3V to 2.7V
= 2.7V to 3.6V
1.7
CC
(1)
V
Input HIGH Voltage
Input LOW Voltage
IH
V
CC
2.0
V
CC
0.7
0.8
V
(1)
(1)
V
IL
V
CC
V
Input Voltage
0
0
V
CC
IN
(1)
OUT
V
Output Voltage
V
CC
V
= 2.3V
= 2.7V
= 3.0V
= 2.3V
= 2.7V
= 3.0V
-6
CC
HIGH-level
Output Current
(1)
OH
I
V
CC
8
-12
6
V
CC
mA
V
CC
LOW-level
Output Current
(1)
OL
I
V
CC
8
V
CC
12
85
10
T
A
Operating Free-Air Temperature
Input Transition Rise or Fall Rate
-40
ºC
At/∆
ns/V
V
Note:
1. Unused control inputs must be held HIGH or LOW to prevent them from floating.
PS8372
01/28/99
3
PI74ALVCHR16269
12-Bit To 24-Bit Registered Bus Exchanger with 3-State Outputs
DC Electrical Characteristics-Continued (Over the Operating Range, T = -40ºC to +85ºC, V = 3.3V ± 10%
A
CC
(1)
Parameters
Test Conditions
VCC
Min. to Max.
2.3V
Min.
VCC -0.2
1.9
Typ.(2)
Max.
Units
IOH = -100µΑ
OH = -4mΑ
OH = -6mΑ
VIH = 1.7V
VIH = 2.0V
VIH = 1.7V
VIH = 2.0V
VIH = 2.0V
VIH = 2.0V
I
2.7V
2.2
VOH
2.3V
1.7
I
3.0V
2.4
I
OH = -8mΑ
OH = -12mΑ
IOL= 100µΑ
2.7V
2.0
I
3.0V
2.0
V
Min. to Max.
2.3V
0.2
0.4
VIL = 0.7V
VIL = 0.8V
VIL = 0.7V
VIL = 0.8V
VIL = 0.8V
VIL = 0.8V
IOL = 4mΑ
2.7V
0.4
VOL
2.3V
0.55
0.55
0.6
IOL = 6mΑ
3.0V
IOL = 8mΑ
2.7V
IOL = 12mΑ
3.0V
0.8
II
VI = VCC or GND
VI = 0.7V
3.6V
±5
45
-45
75
2.3V
3.0V
VI = 1.7V
II (Hold)(3)
VI = 0.8V
VI = 2.0V
-75
µΑ
VI = 0 to 3.6V
VO = VCC or GND
VI = VCC or GND, IO = 0
3.6V
3.6V
3.6V
±500
±10
40
(4)
IOZ
ICC
One input at VCC - 0.6V, Other
inputs at VCC or GND
3V to 3.6V
750
∆ΙCC
CI Control Inputs VI = VCC or GND
CIO A or B Ports VO = VCC or GND
3.3V
3.3V
3.5
8.5
pF
Notes:
1. For Max. or Min. conditions, use appropriate value specified under Electrical Characteristics for the applicable device type.
2. Typical values are at V = 3.3V, +25ºC ambient and maximum loading.
CC
3. Bus hold maximum dynamic current required to switch the input from one state to another
4. For I/O ports, the I includes the input leakage current.
OZ
PS8372
01/28/99
4
PI74ALVCHR16269
12-Bit To 24-Bit Registered Bus Exchanger with 3-State Outputs
Timing Requirements over Operating Range
V
CC
= 2.5V ±
0.2V
V
CC
= 3.3V ±
0.3V
V
CC
= 2.7V
Parameters
Description
Min.
Max.
Min. Max. Min.
Max. Units
135 MHz
f
Clock frequency
95
115
CLOCK
Pulse duration, CLK
High or Low
t
W
5.2
4.3
3.3
A data before CLK↑
B data before CLK↑
SEL before CLK↑
1.4
1.6
0.8
1.4
1.5
1.1
1
1.1
1.3
t
SU
Setup time
CLKENA1 or CLKENA2
before CLK ↑
0.8
1
0.8
ns
OE data before CLK ↑
A data after CLK↑
B data after CLK↑
SEL after CLK↑
1.7
0.9
0.8
1.1
1.6
0.9
0.6
0.8
1.2
1.2
1
1.7
t
H
Hold time
CLKENA1 or CLKENA2
after CLK ↑
1.4
0.9
1
1.6
1.2
OE after CLK↑
0.8
Switching Characteristics over Operating Range(1)
V
= 2.5V ± 0.2V
V
= 2.7V
V = 3.3V ± 0.3V
CC
CC
CC
From
To
Parameters
Units
(INPUT) (OUTPUT)
(2)
(2)
(2)
Min.
95
Max.
Min.
Max.
Min.
135
2.2
2
Max.
f
115
MAX
B
A
2.3
1.9
2.5
2.2
3.3
2.7
7.7
6.4
7.7
6.7
8.1
8
6.9
5.8
6.9
6
5.8
5.2
5.8
5.3
6
t
PD
B
2.3
2.1
2.4
2.1
ns
t
EN
CLK
A
B
A
6.7
6.2
t
DIS
6
Notes:
1. Unused control inputs must be held HIGH or LOW to prevent them from floating.
2. Minimum limits are guaranteed but not tested on Propagation Delays.
Operating Characteristics, TA = 25°C
V
CC
= 2.5V ± 0.2V V = 3.3V ± 0.3V
CC
Test
Typical
Parameter
Power Dissipation
Capacitance per
Exchanger
Conditions
Units
C
PD
Outputs Enabled
Outputs Disabled
142
115
172
129
C = 0pF,
L
F = 10 MHz
pF
Pericom Semiconductor Corporation
2380 Bering Drive • San Jose, CA 95131 • 1-800-435-2336 • Fax (408) 435-1100 • http://www.pericom.com
PS8372
01/28/99
5
相关型号：
PI74ALVCHR16269AE
Bus Exchanger, ALVC/VCX/A Series, 1-Func, 12-Bit, True Output, CMOS, PDSO56, 0.240 INCH, PLASTIC, TSSOP-56
PERICOM
PI74ALVCHR16269AEX
Bus Exchanger, ALVC/VCX/A Series, 1-Func, 12-Bit, True Output, CMOS, PDSO56, 0.240 INCH, PLASTIC, TSSOP-56
PERICOM
PI74ALVCHR16269VEX
Bus Exchanger, ALVC/VCX/A Series, 1-Func, 12-Bit, True Output, CMOS, PDSO56, 0.300 INCH, PLASTIC, SSOP-56
PERICOM
PI74ALVCHT16244V
Bus Driver, ALVC/VCX/A Series, 4-Func, 4-Bit, True Output, CMOS, PDSO48, 0.300 INCH, 0.635 MM PITCH, PLASTIC, SSOP-48
PERICOM
PI74ALVCHT16245AX
Bus Transceiver, ALVC/VCX/A Series, 2-Func, 8-Bit, True Output, CMOS, PDSO48, 0.240 INCH, 1.10 MM HEIGHT, 0.50 MM PITCH, PLASTIC, TSSOP-48
PERICOM
©2020 ICPDF网 联系我们和版权申明