PI74LPT16373 [ETC]
Logic | 16-Bit Transparent Latch ; 逻辑| 16位透明锁存器\n
| 型号： | PI74LPT16373 |
| 厂家： | 
ETC |
| 描述： | Logic | 16-Bit Transparent Latch
|
| 文件： | 总5页 (文件大小：53K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
PI74LPT16373
1
2
Fast CMOS 3.3V 16-Bit
Transparent Latch
Product Features
• CompatiblewithLCX™andLVT™familiesofproducts
Product Description
Pericom Semiconductor’s PI74LPT series of logic circuits are pro-
duced in the Company’s advanced 0.6 micron CMOS technology,
achieving industry leading speed grades.
• Supports 5V Tolerant Mixed Signal Mode Operation
– Input can be 3V or 5V
– Output can be 3V or connected to 5V bus
The PI74LPT16373 is a 16-bit transparent latch designed with
3-state outputs and are intended for bus oriented applications. The
Output Enable and Latch Enable controls are organized to operate
as two 8-bit latches or one 16-bit latch. When Latch Enable (LE) is
HIGH, the flip-flops appear transparent to the data. The data that
meets the set-up time when LE is LOW is latched. When OE is
HIGH, the bus output is in the high impedance state.
3
• Advanced Low Power CMOS Operation
• Excellent output drive capability:
Balanced drives (24 mA sink and source)
• Pin compatible with industry standard double-density
pinouts
4
5
• Low ground bounce outputs
ThePI74LPT16373canbedrivenfromeither3.3Vor5.0Vdevices
allowing this device to be used as a translator in a mixed
3.3/5.0V system.
• Hysteresis on all inputs
• Industrial operating temperature range: –40°C to +85°C
• Multiple center pins and distributed Vcc/GND pins
minimize switching noise
6
• Packages available:
–48-pin240milwidethinplasticTSSOP(A)
–48-pin300milwideplasticSSOP(V)
7
Logic Block Diagram
8
1OE
1LE
2OE
2LE
9
10
11
12
13
14
15
1D0
2D0
D
C
D
C
1O0
2O0
TO 7 OTHER CHANNELS
TO 7 OTHER CHANNELS
PS2069A 01/16/97
1
PI74LPT16373
3.3V 16-BIT TRANSPARENT LATCH
Product Pin Description
Truth Table
Inputs(1)
Outputs(1)
Pin Name
xOE
Description
xDx
H
xLE
H
xOE
L
xOx
H
3-State Output Enable Inputs (Active LOW)
xLE
Latch Enable Inputs (Active HIGH)
L
H
L
L
xDx
Data Inputs
3-State Outputs
Ground
X
X
H
Z
xOx
GND
VCC
Note:
1. H = High Voltage Level, X = Don't Care,
L = Low Voltage Level, Z = High Impedance
Power
Product Pin Configuration
1
OE
1
2
3
4
5
6
7
8
9
48
47
46
1
1
1
LE
1
O
0
1
D
0
1
1
O
D
GND
45 GND
1
O
2
44
43
42
41
40
1D
2
3
1
O
3
1D
V
CC
V
CC
1
O
4
5
1D
4
1
O
1D
5
GND 10
39 GND
1O
1O
2O
2O
6
7
0
1
11
12
13
14
38
37
36
35
1D6
1D7
2D0
2D1
48-PIN
V48
A48
GND 15
34 GND
2
O
O
2
3
16
17
18
19
20
33
32
31
30
29
2
D
2
3
2
2D
V
CC
V
CC
2O
4
5
2D
4
2O
2D
5
GND 21
28 GND
2
O
O
6
7
22
23
27
26
25
2
2
2
D
6
7
2
D
2OE 24
LE
Capacitance (TA = 25°C, f = 1 MHz)
Parameters(1)
Description
Test Conditions
Typ
Max.
Units
CIN
Input Capacitance
Output Capacitance
VIN = 0V
4.5
5.5
6
8
pF
pF
COUT
VOUT = 0V
Note:
1. This parameter is determined by device characterization but is not production tested.
PS2069A 01/16/97
2
PI74LPT16373
3.3V 16-BIT TRANSPARENT LATCH
Maximum Ratings
(Above which the useful life may be impaired. For user guidelines, not tested.)
1
2
Storage Temperature............................................................. –55°C to +125°C
Ambient Temperature with Power Applied............................ –40°C to +85°C
Supply Voltage to Ground Potential (Inputs & Vcc Only)......–0.5V to +7.0V
Supply Voltage to Ground Potential (Outputs & D/O Only) ..–0.5V to +7.0V
DC Input Voltage ....................................................................–0.5V to +7.0V
DC Output Current .............................................................................. 120 mA
Power Dissipation .................................................................................... 1.0W
Note:
Stresses greater than those listed under MAXIMUM
RATINGS may cause permanent damage to the
device. This is a stress rating only and functional
operation of the device at these or any other condi-
tions above those indicated in the operational
sectionsofthisspecificationisnotimplied. Exposure
to absolute maximum rating conditions for extended
periods may affect reliability.
3
4
5
DC Electrical Characteristics (Over the Operating Range, TA = –40°C to +85°C, VCC = 2.7V to 3.6V)
Parameters
Description
Test Conditions(1)
Min. Typ(2) Max. Units
VIH
Input HIGH Voltage (Input pins)
Input HIGH Voltage (I/O pins)
Input LOW Voltage
Guaranteed Logic HIGH Level
2.2
2.0
–0.5
—
—
—
5.5
5.5
0.8
V
V
V
VIL
IIH
IIL
Guaranteed Logic LOW Level
(Input and I/O pins)
6
Input HIGH Current (Input pins)
Input HIGH Current (I/O pins)
Input LOW Current (Input pins)
Input LOW Current (I/O pins)
High Impedance Output Current
(3-State Output pins)
Clamp Diode Voltage
Output HIGH Current
Output LOW Current
Output HIGH Voltage
VCC = Max.
VIN = 5.5V
—
—
—
—
—
—
—
—
—
—
—
—
±1
±1
±1
±1
±1
µA
µA
µA
µA
µA
µA
V
mA
mA
V
VCC = Max.
VIN = VCC
VCC = Max.
VCC = Max.
VCC = Max.
VCC = Max.
VIN = GND
VIN = GND
VOUT = 5.5V
VOUT = GND
7
IOZH
IOZL
VIK
IODH
IODL
VOH
—
±1
VCC = Min., IIN = –18 mA
–0.7
–60
90
–1.2
–110
200
—
—
—
8
VCC = 3.3V, VIN = VIH or VIL, VO = 1.5V(3) –36
VCC = 3.3V, VIN = VIH or VIL, VO = 1.5V(3)
50
IOH = –0.1 mA Vcc-0.2
VCC = Min.
—
9
VIN = VIH or VIL
VCC = 3.0V,
VIN = VIH or VIL
VCC = Min.
VIN = VIH or VIL
IOH = –3 mA
IOH = –8 mA
IOH = –24 mA
IOL = 0.1 mA
IOL = 16 mA
IOL = 24 mA
2.4
2.4(5)
2.0
—
—
—
3.0
3.0
—
V
V
—
10
11
12
13
14
15
VOL
Output LOW Voltage
—
0.2
0.4
0.5
–240
±100
—
V
V
V
mA
µA
mV
0.2
0.3
–85
—
IOS
IOFF
VH
Short Circuit Current(4)
Power Down Disable
Input Hysteresis
VCC = Max.(3), VOUT = GND
VCC = 0V, VIN or VOUT ≤ 4.5V
–60
—
—
150
Notes:
1. For Max. or Min. conditions, use appropriate value specified under Electrical Characteristics for the applicable device type.
2. Typical values are at Vcc = 3.3V, +25°C ambient and maximum loading.
3. Not more than one output should be shorted at one time. Duration of the test should not exceed one second.
4. This parameter is guaranteed but not tested.
5. VOH = VCC – 0.6V at rated current.
PS2069A 01/16/97
3
PI74LPT16373
3.3V 16-BIT TRANSPARENT LATCH
Power Supply Characteristics
Parameters Description
Test Conditions(1)
VCC = Max.
Min. Typ(2) Max. Units
ICC
Quiescent Power Supply Current
VIN = GND or VCC
VIN = VCC – 0.6V(3)
0.1
2.0
10
30
µA
µA
∆ICC
Quiescent Power Supply Current
TTL Inputs HIGH
VCC = Max.
ICCD
Dynamic Power Supply(4)
VCC = Max.,
VIN = VCC
50
75
µA/
Outputs Open
XOE = GND
VIN = GND
MHz
xLE = Vcc
One Bit Toggling
50% Duty Cycle
IC
Total Power Supply
Current(6)
VCC = Max.,
Outputs Open
fI = 10 MHZ
50% Duty Cycle
XOE = GND
XLE = VCC
VIN = VCC – 0.6V
VIN = GND
0.6
2.3
mA
One Bit Toggling
VCC = Max.,
Outputs Open
fI = 2.5 MHZ
50% Duty Cycle
XOE = GND
XLE = VCC
VIN = VCC – 0.6V
VIN = GND
2.1
4.7(5)
16 Bits Toggling
Notes:
1. For Max. or Min. conditions, use appropriate value specified under Electrical Characteristics for the applicable device.
2. Typical values are at Vcc = 3.3V, +25°C ambient.
3. Per TTL driven input; all other inputs at Vcc or GND.
4. This parameter is not directly testable, but is derived for use in Total Power Supply Calculations.
5. Values for these conditions are examples of the Icc formula. These limits are guaranteed but not tested.
6. IC =IQUIESCENT + IINPUTS + IDYNAMIC
IC = ICC + ∆ICC DHNT + ICCD (fCP/2 + fINI)
ICC = Quiescent Current (ICCL, ICCH and ICCZ)
∆ICC = Power Supply Current for a TTL High Input
DH = Duty Cycle for TTL Inputs High
NT = Number of TTL Inputs at DH
ICCD = Dynamic Current Caused by an Input Transition Pair (HLH or LHL)
fCP = Clock Frequency for Register Devices (Zero for Non-Register Devices)
NCP = Number of Clock Inputs at fCP
fI = Input Frequency
NI = Number of Inputs at fI
All currents are in milliamps and all frequencies are in megahertz.
PS2069A 01/16/97
4
PI74LPT16373
3.3V 16-BIT TRANSPARENT LATCH
1
2
Switching Characteristics over Operating Range(1)
LPT16373
Com.
Min(3)
LPT16373A
Com.
LPT16373C
Com.
Parameters Description
Conditions(2)
Max
Min(3)
Max
5.2
Min(3)
Max
4.2
Unit
tPLH
tPHL
Propagation Delay
xDx to xOx
CL = 50 pF
RL = 500Ω
1.5
2.0
1.5
1.5
2.0
1.5
6.0
7.0
1.5
1.5
ns
3
tPLH
tPHL
Propagation Delay
xLE to xOx
7.0
7.2
7.2
2.0
1.5
1.5
2.0
1.5
5.0
6.5
6.5
5.5
2.0
1.5
1.5
2.0
1.5
5.0
5.5
5.5
5.0
ns
ns
ns
ns
ns
ns
ns
tPZH
tPZL
Output Enable Time
xOE to xOx
Output Disable Time(4)
xOE to xOx
4
5
tPHZ
tPLZ
tSU
Setup Time HIGH
or LOW, xDx to xLE
tH
Hold Time HIGH
or LOW, xDx to xLE
xLE Pulse Width(4)
HIGH
6
tW
tSK(o)
Output Skew(5)
0.5
0.5
0.5
7
Notes:
1. Propagation Delays and Enable/Disable times are with Vcc = 3.3V ±0.3V, normal range. For Vcc = 2.7V, extended range, all
8
Propagation Delays and Enable/Disable times should be degraded by 20%.
2. See test circuit and waveforms.
3. Minimum limits are guaranteed but not tested on Propagation Delays.
4. This parameter is guaranteed but not production tested.
5. Skew between any two outputs, of the same package, switching in the same direction. This parameter is guaranteed by design.
9
10
11
12
13
14
15
Pericom Semiconductor Corporation
2380 Bering Drive • San Jose, CA 95131 • 1-800-435-2336 • Fax (408) 435-1100 • http://www.pericom.com
PS2069A 01/16/97
5
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