PI74LPT16543AV [ETC]
Dual 8-bit Bus Transceiver ; 双8位总线收发器\n型号: | PI74LPT16543AV |
厂家: | ETC |
描述: | Dual 8-bit Bus Transceiver
|
文件: | 总5页 (文件大小:255K) |
中文: | 中文翻译 | 下载: | 下载PDF数据表文档文件 |
PI74LPT16543
1
2
Fast CMOS 16-Bit Latched Transceivers
Product Features
ProductDescription
CompatiblewithLCXandLVTfamiliesofproducts
Pericom Semiconductors PI74LPT series of logic circuits are
produced using the Companys advanced 0.6 micron CMOS
technology, achieving industry leading speed grades.
Supports 5V Tolerant Mixed Signal Mode Operation
Input can be 3V or 5V
3
Output can be 3V or connected to 5V bus
ThePI74LPT16543is16-bitlatchedtransceiversorganizedwithtwo
sets of eight D-type latches with separate input and output controls
foreachset.FordataflowfromAtoB,forexample,theA-to-BEnable
(xCEAB)inputmustbeLOWinordertoenterdatafromxAxortotake
data from xBx, as indicated in the Truth Table. With xCEAB LOW,
a LOW signal makes the A-to-B latches transparent; a subsequent
LOW-to-HIGHtransitionofthexLEABsignalputstheAlatchesin
the storage mode and their outputs no longer change the A inputs.
WithxCEABandxOEABbothLOW,the3-stateBoutputbuffersare
active and reflect the data present at the output of the A latches.
ControlofdatafromBtoAissimilar,butusesthexCEAB,xLEAB,
andxOEABinputs.
Advanced Low Power CMOS Operation
Excellent output drive capability:
Balanced drives (24 mA sink and source)
4
5
Pin compatible with industry standard double-density
pinouts
Low ground bounce outputs
Hysteresis on all inputs
Industrial operating temperature range: 40°C to +85°C
Multiple center pins and distributed Vcc/GND pins
minimize switching noise
6
ThePI74LPT16543canbedrivenfromeither3.3Vor5.0Vdevices
allowing this device to be used as a translator in a mixed 3.3/5.0V
system.
Packages available:
56-pin240milwideplasticTSSOP(A)
56-pin300milwideplasticSSOP(V)
7
8
Logic Block Diagram
1OEBA
2OEBA
9
1CEBA
2CEBA
10
11
12
13
14
15
1
LEBA
2
LEBA
1OEAB
2OEAB
1CEAB
2CEAB
1LEAB
2LEAB
C
D
C
D
1B
0
2B0
1A
0
2A0
C
D
C
D
TO 7 OTHER CHANNELS
TO 7 OTHER CHANNELS
PS2072A 01/16/97
1
PI74LPT16543
16-BIT LATCHED TRANSCEIVERS
Truth Table(1)
Product Pin Description
Latch
Status
Output
Buffers
Pin Name
xOEAB
xOEBA
xCEAB
xCEBA
xLEAB
xLEBA
xAx
Description
Inputs
A-to-B Output Enable Input (Active LOW)
B-to-A Output Enable Input (Active LOW)
A-to-B Enable Input (Active LOW)
B-to-A Enable Input (Active LOW)
A-to-B Latch Enable Input (Active LOW)
B-to-A Latch Enable Input (Active LOW)
A-to-B Data Inputs or B-to-A 3-State Outputs
B-to-A Data Inputs or B-to-A 3-State Outputs
Ground
XCEAB XLEAB XOEAB XAX TO XBX
XBX
High Z
X
H
X
X
L
X
H
X
L
X
X
H
L
Storing
Storing
X
High Z
Transparent Current A Inputs
Storing Previous* A Inputs
L
H
L
xBx
NOTES:
GND
1. *Before xLEAB LOW-to-HIGH Transistion
H = High Voltage Level
VCC
Power
L = Low Voltage Level
X = Don't Care or Irrelevant
Z = High Impedance
2. A-to-B data flow shown. B-to-A flow control
is the same, except using xCEBA, xLEBA,
and xOEBA.
Product Pin Configuration
1OEAB
1LEAB
1CEAB
GND
1A0
1OEBA
1LEBA
1CEBA
GND
1B0
1
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
2
3
4
5
1A1
1B1
6
VCC
1A2
VCC
1B2
7
8
1A3
1B3
9
1A4
1B4
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
GND
1A5
GND
1B5
56-Pin
A, V
1A6
1B6
1A7
1B7
2A0
2B0
2A1
2B1
2A2
2B2
GND
2A3
GND
2B3
2A4
2B4
2A5
2B5
VCC
2A6
VCC
2B6
2A7
2B7
GND
2CEAB
2LEAB
2OEAB
GND
2CEBA
2LEBA
2OEBA
PS2072A 01/16/97
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PI74LPT16543
16-BIT LATCHED TRANSCEIVERS
Maximum Ratings
(Above which the useful life may be impaired. For user guidelines, not tested.)
Note:
Storage Temperature............................................................. 55°C to +125°C
Ambient Temperature with Power Applied............................ 40°C to +85°C
Supply Voltage to Ground Potential (Inputs & Vcc Only)......0.5V to +7.0V
Supply Voltage to Ground Potential (Outputs & D/O Only) ..0.5V to +7.0V
DC Input Voltage ....................................................................0.5V to +7.0V
DC Output Current .............................................................................. 120 mA
Power Dissipation .................................................................................... 1.0W
Stresses greater than those listed under MAXIMUM
RATINGS may cause permanent damage to the de-
vice. This is a stress rating only and functional opera-
tionofthedeviceattheseoranyotherconditionsabove
those indicated in the operational sections of this
specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may
affect reliability.
DC Electrical Characteristics (Over the Operating Range, TA = 40°C to +85°C, VCC = 2.7V to 3.6V)
Parameters
Description
Test Conditions(1)
Min. Typ(2) Max. Units
VIH
Input HIGH Voltage (Input pins)
Input HIGH Voltage (I/O pins)
Input LOW Voltage
Guaranteed Logic HIGH Level
2.2
2.0
0.5
5.5
5.5
0.8
V
V
V
VIL
IIH
IIL
Guaranteed Logic LOW Level
(Input and I/O pins)
Input HIGH Current (Input pins)
Input HIGH Current (I/O pins)
Input LOW Current (Input pins)
Input LOW Current (I/O pins)
High Impedance Output Current
(3-State Output pins)
Clamp Diode Voltage
Output HIGH Current
Output LOW Current
Output HIGH Voltage
VCC = Max.
VIN = 5.5V
36
50
±1
±1
±1
±1
±1
µA
µA
µA
µA
µA
µA
V
mA
mA
V
VCC = Max.
VIN = VCC
VCC = Max.
VCC = Max.
VCC = Max.
VCC = Max.
VIN = GND
VIN = GND
VOUT = 5.5V
VOUT = GND
IOZH
IOZL
VIK
IODH
IODL
VOH
±1
VCC = Min., IIN = 18 mA
VCC = 3.3V, VIN = VIH or VIL, VO = 1.5V(3)
VCC = 3.3V, VIN = VIH or VIL, VO = 1.5V(3)
0.7
60
90
1.2
110
200
VCC = Min.
IOH = 0.1 mA Vcc-0.2
VIN = VIH or VIL
VCC = 3.0V,
VIN = VIH or VIL
VCC = Min.
VIN = VIH or VIL
IOH = 3 mA
IOH = 8 mA
IOH = 24 mA
IOL = 0.1 mA
IOL = 16 mA
IOL = 24 mA
2.4
2.4(5)
2.0
60
3.0
3.0
0.2
0.4
0.5
240
±100
V
V
VOL
Output LOW Voltage
V
V
V
mA
µA
mV
0.2
0.3
85
IOS
IOFF
VH
Short Circuit Current(4)
Power Down Disable
Input Hysteresis
VCC = Max.(3), VOUT = GND
VCC = 0V, VIN or VOUT ≤ 4.5V
150
Notes:
1. For Max. or Min. conditions, use appropriate value specified under Electrical Characteristics for the applicable device type.
2. Typical values are at Vcc = 3.3V, +25°C ambient and maximum loading.
3. Not more than one output should be shorted at one time. Duration of the test should not exceed one second.
4. This parameter is guaranteed but not tested.
5. VOH = VCC 0.6V at rated current.
PS2072A 01/16/97
3
PI74LPT16543
16-BIT LATCHED TRANSCEIVERS
Power Supply Characteristics
Parameters Description
Test Conditions(1)
VCC = Max.
Min. Typ(2) Max. Units
ICC
Quiescent Power Supply Current
VIN = GND or VCC
VIN = VCC 0.6V(3)
0.1
2.0
10
30
µA
µA
∆ICC
Quiescent Power Supply Current
TTL Inputs HIGH
VCC = Max.
ICCD
Dynamic Power Supply(4)
VCC = Max.,
VIN = VCC
50
75
µA/
Outputs Open
XOE = GND
VIN = GND
MHz
One Bit Toggling
50% Duty Cycle
IC
Total Power Supply
Current(6)
VCC = Max.,
Outputs Open
fI = 10 MHZ
VIN = VCC 0.6V
VIN = GND
0.6
2.3
mA
50% Duty Cycle
XOE = GND
One Bit Toggling
VCC = Max.,
Outputs Open
fI = 2.5 MHZ
50% Duty Cycle
XOE = GND
VIN = VCC 0.6V
VIN = GND
2.1
4.7(5)
16 Bits Toggling
Notes:
1. For Max. or Min. conditions, use appropriate value specified under Electrical Characteristics for the applicable device.
2. Typical values are at Vcc = 3.3V, +25°C ambient.
3. Per TTL driven input; all other inputs at Vcc or GND.
4. This parameter is not directly testable, but is derived for use in Total Power Supply Calculations.
5. Values for these conditions are examples of the Icc formula. These limits are guaranteed but not tested.
6. IC =IQUIESCENT + IINPUTS + IDYNAMIC
IC = ICC + ∆ICC DHNT + ICCD (fCP/2 + fINI)
ICC = Quiescent Current (ICCL, ICCH and ICCZ)
∆ICC = Power Supply Current for a TTL High Input
DH = Duty Cycle for TTL Inputs High
NT = Number of TTL Inputs at DH
ICCD = Dynamic Current Caused by an Input Transition Pair (HLH or LHL)
fCP = Clock Frequency for Register Devices (Zero for Non-Register Devices)
NCP = Number of Clock Inputs at fCP
fI = Input Frequency
NI = Number of Inputs at fI
All currents are in milliamps and all frequencies are in megahertz.
PS2072A 01/16/97
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PI74LPT16543
16-BIT LATCHED TRANSCEIVERS
Switching Characteristics over Operating Range(1)
1
2
LPT16543
Com.
Conditions(2) Min(3)
LPT16543A
Com.
LPT16543C
Com.
Parameters
Description
Max
Min(3)
Max
Min(3)
Max
5.3
Unit
t
t
PLH
PHL
Propagation Delay
Transparent Mode
C
R
L
L
= 50 pF
= 500
2.5
8.5
2.5
6.5
2.5
ns
Ω
3
xAx to xBx or xBx to xAx
Propagation Delay
xLEBA to xAx, xLEAB to xBx
Output Enable Time
t
t
t
t
t
t
t
PLH
PHL
PZH
PZL
PHZ
PLZ
SU
2.5
2.0
2.0
3.0
2.0
5.0
12.5
12.0
9.0
2.5
2.0
2.0
2.0
2.0
5.0
8.0
9.0
7.5
2.5
2.0
2.0
2.0
2.0
5.0
7.0
8.0
6.5
ns
ns
ns
ns
ns
ns
ns
xOEBA or xOEAB to xAx or xBx
Output Disable Time(4)
xOEBA or xOEAB to xAx or xBx
Setup Time HIGH or LOW
xAx or xBx to xLEAB or xLEBA
Hold Time HIGH or LOW
xAx or xBx to xLEAB or xLEBA
xLEAB or xLEBA Pulse Width
LOW
4
5
t
t
t
H
W
6
SK(o)
Output Skew(5)
0.5
0.5
0.5
Notes:
7
1. Propagation Delays and Enable/Disable times are with Vcc = 3.3V ±0.3V, normal range. For Vcc = 2.7V, extended
range, all Propagation Delays and Enable/Disable times should be degraded by 20%.
2. See test circuit and wave forms.
3. Minimum limits are guaranteed but not tested on Propagation Delays.
4. This parameter is guaranteed but not production tested.
8
5. Skew between any two outputs, of the same package, switching in the same direction. This parameter is guaranteed
by design.
9
10
11
12
13
14
15
Capacitance (TA = 25°C, f = 1 MHz)
Parameters(1)
Description
Test Conditions
Typ
Max.
Units
CIN
Input Capacitance
Output Capacitance
VIN = 0V
4.5
5.5
6
8
pF
pF
COUT
VOUT = 0V
Note:
1. This parameter is determined by device characterization but is not production tested.
Pericom Semiconductor Corporation
2380 Bering Drive • San Jose, CA 95131 • 1-800-435-2336 • Fax (408) 435-1100 • http://www.pericom.com
PS2072A 01/16/97
5
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