PIC12CE5XX [ETC]
;
| 型号： | PIC12CE5XX |
| 厂家： | 
ETC |
| 描述： |
|
| 文件： | 总88页 (文件大小：1869K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
PIC12CE5XX
8-Pin, 8-Bit CMOS Microcontroller with
EEPROM Data Memory
Devices:
Pin Diagram:
PIC12CE518 and PIC12CE519 are 8-bit microcontrol-
lers packaged in 8-lead packages. They are based on
the Enhanced PIC16C5X family.
PDIP, SOIC, Windowed CERDIP
VSS
VDD
1
2
3
4
8
7
6
5
GP0
GP5/OSC1/CLKIN
GP4/OSC2
High-Performance RISC CPU:
• Only 33 single word instructions to learn
GP1
GP3/MCLR/VPP
GP2/T0CKI
• All instructions are single cycle (1 µs) except for
program branches which are two-cycle
• Operating speed: DC - 4 MHz clock input
Special Microcontroller Features:
DC - 1 µs instruction cycle
• In-Circuit Serial Programming (ICSP™) of pro-
gram memory (via two pins)
• Internal 4 MHz RC oscillator with programmable
calibration
Memory
Device
EPROM
Program
RAM
Data
EEPROM
Data
• Power-on Reset (POR)
• Device Reset Timer (DRT)
• Watchdog Timer (WDT) with its own on-chip RC
oscillator for reliable operation
• Programmable code-protection
• Power saving SLEEP mode
• Wake-up from SLEEP on pin change
• Internal weak pull-ups on I/O pins
• Internal pull-up on MCLR pin
PIC12CE518
512 x 12
25 x 8
41 x 8
16 x 8
16 x 8
PIC12CE519 1024 x 12
• 12-bit wide instructions
• 8-bit wide data path
• Special function hardware registers
• Two-level deep hardware stack
• Direct, indirect and relative addressing modes for
data and instructions
• Selectable oscillator options:
- INTRC: Internal 4 MHz RC oscillator
- EXTRC: External low-cost RC oscillator
Peripheral Features:
• 8-bit real-time clock/counter (TMR0) with 8-bit
programmable prescaler
• 1,000,000 erase/write cycle EEPROM data
memory
- XT:
- LP:
Standard crystal/resonator
Power saving, low frequency crystal
CMOS Technology:
• EEPROM data retention > 40 years
• Low-power, high-speed CMOS EPROM/
EEPROM technology
• Fully static design
• Wide temperature range:
- Commercial: 0°C to +70°C
- Industrial: -40°C to +85°C
- Extended: -40°C to +125°C
• Wide operating voltage range:
-Commercial: 3.0V to 5.5V
-Industrial: 3.0V to 5.5V
-Extended: 4.5V to 5.5V
• Low power consumption
- < 2 mA typical @ 5V, 4 MHz
- 15 µA typical @ 3V, 32 kHz
- < 1 µA typical standby current
1997 Microchip Technology Inc.
Preliminary
DS40172A-page 1
PIC12CE5XX
TABLE OF CONTENTS
1.0
2.0
3.0
4.0
5.0
6.0
7.0
8.0
9.0
General Description..................................................................................................................................................................... 3
PIC12CE5XX Device Varieties.................................................................................................................................................... 5
Architectural Overview ................................................................................................................................................................ 7
Memory Organization................................................................................................................................................................ 11
PIC12CE518I/O Port................................................................................................................................................................. 19
EEPROM Peripheral Operation................................................................................................................................................. 21
Timer0 Module and TMR0 Register .......................................................................................................................................... 25
Special Features of the CPU..................................................................................................................................................... 29
Instruction Set Summary........................................................................................................................................................... 41
10.0 Development Support................................................................................................................................................................ 53
11.0 Electrical Characteristics - PIC12CE5XX.................................................................................................................................. 57
12.0 DC and AC Characteristics - PIC12CE5XX .............................................................................................................................. 69
13.0 Packaging Information............................................................................................................................................................... 73
14.0 Appendix A................................................................................................................................................................................ 77
Index .................................................................................................................................................................................................... 83
PIC12CE5XX Product Identification System........................................................................................................................................ 87
To Our Valued Customers
We constantly strive to improve the quality of all our products and documentation. We have spent an exceptional
amount of time to ensure that these documents are correct. However, we realize that we may have missed a few
things. If you find any information that is missing or appears in error, please use the reader response form in the
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DS40172A-page 2
Preliminary
1997 Microchip Technology Inc.
PIC12CE5XX
1.1
Applications
1.0
GENERAL DESCRIPTION
The 8-pin PIC12CE5XX from Microchip Technology is
a family of low-cost, high performance, 8-bit, fully static,
EPROM/EEPROM-based CMOS microcontrollers. It
employs a RISC architecture with only 33 single word/
single cycle instructions. All instructions are single
cycle (1 µs) except for program branches which take
two cycles. The PIC12CE5XX delivers performance an
order of magnitude higher than its competitors in the
same price category. The 12-bit wide instructions are
highly symmetrical resulting in 2:1 code compression
over other 8-bit microcontrollers in its class. The easy
to use and easy to remember instruction set reduces
development time significantly.
The PIC12CE5XX series fits perfectly in applications
ranging from sensory systems, gas detectors and
security systems to low-power remote transmitters/
receivers. The EPROM programming technology
makes customizing application programs (transmitter
codes, appliance settings, receiver frequencies, etc.)
extremely fast and convenient. While the EEPROM
data memory technology allows for the changing of cal-
ibrations factors and security codes, the small footprint
8-pin packages, for through hole or surface mounting,
make this microcontroller series perfect for applications
with space limitations. Low-cost, low-power, high per-
formance, ease of use and I/O flexibility make the
PIC12CE5XX series very versatile even in areas where
no microcontroller use has been considered before
(e.g., timer functions, replacement of “glue” logic and
PLD’s in larger systems, coprocessor applications).
The PIC12CE5XX products are equipped with special
features that reduce system cost and power require-
ments. The Power-On Reset (POR) and Device Reset
Timer (DRT) eliminate the need for external reset cir-
cuitry.There are four oscillator configurations to choose
from, including INTRC internal oscillator mode and the
power-saving LP (Low Power) oscillator. Power saving
SLEEP mode, Watchdog Timer and code protection
features improve system cost, power and reliability.
The PIC12CE5XX are available in the cost-effective
One-Time-Programmable (OTP) versions which are
suitable for production in any volume. The customer
can take full advantage of Microchip’s price leadership
in OTP microcontrollers while benefiting from the OTP’s
flexibility.
The PIC12CE5XX products are supported by a full-fea-
tured macro assembler, a software simulator, an in-cir-
cuit emulator, a ‘C’ compiler, fuzzy logic support tools,
a low-cost development programmer, and a full fea-
tured programmer. All the tools are supported on IBM
PC and compatible machines.
1997 Microchip Technology Inc.
Preliminary
DS40172A-page 3
PIC12CE5XX
TABLE 1-1:
PIC12CXXX FAMILY OF DEVICES
PIC12C508(A) PIC12C509(A) PIC12CE518 PIC12CE519 PIC12C671 PIC12C672
Maximum Frequency
of Operation (MHz)
4
4
4
4
10
10
Clock
EPROM Program
Memory
512 x 12
25
1024 x 12
41
512 x 12
25
1024 x 12
1024 x 14
128
2048 x 14
128
Memory
RAM Data Memory
(bytes)
41
16
EEPROM Data Mem-
ory (bytes)
16
Peripherals
Timer Module(s)
TMR0
—
TMR0
—
TMR0
—
TMR0
—
TMR0
4
TMR0
4
A/D Converter (8-bit)
Channels
Wake-up from
SLEEP on
Yes
Yes
Yes
Yes
Yes
Yes
pin change
Interrupt Sources
I/O Pins
—
5
—
4
4
5
5
5
5
5
Features
Input Pins
1
1
1
1
1
1
Internal Pull-ups
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
In-Circuit Serial Pro- Yes
gramming
Number of Instruc- 33
tions
33
33
33
35
35
Packages
8-pin DIP,
JW, SOIC
8-pin DIP,
JW, SOIC
8-pin DIP,
JW, SOIC
8-pin DIP,
JW, SOIC
8-pin DIP,
JW, SOIC
8-pin DIP,
JW, SOIC
All PIC12CE5XX devices have Power-on Reset, selectable Watchdog Timer, selectable code protect and high I/O current capability.
All PIC12CE5XX devices use serial programming with data pin GP0 and clock pin GP1.
DS40172A-page 4
Preliminary
1997 Microchip Technology Inc.
PIC12CE5XX
2.3
Quick-Turnaround-Production (QTP)
Devices
2.0
PIC12CE5XX DEVICE
VARIETIES
A
variety of packaging options are available.
Microchip offers a QTP Programming Service for
factory production orders. This service is made
available for users who choose not to program a
medium to high quantity of units and whose code
patterns have stabilized. The devices are identical to
the OTP devices but with all EPROM locations and fuse
options already programmed by the factory. Certain
code and prototype verification procedures do apply
before production shipments are available. Please con-
tact your local Microchip Technology sales office for
more details.
Depending on application and production
requirements, the proper device option can be
selected using the information in this section. When
placing orders, please use the PIC12CE5XX Product
Identification System at the back of this data sheet to
specify the correct part number.
2.1
UV Erasable Devices
The UV erasable version, offered in windowed cerdip
package, is optimal for prototype development and
pilot programs.
2.4
Serialized Quick-Turnaround
Production (SQTPSM) Devices
The UV erasable version can be erased and
reprogrammed to any of the configuration modes.
Microchip offers a unique programming service where
few user-defined locations in each device are
Note: Please note that erasing the device will
also erase the pre-programmed internal
calibration value for the internal oscillator.
The calibration value must be saved prior
to erasing the part.
a
programmed with different serial numbers. The serial
numbers may be random, pseudo-random or
sequential.
Serial programming allows each device to have a
unique number which can serve as an entry-code,
password or ID number.
Microchip's PICSTART PLUS and PRO MATE pro-
grammers all support programming of the
PIC12CE5XX. Third party programmers also are avail-
able; refer to the Microchip Third Party Guide for a list
of sources.
2.2
One-Time-Programmable (OTP)
Devices
The availability of OTP devices is especially useful for
customers who need the flexibility for frequent code
updates or small volume applications.
The OTP devices, packaged in plastic packages permit
the user to program them once. In addition to the
program memory, the configuration bits must also be
programmed.
1997 Microchip Technology Inc.
Preliminary
DS40172A-page 5
PIC12CE5XX
NOTES:
DS40172A-page 6
Preliminary
1997 Microchip Technology Inc.
PIC12CE5XX
The PIC12CE5XX device contains an 8-bit ALU and
3.0
ARCHITECTURAL OVERVIEW
working register. The ALU is
a general purpose
The high performance of the PIC12CE5XX family can
be attributed to a number of architectural features
commonly found in RISC microprocessors. To begin
with, the PIC12CE5XX uses a Harvard architecture in
which program and data are accessed on separate
buses. This improves bandwidth over traditional von
Neumann architecture where program and data are
fetched on the same bus. Separating program and
data memory further allows instructions to be sized
differently than the 8-bit wide data word. Instruction
opcodes are 12-bits wide making it possible to have all
arithmetic unit. It performs arithmetic and Boolean
functions between data in the working register and any
register file.
The ALU is 8-bits wide and capable of addition,
subtraction, shift and logical operations. Unless
otherwise mentioned, arithmetic operations are two's
complement in nature. In two-operand instructions,
typically one operand is the W (working) register. The
other operand is either a file register or an immediate
constant. In single operand instructions, the operand
is either the W register or a file register.
single word instructions.
A 12-bit wide program
memory access bus fetches a 12-bit instruction in a
single cycle. A two-stage pipeline overlaps fetch and
execution of instructions. Consequently, all instructions
(33) execute in a single cycle (1µs @ 4MHz) except for
program branches.
The W register is an 8-bit working register used for
ALU operations. It is not an addressable register.
Depending on the instruction executed, the ALU may
affect the values of the Carry (C), Digit Carry (DC),
and Zero (Z) bits in the STATUS register. The C and
DC bits operate as a borrow and digit borrow out bit,
respectively, in subtraction. See the SUBWFand ADDWF
instructions for examples.
The PIC12CE518 addresses 512 x 12 of program
memory, the PIC12CE519 addresses 1K x 12 of
program memory. All program memory is internal.
The PIC12CE5XX can directly or indirectly address its
register files and data memory. All special function
registers including the program counter are mapped in
the data memory. The PIC12CE5XX has a highly
orthogonal (symmetrical) instruction set that makes it
possible to carry out any operation on any register
using any addressing mode. This symmetrical nature
and lack of ‘special optimal situations’ make
programming with the PIC12CE5XX simple yet
efficient. In addition, the learning curve is reduced
significantly.
A simplified block diagram is shown in Figure 3-1, with
the corresponding device pins described in Table 3-1.
The PIC12CE5XX contains
a 16 X 8 EEPROM
memory array for storing non-volatile information such
as calibration data or security codes. This memory
has an endurance of 1,000,000 erase/write cycles and
a retention of 40+ years.
1997 Microchip Technology Inc.
Preliminary
DS40172A-page 7
PIC12CE5XX
FIGURE 3-1: PIC12CE5XX BLOCK DIAGRAM
12
8
GPIO
Data Bus
Program Counter
EPROM
GP0
GP1
512 x 12 or
1024 x 12
RAM
GP2/T0CKI
GP3/MCLR/VPP
GP4/OSC2
GP5/OSC1/CLKIN
Program
STACK1
Memory
25 x 8 or
STACK2
File
Registers
Program
12
RAM Addr
Bus
9
Addr MUX
Instruction reg
Indirect
Addr
5
Direct Addr
5-7
16 X 8
EEPROM
Data
FSR reg
STATUS reg
8
Memory
3
MUX
Device Reset
Timer
Instruction
Decode &
Control
ALU
Power-on
Reset
8
Timing
Generation
Watchdog
Timer
OSC1/CLKIN
OSC2
W reg
Internal RC
OSC
Timer0
MCLR
VDD, VSS
DS40172A-page 8
Preliminary
1997 Microchip Technology Inc.
PIC12CE5XX
TABLE 3-1:
Name
PIC12CE5XX PINOUT DESCRIPTION
DIP
SOIC
Pin #
I/O/P
Type
Buffer
Type
Description
Pin #
GP0
7
7
I/O
TTL/ST Bi-directional I/O port/ serial programming data. Can
be software programmed for internal weak pull-up and
wake-up from SLEEP on pin change. This buffer is a
Schmitt Trigger input when used in serial programming
mode.
GP1
6
6
I/O
TTL/ST Bi-directional I/O port/ serial programming clock. Can
be software programmed for internal weak pull-up and
wake-up from SLEEP on pin change. This buffer is a
Schmitt Trigger input when used in serial programming
mode.
GP2/T0CKI
5
4
5
4
I/O
I
ST
Bi-directional I/O port. Can be configured as T0CKI.
GP3/MCLR/VPP
TTL
Input port/master clear (reset) input/programming volt-
age input. When configured as MCLR, this pin is an
active low reset to the device. Voltage on MCLR/VPP
must not exceed VDD during normal device operation.
Can be software programmed for internal weak pull-up
and wake-up from SLEEP on pin change. Weak pull-
up always on if configured as MCLR
GP4/OSC2
3
2
3
2
I/O
I/O
TTL
Bi-directional I/O port/oscillator crystal output. Con-
nections to crystal or resonator in crystal oscillator
mode (XT and LP modes only, GPIO in other modes).
GP5/OSC1/CLKIN
TTL/ST Bidirectional IO port/oscillator crystal input/external
clock source input (GPIO in Internal RC mode only,
OSC1 in all other oscillator modes). TTL input when
GPIO, ST input in external RC oscillator mode.
VDD
VSS
1
8
1
8
P
P
—
—
Positive supply for logic and I/O pins
Ground reference for logic and I/O pins
Legend: I = input, O = output, I/O = input/output, P = power, — = not used, TTL = TTL input,
ST = Schmitt Trigger input
1997 Microchip Technology Inc.
Preliminary
DS40172A-page 9
PIC12CE5XX
3.1
Clocking Scheme/Instruction Cycle
3.2
Instruction Flow/Pipelining
The clock input (OSC1/CLKIN pin) is internally divided
by four to generate four non-overlapping quadrature
clocks namely Q1, Q2, Q3 and Q4. Internally, the
program counter is incremented every Q1, and the
instruction is fetched from program memory and
latched into instruction register in Q4. It is decoded
and executed during the following Q1 through Q4. The
clocks and instruction execution flow is shown in
Figure 3-2 and Example 3-1.
An Instruction Cycle consists of four Q cycles (Q1, Q2,
Q3 and Q4). The instruction fetch and execute are
pipelined such that fetch takes one instruction cycle
while decode and execute takes another instruction
cycle. However, due to the pipelining, each instruction
effectively executes in one cycle. If an instruction
causes the program counter to change (e.g., GOTO)
then two cycles are required to complete the
instruction (Example 3-1).
A fetch cycle begins with the program counter (PC)
incrementing in Q1.
In the execution cycle, the fetched instruction is
latched into the Instruction Register (IR) in cycle Q1.
This instruction is then decoded and executed during
the Q2, Q3, and Q4 cycles. Data memory is read
during Q2 (operand read) and written during Q4
(destination write).
FIGURE 3-2: CLOCK/INSTRUCTION CYCLE
Q2
Q3
Q4
Q2
Q3
Q4
Q2
Q3
Q4
Q1
Q1
Q1
OSC1
Q1
Q2
Q3
Q4
PC
Internal
phase
clock
PC
PC+1
PC+2
Fetch INST (PC)
Execute INST (PC-1)
Fetch INST (PC+1)
Execute INST (PC)
Fetch INST (PC+2)
Execute INST (PC+1)
EXAMPLE 3-1: INSTRUCTION PIPELINE FLOW
1. MOVLW 03H
2. MOVWF GPIO
3. CALL SUB_1
Fetch 1
Execute 1
Fetch 2
Execute 2
Fetch 3
Execute 3
Fetch 4
4. BSF
GPIO, BIT1
Flush
Fetch SUB_1 Execute SUB_1
All instructions are single cycle, except for any program branches. These take two cycles since the fetch
instruction is “flushed” from the pipeline while the new instruction is being fetched and then executed.
DS40172A-page 10
Preliminary
1997 Microchip Technology Inc.
PIC12CE5XX
FIGURE 4-1: PROGRAM MEMORY MAP
AND STACK FOR THE
4.0
MEMORY ORGANIZATION
PIC12CE5XX memory is organized into program mem-
ory and data memory. For devices with more than 512
bytes of program memory, a paging scheme is used.
Program memory pages are accessed using one STA-
TUS register bit. For the PIC12CE519 with a data
memory register file of more than 32 registers, a bank-
ing scheme is used. Data memory banks are accessed
using the File Select Register (FSR).
PIC12CE5XX
PC<11:0>
12
CALL, RETLW
Stack Level 1
Stack Level 2
4.1
Program Memory Organization
Reset Vector (note 1)
0000h
The PIC12CE5XX devices have a 12-bit Program
Counter (PC) capable of addressing
program memory space.
a 2K x 12
On-chip Program
Memory
Only the first 512
x 12 (0000h-01FFh) for the
PIC12CE518 and 1K x 12 (0000h-03FFh) for the
PIC12CE519 are physically implemented. Refer to
512 Word (PIC12CE518)
01FFh
0200h
Figure 4-1. Accessing
a
location above these
boundaries will cause a wrap-around within the first
512 x 12 space (PIC12CE518) or 1K x 12 space
(PIC12CE519). The effective reset vector is at 000h,
(see Figure 4-1). Location 01FFh (PIC12CE518) or
location 03FFh (PIC12CE519), the hardwired reset
vector location, contains the internal clock oscillator
calibration value. This value is set at Microchip and
On-chip Program
Memory
1024 Word (PIC12CE519)
03FFh
0400h
should never be overwritten.
Upon reset, the
MOVLW XX is executed, the PC wraps to location
0000h, thus making 0000h the effective reset vector.
7FFh
Note 1: Address 0000h becomes the
effective reset vector. Location
01FFh (PIC12CE518) or location
03FFh (PIC12CE519) contains the
MOVLW XX INTRC oscillator
calibration value.
1997 Microchip Technology Inc.
Preliminary
DS40172A-page 11
PIC12CE5XX
4.2
Data Memory Organization
FIGURE 4-2: PIC12CE518 REGISTER FILE
MAP
Data memory is composed of registers, or bytes of
RAM. Therefore, data memory for a device is specified
by its register file. The register file is divided into two
functional groups: special function registers and
general purpose registers.
File Address
INDF(1)
00h
TMR0
PCL
01h
02h
03h
04h
05h
06h
07h
The special function registers include the TMR0
register, the Program Counter (PC), the Status
Register, the I/O registers (ports), and the File Select
Register (FSR). In addition, special purpose registers
are used to control the I/O port configuration and
prescaler options.
STATUS
FSR
OSCCAL
GPIO
The general purpose registers are used for data and
control information under command of the instructions.
For the PIC12CE518, the register file is composed of 7
special function registers and 25 general purpose
registers (Figure 4-2).
General
Purpose
Registers
For the PIC12CE519, the register file is composed of 7
special function registers, 25 general purpose
registers, and 16 general purpose registers that may
be addressed using a banking scheme (Figure 4-3).
1Fh
4.2.1
GENERAL PURPOSE REGISTER FILE
Note 1: Not a physical register. See Indirect
Data Addressing, Section 4.8.
The general purpose register file is accessed either
directly or indirectly through the file select register
FSR (Section 4.8).
FIGURE 4-3: PIC12CE519 REGISTER FILE MAP
FSR<6:5>
File Address
00h
00
01
INDF(1)
TMR0
PCL
20h
01h
02h
03h
04h
05h
Addresses map
back to
addresses
in Bank 0.
STATUS
FSR
OSCCAL
GPIO
06h
07h
General
Purpose
Registers
2Fh
0Fh
10h
1Fh
30h
General
Purpose
Registers
General
Purpose
Registers
3Fh
Bank 0
Bank 1
Note 1: Not a physical register. See Indirect
Data Addressing, Section 4.8.
DS40172A-page 12
Preliminary
1997 Microchip Technology Inc.
PIC12CE5XX
4.2.2
SPECIAL FUNCTION REGISTERS
The special registers can be classified into two sets.
The special function registers associated with the
“core” functions are described in this section. Those
related to the operation of the peripheral features are
described in the section for each peripheral feature.
The Special Function Registers (SFRs) are registers
used by the CPU and peripheral functions to control
the operation of the device (Table 4-1).
TABLE 4-1:
SPECIAL FUNCTION REGISTER (SFR) SUMMARY
Value on
Power-On
Reset
Value on
MCLR and Wake-up on
WDT Reset Pin Change
Value on
Address
Name
Bit 7
Bit 6 Bit 5 Bit 4
Bit 3
Bit 2
Bit 1 Bit 0
—
—
N/A
TRIS
I/O control registers
--11 1111 --11 1111 --11 1111
1111 1111 1111 1111 1111 1111
Contains control bits to configure Timer0, Timer0/WDT
prescaler, wake-up on change, and weak pull-ups
N/A
OPTION
Uses contents of FSR to address data memory (not a physical
register)
00h
01h
INDF
xxxx xxxx uuuu uuuu uuuu uuuu
xxxx xxxx uuuu uuuu uuuu uuuu
TMR0
8-bit real-time clock/counter
Low order 8 bits of PC
(1)
02h
PCL
1111 1111 1111 1111 1111 1111
0001 1xxx 000q quuu 100q quuu
—
03h
04h
04h
STATUS
GPWUF
PA0
TO
PD
Z
DC
C
FSR
(12CE518)
Indirect data memory address pointer
Indirect data memory address pointer
111x xxxx 111u uuuu 111u uuuu
110x xxxx 11uu uuuu 11uu uuuu
FSR
(12CE519)
OSCCAL
(12CE518/
12CE519)
05h
06h
CAL7 CAL6 CAL5 CAL4 CALFST CALSLW
SCL SDA GP5 GP4 GP3 GP2
—
—
0111 00-- uuuu uu-- uuuu uu--
GPIO
GP1 GP0 11xx xxxx 11uu uuuu 11uu uuuu
Legend: Shaded boxes = unimplemented or unused, —= unimplemented, read as '0' (if applicable)
x= unknown, u= unchanged, q= see the tables in Section 8.7 for possible values.
Note 1: The upper byte of the Program Counter is not directly accessible. See Section 4.6
for an explanation of how to access these bits.
1997 Microchip Technology Inc.
Preliminary
DS40172A-page 13
PIC12CE5XX
4.2.3
EEPROM DATA MEMORY
For example, CLRF STATUSwill clear the upper three
bits and set the Z bit. This leaves the STATUS register
as 000u u1uu(where u= unchanged).
The PIC12CE518 and PIC12CE519 each have 16
bytes of EEPROM data memory. The EEPROM data
memory supports a bi-directional 2-wire bus and data
transmission protocol.
EEPROM Peripherals.
It is recommended, therefore, that only BCF, BSF and
MOVWF instructions be used to alter the STATUS
register because these instructions do not affect the Z,
DC or C bits from the STATUS register. For other
instructions, which do affect STATUS bits, see
Instruction Set Summary.
Refer to Section 6.0 on
4.3
STATUS Register
This register contains the arithmetic status of the ALU,
the RESET status, and the page preselect bit for
program memories larger than 512 words.
The STATUS register can be the destination for any
instruction, as with any other register. If the STATUS
register is the destination for an instruction that affects
the Z, DC or C bits, then the write to these three bits is
disabled. These bits are set or cleared according to
the device logic. Furthermore, the TO and PD bits are
not writable. Therefore, the result of an instruction with
the STATUS register as destination may be different
than intended.
FIGURE 4-4: STATUS REGISTER (ADDRESS:03h)
R/W-0
GPWUF
R/W-0
—
R/W-0
PA0
R-1
TO
R-1
PD
R/W-x
Z
R/W-x
DC
R/W-x
C
R = Readable bit
W = Writable bit
- n = Value at POR reset
bit7
6
5
4
3
2
1
bit0
bit 7:
GPWUF: GPIO reset bit
1 = Reset due to wake-up from SLEEP on pin change
0 = After power up or other reset
bit 6:
bit 5:
Unimplemented
PA0: Program page preselect bits
1 = Page 1 (200h - 3FFh) - PIC12CE519
0 = Page 0 (000h - 1FFh) - PIC12CE518 and PIC12CE519
Each page is 512 bytes.
Using the PA0 bit as a general purpose read/write bit in devices which do not use it for program
page preselect is not recommended since this may affect upward compatibility with future products.
bit 4:
bit 3:
bit 2:
bit 1:
TO: Time-out bit
1 = After power-up, CLRWDTinstruction, or SLEEPinstruction
0 = A WDT time-out occurred
PD: Power-down bit
1 = After power-up or by the CLRWDTinstruction
0 = By execution of the SLEEPinstruction
Z: Zero bit
1 = The result of an arithmetic or logic operation is zero
0 = The result of an arithmetic or logic operation is not zero
DC: Digit carry/borrow bit (for ADDWFand SUBWFinstructions)
ADDWF
1 = A carry from the 4th low order bit of the result occurred
0 = A carry from the 4th low order bit of the result did not occur
SUBWF
1 = A borrow from the 4th low order bit of the result did not occur
0 = A borrow from the 4th low order bit of the result occurred
bit 0:
C: Carry/borrow bit (for ADDWF, SUBWFand RRF, RLFinstructions)
ADDWF
SUBWF
RRF or RLF
1 = A carry occurred
0 = A carry did not occur
1 = A borrow did not occur
0 = A borrow occurred
Load bit with LSB or MSB, respectively
DS40172A-page 14
Preliminary
1997 Microchip Technology Inc.
PIC12CE5XX
4.4
OPTION Register
Note: If TRIS bit is set to ‘0’, the wake-up on
change and pull-up functions are disabled
for that pin; i.e., note that TRIS overrides
OPTION control of GPPU and GPWU.
The OPTION register is
register which contains various control bits to
configure the Timer0/WDT prescaler and Timer0.
a
8-bit wide, write-only
By executing the OPTION instruction, the contents of
the W register will be transferred to the OPTION
register. A RESET sets the OPTION<7:0> bits.
Note: If the T0CS bit is set to ‘1’, GP2 is forced to
be an input even if TRIS GP2 = ‘0’.
FIGURE 4-5: OPTION REGISTER
W-1
W-1
GPPU
6
W-1
T0CS
5
W-1
T0SE
4
W-1
PSA
3
W-1
PS2
2
W-1
PS1
1
W-1
PS0
GPWU
W
U
= Writable bit
= Unimplemented bit
bit7
bit0
- n = Value at POR reset
Reference Table 4-1 for
other resets.
bit 7:
bit 6:
bit 5:
bit 4:
bit 3:
GPWU: Enable wake-up on pin change (GP0, GP1, GP3)
1 = Disabled
0 = Enabled
GPPU: Enable weak pull-ups (GP0, GP1, GP3)
1 = Disabled
0 = Enabled
T0CS: Timer0 clock source select bit
1 = Transition on T0CKI pin
0 = Transition on internal instruction cycle clock, Fosc/4
T0SE: Timer0 source edge select bit
1 = Increment on high to low transition on the T0CKI pin
0 = Increment on low to high transition on the T0CKI pin
PSA: Prescaler assignment bit
1 = Prescaler assigned to the WDT
0 = Prescaler assigned to Timer0
bit 2-0: PS2:PS0: Prescaler rate select bits
Bit Value
Timer0 Rate WDT Rate
000
001
010
011
100
101
110
111
1 : 2
1 : 4
1 : 8
1 : 16
1 : 32
1 : 64
1 : 128
1 : 256
1 : 1
1 : 2
1 : 4
1 : 8
1 : 16
1 : 32
1 : 64
1 : 128
1997 Microchip Technology Inc.
Preliminary
DS40172A-page 15
PIC12CE5XX
4.5
OSCCAL Register
The Oscillator Calibration (OSCCAL) register is used to
calibrate the internal 4 MHz oscillator. It contains four
bits for fine calibration and two other bits to either
increase or decrease frequency.
FIGURE 4-6: OSCCAL REGISTER (ADDRESS 8Fh)
R/W-0
CAL3
R/W-1
CAL2
R/W-1
CAL1
R/W-1
CAL0
R/W-0
R/W-0
U-0
—
U-0
—
CALFST CALSLW
R
W
U
= Readable bit
= Writable bit
= Unimplemented bit,
read as ‘0’
bit7
bit0
- n = Value at POR reset
bit 7-4: CAL<3:0>: Fine calibration
bit 3: CALFST: Calibration Fast
1 = Increase frequency
0 = No change
bit 2: CALSLW: Calibration Slow
1 = Decrease frequency
0 = No change
bit 1-0: Unimplemented: Read as '0'
Note: If CALFST = 1 and CALSLW = 1, CALFST has precedence.
DS40172A-page 16
Preliminary
1997 Microchip Technology Inc.
PIC12CE5XX
4.6.1
EFFECTS OF RESET
4.6
Program Counter
The Program Counter is set upon a RESET, which
means that the PC addresses the last location in the
last page i.e., the oscillator calibration instruction. After
executing MOVLW XX, the PC will roll over to location
00h, and begin executing user code.
As a program instruction is executed, the Program
Counter (PC) will contain the address of the next
program instruction to be executed. The PC value is
increased by one every instruction cycle, unless an
instruction changes the PC.
The STATUS register page preselect bits are cleared
upon a RESET, which means that page 0 is pre-
selected.
For a GOTOinstruction, bits 8:0 of the PC are provided
by the GOTO instruction word. The PC Latch (PCL) is
mapped to PC<7:0>. Bit 5 of the STATUS register
provides page information to bit 9 of the PC (Figure 4-
7).
Therefore, upon a RESET, a GOTO instruction will
automatically cause the program to jump to page 0
until the value of the page bits is altered.
For a CALL instruction, or any instruction where the
PCL is the destination, bits 7:0 of the PC again are
provided by the instruction word. However, PC<8>
does not come from the instruction word, but is always
cleared (Figure 4-7).
4.7
Stack
PIC12CE5XX devices have a 12-bit wide hardware
push/pop stack.
Instructions where the PCL is the destination, or
Modify PCL instructions, include MOVWF PC, ADDWF
PC,and BSF PC,5.
A CALLinstruction will push the current value of stack
1 into stack 2 and then push the current program
counter value, incremented by one, into stack level 1. If
more than two sequential CALL’s are executed, only
the most recent two return addresses are stored.
Note: Because PC<8> is cleared in the CALL
instruction, or any Modify PCL instruction,
all subroutine calls or computed jumps are
limited to the first 256 locations of any pro-
gram memory page (512 words long).
A RETLWinstruction will pop the contents of stack level
1 into the program counter and then copy stack level 2
contents into level 1. If more than two sequential
RETLW’s are executed, the stack will be filled with the
address previously stored in level 2. Note that the
W register will be loaded with the literal value specified
in the instruction. This is particularly useful for the
implementation of data look-up tables within the
program memory.
FIGURE 4-7: LOADING OF PC
BRANCH INSTRUCTIONS -
PIC12CE518/CE519
GOTO Instruction
11
10
9
8
7
0
PC
PCL
Instruction Word
0
PA0
7
STATUS
CALL or Modify PCL Instruction
11
10
9
8
7
0
PC
PCL
Instruction Word
Reset to ‘0’
PA0
7
0
STATUS
1997 Microchip Technology Inc.
Preliminary
DS40172A-page 17
PIC12CE5XX
4.8
Indirect Data Addressing; INDF and
FSR Registers
EXAMPLE 4-2: HOW TO CLEAR RAM
USING INDIRECT
ADDRESSING
The INDF register is not
a physical register.
movlw 0x10
;initialize pointer
Addressing INDF actually addresses the register
whose address is contained in the FSR register (FSR
is a pointer). This is indirect addressing.
movwf FSR
; to RAM
;clear INDF register
NEXT
clrf
incf
INDF
FSR,F ;inc pointer
btfsc FSR,4 ;all done?
goto
NEXT
;NO, clear next
EXAMPLE 4-1: INDIRECT ADDRESSING
• Register file 07 contains the value 10h
• Register file 08 contains the value 0Ah
• Load the value 07 into the FSR register
• A read of the INDF register will return the value
of 10h
CONTINUE
:
;YES, continue
The FSR is
a 5-bit wide register. It is used in
conjunction with the INDF register to indirectly address
the data memory area.
• Increment the value of the FSR register by one
(FSR = 08)
• A read of the INDR register now will return the
value of 0Ah.
The FSR<4:0> bits are used to select data memory
addresses 00h to 1Fh.
PIC12CE518: Does not use banking. FSR<6:5> are
unimplemented and read as '1's.
Reading INDF itself indirectly (FSR = 0) will produce
00h. Writing to the INDF register indirectly results in a
no-operation (although STATUS bits may be affected).
PIC12CE519: Uses FSR<5>. Selects between bank 0
and bank 1. FSR<6> is unimplemented, read as '1’ .
A simple program to clear RAM locations 10h-1Fh
using indirect addressing is shown in Example 4-2.
FIGURE 4-8: DIRECT/INDIRECT ADDRESSING
Direct Addressing
Indirect Addressing
(FSR)
4
(opcode)
0
5
(FSR)
0
6
4
5
6
location select
bank select
location select
bank
00
01
00h
Addresses
map back to
addresses
in Bank 0.
Data
Memory
0Fh
10h
(1)
1Fh
Bank 0
3Fh
Bank 1
(2)
Note 1: For register map detail see Section 4.2.
Note 2: PIC12CE519 only
DS40172A-page 18
Preliminary
1997 Microchip Technology Inc.
PIC12CE5XX
5.3
I/O Interfacing
5.0
PIC12CE518 I/O PORT
As with any other register, the I/O register can be
written and read under program control. However,
read instructions (e.g., MOVF GPIO,W) always read the
I/O pins independent of the pin’s input/output modes.
On RESET, all GPIO ports are defined as input (inputs
are at hi-impedance) since the I/O control registers are
all set.
The equivalent circuit for an I/O port pin is shown in
Figure 5-1. All port pins, except GP3 which is input
only, may be used for both input and output
operations. For input operations these ports are non-
latching. Any input must be present until read by an
input instruction (e.g., MOVF GPIO,W). The outputs are
latched and remain unchanged until the output latch is
rewritten. To use
a
port pin as output, the
5.1
GPIO
corresponding direction control bit in TRIS must be
cleared (= 0). For use as an input, the corresponding
TRIS bit must be set. Any I/O pin (except GP3) can be
programmed individually as input or output.
GPIO is an 8-bit I/O register. Only the low order 6 bits
are used (GP5:GP0) for pin control. Bits 6 and 7 (SDA
and SCL) are used by the EEPROM peripheral. Refer
to Section 6.0 and Appendix A for use of SDA and
SCL. Please note that GP3 is an input only pin. The
configuration word can set several I/O’s to alternate
functions. When acting as alternate functions the pins
will read as ‘0’ during port read. Pins GP0, GP1, and
GP3 can be configured with weak pull-ups and also
with wake-up on change. The wake-up on change and
weak pull-up functions are not pin selectable. If pin 4 is
configured as MCLR, weak pull-up is always on and
wake-up on change for this pin is not enabled.
FIGURE 5-1: EQUIVALENT CIRCUIT
FOR A SINGLE I/O PIN
Data
Bus
D
Q
Q
Data
VDD
P
WR
Port
Latch
CK
N
I/O
pin(1)
W
Reg
5.2
TRIS Register
D
Q
Q
The output driver control register is loaded with the
contents of the W register by executing the TRIS f
instruction. A '1' from a TRIS register bit puts the
corresponding output driver in a hi-impedance mode.
A '0' puts the contents of the output data latch on the
selected pins, enabling the output buffer. The
exceptions are GP3 which is input only and GP2 which
may be controlled by the option register, see Figure 4-
5.
TRIS
Latch
VSS
TRIS ‘f’
CK
Reset
Note:
A read of the ports reads the pins, not the
output data latches. That is, if an output
driver on a pin is enabled and driven high,
but the external system is holding it low, a
read of the port will indicate that the pin is
low.
RD Port
Note 1: I/O pins have protection diodes to VDD and VSS.
The TRIS registers are “write-only” and are set (output
drivers disabled) upon RESET.
TABLE 5-1:
SUMMARY OF PORT REGISTERS
Value on
Power-On
Reset
Value on
MCLR and Wake-up on
WDT Reset Pin Change
Value on
Address
Name
TRIS
Bit 7
Bit 6
Bit 5
Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
N/A
N/A
03H
06h
—
—
I/O control registers
--11 1111 --11 1111 --11 1111
1111 1111 1111 1111 1111 1111
0001 1xxx 000q quuu 100q quuu
OPTION GPWU GPPU T0CS T0SE PSA PS2 PS1 PS0
STATUS
GPIO
GPWUF
SCL
—
PA0
TO
PD
Z
DC
C
SDA
GP5
GP4 GP3 GP2 GP1 GP0 11xx xxxx 11uu uuuu 11uu uuuu
Legend: Shaded cells not used by Port Registers, read as ‘0’, — = unimplemented, read as '0', x= unknown, u= unchanged,
q = see tables in Section 8.7 for possible values.
1997 Microchip Technology Inc.
Preliminary
DS40172A-page 19
PIC12CE5XX
5.4
I/O Programming Considerations
BI-DIRECTIONAL I/O PORTS
EXAMPLE 5-1: READ-MODIFY-WRITE
INSTRUCTIONS ON AN
I/O PORT
;Initial GPIO Settings
; GPIO<5:3> Inputs
; GPIO<2:0> Outputs
;
5.4.1
Some instructions operate internally as read followed
by write operations. The BCFand BSFinstructions, for
example, read the entire port into the CPU, execute
the bit operation and re-write the result. Caution must
be used when these instructions are applied to a port
where one or more pins are used as input/outputs. For
example, a BSFoperation on bit5 of GPIO will cause all
eight bits of GPIO to be read into the CPU, bit5 to be
set and the GPIO value to be written to the output
latches. If another bit of GPIO is used as a bi-
directional I/O pin (say bit0) and it is defined as an
input at this time, the input signal present on the pin
itself would be read into the CPU and rewritten to the
data latch of this particular pin, overwriting the
previous content. As long as the pin stays in the input
mode, no problem occurs. However, if bit0 is switched
into output mode later on, the content of the data latch
may now be unknown.
;
;
GPIO latch GPIO pins
---------- ----------
BCF
BCF
MOVLW 007h
TRIS GPIO
GPIO, 5
GPIO, 4
;--01 -ppp
;--10 -ppp
;
--11 pppp
--11 pppp
;--10 -ppp
--11 pppp
;
;Note that the user may have expected the pin
;values to be --00 pppp. The 2nd BCF caused
;GP5 to be latched as the pin value (High).
5.4.2
SUCCESSIVE OPERATIONS ON I/O
PORTS
The actual write to an I/O port happens at the end of
an instruction cycle, whereas for reading, the data
must be valid at the beginning of the instruction cycle
(Figure 5-2). Therefore, care must be exercised if a
write followed by a read operation is carried out on the
same I/O port. The sequence of instructions should
allow the pin voltage to stabilize (load dependent)
before the next instruction, which causes that file to be
read into the CPU, is executed. Otherwise, the
previous state of that pin may be read into the CPU
rather than the new state. When in doubt, it is better to
separate these instructions with a NOP or another
instruction not accessing this I/O port.
Example 5-1 shows the effect of two sequential read-
modify-write instructions (e.g., BCF, BSF, etc.) on an I/
O port.
A pin actively outputting a high or a low should not be
driven from external devices at the same time in order
to change the level on this pin (“wired-or”, “wired-and”).
The resulting high output currents may damage the
chip.
FIGURE 5-2: SUCCESSIVE I/O OPERATION
Q4
Q4
Q4
Q1 Q2
Q4
Q3
Q3
Q3
Q3
Q1 Q2
PC
MOVWF GPIO
Q1 Q2
Q1 Q2
PC + 3
NOP
PC + 1
PC + 2
NOP
This example shows a write to GPIO followed
by a read from GPIO.
Instruction
fetched
MOVF GPIO,W
Data setup time = (0.25 TCY – TPD)
where: TCY = instruction cycle.
TPD = propagation delay
GP5:GP0
Port pin
written here
Port pin
sampled here
Therefore, at higher clock frequencies, a
write followed by a read may be problematic.
Instruction
executed
MOVWF GPIO
(Write to
MOVF GPIO,W
(Read
NOP
GPIO)
GPIO)
DS40172A-page 20
Preliminary
1997 Microchip Technology Inc.
PIC12CE5XX
During data transfer, the data line must remain stable
whenever the clock line is HIGH. Changes in the data
line while the clock line is HIGH will be interpreted as a
START or STOP condition.
6.0
EEPROM PERIPHERAL
OPERATION
The PIC12CE518 and PIC12CE519 each have 16
bytes of EEPROM data memory. The EEPROM mem-
ory has an endurance of 1,000,000 erase/write cycles
and a data retention of greater than 40 years. The
EEPROM data memory supports a bi-directional 2-wire
bus and data transmission protocol. These two-wires
are serial data (SDA) and serial clock (SCL), that are
mapped to bit6 and bit7, respectively, of the GPIO reg-
ister (SFR 06h). Unlike the GP0-GP5 that are con-
nected to the I/O pins, SDA and SCL are only
connected to the internal EEPROM peripheral. For
most applications, all that is required is calls to the fol-
lowing functions:
Accordingly, the following bus conditions have been
defined (Figure 6-1).
6.1.1
Both data and clock lines remain HIGH.
6.1.2 START DATA TRANSFER (B)
BUS NOT BUSY (A)
A HIGH to LOW transition of the SDA line while the
clock (SCL) is HIGH determines a START condition. All
commands must be preceded by a START condition.
6.1.3
STOP DATA TRANSFER (C)
; Byte_Write: Byte write routine
;
;
;
Inputs:EEPROM Address
EEPROM Data
EEADDR
EEDATA
A LOW to HIGH transition of the SDA line while the
clock (SCL) is HIGH determines a STOP condition. All
operations must be ended with a STOP condition.
Outputs:
Return 01 in W if OK, else
return 00 in W
;
6.1.4
DATA VALID (D)
; Read_Current: Read EEPROM at address
currently held by EE device.
The state of the data line represents valid data when,
after a START condition, the data line is stable for the
duration of the HIGH period of the clock signal.
;
;
;
Inputs:NONE
Outputs:
EEPROM Data
EEDATA
Return 01 in W if OK, else
return 00 in W
The data on the line must be changed during the LOW
period of the clock signal. There is one bit of data per
clock pulse.
;
; Read_Random: Read EEPROM byte at supplied
address
;
;
;
Inputs:EEPROM Address
Outputs: EEPROM Data
EEADDR
EEDATA
Each data transfer is initiated with a START condition
and terminated with a STOP condition. The number of
the data bytes transferred between the START and
STOP conditions is determined by the master device
and is theoretically unlimited.
Return 01 in W if OK,
else return 00 in W
The code for these functions is listed in Appendix A,
and is accessed by either including the source code
EEPROM.INC or by linking EEPROM.ASM.
6.1.5
ACKNOWLEDGE
Each receiving device, when addressed, is obliged to
generate an acknowledge after the reception of each
byte. The master device must generate an extra clock
pulse which is associated with this acknowledge bit.
6.0.1
SERIAL DATA
SDA is a bi-directional pin used to transfer addresses
and data into and data out of the device.
For normal data transfer SDA is allowed to change only
during SCL low. Changes during SCL high are
reserved for indicating the START and STOP condi-
tions.
Note: Acknowledge bits are generated if an inter-
nal programming cycle is in progress.
The device that acknowledges has to pull down the
SDA line during the acknowledge clock pulse in such a
way that the SDA line is stable LOW during the HIGH
period of the acknowledge related clock pulse. Of
course, setup and hold times must be taken into
account. A master must signal an end of data to the
slave by not generating an acknowledge bit on the last
byte that has been clocked out of the slave. In this case,
the slave must leave the data line HIGH to enable the
master to generate the STOP condition (Figure 6-2).
6.0.2
SERIAL CLOCK
This SCL input is used to synchronize the data transfer
from and to the device.
6.1
BUS CHARACTERISTICS
The following bus protocol is to be used with the
EEPROM data memory.
• Data transfer may be initiated only when the bus
is not busy.
1997 Microchip Technology Inc.
Preliminary
DS40172A-page 21
PIC12CE5XX
FIGURE 6-1: DATA TRANSFER SEQUENCE ON THE SERIAL BUS
(A)
(B)
(C)
(D)
(C)
(A)
SCL
SDA
START
CONDITION
STOP
CONDITION
ADDRESS OR
ACKNOWLEDGE
VALID
DATA
ALLOWED
TO CHANGE
FIGURE 6-2: ACKNOWLEDGE TIMING
Acknowledge
Bit
1
2
3
4
5
6
7
8
9
1
2
3
SCL
SDA
Data from transmitter
Data from transmitter
Receiver must release the SDA line at this point
so the Transmitter can continue sending data.
Transmitter must release the SDA line at this point
allowing the Receiver to pull the SDA line low to
acknowledge the previous eight bits of data.
6.2
Device Addressing
FIGURE 6-3: CONTROL BYTE FORMAT
Read/Write Bit
After generating a START condition, the bus master
transmits a control byte consisting of a slave address
and a Read/Write bit that indicates what type of opera-
tion is to be performed.The slave address consists of a
4-bit device code (1010) followed by three don't care
bits.
Device Select
Don’t Care
Bits
Bits
S
1
0
1
0
X
X
X R/W ACK
The last bit of the control byte determines the operation
to be performed. When set to a one a read operation is
selected, and when set to a zero a write operation is
selected. (Figure 6-3). The bus is monitored for its cor-
responding slave address all the time. It generates an
acknowledge bit if the slave address was true and it is
not in a programming mode.
Slave Address
Start Bit
Acknowledge Bit
DS40172A-page 22
Preliminary
1997 Microchip Technology Inc.
PIC12CE5XX
6.3
WRITE OPERATIONS
6.4
ACKNOWLEDGE POLLING
6.3.1
BYTE WRITE
Since the device will not acknowledge during a write
cycle, this can be used to determine when the cycle is
complete (this feature can be used to maximize bus
throughput). Once the stop condition for a write com-
mand has been issued from the master, the device ini-
tiates the internally timed write cycle. ACK polling can
be initiated immediately.This involves the master send-
ing a start condition followed by the control byte for a
write command (R/W = 0). If the device is still busy with
the write cycle, then no ACK will be returned. If no ACK
is returned, then the start bit and control byte must be
re-sent. If the cycle is complete, then the device will
return the ACK and the master can then proceed with
the next read or write command. See Figure 6-4 for
flow diagram.
Following the start signal from the master, the device
code (4 bits), the don't care bits (3 bits), and the R/W
bit (which is a logic low) are placed onto the bus by the
master transmitter. This indicates to the addressed
slave receiver that a byte with a word address will follow
after it has generated an acknowledge bit during the
ninth clock cycle. Therefore, the next byte transmitted
by the master is the word address and will be written
into the address pointer. Only the lower four address
bits are used by the device, and the upper four bits are
don’t cares. The address byte is acknowledgeable and
the master device will then transmit the data word to be
written into the addressed memory location. The mem-
ory acknowledges again and the master generates a
stop condition. This initiates the internal write cycle,
and during this time will not generate acknowledge sig-
nals (Figure 6-5). After a byte write command, the inter-
nal address counter will not be incremented and will
point to the same address location that was just written.
If a stop bit is transmitted to the device at any point in
the write command sequence before the entire
sequence is complete, then the command will abort
and no data will be written. If more than 8 data bits are
transmitted before the stop bit is sent, then the device
will clear the previously loaded byte and begin loading
the data buffer again. If more than one data byte is
transmitted to the device and a stop bit is sent before a
full eight data bits have been transmitted, then the write
command will abort and no data will be written. The
EEPROM memory employs a VCC threshold detector
circuit which disables the internal erase/write logic if
the VCC is below minimum VDD.
FIGURE 6-4: ACKNOWLEDGE POLLING
FLOW
Send
Write Command
Send Stop
Condition to
Initiate Write Cycle
Send Start
Send Control Byte
with R/W = 0
Did Device
NO
Acknowledge
(ACK = 0)?
YES
Next
Operation
FIGURE 6-5: BYTE WRITE
S
T
A
R
T
S
T
O
P
BUS ACTIVITY
MASTER
CONTROL
BYTE
WORD
ADDRESS
DATA
SDA LINE
P
S
1
0
1
0
X
X
X
0
X
X
X X
A
C
K
A
C
K
A
C
K
BUS ACTIVITY
X = Don’t Care Bit
1997 Microchip Technology Inc.
Preliminary
DS40172A-page 23
PIC12CE5XX
device as part of a write operation. After the word
address is sent, the master generates a start condition
following the acknowledge. This terminates the write
operation, but not before the internal address pointer is
set. Then the master issues the control byte again but
with the R/W bit set to a one. It will then issue an
acknowledge and transmits the eight bit data word.The
master will not acknowledge the transfer but does gen-
erate a stop condition and the device discontinues
transmission (Figure 6-7). After this command, the
internal address counter will point to the address loca-
tion following the one that was just read.
6.5
READ OPERATIONs
Read operations are initiated in the same way as write
operations with the exception that the R/W bit of the
slave address is set to one.There are three basic types
of read operations: current address read, random read,
and sequential read.
6.5.1
CURRENT ADDRESS READ
It contains an address counter that maintains the
address of the last word accessed, internally incre-
mented by one. Therefore, if the previous read access
was to address n, the next current address read oper-
ation would access data from address n + 1. Upon
receipt of the slave address with the R/W bit set to one,
the device issues an acknowledge and transmits the
eight bit data word. The master will not acknowledge
the transfer but does generate a stop condition and the
device discontinues transmission (Figure 6-6).
6.5.3
SEQUENTIAL READ
Sequential reads are initiated in the same way as a ran-
dom read except that after the device transmits the first
data byte, the master issues an acknowledge as
opposed to a stop condition in a random read. This
directs the device to transmit the next sequentially
addressed 8-bit word (Figure 6-8).
6.5.2
RANDOM READ
To provide sequential reads, it contains an internal
address pointer which is incremented by one at the
completion of each read operation. This address
pointer allows the entire memory contents to be serially
read during one operation.
Random read operations allow the master to access
any memory location in a random manner. To perform
this type of read operation, first the word address must
be set.This is done by sending the word address to the
FIGURE 6-6: CURRENT ADDRESS READ
S
T
S
BUS ACTIVITY
A
CONTROL
BYTE
T
MASTER
R
O
P
T
SDA LINE
S
1 0 1 0 X X X 1
P
A
C
K
N
O
BUS ACTIVITY
DATA
A
C
K
X = Don’t Care Bit
FIGURE 6-7: RANDOM READ
S
T
A
R
T
S
T
A
R
T
S
T
O
P
BUS ACTIVITY
MASTER
CONTROL
BYTE
WORD
ADDRESS (n)
CONTROL
BYTE
X X X X
P
S
1 0 1 0 X X X 0
S
1 0 1 0 X X X 1
SDA LINE
A
C
K
A
C
K
A
C
K
N
O
DATA (n)
BUS ACTIVITY
A
C
K
X = Don’t Care Bit
FIGURE 6-8: SEQUENTIAL READ
S
T
O
P
BUS ACTIVITY
MASTER
CONTROL
BYTE
DATA n
DATA n + 1
DATA n + 2
DATA n + X
SDA LINE
P
A
C
K
A
C
K
A
C
K
A
C
K
N
O
BUS ACTIVITY
A
C
K
DS40172A-page 24
Preliminary
1997 Microchip Technology Inc.
PIC12CE5XX
Counter mode is selected by setting the T0CS bit
(OPTION<5>). In this mode, Timer0 will increment
either on every rising or falling edge of pin T0CKI. The
T0SE bit (OPTION<4>) determines the source edge.
Clearing the T0SE bit selects the rising edge.
Restrictions on the external clock input are discussed
in detail in Section 7.1.
7.0
TIMER0 MODULE AND
TMR0 REGISTER
The Timer0 module has the following features:
• 8-bit timer/counter register, TMR0
- Readable and writable
• 8-bit software programmable prescaler
• Internal or external clock select
- Edge select for external clock
The prescaler may be used by either the Timer0
module or the Watchdog Timer, but not both. The
prescaler assignment is controlled in software by the
control bit PSA (OPTION<3>). Clearing the PSA bit
will assign the prescaler to Timer0. The prescaler is
not readable or writable. When the prescaler is
assigned to the Timer0 module, prescale values of 1:2,
1:4,..., 1:256 are selectable. Section 7.2 details the
operation of the prescaler.
Figure 7-1 is a simplified block diagram of the Timer0
module.
Timer mode is selected by clearing the T0CS bit
(OPTION<5>). In timer mode, the Timer0 module will
increment every instruction cycle (without prescaler). If
TMR0 register is written, the increment is inhibited for
the following two cycles (Figure 7-2 and Figure 7-3).
The user can work around this by writing an adjusted
value to the TMR0 register.
A summary of registers associated with the Timer0
module is found in Table 7-1.
FIGURE 7-1: TIMER0 BLOCK DIAGRAM
Data bus
GP2/T0CKI
Pin
FOSC/4
0
1
PSout
8
1
0
Sync with
Internal
Clocks
TMR0 reg
Programmable
PSout
Sync
(2)
Prescaler
(2 cycle delay)
T0SE
3
(1)
(1)
PS2, PS1, PS0
PSA
(1)
T0CS
Note 1: Bits T0CS, T0SE, PSA, PS2, PS1 and PS0 are located in the OPTION register.
2: The prescaler is shared with the Watchdog Timer (Figure 7-5).
1997 Microchip Technology Inc.
Preliminary
DS40172A-page 25
PIC12CE5XX
FIGURE 7-2: TIMER0 TIMING: INTERNAL CLOCK/NO PRESCALE
Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4
PC
(Program
Counter)
PC-1
PC
PC+1
PC+2
PC+3
PC+4
PC+5
PC+6
Instruction
Fetch
MOVF TMR0,W MOVF TMR0,W MOVF TMR0,W MOVF TMR0,W MOVF TMR0,W
MOVWF TMR0
T0
T0+1
T0+2
NT0
NT0
NT0
NT0+1
NT0+2
Timer0
Instruction
Executed
Read TMR0
reads NT0 + 1
Read TMR0
reads NT0
Read TMR0
reads NT0
Read TMR0
reads NT0
Read TMR0
reads NT0 + 2
Write TMR0
executed
FIGURE 7-3: TIMER0 TIMING: INTERNAL CLOCK/PRESCALE 1:2
Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4
PC
(Program
Counter)
PC-1
PC
PC+1
PC+2
PC+3
PC+4
PC+5
PC+6
MOVF TMR0,W MOVF TMR0,W MOVF TMR0,W MOVF TMR0,W MOVF TMR0,W
MOVWF TMR0
Instruction
Fetch
T0
T0+1
NT0+1
NT0
Timer0
Instruction
Execute
Read TMR0
reads NT0
Read TMR0
reads NT0
Read TMR0
reads NT0
Read TMR0
reads NT0
Read TMR0
reads NT0 + 1
Write TMR0
executed
TABLE 7-1:
REGISTERS ASSOCIATED WITH TIMER0
Value on
Value on
Value on
Power-On
Reset
MCLR and Wake-up on
WDT Reset Pin Change
Address Name
Bit 7
Timer0 - 8-bit real-time clock/counter
OPTION GPWU GPPU T0CS T0SE PSA PS2 PS1 PS0 1111 1111 1111 1111
TRIS I/O control registers
Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
01h
N/A
N/A
TMR0
xxxx xxxx uuuu uuuu
uuuu uuuu
1111 1111
--11 1111 --11 1111 --11 1111
Legend: Shaded cells not used by Timer0, -= unimplemented, x = unknown, u= unchanged,
DS40172A-page 26
Preliminary
1997 Microchip Technology Inc.
PIC12CE5XX
When a prescaler is used, the external clock input is
divided by the asynchronous ripple counter-type
prescaler so that the prescaler output is symmetrical.
For the external clock to meet the sampling
requirement, the ripple counter must be taken into
account. Therefore, it is necessary for T0CKI to have a
period of at least 4TOSC (and a small RC delay of
40 ns) divided by the prescaler value. The only
requirement on T0CKI high and low time is that they
do not violate the minimum pulse width requirement of
10 ns. Refer to parameters 40, 41 and 42 in the
electrical specification of the desired device.
7.1
Using Timer0 with an External Clock
When an external clock input is used for Timer0, it
must meet certain requirements. The external clock
requirement is due to internal phase clock (TOSC)
synchronization. Also, there is a delay in the actual
incrementing of Timer0 after synchronization.
7.1.1
EXTERNAL CLOCK SYNCHRONIZATION
When no prescaler is used, the external clock input is
the same as the prescaler output. The synchronization
of T0CKI with the internal phase clocks is
accomplished by sampling the prescaler output on the
Q2 and Q4 cycles of the internal phase clocks
(Figure 7-4). Therefore, it is necessary for T0CKI to be
high for at least 2TOSC (and a small RC delay of 20 ns)
and low for at least 2TOSC (and a small RC delay of
20 ns). Refer to the electrical specification of the
desired device.
7.1.2
TIMER0 INCREMENT DELAY
Since the prescaler output is synchronized with the
internal clocks, there is a small delay from the time the
external clock edge occurs to the time the Timer0
module is actually incremented. Figure 7-4 shows the
delay from the external clock edge to the timer
incrementing.
7.1.3
OPTION REGISTER EFFECT ON GP2 TRIS
If the option register is set to read TIMER0 from the pin,
the port is forced to an input regardless of theTRIS reg-
ister setting.
FIGURE 7-4: TIMER0 TIMING WITH EXTERNAL CLOCK
Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4
Small pulse
External Clock Input or
misses sampling
Prescaler Output (2)
(1)
External Clock/Prescaler
Output After Sampling
(3)
Increment Timer0 (Q4)
Timer0
T0
T0 + 1
T0 + 2
Note 1: Delay from clock input change to Timer0 increment is 3Tosc to 7Tosc. (Duration of Q = Tosc).
Therefore, the error in measuring the interval between two edges on Timer0 input = ± 4Tosc max.
2: External clock if no prescaler selected, Prescaler output otherwise.
3: The arrows indicate the points in time where sampling occurs.
1997 Microchip Technology Inc.
Preliminary
DS40172A-page 27
PIC12CE5XX
7.2
Prescaler
EXAMPLE 7-1: CHANGING PRESCALER
(TIMER0→WDT)
An 8-bit counter is available as a prescaler for the
Timer0 module, or as a postscaler for the Watchdog
Timer (WDT), respectively (Section 8.6). For simplicity,
this counter is being referred to as “prescaler”
throughout this data sheet. Note that the prescaler
may be used by either the Timer0 module or the WDT,
but not both. Thus, a prescaler assignment for the
Timer0 module means that there is no prescaler for
the WDT, and vice-versa.
1.CLRWDT
2.CLRF
;Clear WDT
TMR0
;Clear TMR0 & Prescaler
3.MOVLW '00xx1111’b;;These 3 lines (5, 6, 7)
4.OPTION
; are required only if
; desired
;PS<2:0> are 000 or 001
5.CLRWDT
6.MOVLW '00xx1xxx’b ;Set Postscaler to
7.OPTION ; desired WDT rate
To change prescaler from the WDT to the Timer0
module, use the sequence shown in Example 7-2. This
sequence must be used even if the WDT is disabled. A
CLRWDTinstruction should be executed before switching
the prescaler.
The PSA and PS2:PS0 bits (OPTION<3:0>)
determine prescaler assignment and prescale ratio.
When assigned to the Timer0 module, all instructions
writing to the TMR0 register (e.g., CLRF 1, MOVWF 1,
BSF 1,x,etc.) will clear the prescaler. When assigned
to WDT, a CLRWDT instruction will clear the prescaler
along with the WDT. The prescaler is neither readable
nor writable. On a RESET, the prescaler contains all
'0's.
EXAMPLE 7-2: CHANGING PRESCALER
(WDT→TIMER0)
CLRWDT
;Clear WDT and
;prescaler
MOVLW 'xxxx0xxx'
;Select TMR0, new
;prescale value and
;clock source
7.2.1
SWITCHING PRESCALER ASSIGNMENT
OPTION
The prescaler assignment is fully under software control
(i.e., it can be changed “on the fly” during program
execution). To avoid an unintended device RESET, the
following instruction sequence (Example 7-1) must be
executed when changing the prescaler assignment from
Timer0 to the WDT.
FIGURE 7-5: BLOCK DIAGRAM OF THE TIMER0/WDT PRESCALER
TCY ( = Fosc/4)
Data Bus
8
0
GP2/T0CKI
M
U
X
1
Pin
M
U
X
Sync
2
Cycles
1
TMR0 reg
0
T0SE
T0CS
PSA
0
1
8-bit Prescaler
M
U
X
8
Watchdog
Timer
8 - to - 1MUX
PS2:PS0
PSA
1
0
WDT Enable bit
MUX
PSA
WDT
Time-Out
Note: T0CS, T0SE, PSA, PS2:PS0 are bits in the OPTION register.
DS40172A-page 28
Preliminary
1997 Microchip Technology Inc.
PIC12CE5XX
The PIC12CE5XX has a Watchdog Timer which can
be shut off only through configuration bit WDTE. It
runs off of its own RC oscillator for added reliability. If
using XT or LP selectable oscillator options, there is
always an 18 ms (nominal) delay provided by the
Device Reset Timer (DRT), intended to keep the chip
in reset until the crystal oscillator is stable. If using
INTRC or EXTRC there is an 18 ms delay only on VDD
power-up. With this timer on-chip, most applications
need no external reset circuitry.
8.0
SPECIAL FEATURES OF THE
CPU
What sets
a
microcontroller apart from other
processors are special circuits to deal with the needs
of real-time applications. The PIC12CE5XX family of
microcontrollers has a host of such features intended
to maximize system reliability, minimize cost through
elimination of external components, provide power
saving operating modes and offer code protection.
These features are:
The SLEEP mode is designed to offer a very low
current power-down mode. The user can wake-up
from SLEEP through a change on input pins or
through a Watchdog Timer time-out. Several oscillator
options are also made available to allow the part to fit
the application, including an internal 4 MHz oscillator.
The EXTRC oscillator option saves system cost while
• Oscillator selection
• Reset
- Power-On Reset (POR)
- Device Reset Timer (DRT)
- Wake-up from SLEEP on pin change
• Watchdog Timer (WDT)
• SLEEP
the LP crystal option saves power.
A set of
configuration bits are used to select various options.
• Code protection
8.1
Configuration Bits
• ID locations
• In-circuit Serial Programming
The PIC12CE5XX configuration word consists of 5
bits. Configuration bits can be programmed to select
various device configurations. Two bits are for the
selection of the oscillator type, one bit is the Watchdog
Timer enable bit, and one bit is the MCLR enable bit.
One bit is the code protection bit (Figure 8-1).
FIGURE 8-1: CONFIGURATION WORD FOR PIC12CE5XX
—
—
—
9
—
8
—
7
—
6
—
5
MCLRE CP
WDTE FOSC1 FOSC0
bit0
Register: CONFIG
(1)
Address
:
FFFh
bit11
10
4
3
2
1
bit 11-5: Unimplemented
bit 4:
bit 3:
bit 2:
MCLRE: MCLR enable bit.
1 = MCLR pin enabled
0 = MCLR tied to VDD, (Internally)
CP: Code protection bit.
1 = Code protection off
0 = Code protection on
WDTE: Watchdog timer enable bit
1 = WDT enabled
0 = WDT disabled
bit 1-0: FOSC1:FOSC0: Oscillator selection bits
11 = EXTRC - external RC oscillator
10 = INTRC - internal RC oscillator
01 = XT oscillator
00 = LP oscillator
Note 1: Refer to the PIC12C5XX Programming Specifications to determine how to access the
configuration word. This register is not user addressable during device operation. Refer to
In-Circuit Serial Programming™ Guide.
1997 Microchip Technology Inc.
Preliminary
DS40172A-page 29
PIC12CE5XX
8.2
Oscillator Configurations
TABLE 8-1:
CAPACITOR SELECTION
FOR CERAMIC RESONATORS
- PIC12CE5XX
8.2.1
OSCILLATOR TYPES
The PIC12CE5XX can be operated in four different
oscillator modes. The user can program two
configuration bits (FOSC1:FOSC0) to select one of
these four modes:
Osc
Type
Resonator Cap. Range Cap. Range
Freq
C1
C2
XT
4.0 MHz
30 pF
30 pF
These values are for design guidance only. Since
each resonator has its own characteristics, the user
should consult the resonator manufacturer for
appropriate values of external components.
• LP:
• XT:
Low Power Crystal
Crystal/Resonator
• INTRC: Internal 4 MHz Oscillator
• EXTRC: External Resistor/Capacitor
TABLE 8-2:
CAPACITOR SELECTION
FOR CRYSTAL OSCILLATOR
- PIC12CE5XX
8.2.2
CRYSTAL OSCILLATOR / CERAMIC
RESONATORS
Osc
Resonator Cap.Range Cap. Range
In XT or LP modes, a crystal or ceramic resonator is
connected to the GP5/OSC1/CLKIN and GP4/OSC2
pins to establish oscillation (Figure 8-2). The
PIC12CE5XX oscillator design requires the use of a
parallel cut crystal. Use of a series cut crystal may
give a frequency out of the crystal manufacturers
specifications. When in XT or LP modes, the device
can have an external clock source drive the GP5/
OSC1/CLKIN pin (Figure 8-3).
Type
Freq
C1
C2
(1)
LP
XT
32 kHz
15 pF
15 pF
200 kHz
1 MHz
4 MHz
47-68 pF
15 pF
15 pF
47-68 pF
15 pF
15 pF
Note 1: For VDD > 4.5V, C1 = C2 ≈ 30 pF is
recommended.
These values are for design guidance only. Rs may
be required in XT mode to avoid overdriving crystals
with low drive level specification. Since each crystal
has its own characteristics, the user should consult
the crystal manufacturer for appropriate values of
external components.
FIGURE 8-2: CRYSTAL OPERATION (OR
CERAMIC RESONATOR) (XT
OR LP OSC
CONFIGURATION)
(1)
C1
OSC1
PIC12CE5XX
SLEEP
XTAL
(3)
RF
To internal
logic
OSC2
(2)
RS
(1)
C2
Note 1: See Capacitor Selection tables for
recommended values of C1 and C2.
2: A series resistor (RS) may be required for
AT strip cut crystals.
3: RF varies with the crystal chosen
(approx. value = 10 MΩ).
FIGURE 8-3: EXTERNAL CLOCK INPUT
OPERATION (XT OR LP OSC
CONFIGURATION)
OSC1
OSC2
Clock from
ext. system
PIC12CE5XX
Open
DS40172A-page 30
Preliminary
1997 Microchip Technology Inc.
PIC12CE5XX
8.2.3
EXTERNAL CRYSTAL OSCILLATOR
CIRCUIT
8.2.4
EXTERNAL RC OSCILLATOR
For timing insensitive applications, the RC device
option offers additional cost savings. The RC oscillator
frequency is a function of the supply voltage, the
resistor (Rext) and capacitor (Cext) values, and the
operating temperature. In addition to this, the oscillator
frequency will vary from unit to unit due to normal
process parameter variation. Furthermore, the
difference in lead frame capacitance between package
types will also affect the oscillation frequency,
especially for low Cext values. The user also needs to
take into account variation due to tolerance of external
R and C components used.
Either a prepackaged oscillator or a simple oscillator
circuit with TTL gates can be used as an external
crystal oscillator circuit. Prepackaged oscillators
provide a wide operating range and better stability. A
well-designed crystal oscillator will provide good
performance with TTL gates. Two types of crystal
oscillator circuits can be used: one with parallel
resonance, or one with series resonance.
Figure 8-4 shows implementation of
a
parallel
resonant oscillator circuit. The circuit is designed to
use the fundamental frequency of the crystal. The
74AS04 inverter performs the 180-degree phase shift
that a parallel oscillator requires. The 4.7 kΩ resistor
provides the negative feedback for stability. The 10 kΩ
potentiometers bias the 74AS04 in the linear region.
This circuit could be used for external oscillator
designs.
Figure 8-6 shows how the R/C combination is
connected to the PIC12CE5XX. For Rext values below
2.2 kΩ, the oscillator operation may become unstable,
or stop completely. For very high Rext values
(e.g., 1 MΩ) the oscillator becomes sensitive to noise,
humidity and leakage. Thus, we recommend keeping
Rext between 3 kΩ and 100 kΩ.
FIGURE 8-4: EXTERNAL PARALLEL
RESONANT CRYSTAL
Although the oscillator will operate with no external
capacitor (Cext = 0 pF), we recommend using values
above 20 pF for noise and stability reasons. With no or
small external capacitance, the oscillation frequency
can vary dramatically due to changes in external
capacitances, such as PCB trace capacitance or
package lead frame capacitance.
OSCILLATOR CIRCUIT
+5V
To Other
Devices
10k
74AS04
PIC12CE5XX
4.7k
74AS04
CLKIN
The Electrical Specifications sections show RC
frequency variation from part to part due to normal
process variation. The variation is larger for larger R
(since leakage current variation will affect RC
frequency more for large R) and for smaller C (since
variation of input capacitance will affect RC frequency
more).
10k
XTAL
10k
Also, see the Electrical Specifications sections for
variation of oscillator frequency due to VDD for given
Rext/Cext values as well as frequency variation due to
operating temperature for given R, C, and VDD values.
20 pF
20 pF
Figure 8-5 shows a series resonant oscillator circuit.
This circuit is also designed to use the fundamental
frequency of the crystal. The inverter performs a 180-
degree phase shift in a series resonant oscillator
circuit. The 330 Ω resistors provide the negative
feedback to bias the inverters in their linear region.
FIGURE 8-6: EXTERNAL RC OSCILLATOR
MODE
VDD
Rext
Internal
FIGURE 8-5: EXTERNAL SERIES
RESONANT CRYSTAL
clock
OSC1
N
OSCILLATOR CIRCUIT
To Other
Devices
Cext
VSS
PIC12CE5XX
330
330
74AS04
74AS04
74AS04
PIC12CE5XX
CLKIN
0.1 µF
XTAL
1997 Microchip Technology Inc.
Preliminary
DS40172A-page 31
PIC12CE5XX
8.2.5
INTERNAL 4 MHz RC OSCILLATOR
resumption of normal operation. The exceptions to this
are TO, PD, and GPWUF bits. They are set or cleared
differently in different reset situations. These bits are
used in software to determine the nature of reset. See
Table 8-3 for a full description of reset states of all
registers.
The internal RC oscillator provides a fixed 4 MHz (nom-
inal) system clock at VDD = 5V and 25°C, see “Electri-
cal Specifications” section for information on variation
over voltage and temperature..
In addition, a calibration instruction is programmed into
the top of memory which contains the calibration value
for the internal RC oscillator.This value is programmed
as a MOVLW XXinstruction where XX is the calibration
value, and is placed at the reset vector. This will load
the W register with the calibration value upon reset and
the PC will then roll over to the users program at
address 0x000. The user then has the option of writing
the value to the OSCCAL Register (05h) or ignoring it.
OSCCAL, when written to with the calibration value, will
“trim” the internal oscillator to remove process variation
from the oscillator frequency. .
Note: Please note that erasing the device will
also erase the pre-programmed internal
calibration value for the internal oscillator.
The calibration value must be saved prior
to erasing the part.
For the PIC12CE518 and PIC12CE519, bits <7:4>,
CAL3-CAL0 are used for fine calibration while bit 3,
CALFST, and bit 2,CALSLW are used for more coarse
adjustment. Adjusting CAL3-0 from 0000 to 1111
yields a higher clock speed. Set CALFST = 1 for
greater increase in frequency or set CALSLW = 1 for
greater decrease in frequency. Note that bits 1 and 0
of OSCCAL are unimplemented and should be written
as 0 when modifying OSCALL for compatibility with
future devices.
For the PIC12CE518 and PIC12CE519, the upper 4
bits of the register are used to allow for future, longer bit
length calibration schemes. Writing a larger value in
this location yields a higher clock speed.
8.3
RESET
The device differentiates between various kinds of
reset:
a) Power on reset (POR)
b) MCLR reset during normal operation
c) MCLR reset during SLEEP
d) WDT time-out reset during normal operation
e) WDT time-out reset during SLEEP
f) Wake-up from SLEEP on pin change
Some registers are not reset in any way; they are
unknown on POR and unchanged in any other reset.
Most other registers are reset to “reset state” on power-
on reset (POR), on MCLR, WDT or wake-up on pin
change reset during normal operation. They are not
affected by a WDT reset during SLEEP or MCLR reset
during SLEEP, since these resets are viewed as
DS40172A-page 32
Preliminary
1997 Microchip Technology Inc.
PIC12CE5XX
TABLE 8-3:
RESET CONDITIONS FOR REGISTERS
MCLR Reset
WDT time-out
Register
Address
Power-on Reset
Wake-up on Pin Change
W
—
qqqq xxxx (1)
xxxx xxxx
xxxx xxxx
1111 1111
0001 1xxx
111x xxxx
110x xxxx
0111 00--
11xx xxxx
1111 1111
--11 1111
qqqq uuuu (1)
uuuu uuuu
uuuu uuuu
1111 1111
?00? ?uuu (2)
111u uuuu
11uu uuuu
uuuu uu--
11uu uuuu
1111 1111
--11 1111
INDF
TMR0
00h
01h
02h
03h
04h
04h
05h
06h
—
PC
STATUS
FSR (12CF518)
FSR (12CF519)
OSCCAL
GPIO
OPTION
TRIS
—
Legend: u= unchanged, x= unknown, -= unimplemented bit, read as ‘0’, ?= value depends on condition.
Note 1:
Note 2:
Bits <7:4> of W register contain oscillator calibration values due to MOVLW XXinstruction at top of memory.
See Table 8-7 for reset value for specific conditions
TABLE 8-4:
RESET CONDITION FOR SPECIAL REGISTERS
STATUS Addr: 03h
PCL Addr: 02h
Power on reset
0001 1xxx
000u uuuu
0001 0uuuu
0000 0uuu
0000 1uuu
1001 0uuu
1111 1111
1111 1111
1111 1111
1111 1111
1111 1111
1111 1111
MCLR reset during normal operation
MCLR reset during SLEEP
WDT reset during SLEEP
WDT reset normal operation
Wake-up from SLEEP on pin change
Legend: u= unchanged, x= unknown, -= unimplemented bit, read as ‘0’.
1997 Microchip Technology Inc.
Preliminary
DS40172A-page 33
PIC12CE5XX
8.3.1
MCLR ENABLE
The Power-On Reset circuit and the Device Reset
Timer (Section 8.5) circuit are closely related. On
power-up, the reset latch is set and the DRT is reset.
The DRT timer begins counting once it detects MCLR
to be high. After the time-out period, which is typically
18 ms, it will reset the reset latch and thus end the on-
chip reset signal.
This configuration bit when unprogrammed (left in the
‘1’ state) enables the external MCLR function. When
programmed, the MCLR function is tied to the internal
VDD, and the pin is assigned to be a GPIO. See
Figure 8-7.
FIGURE 8-7: MCLR SELECT
A power-up example where MCLR is held low is
shown in Figure 8-9. VDD is allowed to rise and
stabilize before bringing MCLR high. The chip will
actually come out of reset TDRT msec after MCLR
goes high.
MCLRE
In Figure 8-10, the on-chip Power-On Reset feature is
being used (MCLR and VDD are tied together or the
pin is programmed to be GP3.). The VDD is stable
before the start-up timer times out and there is no
problem in getting a proper reset. However, Figure 8-
11 depicts a problem situation where VDD rises too
slowly. The time between when the DRT senses that
MCLR is high and when MCLR (and VDD) actually
reach their full value, is too long. In this situation, when
the start-up timer times out, VDD has not reached the
VDD (min) value and the chip is, therefore, not
guaranteed to function correctly. For such situations,
we recommend that external RC circuits be used to
achieve longer POR delay times (Figure 8-10).
WEAK
PULL-UP
INTERNAL MCLR
GP3/MCLR/VPP
8.4
Power-On Reset (POR)
The PIC12CE5XX family incorporates on-chip Power-
On Reset (POR) circuitry which provides an internal
chip reset for most power-up situations.
A Power-on Reset pulse is generated on-chip when
VDD rise is detected (in the range of 1.5V - 2.1V). To
take advantage of the internal POR, program the GP3/
MCLR/VPP pin as MCLR and tie directly to VDD or pro-
gram the pin as GP3. An internal weak pull-up resistor
is implemented using a transistor. Refer to Table 11-7
for the pull-up resistor ranges. This will eliminate exter-
nal RC components usually needed to create a Power-
on Reset. A maximum rise time for VDD is specified.
See Electrical Specifications for details.
Note: When the device starts normal operation
(exits the reset condition), device operat-
ing parameters (voltage, frequency, tem-
perature, etc.) must be meet to ensure
operation. If these conditions are not met,
the device must be held in reset until the
operating conditions are met.
For additional information refer to Application Notes
“Power-Up Considerations” - AN522 and “Power-up
Trouble Shooting” - AN607.
When the device starts normal operation (exits the
reset condition), device operating parameters (voltage,
frequency, temperature, ...) must be met to ensure
operation. If these conditions are not met, the device
must be held in reset until the operating parameters are
met.
A simplified block diagram of the on-chip Power-On
Reset circuit is shown in Figure 8-8.
DS40172A-page 34
Preliminary
1997 Microchip Technology Inc.
PIC12CE5XX
FIGURE 8-8: SIMPLIFIED BLOCK DIAGRAM OF ON-CHIP RESET CIRCUIT
Power-Up
Detect
Pin Change
SLEEP
POR (Power-On Reset)
VDD
Wake-up on
pin change
GP3/MCLR/VPP
WDT Time-out
MCLRE
RESET
S
R
Q
Q
8-bit Asynch
On-Chip
DRT OSC
Ripple Counter
(Start-Up Timer)
CHIP RESET
FIGURE 8-9: TIME-OUT SEQUENCE ON POWER-UP (MCLR PULLED LOW)
VDD
MCLR
INTERNAL POR
TDRT
DRT TIME-OUT
INTERNAL RESET
FIGURE 8-10: TIME-OUT SEQUENCE ON POWER-UP (MCLR TIED TO VDD): FAST VDD RISE TIME
VDD
MCLR
INTERNAL POR
TDRT
DRT TIME-OUT
INTERNAL RESET
1997 Microchip Technology Inc.
Preliminary
DS40172A-page 35
PIC12CE5XX
FIGURE 8-11: TIME-OUT SEQUENCE ON POWER-UP (MCLRTIED TO VDD): SLOW VDD RISETIME
V1
VDD
MCLR
INTERNAL POR
TDRT
DRT TIME-OUT
INTERNAL RESET
When VDD rises slowly, the TDRT time-out expires long before VDD has reached its final value. In
this example, the chip will reset properly if, and only if, V1 ≥ VDD min.
8.5
Device Reset Timer (DRT)
TABLE 8-5:
DRT (DEVICE RESET TIMER
PERIOD)
In the PIC12CE5XX, the DRT runs any time the device
is powered up. DRT runs from RESET and varies
based on oscillator selection (see Table 8-5.)
Oscillator
Configuration
Subsequent
POR Reset
Resets
The Device Reset Timer (DRT) provides a fixed 18 ms
nominal time-out on reset. The DRT operates on an
internal RC oscillator. The processor is kept in RESET
as long as the DRT is active. The DRT delay allows
VDD to rise above VDD min., and for the oscillator to
stabilize.
IntRC &
ExtRC
18 ms (typical)
300 µs
(typical)
XT & LP
18 ms (typical) 18 ms (typical)
8.6
Watchdog Timer (WDT)
Oscillator circuits based on crystals or ceramic
resonators require a certain time after power-up to
establish a stable oscillation. The on-chip DRT keeps
the device in a RESET condition for approximately 18
ms after MCLR has reached a logic high level. Thus,
programming GP3/MCLR/VPP as MCLR and using an
external RC network connected to the MCLR input is
not required in most cases, allowing for savings in
cost-sensitive and/or space restricted applications, as
well as allowing the use of the GP3/MCLR/VPP pin as
a general purpose input.
The Watchdog Timer (WDT) is a free running on-chip
RC oscillator which does not require any external
components. This RC oscillator is separate from the
external RC oscillator of the GP5/OSC1/CLKIN pin
and the internal 4 MHz oscillator. That means that the
WDT will run even if the main processor clock has
been stopped, for example, by execution of a SLEEP
instruction. During normal operation or SLEEP, a WDT
reset or wake-up reset generates a device RESET.
The TO bit (STATUS<4>) will be cleared upon a
Watchdog Timer reset.
The Device Reset time delay will vary from chip to chip
due to VDD, temperature, and process variation. See
AC parameters for details.
The WDT can be permanently disabled by
programming the configuration bit WDTE as a '0'
(Section 8.1). Refer to the PIC12CE5XX Programming
Specifications to determine how to access the
configuration word.
The DRT will also be triggered upon a Watchdog Timer
time-out (only in XT and LP modes). This is
particularly important for applications using the WDT
to wake from SLEEP mode automatically.
DS40172A-page 36
Preliminary
1997 Microchip Technology Inc.
PIC12CE5XX
8.6.1
WDT PERIOD
8.6.2
WDT PROGRAMMING CONSIDERATIONS
The WDT has a nominal time-out period of 18 ms,
(with no prescaler). If a longer time-out period is
desired, a prescaler with a division ratio of up to 1:128
can be assigned to the WDT (under software control)
by writing to the OPTION register. Thus, a time-out
period of a nominal 2.3 seconds can be realized.
These periods vary with temperature, VDD and part-to-
part process variations (see DC specs).
The CLRWDT instruction clears the WDT and the
postscaler, if assigned to the WDT, and prevents it
from timing out and generating a device RESET.
The SLEEP instruction resets the WDT and the
postscaler, if assigned to the WDT. This gives the
maximum SLEEP time before a WDT wake-up reset.
Under worst case conditions (VDD = Min., Temperature
= Max., max. WDT prescaler), it may take several
seconds before a WDT time-out occurs.
FIGURE 8-12: WATCHDOG TIMER BLOCK DIAGRAM
From Timer0 Clock Source
(Figure 7-5)
0
M
Postscaler
1
Watchdog
Timer
U
X
8 - to - 1 MUX
PS2:PS0
PSA
WDT Enable
Configuration Bit
To Timer0 (Figure 7-4)
1
0
PSA
MUX
Note: T0CS, T0SE, PSA, PS2:PS0
are bits in the OPTION register.
WDT
Time-out
TABLE 8-6:
SUMMARY OF REGISTERS ASSOCIATED WITH THE WATCHDOG TIMER
Value on
Power-On
Reset
Value on
MCLR and
WDT Reset Pin Change
Value on
Wake-up on
Address
Name
Bit 7
Bit 6
Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
1111 1111
N/A
OPTION GPWU GPPU T0CS T0SE PSA PS2 PS1 PS0 1111 1111 1111 1111
Legend: Shaded boxes = Not used by Watchdog Timer, —= unimplemented, read as '0', u= unchanged
1997 Microchip Technology Inc.
Preliminary
DS40172A-page 37
PIC12CE5XX
8.7
Time-Out Sequence, Power Down,
8.8
Reset on Brown-Out
and Wake-up from SLEEP Status Bits
(TO/PD/GPWUF)
A brown-out is a condition where device power (VDD)
dips below its minimum value, but not to zero, and then
recovers. The device should be reset in the event of a
brown-out.
The TO, PD, and GPWUF bits in the STATUS register
can be tested to determine if a RESET condition has
been caused by a power-up condition, a MCLR or
Watchdog Timer (WDT) reset, or a MCLR or WDT
reset.
To reset PIC12CE5XX devices when a brown-out
occurs, external brown-out protection circuits may be
built, as shown in Figure 8-13 and Figure 8-14.
FIGURE 8-13: BROWN-OUT PROTECTION
CIRCUIT 1
TABLE 8-7:
TO/PD/GPWUF STATUS
AFTER RESET
GPWUF TO PD
RESET caused by
WDT wake-up from
SLEEP
VDD
0
0
0
0
0
1
0
1
0
VDD
WDT time-out (not from
SLEEP)
33k
Q1
MCLR wake-up from
SLEEP
10k
MCLR
40k*
0
0
1
1
u
1
1
u
0
PIC12CE5XX
Power-up
MCLR not during SLEEP
Wake-up from SLEEP on
pin change
This circuit will activate reset when VDD goes below Vz +
0.7V (where Vz = Zener voltage).
Legend: Legend: u = unchanged
Note 1: The TO, PD, and GPWUF bits main-
*Refer to Figure 8-7 and Table 11-7 for internal weak pull-
up on MCLR.
tain their status (u) until a reset
occurs. A low-pulse on the MCLR
input does not change the TO, PD,
and GPWUF status bits.
FIGURE 8-14: BROWN-OUT PROTECTION
CIRCUIT 2
These STATUS bits are only affected by events listed
in Table 8-8.
VDD
TABLE 8-8:
EVENTS AFFECTING TO/PD
STATUS BITS
VDD
R1
Event
GPWUF TO
PD Remarks
Q1
MCLR
0
0
1
0
1
Power-up
R2
u
WDT Time-out
No effect
on PD
40k
PIC12CE5XX
u
u
1
1
0
1
SLEEP instruction
CLRWDT
instruction
1
1
0
Wake-up from
SLEEP on pin
change
This brown-out circuit is less expensive, although
less accurate. Transistor Q1 turns off when VDD
is below a certain level such that:
Legend: u = unchanged
R1
A WDT time-out will occur regardless of the status of the
TO bit. A SLEEP instruction will be executed, regardless of
the status of the PD bit. Table 8-7 reflects the status of TO
and PD after the corresponding event.
= 0.7V
VDD •
R1 + R2
*Refer to Figure 8-7 and Table 11-7 for internal weak
pull-up on MCLR.
Table 8-4 lists the reset conditions for the special
function registers, while Table 8-3 lists the reset
conditions for all the registers.
DS40172A-page 38
Preliminary
1997 Microchip Technology Inc.
PIC12CE5XX
8.9
Power-Down Mode (SLEEP)
8.10
Program Verification/Code Protection
A device may be powered down (SLEEP) and later
powered up (Wake-up from SLEEP).
If the code protection bit has not been programmed,
the on-chip program memory can be read out for
verification purposes.
8.9.1
SLEEP
The first 64 locations can be read regardless of the
code protection bit setting.
The Power-Down mode is entered by executing a
SLEEPinstruction.
Note: The location containing the pre-pro-
grammed internal RC oscillator calibration
value is never code protected.
If enabled, the Watchdog Timer will be cleared but
keeps running, the TO bit (STATUS<4>) is set, the PD
bit (STATUS<3>) is cleared and the oscillator driver is
turned off. The I/O ports maintain the status they had
before the SLEEP instruction was executed (driving
high, driving low, or hi-impedance).
8.11
ID Locations
Four memory locations are designated as ID locations
where the user can store checksum or other code-
identification numbers. These locations are not
accessible during normal execution but are readable
and writable during program/verify.
It should be noted that a RESET generated by a WDT
time-out does not drive the MCLR pin low.
For lowest current consumption while powered down,
the T0CKI input should be at VDD or VSS and the GP3/
MCLR/VPP pin must be at a logic high level if MCLR is
enabled.
Use only the lower 4 bits of the ID locations and
always program the upper 8 bits as '0's.
8.9.2
WAKE-UP FROM SLEEP
The device can wake-up from SLEEP through one of
the following events:
1. An external reset input on GP3/MCLR/VPP pin,
when configured as MCLR.
2. A Watchdog Timer time-out reset (if WDT was
enabled).
3. A change on input pin GP0, GP1, or GP3/
MCLR/VPP when wake-up on change is
enabled.
These events cause a device reset. The TO, PD, and
GPWUF bits can be used to determine the cause of
device reset. The TO bit is cleared if a WDT time-out
occurred (and caused wake-up). The PD bit, which is
set on power-up, is cleared when SLEEP is invoked.
The GPWUF bit indicates a change in state while in
SLEEP at pins GP0, GP1, or GP3 (since the last time
there was a file or bit operation on GP port).
Caution: Right before entering SLEEP, read the
input pins. When in SLEEP, wake up
occurs when the values at the pins change
from the state they were in at the last
reading. If a wake-up on change occurs
and the pins are not read before
reentering SLEEP, a wake up will occur
immediately even if no pins change while
in SLEEP mode.
The WDT is cleared when the device wakes from
sleep, regardless of the wake-up source.
1997 Microchip Technology Inc.
Preliminary
DS40172A-page 39
PIC12CE5XX
8.12
In-Circuit Serial Programming™
FIGURE 8-15: TYPICAL IN-CIRCUIT SERIAL
PROGRAMMING
The PIC12CE5XX microcontrollers program memory
can be serially programmed while in the end applica-
tion circuit. This is simply done with two lines for clock
and data, and three other lines for power, ground, and
the programming voltage. This allows customers to
manufacture boards with unprogrammed devices, and
then program the microcontroller just before shipping
the product. This also allows the most recent firmware
or a custom firmware to be programmed.
CONNECTION
To Normal
Connections
External
Connector
Signals
PIC12CE5XX
+5V
0V
VDD
VSS
The device is placed into a program/verify mode by
holding the GP1 and GP0 pins low while raising the
MCLR (VPP) pin from VIL to VIHH (see programming
specification). GP1 becomes the programming clock
and GP0 becomes the programming data. Both GP1
and GP0 are Schmitt Trigger inputs in this mode.
VPP
MCLR/VPP
GP1
GP0
CLK
Data I/O
VDD
After reset, a 6-bit command is then supplied to the
device. Depending on the command, 14-bits of pro-
gram data are then supplied to or from the device,
depending if the command was a load or a read. For
complete details of serial programming, please refer to
the PIC12CE5XX Programming Specifications in the
In-Circuit Serial Programming Guide.
To Normal
Connections
A typical in-circuit serial programming connection is
shown in Figure 8-15.
DS40172A-page 40
Preliminary
1997 Microchip Technology Inc.
PIC12CE5XX
All instructions are executed within a single instruction
cycle, unless a conditional test is true or the program
counter is changed as a result of an instruction. In this
case, the execution takes two instruction cycles. One
instruction cycle consists of four oscillator periods.
Thus, for an oscillator frequency of 4 MHz, the normal
instruction execution time is 1 µs. If a conditional test
is true or the program counter is changed as a result of
an instruction, the instruction execution time is 2 µs.
9.0
INSTRUCTION SET SUMMARY
Each PIC12CE5XX instruction is a 12-bit word divided
into an OPCODE, which specifies the instruction type,
and one or more operands which further specify the
operation of the instruction. The PIC12CE5XX
instruction set summary in Table 9-2 groups the
instructions into byte-oriented, bit-oriented, and literal
and control operations. Table 9-1 shows the opcode
field descriptions.
Figure 9-1 shows the three general formats that the
instructions can have. All examples in the figure use the
following format to represent a hexadecimal number:
For byte-oriented instructions, 'f' represents a file
register designator and 'd' represents a destination
designator. The file register designator is used to
specify which one of the 32 file registers is to be used
by the instruction.
0xhhh
where 'h' signifies a hexadecimal digit.
The destination designator specifies where the result
of the operation is to be placed. If 'd' is '0', the result is
placed in the W register. If 'd' is '1', the result is placed
in the file register specified in the instruction.
FIGURE 9-1: GENERAL FORMAT FOR
INSTRUCTIONS
Byte-oriented file register operations
11
6
5
4
0
For bit-oriented instructions, 'b' represents a bit field
designator which selects the number of the bit affected
by the operation, while 'f' represents the number of the
file in which the bit is located.
OPCODE
d
f (FILE #)
d = 0 for destination W
d = 1 for destination f
f = 5-bit file register address
Bit-oriented file register operations
11 8 7
b (BIT #)
For literal and control operations, 'k' represents an
8 or 9-bit constant or literal value.
5
4
0
TABLE 9-1:
OPCODE FIELD
DESCRIPTIONS
OPCODE
f (FILE #)
b = 3-bit bit address
f = 5-bit file register address
Field
Description
f
W
b
k
Register file address (0x00 to 0x7F)
Working register (accumulator)
Literal and control operations (except GOTO)
11
8
7
0
Bit address within an 8-bit file register
Literal field, constant data or label
OPCODE
k (literal)
k = 8-bit immediate value
Literal and control operations - GOTOinstruction
11 0
Don't care location (= 0 or 1)
The assembler will generate code with x = 0. It is
the recommended form of use for compatibility
with all Microchip software tools.
x
d
9
8
OPCODE
k (literal)
Destination select;
d = 0 (store result in W)
d = 1 (store result in file register 'f')
Default is d = 1
k = 9-bit immediate value
label Label name
TOS
PC
Top of Stack
Program Counter
Watchdog Timer Counter
Time-Out bit
WDT
TO
PD
Power-Down bit
Destination, either the W register or the specified
register file location
dest
[ ]
( )
→
Options
Contents
Assigned to
< >
Register bit field
In the set of
italics
User defined term (font is courier)
1997 Microchip Technology Inc.
Preliminary
DS40172A-page 41
PIC12CE5XX
TABLE 9-2:
INSTRUCTION SET SUMMARY
12-Bit Opcode
Mnemonic,
Operands
Status
Description
Cycles MSb
LSb Affected Notes
1
1
1
1
1
1
0001 11df ffff
C,DC,Z 1,2,4
Add W and f
AND W with f
Clear f
Clear W
Complement f
Decrement f
Decrement f, Skip if 0
Increment f
Increment f, Skip if 0
Inclusive OR W with f
Move f
Move W to f
No Operation
Rotate left f through Carry
Rotate right f through Carry
Subtract W from f
Swap f
ADDWF
ANDWF
CLRF
CLRW
COMF
DECF
DECFSZ
INCF
INCFSZ
IORWF
MOVF
MOVWF
NOP
f,d
f,d
f
0001 01df ffff
0000 011f ffff
0000 0100 0000
0010 01df ffff
0000 11df ffff
Z
Z
Z
2,4
4
–
Z
f, d
f, d
f, d
f, d
f, d
f, d
f, d
f
Z
None
Z
None
Z
Z
None
None
C
2,4
2,4
2,4
2,4
2,4
2,4
1,4
1(2) 0010 11df ffff
0010 10df ffff
1(2) 0011 11df ffff
1
1
1
1
1
1
1
1
1
1
0001 00df ffff
0010 00df ffff
0000 001f ffff
0000 0000 0000
0011 01df ffff
0011 00df ffff
0000 10df ffff
0011 10df ffff
0001 10df ffff
–
2,4
2,4
RLF
RRF
SUBWF
SWAPF
XORWF
f, d
f, d
f, d
f, d
f, d
C
C,DC,Z 1,2,4
None
Z
2,4
2,4
Exclusive OR W with f
BIT-ORIENTED FILE REGISTER OPERATIONS
1
1
0100 bbbf ffff
0101 bbbf ffff
None
None
None
None
2,4
2,4
Bit Clear f
Bit Set f
Bit Test f, Skip if Clear
Bit Test f, Skip if Set
BCF
BSF
BTFSC
BTFSS
f, b
f, b
f, b
f, b
1 (2) 0110 bbbf ffff
1 (2) 0111 bbbf ffff
LITERAL AND CONTROL OPERATIONS
1
2
1
2
1
1
1
2
1
1
1
1110 kkkk kkkk
1001 kkkk kkkk
0000 0000 0100
101k kkkk kkkk
1101 kkkk kkkk
1100 kkkk kkkk
0000 0000 0010
1000 kkkk kkkk
0000 0000 0011
0000 0000 0fff
1111 kkkk kkkk
Z
None
AND literal with W
Call subroutine
ANDLW
CALL
CLRWDT
GOTO
IORLW
MOVLW
OPTION
RETLW
SLEEP
TRIS
k
k
k
k
k
k
–
k
–
f
1
3
T
Clear Watchdog Timer
Unconditional branch
Inclusive OR Literal with W
Move Literal to W
Load OPTION register
Return, place Literal in W
Go into standby mode
Load TRIS register
O, PD
None
Z
None
None
None
TO, PD
None
Z
Exclusive OR Literal to W
XORLW
k
Note 1: The 9th bit of the program counter will be forced to a '0' by any instruction that writes to the PC except for GOTO.
(Section 4-5)
2: When an I/O register is modified as a function of itself (e.g. MOVF GPIO, 1), the value used will be that value
present on the pins themselves. For example, if the data latch is '1' for a pin configured as input and is driven
low by an external device, the data will be written back with a '0'.
3: The instruction TRIS f, where f = 6 causes the contents of the W register to be written to the tristate latches of
GPIO. A '1' forces the pin to a hi-impedance state and disables the output buffers.
4: If this instruction is executed on the TMR0 register (and, where applicable, d = 1), the prescaler will be cleared
(if assigned to TMR0).
DS40172A-page 42
Preliminary
1997 Microchip Technology Inc.
PIC12CE5XX
ADDWF
Syntax:
Add W and f
[ label ] ADDWF f,d
0 ≤ f ≤ 31
ANDWF
Syntax:
AND W with f
[ label ] ANDWF f,d
0 ≤ f ≤ 31
Operands:
Operands:
d
[0,1]
d
[0,1]
Operation:
(W) + (f) → (dest)
Operation:
(W) .AND. (f) → (dest)
Status Affected: C, DC, Z
Status Affected:
Encoding:
Z
0001
11df
ffff
0001
01df
ffff
Encoding:
Add the contents of the W register and
register 'f'. If 'd' is 0 the result is stored
in the W register. If 'd' is '1' the result is
stored back in register 'f'.
The contents of the W register are
AND’ed with register 'f'. If 'd' is 0 the
result is stored in the W register. If 'd' is
'1' the result is stored back in register 'f'.
Description:
Description:
Words:
1
Words:
1
1
Cycles:
Example:
1
Cycles:
Example:
ADDWF FSR, 0
ANDWF FSR,
1
Before Instruction
Before Instruction
0x17
W
=
0x17
W
=
FSR = 0xC2
FSR = 0xC2
After Instruction
After Instruction
W
=
0xD9
W
=
0x17
FSR = 0xC2
FSR = 0x02
ANDLW
And literal with W
BCF
Bit Clear f
Syntax:
[ label ] ANDLW
k
Syntax:
Operands:
[ label ] BCF f,b
Operands:
Operation:
Status Affected:
Encoding:
Description:
0 ≤ k ≤ 255
0 ≤ f ≤ 31
0 ≤ b ≤ 7
(W).AND. (k) → (W)
Operation:
0 → (f<b>)
Z
Status Affected: None
1110
kkkk
kkkk
0100
bbbf
ffff
Encoding:
Description:
Words:
The contents of the W register are
AND’ed with the eight-bit literal 'k'. The
result is placed in the W register.
Bit 'b' in register 'f' is cleared.
1
1
Words:
1
Cycles:
Cycles:
Example:
1
BCF
FLAG_REG,
7
Example:
ANDLW 0x5F
Before Instruction
FLAG_REG = 0xC7
Before Instruction
0xA3
W
=
After Instruction
FLAG_REG = 0x47
After Instruction
0x03
W
=
1997 Microchip Technology Inc.
Preliminary
DS40172A-page 43
PIC12CE5XX
BSF
Bit Set f
BTFSS
Bit Test f, Skip if Set
Syntax:
Operands:
[ label ] BSF f,b
Syntax:
[ label ] BTFSS f,b
0 ≤ f ≤ 31
0 ≤ b ≤ 7
Operands:
0 ≤ f ≤ 31
0 ≤ b < 7
Operation:
1 → (f<b>)
Operation:
skip if (f<b>) = 1
Status Affected: None
Status Affected: None
0101
bbbf
ffff
0111
bbbf
ffff
Encoding:
Description:
Words:
Encoding:
Bit 'b' in register 'f' is set.
If bit 'b' in register 'f' is '1' then the next
instruction is skipped.
Description:
1
1
If bit 'b' is '1', then the next instruction
fetched during the current instruction
execution, is discarded and an NOP is
executed instead, making this a 2 cycle
instruction.
Cycles:
BSF
FLAG_REG,
7
Example:
Before Instruction
FLAG_REG = 0x0A
Words:
1
After Instruction
FLAG_REG = 0x8A
Cycles:
Example:
1(2)
HERE
FALSE GOTO
TRUE
BTFSS FLAG,1
PROCESS_CODE
•
BTFSC
Bit Test f, Skip if Clear
•
•
Syntax:
[ label ] BTFSC f,b
Operands:
0 ≤ f ≤ 31
0 ≤ b ≤ 7
Before Instruction
PC
=
address (HERE)
After Instruction
If FLAG<1>
PC
Operation:
skip if (f<b>) = 0
=
=
=
=
0,
Status Affected: None
address (FALSE);
1,
address (TRUE)
bbbf
ffff
if FLAG<1>
PC
Encoding:
0110
If bit 'b' in register 'f' is 0 then the next
instruction is skipped.
Description:
If bit 'b' is 0 then the next instruction
fetched during the current instruction
execution is discarded, and an NOP is
executed instead, making this a 2 cycle
instruction.
Words:
1
Cycles:
Example:
1(2)
HERE
FALSE GOTO
TRUE
BTFSC
FLAG,1
PROCESS_CODE
•
•
•
Before Instruction
PC
=
address (HERE)
After Instruction
if FLAG<1>
PC
=
=
=
=
0,
address (TRUE);
1,
address(FALSE)
if FLAG<1>
PC
DS40172A-page 44
Preliminary
1997 Microchip Technology Inc.
PIC12CE5XX
CALL
Subroutine Call
[ label ] CALL
0 ≤ k ≤ 255
CLRW
Clear W
Syntax:
k
Syntax:
[ label ] CLRW
None
Operands:
Operation:
Operands:
Operation:
(PC) + 1→ Top of Stack;
k → PC<7:0>;
00h → (W);
1 → Z
(STATUS<6:5>) → PC<10:9>;
0 → PC<8>
Status Affected:
Encoding:
Z
0000
0100
0000
Status Affected: None
The W register is cleared. Zero bit (Z)
is set.
Description:
1001
kkkk
kkkk
Encoding:
Subroutine call. First, return address
(PC+1) is pushed onto the stack. The
eight bit immediate address is loaded
into PC bits <7:0>. The upper bits
PC<10:9> are loaded from STA-
TUS<6:5>, PC<8> is cleared.CALLis a
two cycle instruction.
Description:
Words:
1
Cycles:
Example:
1
CLRW
Before Instruction
0x5A
W
=
After Instruction
Words:
1
2
W
=
0x00
Cycles:
Example:
Z
=
1
HERE
CALL
THERE
Before Instruction
PC address (HERE)
CLRWDT
Clear Watchdog Timer
[ label ] CLRWDT
None
=
Syntax:
After Instruction
PC address (THERE)
TOS =
=
Operands:
Operation:
address (HERE + 1)
00h → WDT;
0 → WDT prescaler (if assigned);
1 → TO;
1 → PD
CLRF
Clear f
Syntax:
[ label ] CLRF
f
Status Affected: TO, PD
Operands:
Operation:
0 ≤ f ≤ 31
0000
0000
0100
Encoding:
00h → (f);
1 → Z
The CLRWDTinstruction resets the
WDT. It also resets the prescaler, if the
prescaler is assigned to the WDT and
not Timer0. Status bits TO and PD are
set.
Description:
Status Affected:
Encoding:
Z
0000
011f
ffff
The contents of register 'f' are cleared
and the Z bit is set.
Description:
Words:
1
Cycles:
Example:
1
Words:
1
1
CLRWDT
Cycles:
Example:
Before Instruction
CLRF
FLAG_REG
WDT counter
=
=
?
Before Instruction
FLAG_REG
After Instruction
WDT counter
=
0x5A
0x00
After Instruction
WDT prescale =
0
1
1
FLAG_REG
Z
=
=
0x00
1
TO
PD
=
=
1997 Microchip Technology Inc.
Preliminary
DS40172A-page 45
PIC12CE5XX
COMF
Complement f
[ label ] COMF f,d
0 ≤ f ≤ 31
DECFSZ
Syntax:
Decrement f, Skip if 0
[ label ] DECFSZ f,d
0 ≤ f ≤ 31
Syntax:
Operands:
Operands:
d
[0,1]
d
[0,1]
Operation:
(f) → (dest)
Operation:
(f) – 1 → d; skip if result = 0
Status Affected:
Encoding:
Z
Status Affected: None
0010
01df
ffff
0010
11df
ffff
Encoding:
The contents of register 'f' are comple-
mented. If 'd' is 0 the result is stored in
the W register. If 'd' is 1 the result is
stored back in register 'f'.
The contents of register 'f' are decre-
mented. If 'd' is 0 the result is placed in
the W register. If 'd' is 1 the result is
placed back in register 'f'.
Description:
Description:
If the result is 0, the next instruction,
which is already fetched, is discarded
and an NOP is executed instead mak-
ing it a two cycle instruction.
Words:
1
1
Cycles:
Example:
COMF
REG1,0
Words:
1
Before Instruction
REG1
=
0x13
0x13
Cycles:
Example:
1(2)
After Instruction
HERE
DECFSZ
GOTO
CONTINUE •
CNT, 1
LOOP
REG1
=
W
=
0xEC
•
•
DECF
Decrement f
[ label ] DECF f,d
0 ≤ f ≤ 31
Before Instruction
PC
=
address (HERE)
Syntax:
After Instruction
Operands:
CNT
if CNT
PC
if CNT
PC
=
=
=
≠
=
CNT - 1;
0,
address (CONTINUE);
0,
d
[0,1]
Operation:
(f) – 1 → (dest)
Status Affected:
Encoding:
Z
address (HERE+1)
0000
11df
ffff
Decrement register 'f'. If 'd' is 0 the
result is stored in the W register. If 'd' is
1 the result is stored back in register 'f'.
Description:
GOTO
Unconditional Branch
Syntax:
[ label ] GOTO
0 ≤ k ≤ 511
k
Words:
1
1
Operands:
Cycles:
Example:
Operation:
k → PC<8:0>;
STATUS<6:5> → PC<10:9>
DECF
CNT,
1
Before Instruction
Status Affected: None
CNT
=
0x01
0
101k
kkkk
kkkk
Encoding:
Z
=
GOTOis an unconditional branch. The
9-bit immediate value is loaded into PC
bits <8:0>. The upper bits of PC are
loaded from STATUS<6:5>. GOTOis a
two cycle instruction.
Description:
After Instruction
CNT
=
0x00
1
Z
=
Words:
1
Cycles:
Example:
2
GOTO THERE
After Instruction
PC
=
address (THERE)
DS40172A-page 46
Preliminary
1997 Microchip Technology Inc.
PIC12CE5XX
INCF
Increment f
IORLW
Inclusive OR literal with W
Syntax:
Operands:
[ label ] INCF f,d
0 ≤ f ≤ 31
Syntax:
[ label ] IORLW k
Operands:
Operation:
Status Affected:
Encoding:
Description:
0 ≤ k ≤ 255
d
[0,1]
(W) .OR. (k) → (W)
Operation:
(f) + 1 → (dest)
Z
Status Affected:
Encoding:
Z
1101
kkkk
kkkk
0010
10df
ffff
The contents of the W register are
OR’ed with the eight bit literal 'k'. The
result is placed in the W register.
The contents of register 'f' are incre-
mented. If 'd' is 0 the result is placed in
the W register. If 'd' is 1 the result is
placed back in register 'f'.
Description:
Words:
1
Cycles:
Example:
1
Words:
1
1
IORLW 0x35
Cycles:
Example:
Before Instruction
0x9A
INCF
CNT,
1
W
=
Before Instruction
After Instruction
CNT
=
0xFF
0
W
=
0xBF
Z
=
Z
=
0
After Instruction
CNT
Z
=
=
0x00
1
IORWF
Inclusive OR W with f
[ label ] IORWF f,d
0 ≤ f ≤ 31
Syntax:
Operands:
INCFSZ
Increment f, Skip if 0
[ label ] INCFSZ f,d
0 ≤ f ≤ 31
d
[0,1]
Syntax:
Operation:
(W).OR. (f) → (dest)
Operands:
Status Affected:
Encoding:
Z
d
[0,1]
0001
00df
ffff
Operation:
(f) + 1 → (dest), skip if result = 0
Inclusive OR the W register with regis-
ter 'f'. If 'd' is 0 the result is placed in
the W register. If 'd' is 1 the result is
placed back in register 'f'.
Description:
Status Affected: None
0011
11df
ffff
Encoding:
The contents of register 'f' are incre-
mented. If 'd' is 0 the result is placed in
the W register. If 'd' is 1 the result is
placed back in register 'f'.
Description:
Words:
1
1
Cycles:
Example:
If the result is 0, then the next instruc-
tion, which is already fetched, is dis-
carded and an NOP is executed
instead making it a two cycle instruc-
tion.
IORWF
RESULT, 0
Before Instruction
RESULT
W
=
0x13
=
0x91
After Instruction
Words:
1
RESULT
=
=
=
0x13
0x93
0
Cycles:
Example:
1(2)
W
Z
HERE
INCFSZ
GOTO
CNT,
LOOP
1
CONTINUE •
•
•
Before Instruction
PC
=
address (HERE)
After Instruction
CNT
if CNT
PC
if CNT
PC
=
=
=
≠
=
CNT + 1;
0,
address (CONTINUE);
0,
address (HERE +1)
1997 Microchip Technology Inc.
Preliminary
DS40172A-page 47
PIC12CE5XX
MOVF
Move f
MOVWF
Syntax:
Move W to f
[ label ] MOVWF
0 ≤ f ≤ 31
Syntax:
Operands:
[ label ] MOVF f,d
0 ≤ f ≤ 31
f
Operands:
Operation:
d
[0,1]
(W) → (f)
Operation:
(f) → (dest)
Status Affected: None
Status Affected:
Encoding:
Z
0000
001f
ffff
Encoding:
0010
00df
ffff
Move data from the W register to regis-
ter 'f'.
Description:
The contents of register 'f' is moved to
destination 'd'. If 'd' is 0, destination is
the W register. If 'd' is 1, the destination
is file register 'f'. 'd' is 1 is useful to test
a file register since status flag Z is
affected.
Description:
Words:
1
Cycles:
Example:
1
MOVWF TEMP_REG
Before Instruction
Words:
1
1
TEMP_REG
W
=
=
0xFF
0x4F
Cycles:
Example:
MOVF
FSR,
0
After Instruction
TEMP_REG
W
=
=
0x4F
0x4F
After Instruction
W
=
value in FSR register
NOP
No Operation
[ label ] NOP
None
MOVLW
Move Literal to W
[ label ] MOVLW
0 ≤ k ≤ 255
Syntax:
Syntax:
k
Operands:
Operation:
Operands:
Operation:
No operation
k → (W)
Status Affected: None
0000
0000
0000
Status Affected: None
Encoding:
Description:
Words:
1100
kkkk
kkkk
Encoding:
No operation.
The eight bit literal 'k' is loaded into the
W register. The don’t cares will assem-
ble as 0s.
Description:
1
Cycles:
1
NOP
Example:
Words:
1
Cycles:
Example:
1
MOVLW 0x5A
After Instruction
W
=
0x5A
DS40172A-page 48
Preliminary
1997 Microchip Technology Inc.
PIC12CE5XX
OPTION
Syntax:
Load OPTION Register
[ label ] OPTION
None
RLF
Rotate Left f through Carry
[ label ] RLF f,d
0 ≤ f ≤ 31
Syntax:
Operands:
Operands:
Operation:
d
[0,1]
(W) → OPTION
Status Affected: None
Operation:
See description below
C
0000
0000
0010
Encoding:
Status Affected:
Encoding:
The content of the W register is loaded
into the OPTION register.
Description:
0011
01df
ffff
The contents of register 'f' are rotated
one bit to the left through the Carry
Flag. If 'd' is 0 the result is placed in the
W register. If 'd' is 1 the result is stored
back in register 'f'.
Description:
Words:
Cycles:
Example
1
1
OPTION
Before Instruction
register 'f'
C
W
=
0x07
0x07
After Instruction
OPTION
Words:
1
=
Cycles:
Example:
1
RLF
REG1,0
RETLW
Return with Literal in W
Before Instruction
Syntax:
[ label ] RETLW
k
REG1
C
=
=
1110 0110
0
Operands:
Operation:
0 ≤ k ≤ 255
After Instruction
k → (W);
TOS → PC
REG1
W
C
=
=
=
1110 0110
1100 1100
1
Status Affected: None
1000
kkkk
kkkk
Encoding:
The W register is loaded with the eight
bit literal 'k'. The program counter is
loaded from the top of the stack (the
return address). This is a two cycle
instruction.
Description:
RRF
Rotate Right f through Carry
[ label ] RRF f,d
0 ≤ f ≤ 31
Syntax:
Operands:
d
[0,1]
Words:
1
2
Operation:
See description below
C
Cycles:
Example:
Status Affected:
Encoding:
CALL TABLE ;W contains
;table offset
;value.
0011
00df
ffff
The contents of register 'f' are rotated
one bit to the right through the Carry
Flag. If 'd' is 0 the result is placed in the
W register. If 'd' is 1 the result is placed
back in register 'f'.
Description:
•
•
;W now has table
;value.
•
TABLE
ADDWF PC
RETLW k1
RETLW k2
;W = offset
;Begin table
;
register 'f'
C
•
•
Words:
1
•
Cycles:
Example:
1
RETLW kn
; End of table
RRF
REG1,0
Before Instruction
W
=
0x07
Before Instruction
REG1
C
=
=
1110 0110
0
After Instruction
value of k8
W
=
After Instruction
REG1
W
C
=
=
=
1110 0110
0111 0011
0
1997 Microchip Technology Inc.
Preliminary
DS40172A-page 49
PIC12CE5XX
SLEEP
Enter SLEEP Mode
SUBWF
Subtract W from f
Syntax:
Syntax:
[label]
[label] SUBWF f,d
SLEEP
Operands:
0 ≤ f ≤ 31
Operands:
Operation:
None
d
[0,1]
00h → WDT;
0 → WDT prescaler;
1 → TO;
Operation:
(f) – (W) → (dest)
Status Affected: C, DC, Z
0 → PD
0000
10df
ffff
Encoding:
Status Affected: TO, PD, GPWUF
Subtract (2’s complement method) the
W register from register 'f'. If 'd' is 0 the
result is stored in the W register. If 'd' is
1 the result is stored back in register 'f'.
Description:
0000
0000
0011
Encoding:
Time-out status bit (TO) is set. The
power down status bit (PD) is cleared.
Description:
Words:
1
1
GPWUF is unaffected.
The WDT and its prescaler are
cleared.
Cycles:
SUBWF
REG1, 1
Example 1:
The processor is put into SLEEP mode
with the oscillator stopped. See sec-
tion on SLEEP for more details.
Before Instruction
REG1
W
C
=
=
=
3
2
?
Words:
1
Cycles:
Example:
1
After Instruction
SLEEP
REG1
=
=
=
1
2
1
W
C
; result is positive
Example 2:
Before Instruction
REG1
W
C
=
=
=
2
2
?
After Instruction
REG1
W
C
=
=
=
0
2
1
; result is zero
Example 3:
Before Instruction
REG1
W
C
=
=
=
1
2
?
After Instruction
REG1
W
C
=
=
=
FF
2
0
; result is negative
DS40172A-page 50
Preliminary
1997 Microchip Technology Inc.
PIC12CE5XX
SWAPF
Syntax:
Swap Nibbles in f
[ label ] SWAPF f,d
0 ≤ f ≤ 31
XORLW
Exclusive OR literal with W
Syntax:
[label] XORLW
0 ≤ k ≤ 255
k
Operands:
Operands:
d
[0,1]
Operation:
(W) .XOR. k → (W)
Z
Operation:
(f<3:0>) → (dest<7:4>);
(f<7:4>) → (dest<3:0>)
Status Affected:
Encoding:
1111
kkkk
kkkk
Status Affected: None
The contents of the W register are
XOR’ed with the eight bit literal 'k'. The
result is placed in the W register.
Description:
0011
10df
ffff
Encoding:
The upper and lower nibbles of register
'f' are exchanged. If 'd' is 0 the result is
placed in W register. If 'd' is 1 the result
is placed in register 'f'.
Description:
Words:
1
Cycles:
Example:
1
Words:
Cycles:
Example
1
1
XORLW 0xAF
Before Instruction
0xB5
W
=
SWAPF
REG1,
0
After Instruction
Before Instruction
REG1
W
=
0x1A
=
0xA5
After Instruction
REG1
W
=
=
0xA5
0X5A
XORWF
Exclusive OR W with f
[ label ] XORWF f,d
0 ≤ f ≤ 31
Syntax:
Operands:
TRIS
Load TRIS Register
d
[0,1]
Syntax:
[ label ] TRIS
f = 6
f
Operation:
(W) .XOR. (f) → (dest)
Operands:
Operation:
Status Affected:
Encoding:
Z
(W) → TRIS register f
0001
10df
ffff
Status Affected: None
Exclusive OR the contents of the W
register with register 'f'. If 'd' is 0 the
result is stored in the W register. If 'd' is
1 the result is stored back in register 'f'.
Description:
0000
0000
0fff
Encoding:
TRIS register 'f' (f = 6) is loaded with the
contents of the W register
Description:
Words:
Cycles:
Example
1
1
Words:
Cycles:
Example
1
1
TRIS
GPIO
REG,1
XORWF
Before Instruction
Before Instruction
W
=
0XA5
REG
=
0xAF
W
=
0xB5
After Instruction
TRIS
=
0XA5
After Instruction
REG
W
=
=
0x1A
0xB5
Note: f = 6 for PIC12C5XX only.
1997 Microchip Technology Inc.
Preliminary
DS40172A-page 51
PIC12CE5XX
NOTES:
DS40172A-page 52
Preliminary
1997 Microchip Technology Inc.
PIC12CE5XX
10.3
ICEPIC: Low-Cost PICmicro™
In-Circuit Emulator
10.0 DEVELOPMENT SUPPORT
10.1
Development Tools
ICEPIC is a low-cost in-circuit emulator solution for the
Microchip PIC12CXXX, PIC16C5X and PIC16CXXX
families of 8-bit OTP microcontrollers.
The PICmicrο microcontrollers are supported with a
full range of hardware and software development tools:
• PICMASTER/PICMASTER CE Real-Time
In-Circuit Emulator
ICEPIC is designed to operate on PC-compatible
machines ranging from 286-AT through Pentium
based machines under Windows 3.x environment.
ICEPIC features real time, non-intrusive emulation.
• ICEPIC Low-Cost PIC16C5X and PIC16CXXX
In-Circuit Emulator
• PRO MATE II Universal Programmer
10.4
PRO MATE II: Universal Programmer
• PICSTART Plus Entry-Level Prototype
Programmer
The PRO MATE II Universal Programmer is a full-fea-
tured programmer capable of operating in stand-alone
mode as well as PC-hosted mode.
• PICDEM-1 Low-Cost Demonstration Board
• PICDEM-2 Low-Cost Demonstration Board
• PICDEM-3 Low-Cost Demonstration Board
• MPASM Assembler
The PRO MATE II has programmable VDD and VPP
supplies which allows it to verify programmed memory
at VDD min and VDD max for maximum reliability. It has
an LCD display for displaying error messages, keys to
enter commands and a modular detachable socket
assembly to support various package types. In stand-
alone mode the PRO MATE II can read, verify or pro-
• MPLAB SIM Software Simulator
• MPLAB-C (C Compiler)
• Fuzzy Logic Development System
(fuzzyTECH −MP)
gram
PIC12CXXX,
PIC14C000,
PIC16C5X,
10.2
PICMASTER: High Performance
Universal In-Circuit Emulator with
MPLAB IDE
PIC16CXXX and PIC17CXX devices. It can also set
configuration and code-protect bits in this mode.
10.5
PICSTART Plus Entry Level
Development System
The PICMASTER Universal In-Circuit Emulator is
intended to provide the product development engineer
with a complete microcontroller design tool set for all
microcontrollers in the PIC12CXXX, PIC14C000,
PIC16C5X, PIC16CXXX and PIC17CXX families.
PICMASTER is supplied with the MPLAB Integrated
Development Environment (IDE), which allows editing,
“make” and download, and source debugging from a
single environment.
The PICSTART programmer is an easy-to-use, low-
cost prototype programmer. It connects to the PC via
one of the COM (RS-232) ports. MPLAB Integrated
Development Environment software makes using the
programmer simple and efficient. PICSTART Plus is
not recommended for production programming.
PICSTART Plus supports all PIC12CXXX, PIC14C000,
PIC16C5X, PIC16CXXX and PIC17CXX devices with
up to 40 pins. Larger pin count devices such as the
PIC16C923 and PIC16C924 may be supported with an
adapter socket.
Interchangeable target probes allow the system to be
easily reconfigured for emulation of different proces-
sors. The universal architecture of the PICMASTER
allows expansion to support all new Microchip micro-
controllers.
The PICMASTER Emulator System has been
designed as
a real-time emulation system with
advanced features that are generally found on more
expensive development tools. The PC compatible 386
(and higher) machine platform and Microsoft Windows
3.x environment were chosen to best make these fea-
tures available to you, the end user.
A CE compliant version of PICMASTER is available for
European Union (EU) countries.
1997 Microchip Technology Inc.
Preliminary
DS40172A - page 53
PIC12CE5XX
an RS-232 interface, push-button switches, a potenti-
ometer for simulated analog input, a thermistor and
separate headers for connection to an external LCD
module and a keypad. Also provided on the PICDEM-3
board is an LCD panel, with 4 commons and 12 seg-
ments, that is capable of displaying time, temperature
and day of the week. The PICDEM-3 provides an addi-
tional RS-232 interface and Windows 3.1 software for
showing the demultiplexed LCD signals on a PC. A sim-
ple serial interface allows the user to construct a hard-
ware demultiplexer for the LCD signals.
10.6
PICDEM-1 Low-Cost PICmicro
Demonstration Board
The PICDEM-1 is a simple board which demonstrates
the capabilities of several of Microchip’s microcontrol-
lers. The microcontrollers supported are: PIC16C5X
(PIC16C54 to PIC16C58A), PIC16C61, PIC16C62X,
PIC16C71, PIC16C8X, PIC17C42, PIC17C43 and
PIC17C44. All necessary hardware and software is
included to run basic demo programs. The users can
program the sample microcontrollers provided with
the PICDEM-1 board, on
a PRO MATE II or
10.9
MPLAB™ Integrated Development
Environment Software
PICSTART-Plus programmer, and easily test firm-
ware. The user can also connect the PICDEM-1
board to the PICMASTER emulator and download
the firmware to the emulator for testing. Additional pro-
totype area is available for the user to build some addi-
tional hardware and connect it to the microcontroller
socket(s). Some of the features include an RS-232
interface, a potentiometer for simulated analog input,
push-button switches and eight LEDs connected to
PORTB.
The MPLAB IDE Software brings an ease of software
development previously unseen in the 8-bit microcon-
troller market. MPLAB is a windows based application
which contains:
• A full featured editor
• Three operating modes
- editor
- emulator
- simulator
• A project manager
• Customizable tool bar and key mapping
• A status bar with project information
• Extensive on-line help
10.7
PICDEM-2 Low-Cost PIC16CXX
Demonstration Board
The PICDEM-2 is a simple demonstration board that
supports the PIC16C62, PIC16C64, PIC16C65,
PIC16C73 and PIC16C74 microcontrollers. All the
necessary hardware and software is included to
run the basic demonstration programs. The user
can program the sample microcontrollers provided
with the PICDEM-2 board, on a PRO MATE II pro-
grammer or PICSTART-Plus, and easily test firmware.
The PICMASTER emulator may also be used with the
PICDEM-2 board to test firmware. Additional prototype
area has been provided to the user for adding addi-
tional hardware and connecting it to the microcontroller
socket(s). Some of the features include a RS-232 inter-
face, push-button switches, a potentiometer for simu-
lated analog input, a Serial EEPROM to demonstrate
MPLAB allows you to:
• Edit your source files (either assembly or ‘C’)
• One touch assemble (or compile) and download
to PICmicro tools (automatically updates all
project information)
• Debug using:
- source files
- absolute listing file
• Transfer data dynamically via DDE (soon to be
replaced by OLE)
• Run up to four emulators on the same PC
The ability to use MPLAB with Microchip’s simulator
allows a consistent platform and the ability to easily
switch from the low cost simulator to the full featured
emulator with minimal retraining due to development
tools.
2
usage of the I C bus and separate headers for connec-
tion to an LCD module and a keypad.
10.8
PICDEM-3 Low-Cost PIC16CXXX
Demonstration Board
10.10 Assembler (MPASM)
The PICDEM-3 is a simple demonstration board that
supports the PIC16C923 and PIC16C924 in the PLCC
package. It will also support future 44-pin PLCC
microcontrollers with a LCD Module. All the neces-
sary hardware and software is included to run the
basic demonstration programs. The user can pro-
gram the sample microcontrollers provided with
the PICDEM-3 board, on a PRO MATE II program-
mer or PICSTART Plus with an adapter socket, and
easily test firmware. The PICMASTER emulator may
also be used with the PICDEM-3 board to test firm-
ware. Additional prototype area has been provided to
the user for adding hardware and connecting it to the
microcontroller socket(s). Some of the features include
The MPASM Universal Macro Assembler is a PC-
hosted symbolic assembler. It supports all microcon-
troller series including the PIC12C5XX, PIC14000,
PIC16C5X, PIC16CXXX, and PIC17CXX families.
MPASM offers full featured Macro capabilities, condi-
tional assembly, and several source and listing formats.
It generates various object code formats to support
Microchip's development tools as well as third party
programmers.
MPASM allows full symbolic debugging from
PICMASTER, Microchip’s Universal Emulator System.
DS40172A - page 54
Preliminary
1997 Microchip Technology Inc.
PIC12CE5XX
MPASM has the following features to assist in develop-
ing software for specific use applications.
10.14 MP-DriveWay – Application Code
Generator
• Provides translation of Assembler source code to
object code for all Microchip microcontrollers.
MP-DriveWay is an easy-to-use Windows-based Appli-
cation Code Generator. With MP-DriveWay you can
visually configure all the peripherals in a PICmicro
device and, with a click of the mouse, generate all the
initialization and many functional code modules in C
language. The output is fully compatible with Micro-
chip’s MPLAB-C C compiler. The code produced is
highly modular and allows easy integration of your own
code. MP-DriveWay is intelligent enough to maintain
your code through subsequent code generation.
• Macro assembly capability.
• Produces all the files (Object, Listing, Symbol,
and special) required for symbolic debug with
Microchip’s emulator systems.
• Supports Hex (default), Decimal and Octal source
and listing formats.
MPASM provides a rich directive language to support
programming of the PICmicro. Directives are helpful in
making the development of your assemble source code
shorter and more maintainable.
10.15 SEEVAL Evaluation and
Programming System
10.11 Software Simulator (MPLAB-SIM)
The SEEVAL SEEPROM Designer’s Kit supports all
Microchip 2-wire and 3-wire Serial EEPROMs. The kit
includes everything necessary to read, write, erase or
program special features of any Microchip SEEPROM
product including Smart Serials and secure serials.
The Total Endurance Disk is included to aid in trade-
off analysis and reliability calculations. The total kit can
significantly reduce time-to-market and result in an
optimized system.
The MPLAB-SIM Software Simulator allows code
development in a PC host environment. It allows the
user to simulate the PICmicro series microcontrollers
on an instruction level. On any given instruction, the
user may examine or modify any of the data areas or
provide external stimulus to any of the pins. The input/
output radix can be set by the user and the execution
can be performed in; single step, execute until break, or
in a trace mode.
10.16 KEELOQ Evaluation and
Programming Tools
MPLAB-SIM fully supports symbolic debugging using
MPLAB-C and MPASM. The Software Simulator offers
the low cost flexibility to develop and debug code out-
side of the laboratory environment making it an excel-
lent multi-project software development tool.
KEELOQ evaluation and programming tools support
Microchips HCS Secure Data Products.The HCS eval-
uation kit includes an LCD display to show changing
codes, a decoder to decode transmissions, and a pro-
gramming interface to program test transmitters.
10.12 C Compiler (MPLAB-C)
The MPLAB-C Code Development System is
a
complete ‘C’ compiler and integrated development
environment for Microchip’s PICmicro™ family of
microcontrollers. The compiler provides powerful inte-
gration capabilities and ease of use not found with
other compilers.
For easier source level debugging, the compiler pro-
vides symbol information that is compatible with the
MPLAB IDE memory display.
10.13 Fuzzy Logic Development System
(fuzzyTECH-MP)
fuzzyTECH-MP fuzzy logic development tool is avail-
able in two versions - a low cost introductory version,
MP Explorer, for designers to gain a comprehensive
working knowledge of fuzzy logic system design; and a
full-featured version, fuzzyTECH-MP, edition for imple-
menting more complex systems.
Both versions include Microchip’s fuzzyLAB demon-
stration board for hands-on experience with fuzzy logic
systems implementation.
1997 Microchip Technology Inc.
Preliminary
DS40172A - page 55
24CXX HCS200
PIC12CXXX PIC14000 PIC16C5X PIC16CXXX PIC16C6X PIC16C7XX PIC16C8X PIC16C9XX PIC17C4X PIC17C75X 25CXX HCS300
93CXX HCS301
PICMASTER
/
PICMASTER-CE
In-Circuit Emulator
✔
✔
✔
✔
✔
✔
✔
✔
✔
✔
✔
✔
✔
✔
✔
✔
ICEPIC Low-Cost
In-Circuit Emulator
MPLAB
Integrated
Development
Environment
✔
✔
✔
✔
✔
✔
✔
✔
✔
✔
✔
✔
✔
✔
✔
✔
✔
✔
✔
✔
MPLAB
C
Compiler
fuzzyTECH -MP
Explorer/Edition
Fuzzy Logic
✔
✔
✔
✔
✔
✔
✔
✔
✔
✔
✔
✔
✔
✔
✔
Dev. Tool
MP-DriveWay
Applications
Code Generator
Total Endurance
Software Model
✔
PICSTART
Lite Ultra Low-Cost
Dev. Kit
✔
✔
✔
✔
✔
✔
✔
✔
✔
✔
✔
✔
PICSTART
Plus Low-Cost
Universal Dev. Kit
✔
✔
✔
✔
✔
✔
✔
✔
✔
✔
✔
✔
PRO MATE II
Universal
Programmer
✔
✔
✔
✔
KEELOQ
Programmer
SEEVAL
Designers Kit
PICDEM-1
PICDEM-2
PICDEM-3
✔
✔
✔
✔
✔
✔
✔
KEELOQ
Evaluation Kit
✔
PIC12CE5XX
11.0 ELECTRICAL CHARACTERISTICS - PIC12CE5XX
Absolute Maximum Ratings†
Ambient Temperature under bias ........................................................................................................... –40˚C to +125˚C
Storage Temperature.............................................................................................................................. –65˚C to +150˚C
Voltage on VDD with respect to VSS .................................................................................................................0 to +7.0 V
Voltage on MCLR with respect to VSS...............................................................................................................0 to +14 V
Voltage on all other pins with respect to VSS ................................................................................–0.6 V to (VDD + 0.6 V)
(1)
Total Power Dissipation ....................................................................................................................................700 mW
Max. Current out of VSS pin...................................................................................................................................200 mA
Max. Current into VDD pin......................................................................................................................................150 mA
Input Clamp Current, IIK (VI < 0 or VI > VDD) ....................................................................................................................±20 mA
Output Clamp Current, IOK (VO < 0 or VO > VDD) ............................................................................................................±20 mA
Max. Output Current sunk by any I/O pin................................................................................................................25 mA
Max. Output Current sourced by any I/O pin...........................................................................................................25 mA
Max. Output Current sourced by I/O port (GPIO)..................................................................................................100 mA
Max. Output Current sunk by I/O port (GPIO )......................................................................................................100 mA
Note 1: Power Dissipation is calculated as follows: PDIS = VDD x {IDD - ∑ IOH} + ∑ {(VDD-VOH) x IOH} + ∑(VOL x IOL)
†
NOTICE: Stresses above those listed under "Maximum Ratings" may cause permanent damage to the device.
This is a stress rating only and functional operation of the device at those or any other conditions above those
indicated in the operation listings of this specification is not implied. Exposure to maximum rating conditions for
extended periods may affect device reliability.
1997 Microchip Technology Inc.
Preliminary
DS40172A-page 57
PIC12CE5XX
11.1
DC CHARACTERISTICS:
PIC12CE518/519 (Commercial)
PIC12CE518/519 (Industrial)
PIC12CE518/519 (Extended)
Standard Operating Conditions (unless otherwise specified)
DC Characteristics
Power Supply Pins
Operating Temperature
0°C ≤ TA ≤ +70°C (commercial)
–40°C ≤ TA ≤ +85°C (industrial)
–40°C ≤ TA ≤ +125°C (extended)
(1)
Characteristic
Sym
Min
Max
Units
Conditions
Typ
Supply Voltage
VDD
3.0
5.5
V
FOSC = DC to 4 MHz (Commercial/
Industrial)
4.5
5.5
V
V
FOSC = DC to 4 MHz (Extended)
RAM Data Retention
VDR
1.5*
Device in SLEEP mode
(2)
Voltage
VDD Start Voltage to ensure VPOR
VSS
V
See section on Power-on Reset for details
Power-on Reset
VDD Rise Rate to ensure
Power-on Reset
SVDD 0.05*
V/ms See section on Power-on Reset for details
(3)
IDD
—
—
—
—
—
1.8
1.8
15
19
19
2.4
2.4
27
35
35
mA
mA
µA
µA
µA
XT and EXTRC options (Note 4)
FOSC = 4 MHz, VDD = 5.5V
INTRC Option
Supply Current
No read/write to EEPROM
peripheral
FOSC = 4 MHz, VDD = 5.5V
LP OPTION, Commercial Temperature
FOSC = 32 kHz, VDD = 3.0V, WDT disabled
LP OPTION, Industrial Temperature
FOSC = 32 kHz, VDD = 3.0V, WDT disabled
LP OPTION, Extended Temperature
FOSC = 32 kHz, VDD = 4.5V, WDT disabled
(3)
IDD
—
—
1.9
1.9
2.6
2.6
mA
mA
XT and EXTRC options (Note 4)
FOSC = 4 MHz, VDD = 5.5V,
SCL = 400 kHz
Supply Current
During read/write to
EEPROM peripheral
INTRC Option
FOSC = 4 MHz, VDD = 5.5V
SCL = 400 kHz
* These parameters are characterized but not tested.
Note 1: Data in the Typical (“Typ”) column is based on characterization results at 25°C. This data is for design guid-
ance only and is not tested.
2: This is the limit to which VDD can be lowered in SLEEP mode without losing RAM data.
3: The supply current is mainly a function of the operating voltage and frequency. Other factors such as bus
loading, oscillator type, bus rate, internal code execution pattern, and temperature also have an impact on
the current consumption.
a) The test conditions for all IDD measurements in active operation mode are:
OSC1 = external square wave, from rail-to-rail; all I/O pins tristated, pulled to
Vss, T0CKI = VDD, MCLR = VDD; WDT enabled/disabled as specified.
b) For standby current measurements, the conditions are the same, except that
the device is in SLEEP mode.
c) EEPROM data memory in standby unless otherwise indicated.
4: Does not include current through Rext. The current through the resistor can be estimated by the
formula: IR = VDD/2Rext (mA) with Rext in kOhm.
5: The power down current in SLEEP mode does not depend on the oscillator type. Power down current is mea-
sured with the part in SLEEP mode, with all I/O pins in hi-impedance state and tied to VDD or VSS. EEPROM
data memory in standby.
DS40172A-page 58
Preliminary
1997 Microchip Technology Inc.
PIC12CE5XX
Standard Operating Conditions (unless otherwise specified)
DC Characteristics
Power Supply Pins
Operating Temperature
0°C ≤ TA ≤ +70°C (commercial)
–40°C ≤ TA ≤ +85°C (industrial)
–40°C ≤ TA ≤ +125°C (extended)
(1)
Characteristic
(5)
Sym
Min
Max
Units
Conditions
Typ
IPD
Power-Down Current
—
—
—
—
—
—
4
4
5
13
14
23
5
6
13
µA
µA
µA
µA
µA
µA
VDD = 3.0V, Commercial
WDT Enabled
VDD = 3.0V, Industrial
VDD = 4.5V, Extended
VDD = 3.0V, Commercial
VDD = 3.0V, Industrial
VDD = 4.5V, Extended
0.26
0.26
2
WDT Disabled
* These parameters are characterized but not tested.
Note 1: Data in the Typical (“Typ”) column is based on characterization results at 25°C. This data is for design guid-
ance only and is not tested.
2: This is the limit to which VDD can be lowered in SLEEP mode without losing RAM data.
3: The supply current is mainly a function of the operating voltage and frequency. Other factors such as bus
loading, oscillator type, bus rate, internal code execution pattern, and temperature also have an impact on
the current consumption.
a) The test conditions for all IDD measurements in active operation mode are:
OSC1 = external square wave, from rail-to-rail; all I/O pins tristated, pulled to
Vss, T0CKI = VDD, MCLR = VDD; WDT enabled/disabled as specified.
b) For standby current measurements, the conditions are the same, except that
the device is in SLEEP mode.
c) EEPROM data memory in standby unless otherwise indicated.
4: Does not include current through Rext. The current through the resistor can be estimated by the
formula: IR = VDD/2Rext (mA) with Rext in kOhm.
5: The power down current in SLEEP mode does not depend on the oscillator type. Power down current is mea-
sured with the part in SLEEP mode, with all I/O pins in hi-impedance state and tied to VDD or VSS. EEPROM
data memory in standby.
1997 Microchip Technology Inc.
Preliminary
DS40172A-page 59
PIC12CE5XX
11.2
DC CHARACTERISTICS:
PIC12CE518/519 (Commercial)
PIC12CE518/519 (Industrial)
PIC12CE518/519 (Extended)
Standard Operating Conditions (unless otherwise specified)
DC Characteristics
All Pins Except
Power Supply Pins
Operating Temperature
0°C ≤ TA ≤ +70°C (commercial)
–40°C ≤ TA ≤ +85°C (industrial)
–40°C ≤ TA ≤ +125°C (extended)
Operating Voltage VDD range is described in Section 11.1.
(1)
Characteristic
Sym
Min
Typ
Max
Units
Conditions
Input Low Voltage
I/O ports
VIL
VIH
IIL
VSS
VSS
0.8
V
V
Pin at hi-impedance
4.5V < VDD ≤ 5.5V
Pin at hi-impedance
3.0V < VDD ≤ 4.5V
0.15 VDD
MCLR and GP2 (Schmitt Trigger)
OSC1
OSC1
VSS
VSS
VSS
0.15 VDD
0.15 VDD
0.3 VDD
V
V
V
(4)
EXTRC option only
XT and LP options
Input High Voltage
I/O ports
0.25VDD+0.8V
2.0
0.2VDD+1V
0.85 VDD
0.85 VDD
0.7 VDD
VDD
VDD
VDD
VDD
VDD
VDD
V
V
V
V
V
V
3.0V < VDD ≤ 4.5V
(5)
4.5V < VDD ≤ 5.5V
(5)
Full VDD range
MCLR and GP2 (Schmitt Trigger)
OSC1 (Schmitt Trigger)
(4)
EXTRC option only
XT and LP options
IPUR
(2,3)
Input Leakage Current
For VDD ≤ 5.5V
I/O ports
–1
20
–3
0.5
+1
µA
VSS ≤ VPIN ≤ VDD,
Pin at hi-impedance
VPIN = VSS + 0.25V
VPIN = VDD
VSS ≤ VPIN ≤ VDD,
XT and LP options
(2)
MCLR
130
0.5
0.5
250
+5
+3
µA
µA
µA
OSC1
Output Low Voltage
Vol
I/O ports
0.6
V
V
IOL = 8.7 mA, VDD = 4.5V
IOH = –5.4 mA, VDD = 4.5V
(3,4)
Output High Voltage
I/O ports
VoH
VDD –0.7
* These parameters are characterized but not tested.
Note 1: Data in the Typical (“Typ”) column is based on characterization results at 25°C. This data is for design guid-
ance only and is not tested.
2: The leakage current on the MCLR/VPP pin is strongly dependent on the applied voltage level. The specified
levels represent normal operating conditions. Higher leakage current may be measured at different input
voltage.
3: Negative current is defined as coming out of the pin.
4: For PIC12CE5XX devices, the OSC1/CLKIN pin is a Schmitt Trigger input. It is not recommended that the
PIC12CE5XX be driven with external clock in RC mode.
5: The user may use the better of the two specifications.
DS40172A-page 60
Preliminary
1997 Microchip Technology Inc.
PIC12CE5XX
11.3
Timing Parameter Symbology and Load Conditions
The timing parameter symbols have been created following one of the following formats:
1. TppS2ppS
2. TppS
T
F
Frequency
Lowercase subscripts (pp) and their meanings:
pp
T
Time
2
to
mc
osc
os
MCLR
ck
cy
drt
io
CLKOUT
cycle time
device reset timer
I/O port
oscillator
OSC1
t0
T0CKI
wdt
watchdog timer
Uppercase letters and their meanings:
S
F
H
I
Fall
P
R
V
Z
Period
High
Rise
Invalid (Hi-impedance)
Low
Valid
L
Hi-impedance
FIGURE 11-1: LOAD CONDITIONS - PIC12CE5XX
Pin
CL = 50 pF for all pins except OSC2
CL
15 pF for OSC2 in XT or LP modes
when external clock is used
to drive OSC1
VSS
1997 Microchip Technology Inc.
Preliminary
DS40172A-page 61
PIC12CE5XX
11.4
Timing Diagrams and Specifications
FIGURE 11-2: EXTERNAL CLOCK TIMING - PIC12CE5XX
Q4
Q3
Q4
4
Q1
Q1
Q2
OSC1
1
3
3
4
2
TABLE 11-1: EXTERNAL CLOCK TIMING REQUIREMENTS - PIC12CE5XX
AC Characteristics
Standard Operating Conditions (unless otherwise specified)
Operating Temperature
0°C ≤ TA ≤ +70°C (commercial),
–40°C ≤ TA ≤ +85°C (industrial),
–40°C ≤ TA ≤ +125°C (extended)
Operating Voltage VDD range is described in Section 11.1
Parameter
Sym
(1)
Characteristic
Min
Max Units
Conditions
Typ
No.
(2)
FOSC
DC
DC
DC
0.1
DC
250
5
—
—
4
200
4
MHz XT osc mode
kHz LP osc mode
MHz EXTRC osc mode
MHz XT osc mode
kHz LP osc mode
ns XT osc mode
ms LP osc mode
ns EXTRC osc mode
ns XT osc mode
ms LP osc mode
—
External CLKIN Frequency
(2)
—
Oscillator Frequency
—
4
—
200
—
(2)
1
Tosc
Tcy
—
External CLKIN Period
—
—
(2)
250
250
5
—
—
Oscillator Period
—
10,000
—
—
(3)
2
3
—
4/FOSC
—
Instruction Cycle Time
TosL, TosH Clock in (OSC1) Low or High Time
50*
2*
—
—
—
—
—
—
ns XT oscillator
ms LP oscillator
ns XT oscillator
ns LP oscillator
4
TosR, TosF Clock in (OSC1) Rise or Fall Time
—
25*
50*
—
*
These parameters are characterized but not tested.
Note 1: Data in the Typical (“Typ”) column is at 5V, 25°C unless otherwise stated. These parameters are for design
guidance only and are not tested.
2: All specified values are based on characterization data for that particular oscillator type under standard oper-
ating conditions with the device executing code. Exceeding these specified limits may result in an unstable
oscillator operation and/or higher than expected current consumption.
When an external clock input is used, the “max” cycle time limit is “DC” (no clock) for all devices.
3: Instruction cycle period (TCY) equals four times the input oscillator time base period.
DS40172A-page 62
Preliminary
1997 Microchip Technology Inc.
PIC12CE5XX
FIGURE 11-3: I/O TIMING - PIC12CE5XX
Q1
Q2
Q3
Q4
OSC1
I/O Pin
(input)
17
18
19
I/O Pin
Old Value
(output)
New Value
20, 21
Note: All tests must be done with specified capacitive loads (see data sheet) 50 pF on I/O pins and CLKOUT.
TABLE 11-2: TIMING REQUIREMENTS - PIC12CE5XX
AC Characteristics
Standard Operating Conditions (unless otherwise specified)
Operating Temperature
0°C ≤ TA ≤ +70°C (commercial)
–40°C ≤ TA ≤ +85°C (industrial)
–40°C ≤ TA ≤ +125°C (extended)
Operating Voltage VDD range is described in Section 11.1
Parameter
(1)
No.
Sym
TosH2ioV
TosH2ioI
Characteristic
Min
—
Typ
Max
100*
—
Units
ns
(3)
—
—
17
OSC1↑ (Q1 cycle) to Port out valid
OSC1↑ (Q2 cycle) to Port input invalid
TBD
ns
18
(I/O in hold time)
TioV2osH
Port input valid to OSC1↑
TBD
—
—
ns
19
(I/O in setup time)
(3)
TioR
TioF
—
—
10
10
25**
25**
ns
ns
20
21
Port output rise time
(3)
Port output fall time
*
These parameters are characterized but not tested.
** These parameters are design targets and are not tested. No characterization data available at this time.
Note 1: Data in the Typical (“Typ”) column is at 5V, 25˚C unless otherwise stated. These parameters are for design
guidance only and are not tested.
2: Measurements are taken in EXTRC mode.
3: See Figure 11-1 for loading conditions.
1997 Microchip Technology Inc.
Preliminary
DS40172A-page 63
PIC12CE5XX
FIGURE 11-4: RESET, WATCHDOG TIMER, AND DEVICE RESET TIMER TIMING - PIC12CE5XX
VDD
MCLR
30
Internal
POR
32
32
32
DRT
Timeout
(Note 2)
Internal
RESET
Watchdog
Timer
RESET
31
34
34
I/O pin
(Note 1)
Note 1: I/O pins must be taken out of hi-impedance mode by enabling the output drivers in software.
2: Runs in MCLR or WDT reset only in XT and LP modes.
TABLE 11-3: RESET, WATCHDOG TIMER, AND DEVICE RESET TIMER - PIC12CE5XX
AC Characteristics Standard Operating Conditions (unless otherwise specified)
Operating Temperature
0°C ≤ TA ≤ +70°C (commercial)
–40°C ≤ TA ≤ +85°C (industrial)
–40°C ≤ TA ≤ +125°C (extended)
Operating Voltage VDD range is described in Section 11.1
Parameter
No.
(1)
Sym Characteristic
Min Typ
Max Units
Conditions
30
31
TmcL MCLR Pulse Width (low)
2000*
9*
—
—
ns VDD = 5 V
Twdt Watchdog Timer Time-out Period
(No Prescaler)
18*
30*
ms VDD = 5 V (Commercial)
(2)
32
34
TDRT Device Reset Timer Period
9*
—
18*
—
30*
ms VDD = 5 V (Commercial)
ns
TioZ I/O Hi-impedance from MCLR Low
2000*
*
These parameters are characterized but not tested.
Note 1: Data in the Typical (“Typ”) column is at 5V, 25°C unless otherwise stated. These parameters are for design
guidance only and are not tested.
TABLE 11-4: DRT (DEVICE RESET TIMER PERIOD) TIME OUT
Oscillator Configuration
POR Reset
Subsequent Resets
IntRC & ExtRC
XT & LP
18 ms (typical)
18 ms (typical)
300 µs (typical)
18 ms (typical)
DS40172A-page 64
Preliminary
1997 Microchip Technology Inc.
PIC12CE5XX
FIGURE 11-5: TIMER0 CLOCK TIMINGS - PIC12CE5XX
T0CKI
40
41
42
TABLE 11-5: TIMER0 CLOCK REQUIREMENTS - PIC12CE5XX
AC Characteristics Standard Operating Conditions (unless otherwise specified)
Operating Temperature 0°C ≤ TA ≤ +70°C (commercial)
–40°C ≤ TA ≤ +85°C (industrial)
–40°C ≤ TA ≤ +125°C (extended)
Operating Voltage VDD range is described in Section 11.1.
Parameter
(1)
Sym Characteristic
Min
Typ
Max Units Conditions
No.
40
Tt0H T0CKI High Pulse Width - No Prescaler
- With Prescaler
0.5 TCY + 20*
10*
—
—
—
—
—
—
—
—
—
—
ns
ns
ns
ns
41
42
Tt0L T0CKI Low Pulse Width - No Prescaler
- With Prescaler
0.5 TCY + 20*
10*
Tt0P T0CKI Period
20 or TCY + 40*
N
ns Whichever is greater.
N = Prescale Value
(1, 2, 4,..., 256)
*
These parameters are characterized but not tested.
Note 1: Data in the Typical (“Typ”) column is at 5V, 25˚C unless otherwise stated. These parameters are for design guidance only
and are not tested.
FIGURE 11-6: EEPROM MEMORY BUS TIMING DATA
THIGH
TF
TR
TSU:STA
SCL
TSU:STO
THD:DAT
TSU:DAT
TLOW
THD:STA
SDA
IN
TSP
TBUF
TAA
SDA
OUT
1997 Microchip Technology Inc.
Preliminary
DS40172A-page 65
PIC12CE5XX
TABLE 11-6: EEPROM MEMORY BUS TIMING REQUIREMENTS
AC Characteristics
Standard Operating Conditions (unless otherwise specified)
Operating Temperature 0°C ≤ TA ≤ +70°C, Vcc = 3.0V to 5.5V (commercial)
–40°C ≤ TA ≤ +85°C, Vcc = 3.0V to 5.5V (industrial)
–40°C ≤ TA ≤ +125°C, Vcc = 4.5V to 5.5V (extended)
Operating Voltage VDD range is described in Section 11.1
Parameter
Symbol
Min
Max
Units
Conditions
Clock frequency
FCLK
—
—
—
100
100
400
kHz
4.5V ≤ Vcc ≤ 5.5V (E Temp range)
3.0V ≤ Vcc ≤ 4.5V
4.5V ≤ Vcc ≤ 5.5V
Clock high time
Clock low time
THIGH
TLOW
TR
4000
4000
600
—
—
—
ns
ns
ns
4.5V ≤ Vcc ≤ 5.5V (E Temp range)
3.0V ≤ Vcc ≤ 4.5V
4.5V ≤ Vcc ≤ 5.5V
4700
4700
1300
—
—
—
4.5V ≤ Vcc ≤ 5.5V (E Temp range)
3.0V ≤ Vcc ≤ 4.5V
4.5V ≤ Vcc ≤ 5.5V
SDA and SCL rise time
(Note 1)
—
—
—
1000
1000
300
4.5V ≤ Vcc ≤ 5.5V (E Temp range)
3.0V ≤ Vcc ≤ 4.5V
4.5V ≤ Vcc ≤ 5.5V
SDA and SCL fall time
TF
—
300
ns
ns
(Note 1)
START condition hold time
THD:STA
4000
4000
600
—
—
—
4.5V ≤ Vcc ≤ 5.5V (E Temp range)
3.0V ≤ Vcc ≤ 4.5V
4.5V ≤ Vcc ≤ 5.5V
START condition setup time
TSU:STA
4700
4700
600
—
—
—
ns
4.5V ≤ Vcc ≤ 5.5V (E Temp range)
3.0V ≤ Vcc ≤ 4.5V
4.5V ≤ Vcc ≤ 5.5V
Data input hold time
Data input setup time
THD:DAT
TSU:DAT
0
—
ns
ns
(Note 2)
250
250
100
—
—
—
4.5V ≤ Vcc ≤ 5.5V (E Temp range)
3.0V ≤ Vcc ≤ 4.5V
4.5V ≤ Vcc ≤ 5.5V
STOP condition setup time
TSU:STO
TAA
4000
4000
600
—
—
—
ns
ns
ns
4.5V ≤ Vcc ≤ 5.5V (E Temp range)
3.0V ≤ Vcc ≤ 4.5V
4.5V ≤ Vcc ≤ 5.5V
Output valid from clock
(Note 2)
—
—
—
3500
3500
900
4.5V ≤ Vcc ≤ 5.5V (E Temp range)
3.0V ≤ Vcc ≤ 4.5V
4.5V ≤ Vcc ≤ 5.5V
Bus free time: Time the bus must
be free before a new transmission
can start
TBUF
4700
4700
1300
—
—
—
4.5V ≤ Vcc ≤ 5.5V (E Temp range)
3.0V ≤ Vcc ≤ 4.5V
4.5V ≤ Vcc ≤ 5.5V
Output fall time from VIH
minimum to VIL maximum
TOF
TSP
TWC
20+0.1
CB
250
ns
ns
(Note 1), CB ≤ 100 pF
Input filter spike suppression
(SDA and SCL pins)
—
50
(Notes 1, 3)
Write cycle time
Endurance
—
4
ms
1M
—
cycles 25°C, VCC = 5.0V, Block Mode (Note 4)
Note 1: Not 100% tested. CB = total capacitance of one bus line in pF.
2: As a transmitter, the device must provide an internal minimum delay time to bridge the undefined region
(minimum 300 ns) of the falling edge of SCL to avoid unintended generation of START or STOP conditions.
3: The combined TSP and VHYS specifications are due to new Schmitt trigger inputs which provide improved
noise spike suppression. This eliminates the need for a TI specification for standard operation.
4: This parameter is not tested but guaranteed by characterization. For endurance estimates in a specific
application, please consult the Total Endurance Model which can be obtained on Microchip’s BBS or web-
site.
DS40172A-page 66
Preliminary
1997 Microchip Technology Inc.
PIC12CE5XX
TABLE 11-7: PULL-UP RESISTOR RANGES
VDD (Volts)
Temperature (°C)
Min
Typ
Max
Units
GP0/GP1
3.0
-40
25
27K
33K
33K
37K
15K
18K
19K
22K
32K
38K
39K
42K
17K
20K
22K
24K
35K
43K
43K
60K
20K
23K
25K
28K
Ω
Ω
Ω
Ω
Ω
Ω
Ω
Ω
85
125
-40
25
5.5
85
125
GP3
3.0
5.5
-40
25
271K
327K
348K
400K
247K
288K
306K
351K
326K
390K
427K
472K
292K
341K
371K
407K
395K
492K
500K
567K
360K
437K
448K
500K
Ω
Ω
Ω
Ω
Ω
Ω
Ω
Ω
85
125
-40
25
85
125
*
These parameters are characterized but not tested.
1997 Microchip Technology Inc.
Preliminary
DS40172A-page 67
PIC12CE5XX
NOTES:
DS40172A-page 68
Preliminary
1997 Microchip Technology Inc.
PIC12CE5XX
12.0 DC AND AC CHARACTERISTICS - PIC12CE5XX
The graphs and tables provided in this section are for design guidance and are not tested or guaranteed. In some
graphs or tables the data presented are outside specified operating range (e.g., outside specified VDD range). This is
for information only and devices will operate properly only within the specified range.
The data presented in this section is a statistical summary of data collected on units from different lots over a period of
time. “Typical” represents the mean of the distribution while “max” or “min” represents (mean + 3σ) and (mean – 3σ)
respectively, where σ is standard deviation.
FIGURE 12-1: CALIBRATED INTERNAL RC FREQUENCY RANGE VS.TEMPERATURE (VDD = 5.0V)
(INTERNAL RC IS CALIBRATED TO 25°C, 5.0V)
Not available at this time.
FIGURE 12-2: CALIBRATED INTERNAL RC FREQUENCY RANGE VS.TEMPERATURE (VDD = 3.0V)
(INTERNAL RC IS CALIBRATED TO 25°C, 5.0V)
Not available at this time.
1997 Microchip Technology Inc.
Preliminary
DS40172A-page 69
PIC12CE5XX
FIGURE 12-3: INTERNAL RC FREQUENCY VS. CALIBRATION VALUE (VDD = 5.5V)
Not available at this time.
FIGURE 12-4: INTERNAL RC FREQUENCY VS. CALIBRATION VALUE (VDD = 3.0V)
Not available at this time.
TABLE 12-1: DYNAMIC IDD (TYPICAL) - WDT ENABLED, 25°C
Oscillator
Frequency
VDD =3.0V
VDD = 5.5V
External RC
Internal RC
XT
4 MHz
4 MHz
4 MHz
32 KHz
300 µA*
520 µA
300 µA
10 µA
620 µA*
1.1 mA
775 µA
37 µA
LP
*Does not include current through external R&C.
DS40172A-page 70
Preliminary
1997 Microchip Technology Inc.
PIC12CE5XX
FIGURE 12-5: WDT TIMER TIME-OUT
PERIOD vs. VDD
FIGURE 12-6: SHORT DRT PERIOD VS. VDD
1000
50
45
40
900
800
700
600
35
30
500
25
Max +125°C
400
Max +125°C
Max +85°C
Typ +25°C
20
15
Max +85°C
300
Typ +25°C
200
MIn –40°C
MIn –40°C
10
5
100
2
3
4
5
6
7
2
3
4
5
6
7
VDD (Volts)
VDD (Volts)
1997 Microchip Technology Inc.
Preliminary
DS40172A-page 71
PIC12CE5XX
FIGURE 12-7: IOH vs. VOH, VDD = 3.5 V
FIGURE 12-9: IOL vs. VOL, VDD = 3.5 V
0
35
30
-5
-10
25
20
-15
-20
15
10
-25
-30
5
0
1.5
2.0
2.5
3.0
3.5
VOH (Volts)
0
500.0m
750.0m
1.0
VOL (Volts)
FIGURE 12-8: IOH vs. VOH, VDD = 5.5 V
FIGURE 12-10: IOL vs. VOL, VDD = 5.5 V
0
50
-5
Max –40°C
40
30
20
10
-10
Typ +25°C
Min +85°C
-15
-20
Min +125°C
-25
-30
3.5
4.0
4.5
5.0
5.5
0
VOH (Volts)
250.0m
500.0m
750.0m
1.0
VOL (Volts)
DS40172A-page 72
Preliminary
1997 Microchip Technology Inc.
PIC12CE5XX
13.0 PACKAGING INFORMATION
13.1
Package Marking Information
8-Lead PDIP (300 mil)
Example
12CE518
MMMMMMMM
XXXXXCDE
04I/PSAZ
AABB
9625
8-Lead SOIC (208 mil)
Example
MMMMMMM
XXXXXXX
AABBCDE
12CE518
04I/SM
9624SAZ
Example
8-Lead Windowed Ceramic Side Brazed (300 mil)
JW
MM
12CE518
MMMMMMM
Legend: MM...M Microchip part number information
XX...X Customer specific information*
AA
BB
C
Year code (last 2 digits of calendar year)
Week code (week of January 1 is week ‘01’)
Facility code of the plant at which wafer is manufactured
C = Chandler, Arizona, U.S.A.,
S = Tempe, Arizona, U.S.A.
D
E
Mask revision number
Assembly code of the plant or country of origin in which
part was assembled
Note: In the event the full Microchip part number cannot be marked on one line,
it will be carried over to the next line thus limiting the number of available
characters for customer specific information.
*
Standard OTP marking consists of Microchip part number, year code, week
code, facility code, mask rev#, and assembly code. For OTP marking
beyond this, certain price adders apply. Please check with your Microchip
Sales Office. For QTP devices, any special marking adders are included in
QTP price.
1997 Microchip Technology Inc.
Preliminary
DS40172A-page 73
PIC12CE5XX
13.2
8-Lead Plastic Dual In-line (300 mil)
N
α
C
E
E1
eA
eB
Pin No. 1
Indicator
Area
D
S
S1
Base
Plane
Seating
Plane
L
B1
D1
A
A2
A1
e1
B
Package Group: Plastic Dual In-Line (PLA)
Millimeters
Inches
Symbol
Min
Max
Notes
Min
Max
Notes
α
0°
10°
4.064
–
0°
10°
0.160
–
A
–
–
A1
A2
B
0.381
3.048
0.355
1.397
0.203
9.017
7.620
7.620
6.096
2.489
7.620
7.874
3.048
8
0.015
0.120
0.014
0.055
0.008
0.355
0.300
0.300
0.240
0.098
0.300
0.310
0.120
8
3.810
0.559
1.651
0.381
10.922
7.620
8.255
7.112
2.591
7.620
9.906
3.556
8
0.150
0.022
0.065
0.015
0.430
0.300
0.325
0.280
0.102
0.300
0.390
0.140
8
B1
C
Typical
Typical
D
D1
E
Reference
Reference
E1
e1
eA
eB
L
Typical
Typical
Reference
Reference
N
S
0.889
0.254
–
0.035
0.010
–
S1
–
–
DS40172A-page 74
Preliminary
1997 Microchip Technology Inc.
PIC12CE5XX
13.3
8-Lead Plastic Surface Mount (SOIC - Medium, 208 mil Body)
e
h x 45°
B
N
Index
Area
α
C
H
E
L
Chamfer
h x 45°
1
2
3
D
Base
Plane
CP
Seating
Plane
A1
A
Package Group: Plastic SOIC (SM)
Millimeters
Max
Inches
Symbol
Min
Notes
Min
Max
Notes
α
A
0°
8°
0°
8°
1.778
0.101
0.355
0.190
5.080
5.156
1.270
7.670
0.381
0.508
14
2.00
0.070
0.004
0.014
0.007
0.200
0.203
0.050
0.302
0.015
0.020
14
0.079
0.010
0.019
0.010
0.210
0.213
0.050
0.319
0.030
0.040
14
A1
B
0.249
0.483
0.249
5.334
5.411
1.270
8.103
0.762
1.016
14
C
D
E
e
Reference
Reference
H*
h
L
N
CP
–
0.102
–
0.004
1997 Microchip Technology Inc.
Preliminary
DS40172A-page 75
PIC12CE5XX
13.4
8-Lead Ceramic Side Brazed Dual In-Line with Window (JW) (300 mil)
N
α
C
E
E1
eA
eB
Pin No. 1
Indicator
Area
D
S
S1
Base
Plane
Seating
Plane
L
B1
e1
A
A3
A2
A1
B
D1
Package Group: Ceramic Side Brazed Dual In-Line (CER)
Millimeters
Max
Inches
Symbol
Min
Notes
Min
Max
Notes
α
0°
10°
5.030
1.143
3.429
2.413
0.508
1.371
0.305
13.412
7.824
8.230
7.620
2.540
7.620
9.652
4.064
3.048
—
0°
10°
A
3.937
0.635
2.921
1.778
0.406
1.371
0.228
0.155
0.025
0.115
0.070
0.016
0.054
0.009
0.512
0.292
0.298
0.280
0.100
0.300
0.300
0.130
0.100
0.005
0.198
0.045
0.135
0.095
0.020
0.054
0.012
0.528
0.308
0.324
0.300
0.100
0.300
0.380
0.160
0.120
—
A1
A2
A3
B
B1
C
Typical
Typical
Typical
Typical
D
13.004
7.416
7.569
7.112
2.540
7.620
7.620
3.302
2.540
0.127
D1
E
BSC
BSC
E1
e1
eA
eB
L
Typical
BSC
Typical
BSC
S
S1
DS40172A-page 76
Preliminary
1997 Microchip Technology Inc.
PIC12CE5XX
The following example requires:
14.0 APPENDIX A
• Code Space: 77 words
The following routines are written for 4 MHz clock oper-
ation, where the worst case timing occurs; the routines
can be used at lower frequencies without modification.
For those using clock speeds much less than 4MHz, it
may be possible to reduce code size by removing some
of the NOPs (see code listing).
• RAM Space: 5 bytes (4 are overlayable)
• Stack Levels:1 (The call to the function itself. The
functions do not call any lower level functions.)
• Timing:
- WRITE_BYTE takes 328 cycles
- READ_CURRENT takes 212 cycles
- READ_RANDOM takes 416 cycles.
• IO Pins: 0 (No external IO pins are used)
14.1
SDA and SCL
The EEPROM interface is a 2-wire bus protocol con-
sisting of data (SDA) and a clock (SCL). Although
these lines are mapped into the GPIO register, they are
not accessible as external pins; only to the internal
EEPROM peripheral. SDA and SCL operation is also
slightly different than GPO-GP5 as listed below.
Namely, to avoid code overhead in modifying the TRIS
register, both SDA and SCL are always outputs. To
read data from the EEPROM peripheral requires out-
putting a ‘1’ on SDA placing it in high-Z state, where
only the internal 100K pull-up is active on the SDA line.
This code must reside in the lower half of a page. The
code achieves it’s small size without additional calls
through the use of a sequencing table. The table is a
list of procedures that must be called in order. The
table uses an ADDWF PCL,F instruction, effectively a
computed goto, to sequence to the next procedure.
However the ADDWF PCL,F instruction yields an 8 bit
address, forcing the code to reside in the first 256
addresses of a page.
SDA:
Built-in 100K pull-up to VDD
Open-drain (pull-down only)
Always an output, regardless of TRIS<6>
Outputs a ‘1’ on reset
SCL:
Full CMOS output
Always an output regardless of TRIS<7>
Outputs a ‘1’ on reset
14.2
Example Code for Reading/Writing to EEPROM Data Memory
TITLE "PIC with EEPROM Data Memory Interface"
LIST P=12CE518
; Change to 12CE519 if using PIC12CE519
#include <p12CE518.inc>
;
;
;
;
;
Program:
Revision Date:
EEPROM.ASM
10-10-97
Adapted to 12CE51x parts
; PIC12CE51X EEPROM communication code. This code should be linked in
; with the application. These routines provide the following functionality:
; write byte random address
; read byte random address
; read byte next address
;
; read sequential is not supported.
;
; If the operation is successful, bit 7 of PC_OFFSET will be set, and
; the functions will return W=1. If the memory is busy with a write
; cycle, it will not ACK the command. The functions will return with
; bit 7 of PC_OFFSET cleared and and W will be set to 0.
;
; Based on Franco code.
;
; Must reside on the lower half of code page (address 0-FF).
;
; This provides users with highly compressed assembly code for
; communication between the EEPROM and the Microcontroller, which
; leaves a maximum amount of code space for the core application.
1997 Microchip Technology Inc.
Preliminary
DS40172A-page 77
PIC12CE5XX
;
; NOPs have been added to meet the timing specs for the memory at 4 MHz
; and low voltage. Applications running at slower clock rates and those
; operating within 4.5-5.5V may be able to remove some of the NOPs.
;
; This code is specifically written for the interface hardware of the
; 12CE51x parts. See AN571 for the unmodified routines.
;***************************************************************************
;*************************** EEPROM Subroutines **************************
;***************************************************************************
; Communication for EEPROM based on I2C protocol, with Acknowledge.
;
; Byte_Write: Byte write routine
;
;
;
;
Inputs:
EEPROM Address
EEPROM Data
Return 01 in W if OK, else return 00 in W
EEADDR
EEDATA
Outputs:
; Read_Current:
Read EEPROM at address currently held by EE device.
NONE
;
;
;
;
Inputs:
Outputs:
EEPROM Data
EEDATA
Return 01 in W if OK, else return 00 in W
; Read_Random:
Read EEPROM byte at supplied address
;
;
;
;
Inputs:
Outputs:
EEPROM Address
EEPROM Data
Return 01 in W if OK, else return 00 in W
EEADDR
EEDATA
; Note: EEPROM subroutines will set bit 7 in PC_OFFSET register if the
;
;
EEPROM acknowledged OK, else that bit will be cleared. This bit
can be checked instead of refering to the value returned in W
;***************************************************************************
;
; OPERATION:
;
;
;
;
;
;
;
;
;
;
;
;
;
;
Byte Write:
load EEADDR and EEDATA
then CALL BYTE_WRITE
Read Random:
Load EEADDR
then CALL READ_RANDOM
data read returned in EEDATA
Read Current
no setup necessary
CALL READ_CURRENT
data read returned in EEDATA
;***************************************************************************
;
; These functions consume:
; 77 words Programming Memory
; 5 file registers which are overlayable. That is, they can share with
; other functions as long as they are mutually exclusive in time. See
; udata_ovr in the linker manual.
; 1 stack level (the call to the function itself. These functions do not
; call any lower level functions).
;
;
DS40172A-page 78
Preliminary
1997 Microchip Technology Inc.
PIC12CE5XX
;***************************************************************************
;*************************** Variable Listing ****************************
;***************************************************************************
OK
NO
EQU
EQU
01H
00H
I2C_PORT
SCL
SDA
EQU
EQU
EQU
GPIO
07H
06H
; Port B control register, used for I2C
; EEPROM Clock, SCL (I/O bit 7)
; EEPROM Data, SDA (I/O bit 6)
EE_OK
EQU
RES
07H
1
; Bit 7 in PC_OFFSET used as OK flag for EE
udata_ovr
PC_OFFSET
; PC offset register (low order 4 bits),
;
;
value based on operating mode of EEPROM.
Also, bit 7 used for EE_OK flag
EEADDR
EEBYTE
res
res
1
1
; EEPROM Address
; Byte sent to or received from
; EEPROM (control, address, or data)
; Bit counter for serial transfer
COUNTER
res
res
1
1
udata
EEDATA
; EEPROM Data
global
READ_CURRENT
READ_RANDOM
WRITE_BYTE
EEADDR
EEDATA
PC_OFFSET
global
global
global
global
global
;********************** Set up EEPROM control bytes ************************
;***************************************************************************
code
READ_CURRENT
MOVLW
MOVWF
GOTO
B'10000100'
PC_OFFSET
INIT_READ_CONTROL
; PC offset for read current addr. EE_OK bit7='1'
; Load PC offset
WRITE_BYTE
MOVLW
B'10000000'
INIT_WRITE_CONTROL
; PC offset for write byte. EE_OK: bit7 = '1'
; PC offset for read random. EE_OK: bit7 = '1'
GOTO
READ_RANDOM
MOVLW
B'10000011'
INIT_WRITE_CONTROL
MOVWF
MOVLW
PC_OFFSET
B'10100000'
; Load PC offset register, value preset in W
; Control byte with write bit, bit 0 = '0'
START_BIT
BCF
I2C_PORT,SDA
; Start bit, SDA and SCL preset to '1'
;******* Set up output data (control, address, or data) and counter ********
;***************************************************************************
PREP_TRANSFER_BYTE
MOVWF
MOVLW
MOVWF
EEBYTE
.8
COUNTER
; Byte to transfer to EEPROM already in W
; Counter to transfer 8 bits
1997 Microchip Technology Inc.
Preliminary
DS40172A-page 79
PIC12CE5XX
;************ Clock out data (control, address, or data) byte ************
;***************************************************************************
OUTPUT_BYTE
BCF
RLF
BCF
SKPNC
BSF
NOP
BSF
I2C_PORT,SCL
EEBYTE, F
I2C_PORT,SDA
; Set clock low during data set-up
; Rotate left, high order bit into carry bit
; Set data low, if rotated carry bit is
;
a '1', then:
I2C_PORT,SDA
I2C_PORT,SCL
; reset data pin to a one, otherwise leave low
; clock data into EEPROM
DECFSZ COUNTER, F
; Repeat until entire byte is sent
GOTO
NOP
OUTPUT_BYTE
; Needed to meet Timing (Thigh=4000nS)
;************************** Acknowkedge Check *****************************
;***************************************************************************
BCF
NOP
BSF
GOTO
NOP
NOP
BSF
I2C_PORT,SCL
; Set SCL low, 0.5us < ack valid < 3us
; Needed to meet Timing (Tlow= 4700nS)
I2C_PORT,SDA
$+1
;
;
;
; Necessary for SCL Tlow at low voltage,
; Tlow=4700nS
I2C_PORT,SCL
; Raise SCL, EEPROM acknowledge still valid
; Check SDA for acknowledge (low)
; If SDA not low (no ack), set error flag
; Lower SCL, EEPROM release bus
; If no error continue, else stop bit
BTFSC I2C_PORT,SDA
BCF
BCF
BTFSS PC_OFFSET,EE_OK
GOTO STOP_BIT
PC_OFFSET,EE_OK
I2C_PORT,SCL
;***** Set up program counter offset, based on EEPROM operating mode *****
;***************************************************************************
MOVF
ANDLW
ADDWF
PC_OFFSET,W
B'00001111'
PCL, F
GOTO
GOTO
GOTO
GOTO
GOTO
GOTO
GOTO
INIT_ADDRESS
INIT_WRITE_DATA
STOP_BIT
INIT_ADDRESS
INIT_READ_CONTROL
READ_BIT_COUNTER
STOP_BIT
;PC offset=0, write control done, send address
;PC offset=1, write address done, send data
;PC offset=2, write done, send stop bit
;PC offset=3, write control done, send address
;PC offset=4, send read control
;PC offset=5, set counter and read byte
;PC offset=6, random read done, send stop
;********** Initalize EEPROM data (address, data, or control) bytes ******
;***************************************************************************
INIT_ADDRESS
INCF
MOVF
GOTO
PC_OFFSET, F
EEADDR,W
PREP_TRANSFER_BYTE
; Increment PC offset to 2 (write) or to 4 (read)
; Put EEPROM address in W, ready to send to EEPROM
INIT_WRITE_DATA
INCF
MOVF
GOTO
PC_OFFSET, F
EEDATA,W
PREP_TRANSFER_BYTE
; Increment PC offset to go to STOP_BIT next
; Put EEPROM data in W, ready to send to EEPROM
INIT_READ_CONTROL
BSF
I2C_PORT,SCL
; Raise SCL
BSF
INCF
I2C_PORT,SDA
PC_OFFSET, F
; raise SDA
; Increment PC offset to go to READ_BIT_COUNTER next
; Set up read control byte, ready to send to EEPROM
MOVLW B'10100001'
GOTO START_BIT
;
bit 0 = '1' for read operation
DS40172A-page 80
Preliminary
1997 Microchip Technology Inc.
PIC12CE5XX
;************************** Read EEPROM data *****************************
;***************************************************************************
READ_BIT_COUNTER
BSF
NOP
BSF
I2C_PORT,SDA
; set data bit to 1 so we're not pulling bus down.
I2C_PORT,SCL
MOVLW .8
; Set counter so 8 bits will be read into EEDATA
MOVWF COUNTER
READ_BYTE
BSF
SETC
I2C_PORT,SCL
; Raise SCL, SDA valid. SDA still input from ack
; Assume bit to be read = 1
; Check if SDA = 1
; if SDA not = 1 then clear carry bit
; rotate carry bit (=SDA) into EEDATA;
; Lower SCL
BTFSS I2C_PORT,SDA
CLRC
RLF
BCF
bsf
EEDATA, F
I2C_PORT,SCL
I2C_PORT,SDA
; reset SDA
DECFSZ COUNTER, F
; Decrement counter
GOTO
READ_BYTE
; Read next bit if not finished reading byte
BSF
NOP
BCF
I2C_PORT,SCL
I2C_PORT,SCL
;****************** Generate a STOP bit and RETURN ***********************
;***************************************************************************
STOP_BIT
BCF
BSF
GOTO
GOTO
BSF
I2C_PORT,SDA
I2C_PORT,SCL
$+1
$+1
I2C_PORT,SDA
; SDA=0, on TRIS, to prepare for transition to '1'
; SCL = 1 to prepare for STOP bit
; equivalent 4 NOPs neccessary for I2C spec Tsu:sto = 4.7us
; Stop bit, SDA transition to '1' while SCL high
BTFSS PC_OFFSET,EE_OK
RETLW NO
RETLW OK
; Check for error
; if error, send back NO
; if no error, send back OK
;****************************************************************************
;************************ End EEPROM Subroutines **************************
end
1997 Microchip Technology Inc.
Preliminary
DS40172A-page 81
PIC12CE5XX
NOTES:
DS40172A-page 82
Preliminary
1997 Microchip Technology Inc.
PIC12CE5XX
INDEX
A
O
OPTION Register ............................................................... 15
OSC selection..................................................................... 29
OSCCAL Register .............................................................. 16
Oscillator Configurations .................................................... 30
Oscillator Types
ALU....................................................................................... 7
Applications........................................................................... 3
Architectural Overview.......................................................... 7
Assembler
HS............................................................................... 30
LP ............................................................................... 30
RC .............................................................................. 30
XT............................................................................... 30
MPASM Assembler..................................................... 54
B
Block Diagram
On-Chip Reset Circuit................................................. 35
Timer0......................................................................... 25
TMR0/WDT Prescaler................................................. 28
Watchdog Timer.......................................................... 37
Brown-Out Protection Circuit .............................................. 38
P
Package Marking Information............................................. 73
Packaging Information........................................................ 73
PC....................................................................................... 17
PICDEM-1 Low-Cost PICmicro Demo Board ..................... 54
PICDEM-2 Low-Cost PIC16CXX Demo Board................... 54
PICDEM-3 Low-Cost PIC16CXXX Demo Board ................ 54
PICMASTER In-Circuit Emulator..................................... 53
PICSTART Plus Entry Level Development System......... 53
POR
Device Reset Timer (DRT) ................................... 29, 36
PD............................................................................... 38
Power-On Reset (POR).............................................. 29
TO............................................................................... 38
PORTA ............................................................................... 19
Power-Down Mode............................................................. 39
Prescaler ............................................................................ 28
PRO MATE II Universal Programmer.............................. 53
Program Counter................................................................ 17
C
CAL0 bit .............................................................................. 16
CAL1 bit .............................................................................. 16
CAL2 bit .............................................................................. 16
CAL3 bit .............................................................................. 16
CALFST bit ......................................................................... 16
CALSLW bit ........................................................................ 16
Carry ..................................................................................... 7
Clocking Scheme................................................................ 10
Code Protection ............................................................ 29, 39
Configuration Bits................................................................ 29
Configuration Word............................................................. 29
D
DC and AC Characteristics................................................. 69
Development Support ......................................................... 53
Development Tools............................................................. 53
Device Varieties.................................................................... 5
Digit Carry............................................................................. 7
Q
Q cycles.............................................................................. 10
R
RC Oscillator ...................................................................... 31
Read Modify Write.............................................................. 20
Register File Map ............................................................... 12
Registers
Special Function......................................................... 13
Reset .................................................................................. 29
Reset on Brown-Out........................................................... 38
E
EEPROM Peripheral Operation .......................................... 21
F
Family of Devices.................................................................. 4
Features................................................................................ 1
FSR..................................................................................... 18
Fuzzy Logic Dev. System (fuzzyTECH -MP) .................... 55
S
SEEVAL Evaluation and Programming System .............. 55
SLEEP.......................................................................... 29, 39
Software Simulator (MPLAB-SIM)...................................... 55
Special Features of the CPU.............................................. 29
Special Function Registers................................................. 13
Stack................................................................................... 17
STATUS ................................................................................7
STATUS Register............................................................... 14
I
I/O Interfacing ..................................................................... 19
I/O Port................................................................................ 19
I/O Programming Considerations........................................ 20
ICEPIC Low-Cost PIC16CXXX In-Circuit Emulator ............ 53
ID Locations.................................................................. 29, 39
INDF.................................................................................... 18
Indirect Data Addressing..................................................... 18
Instruction Cycle ................................................................. 10
Instruction Flow/Pipelining .................................................. 10
Instruction Set Summary..................................................... 42
T
Timer0
Switching Prescaler Assignment ................................ 28
Timer0 ........................................................................ 25
Timer0 (TMR0) Module .............................................. 25
TMR0 with External Clock .......................................... 27
Timing Diagrams and Specifications .................................. 62
Timing Parameter Symbology and Load Conditions .......... 61
TRIS Registers ................................................................... 19
K
KeeLoq Evaluation and Programming Tools.................... 55
L
Loading of PC ..................................................................... 17
M
W
Memory Organization.......................................................... 11
Data Memory .............................................................. 12
Program Memory ........................................................ 11
MP-DriveWay™ - Application Code Generator................... 55
MPLAB C ............................................................................ 55
MPLAB Integrated Development Environment Software.... 54
Wake-up from SLEEP ........................................................ 39
Watchdog Timer (WDT)................................................ 29, 36
Period ......................................................................... 37
Programming Considerations..................................... 37
1997 Microchip Technology Inc.
Preliminary
DS40172A-page 83
PIC12CE5XX
Figure 11-3: I/O Timing - PIC12CE5XX.......................... 63
Figure 11-4: Reset, Watchdog Timer, and Device
Reset Timer Timing - PIC12CE5XX........... 64
Figure 11-5: Timer0 Clock Timings - PIC12CE5XX........ 65
Figure 11-6: EEPROM Memory Bus Timing
Data............................................................ 65
Figure 12-1: Calibrated Internal RC Frequency
Range vs. Temperature (VDD = 5.0V)
(internal RC is calibrated to 25°C, 5.0V) .... 69
Figure 12-2: Calibrated Internal RC Frequency
Range vs. Temperature (VDD = 3.0V)
(internal RC is calibrated to 25°C, 5.0V) .... 69
Figure 12-3: Internal RC Frequency vs. calibration
value (VDD = 5.5V) ..................................... 70
Z
Zero bit..................................................................................7
LIST OF FIGURES
Figure 3-1:
Figure 3-2:
Figure 4-1:
PIC12CE5XX Block Diagram........................8
Clock/Instruction Cycle ...............................10
Program Memory Map and Stack for the
PIC12CE5XX..............................................11
PIC12CE518 Register File Map..................12
PIC12CE519 Register File Map..................12
STATUS Register (Address:03h)................14
OPTION Register........................................15
OSCCAL Register (Address 8Fh)...............16
Loading of PC Branch Instructions -
PIC12CE518/CE519...................................17
Direct/Indirect Addressing...........................18
Equivalent Circuit
for a Single I/O Pin......................................19
Successive I/O Operation...........................20
Data Transfer Sequence On The
Serial Bus ...................................................22
Acknowledge Timing...................................22
Control Byte format.....................................22
Acknowledge Polling Flow..........................23
Byte Write ...................................................23
Current Address Read................................24
Random Read.............................................24
Sequential Read .........................................24
Timer0 Block Diagram ................................25
Timer0 Timing: Internal Clock/No
Prescale......................................................26
Timer0 Timing: Internal Clock/
Prescale 1:2................................................26
Timer0 Timing With External Clock ............27
Block Diagram of the Timer0/WDT
Figure 4-2:
Figure 4-3:
Figure 4-4:
Figure 4-5:
Figure 4-6:
Figure 4-7:
Figure 12-4: Internal RC Frequency vs. calibration
value (VDD = 3.0V) ..................................... 70
Figure 4-8:
Figure 5-1:
Figure 12-5: WDT Timer Time-out Period vs. VDD ......... 71
Figure 12-6: Short DRT period vs. vDD........................... 71
Figure 12-7: IOH vs. VOH, VDD = 3.5 V............................ 72
Figure 12-8: IOH vs. VOH, VDD = 5.5 V............................ 72
Figure 12-9: IOL vs. VOL, VDD = 3.5 V............................. 72
Figure 12-10: IOL vs. VOL, VDD = 5.5 V............................. 72
Figure 5-2:
Figure 6-1:
Figure 6-2:
Figure 6-3:
Figure 6-4:
Figure 6-5:
Figure 6-6:
Figure 6-7:
Figure 6-8:
Figure 7-1:
Figure 7-2:
LIST OF TABLES
Table 1-1:
Table 3-1:
Table 4-1:
PIC12CXXX Family of Devices...................... 4
PIC12CE5XX Pinout description.................... 9
Special Function Register (SFR)
Summary...................................................... 13
Summary of Port Registers.......................... 19
Registers Associated With Timer0............... 26
Capacitor Selection for Ceramic
Table 5-1:
Table 7-1:
Table 8-1:
Resonators - PIC12CE5XX.......................... 30
Capacitor Selection
Figure 7-3:
Table 8-2:
for Crystal Oscillator - PIC12CE5XX............ 30
Reset Conditions for Registers .................... 33
Reset Condition for Special Registers ......... 33
DRT (Device Reset Timer Period) ............... 36
Summary of Registers Associated
Figure 7-4:
Figure 7-5:
Table 8-3:
Table 8-4:
Table 8-5:
Table 8-6:
Prescaler.....................................................28
Configuration Word for PIC12CE5XX.........29
Crystal Operation (or Ceramic
Figure 8-1:
Figure 8-2:
with the Watchdog Timer ............................. 37
TO/PD/GPWUF Status After Reset.............. 38
Events Affecting TO/PD Status Bits............. 38
OPCODE Field Descriptions........................ 41
Instruction Set Summary.............................. 42
Resonator) (XT or LP OSC
Configuration) .............................................30
External Clock Input Operation
(XT or LP OSC Configuration)....................30
External Parallel Resonant Crystal
Oscillator Circuit..........................................31
External Series Resonant Crystal
Oscillator Circuit..........................................31
External RC Oscillator Mode ......................31
MCLR SELECT...........................................34
Simplified Block Diagram of On-
Chip Reset Circuit.......................................35
Time-Out Sequence on Power-Up
Table 8-7:
Table 8-8:
Table 9-1:
Table 9-2:
Figure 8-3:
Figure 8-4:
Figure 8-5:
Table 10-1: Development Tools From Microchip ............ 56
Table 11-1: External Clock Timing Requirements -
PIC12CE5XX ............................................... 62
Table 11-2: Timing Requirements - PIC12CE5XX.......... 63
Table 11-3: Reset, Watchdog Timer, and Device
Reset Timer - PIC12CE5XX ........................ 64
Table 11-4: DRT (Device Reset Timer Period)
Time Out ...................................................... 64
Table 11-5: Timer0 Clock Requirements -
Figure 8-6:
Figure 8-7:
Figure 8-8:
Figure 8-9:
(MCLR Pulled Low).....................................35
PIC12CE5XX ............................................... 65
Table 11-6: EEPROM Memory Bus Timing
Figure 8-10: Time-Out Sequence on Power-Up
(MCLR Tied to VDD): Fast VDD
Requirements............................................... 66
Table 11-7: Pull-up Resistor Ranges .............................. 67
Table 12-1: Dynamic iDD (typical) - wdt enabled,
25°C............................................................. 70
Rise Time....................................................35
Figure 8-11: Time-Out Sequence on Power-Up
(MCLR Tied to VDD): Slow VDD
Rise Time....................................................36
Figure 8-12: Watchdog Timer Block Diagram.................37
Figure 8-13: Brown-Out Protection Circuit 1 ...................38
Figure 8-14: Brown-Out Protection Circuit 2 ...................38
Figure 8-15: Typical In-Circuit Serial Programming
Connection..................................................40
Figure 9-1:
General Format for Instructions..................41
Figure 11-1: Load Conditions - PIC12CE5XX.................61
Figure 11-2: External Clock Timing - PIC12CE5XX........62
DS40172A-page 84
1997 Microchip Technology Inc.
PIC12CE5XX
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1997 Microchip Technology Inc.
Preliminary
DS40172A-page 85
PIC12CE5XX
READER RESPONSE
It is our intention to provide you with the best documentation possible to ensure successful use of your Microchip product.
If you wish to provide your comments on organization, clarity, subject matter, and ways in which our documentation can
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Device:
PIC12CE5XX
Literature Number:
DS40172A
Questions:
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DS40172A-page 86
Preliminary
1997 Microchip Technology Inc.
PIC12CE5XX
PIC12CE5XX Product Identification System
Examples
PART NO. -XX X /XX XXX
Pattern:
Special Requirements
a)
b)
c)
PIC12CE518-04/P
Commercial Temp.,
PDIP Package, 4 MHz,
normal VDD limits
Package:
SM
P
JW
=
=
=
208 mil SOIC
300 mil PDIP
300 mil Windowed CERDIP
PIC12CE518-04I/SM
Industrial Temp., SOIC
package,4 MHz,normal
VDD limits
Temperature
Range:
-
=
=
=
0°C to +70°C
-40°C to +85°C
-40°C to +125°C
I
E
Frequency
Range:
04
=
4 MHz
PIC12CE519-04I/P
Industrial Temp.,
PDIP package, 4 MHz,
normal VDD limits
Device
PIC12CE518
PIC12CE519
PIC12CE518T (Tape & reel for SOIC only)
PIC12CE519T (Tape & reel for SOIC only)
Please contact your local sales office for exact ordering procedures.
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For latest version information and upgrade kits for Microchip Development Tools, please call 1-800-755-2345 or 1-602-786-7302.
1997 Microchip Technology Inc.
Preliminary
DS40172A-page 87
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Germany
Arizona Microchip Technology GmbH
Gustav-Heinemann-Ring 125
D-81739 Müchen, Germany
Tel: 49-89-627-144 0 Fax: 49-89-627-144-44
Korea
Microchip Technology Korea
168-1, Youngbo Bldg. 3 Floor
Samsung-Dong, Kangnam-Ku
Seoul, Korea
Chicago
Microchip Technology Inc.
333 Pierce Road, Suite 180
Itasca, IL 60143
Italy
Tel: 82-2-554-7200 Fax: 82-2-558-5934
Arizona Microchip Technology SRL
Centro Direzionale Colleoni
Palazzo Taurus 1 V. Le Colleoni 1
20041 Agrate Brianza
Milan, Italy
Tel: 39-39-6899939 Fax: 39-39-6899883
Shanghai
Microchip Technology
RM 406 Shanghai Golden Bridge Bldg.
2077 Yan’an Road West, Hong Qiao District
Shanghai, PRC 200335
Tel: 630-285-0071 Fax: 630-285-0075
Dallas
Microchip Technology Inc.
14651 Dallas Parkway, Suite 816
Dallas, TX 75240-8809
Tel: 972-991-7177 Fax: 972-991-8588
Tel: 86-21-6275-5700
Fax: 86 21-6275-5060
JAPAN
Singapore
Microchip Technology Taiwan
Singapore Branch
200 Middle Road
#07-02 Prime Centre
Microchip Technology Intl. Inc.
Benex S-1 6F
Dayton
Microchip Technology Inc.
Two Prestige Place, Suite 150
Miamisburg, OH 45342
Tel: 937-291-1654 Fax: 937-291-9175
3-18-20, Shinyokohama
Kohoku-Ku, Yokohama-shi
Kanagawa 222 Japan
Singapore 188980
Tel: 65-334-8870 Fax: 65-334-8850
Tel: 81-45-471- 6166 Fax: 81-45-471-6122
Los Angeles
Microchip Technology Inc.
18201 Von Karman, Suite 1090
Irvine, CA 92612
Taiwan, R.O.C
Microchip Technology Taiwan
10F-1C 207
Tung Hua North Road
Taipei, Taiwan, ROC
8/29/97
Tel: 714-263-1888 Fax: 714-263-1338
NewYork
Tel: 886 2-717-7175 Fax: 886-2-545-0139
Microchip Technology Inc.
150 Motor Parkway, Suite 416
Hauppauge, NY 11788
Tel: 516-273-5305 Fax: 516-273-5335
San Jose
Microchip Technology Inc.
2107 North First Street, Suite 590
San Jose, CA 95131
Tel: 408-436-7950 Fax: 408-436-7955
Toronto
Microchip Technology Inc.
5925 Airport Road, Suite 200
Mississauga, Ontario L4V 1W1, Canada
Tel: 905-405-6279 Fax: 905-405-6253
All rights reserved. © 1997, Microchip Technology Incorporated, USA. 10/97
Printed on recycled paper.
Information contained in this publication regarding device applications and the like is intended for suggestion only and may be superseded by updates. No representation or
warranty is given and no liability is assumed by Microchip Technology Incorporated with respect to the accuracy or use of such information, or infringement of patents or other
intellectual property rights arising from such use or otherwise. Use of Microchip’s products as critical components in life support systems is not authorized except with express
written approval by Microchip. No licenses are conveyed, implicitly or otherwise, under any intellectual property rights.The Microchip logo and name are registered trademarks
of Microchip Technology Inc. in the U.S.A. and other countries. All rights reserved. All other trademarks mentioned herein are the property of their respective companies.
DS40172A-page 88
1997 Microchip Technology Inc.
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