PIC16LF872-E/SP [ETC]
Microcontroller ; 微控制器\n
| 型号： | PIC16LF872-E/SP |
| 厂家： | 
ETC |
| 描述： | Microcontroller
|
| 文件： | 总168页 (文件大小：2769K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
M
PIC16F872
Data Sheet
28-Pin, 8-Bit CMOS FLASH
Microcontroller with 10-Bit A/D
2002 Microchip Technology Inc.
DS30221B
®
Note the following details of the code protection feature on PICmicro MCUs.
•
•
The PICmicro family meets the specifications contained in the Microchip Data Sheet.
Microchip believes that its family of PICmicro microcontrollers is one of the most secure products of its kind on the market today,
when used in the intended manner and under normal conditions.
•
There are dishonest and possibly illegal methods used to breach the code protection feature. All of these methods, to our knowl-
edge, require using the PICmicro microcontroller in a manner outside the operating specifications contained in the data sheet.
The person doing so may be engaged in theft of intellectual property.
•
•
Microchip is willing to work with the customer who is concerned about the integrity of their code.
Neither Microchip nor any other semiconductor manufacturer can guarantee the security of their code. Code protection does not
mean that we are guaranteeing the product as “unbreakable”.
•
Code protection is constantly evolving. We at Microchip are committed to continuously improving the code protection features of
our product.
If you have any further questions about this matter, please contact the local sales office nearest to you.
Information contained in this publication regarding device
applications and the like is intended through suggestion only
and may be superseded by updates. It is your responsibility to
ensure that your application meets with your specifications.
No representation or warranty is given and no liability is
assumed by Microchip Technology Incorporated with respect
to the accuracy or use of such information, or infringement of
patents or other intellectual property rights arising from such
use or otherwise. Use of Microchip’s products as critical com-
ponents in life support systems is not authorized except with
express written approval by Microchip. No licenses are con-
veyed, implicitly or otherwise, under any intellectual property
rights.
Trademarks
The Microchip name and logo, the Microchip logo, FilterLab,
KEELOQ, MPLAB, PIC, PICmicro, PICMASTER, PICSTART,
PRO MATE, SEEVAL and The Embedded Control Solutions
Company are registered trademarks of Microchip Technology
Incorporated in the U.S.A. and other countries.
dsPIC, ECONOMONITOR, FanSense, FlexROM, fuzzyLAB,
In-Circuit Serial Programming, ICSP, ICEPIC, microID,
microPort, Migratable Memory, MPASM, MPLIB, MPLINK,
MPSIM, MXDEV, PICC, PICDEM, PICDEM.net, rfPIC, Select
Mode and Total Endurance are trademarks of Microchip
Technology Incorporated in the U.S.A.
Serialized Quick Term Programming (SQTP) is a service mark
of Microchip Technology Incorporated in the U.S.A.
All other trademarks mentioned herein are property of their
respective companies.
© 2002, Microchip Technology Incorporated, Printed in the
U.S.A., All Rights Reserved.
Printed on recycled paper.
Microchip received QS-9000 quality system
certification for its worldwide headquarters,
design and wafer fabrication facilities in
Chandler and Tempe, Arizona in July 1999. The
Company’s quality system processes and
procedures are QS-9000 compliant for its
PICmicro® 8-bit MCUs, KEELOQ® code hopping
devices, Serial EEPROMs and microperipheral
products. In addition, Microchip’s quality
system for the design and manufacture of
development systems is ISO 9001 certified.
DS30221B - page ii
2002 Microchip Technology Inc.
PIC16F872
M
28-Pin, 8-Bit CMOS FLASH Microcontroller
with 10-bit A/D
High Performance RISC CPU:
Pin Diagram
DIP, SOIC, SSOP
• Only 35 single word instructions to learn
• All single cycle instructions except for program
branches, which are two-cycle
1
2
3
4
5
6
7
8
9
28
27
26
25
24
23
22
21
20
19
18
17
16
15
RB7/PGD
RB6/PGC
RB5
RB4
RB3/PGM
RB2
RB1
RB0/INT
VDD
MCLR/VPP
RA0/AN0
RA1/AN1
• Operating speed: DC - 20 MHz clock input
DC - 200 ns instruction cycle
RA2/AN2/VREF-
RA3/AN3/VREF+
RA4/T0CKI
• 2K x 14 words of FLASH Program Memory
• 128 bytes of Data Memory (RAM)
RA5/AN4/SS
VSS
• 64 bytes of EEPROM Data Memory
• Pinout compatible to the PIC16C72A
• Interrupt capability (up to 10 sources)
• Eight level deep hardware stack
OSC1/CLKIN
OSC2/CLKOUT
RC0/T1OSO/T1CKI
RC1/T1OSI/CCP2
RC2/CCP1
VSS
10
11
RC7/RX/DT
RC6/TX/CK
RC5/SDO
RC4/SDI/SDA
12
13
14
• Direct, Indirect and Relative Addressing modes
RC3/SCK/SCL
Peripheral Features:
• High Sink/Source Current: 25 mA
• Timer0: 8-bit timer/counter with 8-bit prescaler
Special Microcontroller Features:
• Timer1: 16-bit timer/counter with prescaler,
can be incremented during SLEEP via external
crystal/clock
• Power-on Reset (POR), Power-up Timer (PWRT)
and Oscillator Start-up Timer (OST)
• Timer2: 8-bit timer/counter with 8-bit period
• Watchdog Timer (WDT) with its own on-chip RC
register, prescaler and postscaler
oscillator for reliable operation
• One Capture, Compare, PWM module
- Capture is 16-bit, max. resolution is 12.5 ns
- Compare is 16-bit, max. resolution is 200 ns
- PWM max. resolution is 10-bit
• Programmable code protection
• Power saving SLEEP mode
• Selectable oscillator options
• In-Circuit Serial Programming (ICSP) via two
pins
• 10-bit, 5-channel Analog-to-Digital converter (A/D)
• Single 5V In-Circuit Serial Programming capability
• In-Circuit Debugging via two pins
• Synchronous Serial Port (SSP) with SPI (Master
mode) and I2C (Master/Slave)
• Brown-out detection circuitry for
Brown-out Reset (BOR)
• Processor read/write access to program memory
CMOS Technology:
• Low power, high speed CMOS FLASH/EEPROM
technology
• Wide operating voltage range: 2.0V to 5.5V
• Fully static design
• Commercial, Industrial and Extended temperature
ranges
• Low power consumption:
- < 2 mA typical @ 5V, 4 MHz
- 20 µA typical @ 3V, 32 kHz
- < 1 µA typical standby current
2002 Microchip Technology Inc.
DS30221B-page 1
PIC16F872
Table of Contents
1.0 Device Overview......................................................................................................................................................................... 3
2.0 Memory Organization.................................................................................................................................................................. 7
3.0 Data EEPROM and FLASH Program Memory ......................................................................................................................... 23
4.0 I/O Ports.................................................................................................................................................................................... 29
5.0 Timer0 Module.......................................................................................................................................................................... 35
6.0 Timer1 Module.......................................................................................................................................................................... 39
7.0 Timer2 Module.......................................................................................................................................................................... 43
8.0 Capture/Compare/PWM Module............................................................................................................................................... 45
9.0 Master Synchronous Serial Port (MSSP) Module..................................................................................................................... 51
10.0 Analog-to-Digital Converter (A/D) Module ................................................................................................................................ 79
11.0 Special Features of the CPU .................................................................................................................................................... 87
12.0 Instruction Set Summary......................................................................................................................................................... 103
13.0 Development Support ............................................................................................................................................................. 111
14.0 Electrical Characteristics......................................................................................................................................................... 117
15.0 DC and AC Characteristics Graphs and Tables ..................................................................................................................... 139
16.0 Packaging Information ............................................................................................................................................................ 151
Appendix A: Revision History ........................................................................................................................................................... 155
Appendix B: Conversion Considerations........................................................................................................................................... 155
Index ................................................................................................................................................................................................. 157
On-Line Support................................................................................................................................................................................ 163
Reader Response ............................................................................................................................................................................. 164
PIC16F872 Product Identification System ........................................................................................................................................ 165
TO OUR VALUED CUSTOMERS
It is our intention to provide our valued customers with the best documentation possible to ensure successful use of your Microchip
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Most Current Data Sheet
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You can determine the version of a data sheet by examining its literature number found on the bottom outside corner of any page.
The last character of the literature number is the version number, (e.g., DS30000A is version A of document DS30000).
Errata
An errata sheet, describing minor operational differences from the data sheet and recommended workarounds, may exist for current
devices. As device/documentation issues become known to us, we will publish an errata sheet. The errata will specify the revision
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To determine if an errata sheet exists for a particular device, please check with one of the following:
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DS30221B-page 2
2002 Microchip Technology Inc.
PIC16F872
document to this data sheet, and is highly recom-
mended reading for a better understanding of the
device architecture and operation of the peripheral
modules.
1.0
DEVICE OVERVIEW
This document contains device specific information
about the PIC16F872 microcontroller. Additional infor-
mation may be found in the PICmicro™ Mid-Range
Reference Manual (DS33023), which may be obtained
from your local Microchip Sales Representative or
downloaded from the Microchip website. The Refer-
ence Manual should be considered a complementary
The block diagram of the PIC16F872 architecture is
shown in Figure 1-1. A pinout description is provided in
Table 1-2.
TABLE 1-1:
KEY FEATURES OF THE PIC16F872
Operating Frequency
RESETS (and Delays)
FLASH Program Memory (14-bit words)
Data Memory (bytes)
EEPROM Data Memory (bytes)
Interrupts
DC - 20 MHz
POR, BOR (PWRT, OST)
2K
128
64
10
Ports A, B, C
3
I/O Ports
Timers
Capture/Compare/PWM module
Serial Communications
10-bit Analog-to-Digital Module
Instruction Set
1
MSSP
5 input channels
35 Instructions
Packaging
28-lead PDIP
28-lead SOIC
28-lead SSOP
2002 Microchip Technology Inc.
DS30221B-page 3
PIC16F872
FIGURE 1-1:
PIC16F872 BLOCK DIAGRAM
13
8
PORTA
Data Bus
Program Counter
RA0/AN0
RA1/AN1
RA2/AN2/VREF-
RA3/AN3/VREF+
RA4/T0CKI
FLASH
Program
Memory
RAM
File
Registers
8 Level Stack
(13-bit)
RA5/AN4/SS
Program
Bus
14
RAM Addr (1)
9
PORTB
Addr MUX
Instruction reg
RB0/INT
RB1
RB2
Indirect
Addr
7
Direct Addr
8
RB3/PGM
RB4
FSR reg
RB5
RB6/PGC
RB7/PGD
STATUS reg
8
3
MUX
Power-up
Timer
PORTC
RC0/T1OSO/T1CKI
RC1/T1OSI/CCP2
RC2/CCP1
RC3/SCK/SCL
RC4/SDI/SDA
RC5/SDO
RC6
Oscillator
Instruction
Decode &
Control
Start-up Timer
ALU
Power-on
Reset
8
Watchdog
Timer
Timing
Generation
W reg
Brown-out
Reset
OSC1/CLKIN
OSC2/CLKOUT
RC7
In-Circuit
Debugger
Low Voltage
Programming
MCLR VDD, VSS
Timer1
Timer0
Timer2
Synchronous
Serial Port
Data EEPROM
CCP
10-bit A/D
Note 1:
Higher order bits are from the STATUS register.
DS30221B-page 4
2002 Microchip Technology Inc.
PIC16F872
TABLE 1-2:
Pin Name
PIC16F872 PINOUT DESCRIPTION
I/O/P
Type
Buffer
Type
Pin#
Description
OSC1/CLKI
OSC1
9
I
ST/CMOS Oscillator crystal or external clock input.
Oscillator crystal input or external clock source input. ST
buffer when configured in RC mode. Otherwise CMOS.
External clock source input. Always associated with pin
function OSC1 (see OSC2/CLKO pin).
CLKI
OSC2/CLKO
OSC2
10
O
—
Oscillator crystal or clock output.
Oscillator crystal output.
Connects to crystal or resonator in Crystal Oscillator
mode.
CLKO
In RC mode, OSC2 pin outputs CLKO, which has 1/4 the
frequency of OSC1 and denotes the instruction cycle rate.
MCLR/VPP
MCLR
1
I/P
ST
Master Clear (input) or programming voltage (output).
Master Clear (Reset) input. This pin is an active low
RESET to the device.
VPP
Programming voltage input.
PORTA is a bi-directional I/O port.
RA0/AN0
RA0
2
3
4
I/O
I/O
I/O
TTL
TTL
TTL
Digital I/O.
Analog input 0.
AN0
RA1/AN1
RA1
Digital I/O.
Analog input 1.
AN1
RA2/AN2/VREF-
RA2
Digital I/O.
AN2
Analog input 2.
VREF-
Negative analog reference voltage.
RA3/AN3/VREF+
RA3
5
I/O
TTL
Digital I/O.
AN3
Analog input 3.
VREF+
Positive analog reference voltage.
RA4/T0CKI
RA4
6
7
I/O
I/O
ST
Digital I/O; open drain when configured as output.
Timer0 clock input.
T0CKI
RA5/SS/AN4
RA5
TTL
Digital I/O.
SS
AN4
Slave Select for the Synchronous Serial Port.
Analog input 4.
Legend: I = input
O = output
I/O = input/output
P = power
— = Not used
TTL = TTL input
ST = Schmitt Trigger input
Note 1: This buffer is a Schmitt Trigger input when configured as the external interrupt.
2: This buffer is a Schmitt Trigger input when used in Serial Programming mode.
2002 Microchip Technology Inc.
DS30221B-page 5
PIC16F872
TABLE 1-2:
PIC16F872 PINOUT DESCRIPTION (CONTINUED)
I/O/P
Type
Buffer
Type
Pin Name
Pin#
Description
PORTB is a bi-directional I/O port. PORTB can be software
programmed for internal weak pull-up on all inputs.
RB0/INT
RB0
21
I/O
TTL/ST(1)
Digital I/O.
INT
External interrupt pin.
RB1
RB2
22
23
24
I/O
I/O
I/O
TTL
TTL
TTL
Digital I/O.
Digital I/O.
RB3/PGM
RB3
Digital I/O.
PGM
Low voltage ICSP programming enable pin.
RB4
RB5
25
26
27
I/O
I/O
I/O
TTL
TTL
TTL/ST(2)
Digital I/O.
Digital I/O.
RB6/PGC
RB6
Digital I/O.
PGC
In-Circuit Debugger and ICSP programming clock.
RB7/PGD
RB7
28
11
I/O
I/O
TTL/ST(2)
Digital I/O.
PGD
In-Circuit Debugger and ICSP programming data.
PORTC is a bi-directional I/O port.
RC0/T1OSO/T1CKI
RC0
ST
Digital I/O.
T1OSO
T1CKI
Timer1 oscillator output.
Timer1 clock input.
RC1/T1OSI
RC1
12
13
14
I/O
I/O
I/O
ST
ST
ST
Digital I/O.
Timer1 oscillator input.
T1OSI
RC2/CCP1
RC2
Digital I/O.
CCP1
Capture1 input/Compare1 output/PWM1 output.
RC3/SCK/SCL
RC3
Digital I/O.
SCK
SCL
Synchronous serial clock input/output for SPI mode.
Synchronous serial clock input/output for I2C mode.
RC4/SDI/SDA
RC4
15
16
I/O
I/O
ST
ST
Digital I/O.
SDI
SDA
SPI Data In pin (SPI mode).
SPI Data I/O pin (I2C mode).
RC5/SDO
RC5
Digital I/O.
SDO
SPI Data Out pin (SPI mode).
RC6
17
18
I/O
ST
ST
—
Digital I/O.
RC7
I/O
Digital I/O.
VSS
8, 19
20
P
Ground reference for logic and I/O pins.
Positive supply for logic and I/O pins.
VDD
P
—
Legend: I = input
O = output
I/O = input/output
P = power
— = Not used
TTL = TTL input
ST = Schmitt Trigger input
Note 1: This buffer is a Schmitt Trigger input when configured as the external interrupt.
2: This buffer is a Schmitt Trigger input when used in Serial Programming mode.
DS30221B-page 6
2002 Microchip Technology Inc.
PIC16F872
2.2
Data Memory Organization
2.0
MEMORY ORGANIZATION
The data memory is partitioned into multiple banks
which contain the General Purpose Registers and the
Special Function Registers. Bits RP1 (STATUS<6>)
and RP0 (STATUS<5>) are the bank select bits.
There are three memory blocks in the PIC16F872. The
Program Memory and Data Memory have separate
buses so that concurrent access can occur. Data mem-
ory is covered in this section; the EEPROM data mem-
ory and FLASH program memory blocks are detailed in
Section 3.0.
RP1:RP0
Bank
00
01
10
11
0
1
2
3
Additional information on device memory may be found
in the PICmicro Mid-Range Reference Manual
(DS33023).
2.1
Program Memory Organization
Each bank extends up to 7Fh (128 bytes). The lower
locations of each bank are reserved for the Special
Function Registers. Above the Special Function Regis-
ters are General Purpose Registers, implemented as
static RAM. All implemented banks contain Special
Function Registers. Some frequently used Special
Function Registers from one bank may be mirrored in
another bank for code reduction and quicker access.
The PIC16F872 has a 13-bit program counter capable
of addressing an 8K word x 14 bit program memory
space. The PIC16F872 device actually has 2K words of
FLASH program memory. Accessing a location above
the physically implemented address will cause a wrap-
around.
The RESET vector is at 0000h and the interrupt vector
is at 0004h.
Note: EEPROM Data Memory description can be
found in Section 4.0 of this data sheet.
FIGURE 2-1:
PIC16F872 PROGRAM
MEMORY MAP AND
STACK
2.2.1
GENERAL PURPOSE REGISTER
FILE
PC<12:0>
13
The register file can be accessed either directly, or indi-
rectly through the File Select Register (FSR).
CALL, RETURN
RETFIE, RETLW
Stack Level 1
Stack Level 2
Stack Level 8
0000h
Reset Vector
Interrupt Vector
Page 0
0004h
0005h
On-Chip
Program
Memory
07FFh
1FFFh
2002 Microchip Technology Inc.
DS30221B-page 7
PIC16F872
FIGURE 2-2:
PIC16F872 REGISTER FILE MAP
File
Address
File
Address
File
Address
File
Address
Indirect addr.(*)
Indirect addr.(*)
OPTION_REG
PCL
Indirect addr.(*)
Indirect addr.(*)
OPTION_REG
100h
101h
102h
103h
104h
105h
106h
107h
108h
109h
10Ah
10Bh
10Ch
10Dh
10Eh
10Fh
110h
00h
01h
02h
03h
04h
05h
06h
07h
08h
09h
0Ah
0Bh
0Ch
0Dh
0Eh
0Fh
10h
11h
12h
13h
14h
15h
16h
17h
18h
19h
1Ah
1Bh
1Ch
1Dh
1Eh
1Fh
20h
180h
181h
182h
183h
184h
185h
186h
187h
188h
189h
18Ah
18Bh
18Ch
18Dh
18Eh
18Fh
190h
80h
81h
82h
83h
84h
85h
86h
87h
88h
89h
8Ah
8Bh
8Ch
8Dh
8Eh
8Fh
90h
91h
92h
93h
94h
95h
96h
97h
98h
99h
9Ah
9Bh
9Ch
9Dh
9Eh
9Fh
TMR0
PCL
TMR0
PCL
PCL
STATUS
FSR
STATUS
FSR
STATUS
FSR
STATUS
FSR
PORTA
PORTB
PORTC
TRISA
TRISB
TRISC
TRISB
PORTB
PCLATH
INTCON
EEDATA
EEADR
PCLATH
INTCON
PIR1
PCLATH
INTCON
EECON1
EECON2
Reserved(1)
Reserved(1)
PCLATH
INTCON
PIE1
PIR2
PIE2
TMR1L
TMR1H
T1CON
TMR2
EEDATH
EEADRH
PCON
SSPCON2
PR2
T2CON
SSPBUF
SSPCON
CCPR1L
CCPR1H
CCP1CON
SSPADD
SSPSTAT
ADRESL
ADCON1
ADRESH
ADCON0
1A0h
120h
A0h
General
Purpose
Register
accesses
A0h - BFh
accesses
20h-7Fh
General
Purpose
Register
32 Bytes
1BFh
1C0h
BFh
C0h
96 Bytes
16Fh
170h
1EFh
1F0h
EFh
F0h
accesses
70h-7Fh
accesses
70h-7Fh
accesses
70h-7Fh
17Fh
1FFh
7Fh
FFh
Bank 3
Bank 1
Bank 2
Bank 0
Unimplemented data memory locations, read as ’0’.
* Not a physical register.
Note 1: These registers are reserved; maintain these registers clear.
DS30221B-page 8
2002 Microchip Technology Inc.
PIC16F872
The Special Function Registers can be classified into
two sets: core (CPU) and peripheral. Those registers
associated with the core functions are described in
detail in this section. Those related to the operation of
the peripheral features are described in detail in the
peripheral feature section.
2.2.2
SPECIAL FUNCTION REGISTERS
The Special Function Registers are registers used by
the CPU and peripheral modules for controlling the
desired operation of the device. These registers are
implemented as static RAM. A list of these registers is
given in Table 2-1.
TABLE 2-1:
SPECIAL FUNCTION REGISTER SUMMARY
Value on: Details
Address
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
POR,
BOR
on
page:
Bank 0
(2)
00h
INDF
Addressing this location uses contents of FSR to address data memory
(not a physical register)
0000 0000 21, 93
01h
02h
03h
04h
05h
06h
07h
08h
09h
TMR0
PCL
Timer0 Module Register
xxxx xxxx 35, 93
0000 0000 20, 93
0001 1xxx 12, 93
xxxx xxxx 21, 93
--0x 0000 29, 93
xxxx xxxx 31, 93
xxxx xxxx 33, 93
(2)
(2)
(2)
Program Counter (PC) Least Significant Byte
STATUS
FSR
IRP
Indirect Data Memory Address Pointer
PORTA Data Latch when written: PORTA pins when read
RP1
RP0
TO
PD
Z
DC
C
PORTA
PORTB
PORTC
—
—
—
PORTB Data Latch when written: PORTB pins when read
PORTC Data Latch when written: PORTC pins when read
Unimplemented
—
—
—
—
—
Unimplemented
(1,2)
0Ah
0Bh
PCLATH
INTCON
PIR1
—
GIE
(3)
—
—
TMR0IE
(3)
Write Buffer for the upper 5 bits of the Program Counter ---0 0000 20, 93
(2)
PEIE
ADIF
(3)
INTE
(3)
RBIE
SSPIF
BCLIF
TMR0IF
INTF
RBIF
0000 000x 14, 93
0Ch
0Dh
0Eh
0Fh
10h
11h
12h
13h
14h
15h
16h
17h
18h
19h
1Ah
1Bh
1Ch
1Dh
1Eh
1Fh
CCP1IF TMR2IF TMR1IF r0rr 0000 16, 93
PIR2
—
—
EEIF
—
—
(3)
-r-0 0--r 18, 93
xxxx xxxx 40, 94
xxxx xxxx 40, 94
TMR1L
TMR1H
T1CON
TMR2
T2CON
SSPBUF
SSPCON
CCPR1L
CCPR1H
CCP1CON
—
Holding Register for the Least Significant Byte of the 16-bit TMR1 Register
Holding Register for the Most Significant Byte of the 16-bit TMR1 Register
—
—
T1CKPS1 T1CKPS0 T1OSCEN T1SYNC TMR1CS TMR1ON --00 0000 39, 94
0000 0000 43, 94
Timer2 Module Register
—
TOUTPS3 TOUTPS2 TOUTPS1 TOUTPS0 TMR2ON T2CKPS1 T2CKPS0 -000 0000 43, 94
Synchronous Serial Port Receive Buffer/Transmit Register
WCOL SSPOV SSPEN CKP SSPM3
xxxx xxxx 55, 94
SSPM0 0000 0000 53, 94
xxxx xxxx 45, 94
SSPM2
SSPM1
Capture/Compare/PWM Register1 (LSB)
Capture/Compare/PWM Register1 (MSB)
xxxx xxxx 45, 94
—
—
CCP1X
CCP1Y
CCP1M3 CCP1M2 CCP1M1 CCP1M0 --00 0000 45, 94
Unimplemented
Unimplemented
Unimplemented
Unimplemented
Unimplemented
Unimplemented
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
ADRESH
ADCON0
A/D Result Register High Byte
ADCS1 ADCS0 CHS2
xxxx xxxx 84, 94
CHS1
CHS0
GO/
DONE
—
ADON
0000 00-0 79, 94
Legend: x= unknown, u= unchanged, q= value depends on condition, - = unimplemented, read as '0', r= reserved.
Shaded locations are unimplemented, read as ‘0’.
Note 1: The upper byte of the program counter is not directly accessible. PCLATH is a holding register for the PC<12:8> whose contents are
transferred to the upper byte of the program counter.
2: These registers can be addressed from any bank.
3: These bits are reserved; always maintain these bits clear.
2002 Microchip Technology Inc.
DS30221B-page 9
PIC16F872
TABLE 2-1:
SPECIAL FUNCTION REGISTER SUMMARY (CONTINUED)
Value on: Details
Address
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
POR,
BOR
on
page:
Bank 1
(2)
80h
INDF
Addressing this location uses contents of FSR to address data memory
(not a physical register)
0000 0000 21, 93
81h
82h
83h
84h
85h
86h
87h
88h
89h
OPTION_REG RBPU
INTEDG
Program Counter (PC) Least Significant Byte
IRP RP1 RP0 TO
Indirect data memory address pointer
PORTA Data Direction Register
T0CS
T0SE
PSA
PS2
PS1
DC
PS0
C
1111 1111 13, 94
0000 0000 20, 93
0001 1xxx 12, 93
xxxx xxxx 21, 93
--11 1111 29, 94
1111 1111 31, 94
1111 1111 33, 94
(2)
(2)
(2)
PCL
STATUS
FSR
PD
Z
TRISA
TRISB
TRISC
—
—
—
PORTB Data Direction Register
PORTC Data Direction Register
Unimplemented
—
—
—
—
—
Unimplemented
(1,2)
8Ah
8Bh
PCLATH
INTCON
PIE1
—
GIE
(3)
—
—
PEIE
ADIE
(3)
—
TMR0IE
(3)
Write Buffer for the upper 5 bits of the Program Counter ---0 0000 20, 93
(2)
INTE
(3)
RBIE
SSPIE
BCLIE
—
TMR0IF
INTF
RBIF
0000 000x 14, 93
8Ch
8Dh
8Eh
8Fh
90h
91h
92h
93h
CCP1IE TMR2IE TMR1IE r0rr 0000 15, 94
PIE2
—
EEIE
—
—
—
—
(3)
-r-0 0--r 17, 94
---- --qq 19, 94
PCON
—
—
—
—
POR
BOR
Unimplemented
Unimplemented
—
—
—
—
—
SSPCON2
PR2
GCEN ACKSTAT ACKDT
ACKEN
RCEN
PEN
R/W
RSEN
UA
SEN
BF
0000 0000 54, 94
1111 1111 43, 94
0000 0000 58, 94
Timer2 Period Register
2
SSPADD
Synchronous Serial Port (I C mode) Address Register
94h
95h
96h
97h
95h
95h
9Ah
9Bh
9Ch
9Dh
9Eh
9Fh
SSPSTAT
SMP
CKE
D/A
P
S
0000 0000 52, 94
—
Unimplemented
Unimplemented
Unimplemented
Unimplemented
Unimplemented
Unimplemented
Unimplemented
Unimplemented
Unimplemented
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
ADRESL
ADCON1
A/D Result Register Low Byte
ADFM
xxxx xxxx 84, 94
PCFG0 0---0000 80, 94
—
—
—
PCFG3
PCFG2
PCFG1
Legend: x= unknown, u= unchanged, q= value depends on condition, - = unimplemented, read as '0', r= reserved.
Shaded locations are unimplemented, read as ‘0’.
Note 1: The upper byte of the program counter is not directly accessible. PCLATH is a holding register for the PC<12:8> whose contents are
transferred to the upper byte of the program counter.
2: These registers can be addressed from any bank.
3: These bits are reserved; always maintain these bits clear.
DS30221B-page 10
2002 Microchip Technology Inc.
PIC16F872
TABLE 2-1:
SPECIAL FUNCTION REGISTER SUMMARY (CONTINUED)
Value on: Details
Address
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
POR,
BOR
on
page:
Bank 2
(2)
100h
INDF
Addressing this location uses contents of FSR to address data memory
(not a physical register)
0000 0000 21, 93
101h
102h
103h
104h
105h
106h
107h
108h
109h
TMR0
PCL
Timer0 Module Register
xxxx xxxx 35, 93
0000 0000 20, 93
0001 1xxx 12, 93
xxxx xxxx 21, 93
(2)
(2)
(2)
Program Counter (PC) Least Significant Byte
STATUS
FSR
IRP
RP1
RP0
TO
PD
Z
DC
C
Indirect Data Memory Address Pointer
Unimplemented
—
—
—
PORTB
—
PORTB Data Latch when written: PORTB pins when read
xxxx xxxx 31, 93
Unimplemented
Unimplemented
Unimplemented
—
—
—
—
—
—
—
—
(1,2)
10Ah
10Bh
PCLATH
INTCON
EEDATA
EEADR
EEDATH
EEADRH
—
—
—
Write Buffer for the upper 5 bits of the Program Counter ---0 0000 20, 93
(2)
GIE
PEIE
TMR0IE
INTE
RBIE
TMR0IF
INTF
RBIF
0000 000x 14, 93
xxxx xxxx 23, 94
xxxx xxxx 23, 94
xxxx xxxx 23, 94
xxxx xxxx 23, 94
10Ch
10Dh
10Eh
10Fh
EEPROM Data Register Low Byte
EEPROM Address Register Low Byte
—
—
—
—
EEPROM Data Register High Byte
EEPROM Address Register High Byte
—
Bank 3
(2)
180h
INDF
Addressing this location uses contents of FSR to address data memory
(not a physical register)
0000 0000 21, 93
181h
182h
183h
184h
185h
186h
187h
188h
189h
OPTION_REG RBPU
INTEDG
Program Counter (PC) Least Significant Byte
IRP RP1 RP0 TO
T0CS
T0SE
PSA
PS2
PS1
DC
PS0
C
1111 1111 13, 94
0000 0000 20, 93
0001 1xxx 12, 93
xxxx xxxx 21, 93
(2)
(2)
(2)
PCL
STATUS
FSR
PD
Z
Indirect Data Memory Address Pointer
Unimplemented
—
—
—
TRISB
—
PORTB Data Direction Register
Unimplemented
1111 1111 31, 94
—
—
—
—
—
—
—
Unimplemented
—
Unimplemented
(1,2)
18Ah
18Bh
PCLATH
INTCON
EECON1
EECON2
—
—
—
PEIE
—
—
TMR0IE
—
Write Buffer for the upper 5 bits of the Program Counter ---0 0000 20, 93
(2)
GIE
INTE
RBIE
TMR0IF
WREN
INTF
WR
RBIF
RD
0000 000x 14, 93
x--- x000 24, 94
---- ---- 23, 94
18Ch
18Dh
18Eh
18Fh
EEPGD
—
WRERR
EEPROM Control Register2 (not a physical register)
Reserved; maintain clear
0000 0000
0000 0000
—
—
—
Reserved; maintain clear
Legend: x= unknown, u= unchanged, q= value depends on condition, - = unimplemented, read as '0', r= reserved.
Shaded locations are unimplemented, read as ‘0’.
Note 1: The upper byte of the program counter is not directly accessible. PCLATH is a holding register for the PC<12:8> whose contents are
transferred to the upper byte of the program counter.
2: These registers can be addressed from any bank.
3: These bits are reserved; always maintain these bits clear.
2002 Microchip Technology Inc.
DS30221B-page 11
PIC16F872
For example, CLRF STATUSwill clear the upper three
bits and set the Z bit. This leaves the STATUS register
as 000u u1uu(where u= unchanged).
2.2.2.1
STATUS Register
The STATUS register contains the arithmetic status of
the ALU, the RESET status and the bank select bits for
data memory.
It is recommended, therefore, that only BCF, BSF,
SWAPF and MOVWF instructions are used to alter the
STATUS register, because these instructions do not
affect the Z, C or DC bits from the STATUS register. For
other instructions not affecting any status bits, see the
“Instruction Set Summary."
The STATUS register can be the destination for any
instruction, as with any other register. If the STATUS
register is the destination for an instruction that affects
the Z, DC or C bits, then the write to these three bits is
disabled. These bits are set or cleared according to the
device logic. Furthermore, the TO and PD bits are not
writable, therefore, the result of an instruction with the
STATUS register as destination may be different than
intended.
Note: The C and DC bits operate as a borrow
and digit borrow bit, respectively, in sub-
traction. See the SUBLW and SUBWF
instructions for examples.
REGISTER 2-1:
STATUS REGISTER (ADDRESS: 03h, 83h, 103h, 183h)
R/W-0
IRP
R/W-0
RP1
R/W-0
RP0
R-1
TO
R-1
PD
R/W-x
Z
R/W-x
DC
R/W-x
C
bit 7
bit 0
bit 7
IRP: Register Bank Select bit (used for indirect addressing)
1= Bank 2, 3 (100h - 1FFh)
0= Bank 0, 1 (00h - FFh)
bit 6:5
RP1:RP0: Register Bank Select bits (used for direct addressing)
11= Bank 3 (180h - 1FFh)
10= Bank 2 (100h - 17Fh)
01= Bank 1 (80h - FFh)
00= Bank 0 (00h - 7Fh)
Each bank is 128 bytes
bit 4
bit 3
bit 2
bit 1
TO: Time-out bit
1= After power-up, CLRWDTinstruction, or SLEEPinstruction
0= A WDT time-out occurred
PD: Power-down bit
1= After power-up or by the CLRWDTinstruction
0= By execution of the SLEEPinstruction
Z: Zero bit
1= The result of an arithmetic or logic operation is zero
0= The result of an arithmetic or logic operation is not zero
DC: Digit carry/borrow bit (ADDWF, ADDLW,SUBLW,SUBWFinstructions)
(for borrow the polarity is reversed)
1= A carry-out from the 4th low order bit of the result occurred
0= No carry-out from the 4th low order bit of the result
bit 0
C: Carry/borrow bit (ADDWF, ADDLW,SUBLW,SUBWF instructions)
1= A carry-out from the Most Significant bit of the result occurred
0= No carry-out from the Most Significant bit of the result occurred
Note:
For borrow the polarity is reversed. A subtraction is executed by adding the two’s
complement of the second operand. For rotate (RRF, RLF) instructions, this bit is
loaded with either the high or low order bit of the source register.
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
’0’ = Bit is cleared x = Bit is unknown
- n = Value at POR
’1’ = Bit is set
DS30221B-page 12
2002 Microchip Technology Inc.
PIC16F872
2.2.2.2
OPTION_REG Register
Note: To achieve a 1:1 prescaler assignment for
the TMR0 register, assign the prescaler to
the Watchdog Timer.
The OPTION_REG Register is a readable and writable
register, which contains various control bits to configure
the TMR0 prescaler/WDT postscaler (single assign-
able register known also as the prescaler), the External
INT Interrupt, TMR0 and the weak pull-ups on PORTB.
REGISTER 2-2:
OPTION_REG REGISTER (ADDRESS 81h, 181h)
R/W-1
RBPU
R/W-1
R/W-1
T0CS
R/W-1
T0SE
R/W-1
PSA
R/W-1
PS2
R/W-1
PS1
R/W-1
PS0
INTEDG
bit 7
bit 0
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2-0
RBPU: PORTB Pull-up Enable bit
1= PORTB pull-ups are disabled
0= PORTB pull-ups are enabled by individual port latch values
INTEDG: Interrupt Edge Select bit
1= Interrupt on rising edge of RB0/INT pin
0= Interrupt on falling edge of RB0/INT pin
T0CS: TMR0 Clock Source Select bit
1= Transition on RA4/T0CKI pin
0= Internal instruction cycle clock (CLKOUT)
T0SE: TMR0 Source Edge Select bit
1= Increment on high-to-low transition on RA4/T0CKI pin
0= Increment on low-to-high transition on RA4/T0CKI pin
PSA: Prescaler Assignment bit
1= Prescaler is assigned to the WDT
0= Prescaler is assigned to the Timer0 module
PS2:PS0: Prescaler Rate Select bits
Bit Value TMR0 Rate WDT Rate
000
001
010
011
100
101
110
111
1 : 1
1 : 2
1 : 4
1 : 8
1 : 16
1 : 32
1 : 64
1 : 128
1 : 2
1 : 4
1 : 8
1 : 16
1 : 32
1 : 64
1 : 128
1 : 256
Legend:
R = Readable bit
W = Writable bit
’1’ = Bit is set
U = Unimplemented bit, read as ‘0’
- n = Value at POR
’0’ = Bit is cleared
x = Bit is unknown
Note: When using low voltage ICSP programming (LVP) and the pull-ups on PORTB are enabled, bit 3
in the TRISB register must be cleared to disable the pull-up on RB3 and ensure the proper oper-
ation of the device
2002 Microchip Technology Inc.
DS30221B-page 13
PIC16F872
2.2.2.3
INTCON Register
Note: Interrupt flag bits are set when an interrupt
condition occurs, regardless of the state of
its corresponding enable bit or the global
enable bit, GIE (INTCON<7>). User soft-
ware should ensure the appropriate inter-
rupt flag bits are clear prior to enabling an
interrupt.
The INTCON Register is a readable and writable regis-
ter, which contains various enable and flag bits for the
TMR0 register overflow, RB Port change and External
RB0/INT pin interrupts.
REGISTER 2-3:
INTCON REGISTER (ADDRESS: 0Bh, 8Bh, 10Bh, 18Bh)
R/W-0
GIE
R/W-0
PEIE
R/W-0
R/W-0
INTE
R/W-0
RBIE
R/W-0
R/W-0
INTF
R/W-x
RBIF
TMR0IE
TMR0IF
bit 7
bit 0
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
GIE: Global Interrupt Enable bit
1= Enables all unmasked interrupts
0= Disables all interrupts
PEIE: Peripheral Interrupt Enable bit
1= Enables all unmasked peripheral interrupts
0= Disables all peripheral interrupts
TMR0IE: TMR0 Overflow Interrupt Enable bit
1= Enables the TMR0 interrupt
0= Disables the TMR0 interrupt
INTE: RB0/INT External Interrupt Enable bit
1= Enables the RB0/INT external interrupt
0= Disables the RB0/INT external interrupt
RBIE: RB Port Change Interrupt Enable bit
1= Enables the RB port change interrupt
0= Disables the RB port change interrupt
TMR0IF: TMR0 Overflow Interrupt Flag bit
1= TMR0 register has overflowed (must be cleared in software)
0= TMR0 register did not overflow
INTF: RB0/INT External Interrupt Flag bit
1= The RB0/INT external interrupt occurred (must be cleared in software)
0= The RB0/INT external interrupt did not occur
RBIF: RB Port Change Interrupt Flag bit
1= At least one of the RB7:RB4 pins changed state; a mismatch condition will continue to set
the bit. Reading PORTB will end the mismatch condition and allow the bit to be cleared
(must be cleared in software).
0= None of the RB7:RB4 pins have changed state
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
’0’ = Bit is cleared x = Bit is unknown
- n = Value at POR
’1’ = Bit is set
DS30221B-page 14
2002 Microchip Technology Inc.
PIC16F872
2.2.2.4
PIE1 Register
Note: Bit PEIE (INTCON<6>) must be set to
enable any peripheral interrupt.
The PIE1 register contains the individual enable bits for
the peripheral interrupts.
REGISTER 2-4:
PIE1 REGISTER (ADDRESS: 8Ch)
R/W-0
reserved
bit 7
R/W-0
ADIE
R/W-0
R/W-0
R/W-0
SSPIE
R/W-0
R/W-0
R/W-0
TMR1IE
bit 0
reserved reserved
CCP1IE
TMR2IE
bit 7
bit 6
Reserved: Always maintain these bits clear
ADIE: A/D Converter Interrupt Enable bit
1= Enables the A/D converter interrupt
0= Disables the A/D converter interrupt
bit 5-4
bit 3
Reserved: Always maintain these bits clear
SSPIE: Synchronous Serial Port Interrupt Enable bit
1= Enables the SSP interrupt
0= Disables the SSP interrupt
bit 2
bit 1
bit 0
CCP1IE: CCP1 Interrupt Enable bit
1= Enables the CCP1 interrupt
0= Disables the CCP1 interrupt
TMR2IE: TMR2 to PR2 Match Interrupt Enable bit
1= Enables the TMR2 to PR2 match interrupt
0= Disables the TMR2 to PR2 match interrupt
TMR1IE: TMR1 Overflow Interrupt Enable bit
1= Enables the TMR1 overflow interrupt
0= Disables the TMR1 overflow interrupt
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
’0’ = Bit is cleared x = Bit is unknown
- n = Value at POR
’1’ = Bit is set
2002 Microchip Technology Inc.
DS30221B-page 15
PIC16F872
2.2.2.5
PIR1 Register
Note: Interrupt flag bits are set when an interrupt
condition occurs, regardless of the state of
its corresponding enable bit or the global
enable bit, GIE (INTCON<7>). User soft-
ware should ensure the appropriate inter-
rupt bits are clear prior to enabling an
interrupt.
The PIR1 register contains the individual flag bits for
the peripheral interrupts.
REGISTER 2-5:
PIR1 REGISTER (ADDRESS: 0Ch)
R/W-0
reserved
bit 7
R/W-0
ADIF
R/W-0
R/W-0
R/W-0
SSPIF
R/W-0
R/W-0
R/W-0
reserved reserved
CCP1IF
TMR2IF
TMR1IF
bit 0
bit 7
bit 6
Reserved: Always maintain these bits clear
ADIF: A/D Converter Interrupt Flag bit
1= An A/D conversion completed
0= The A/D conversion is not complete
bit 5-4
bit 3
Reserved: Always maintain these bits clear
SSPIF: Synchronous Serial Port (SSP) Interrupt Flag
1= The SSP interrupt condition has occurred, and must be cleared in software before returning
from the Interrupt Service Routine. The conditions that will set this bit are:
• SPI
- A transmission/reception has taken place
•
I2C Slave
- A transmission/reception has taken place
• I2C Master
- A transmission/reception has taken place
- The initiated START condition was completed by the SSP module
- The initiated STOP condition was completed by the SSP module
- The initiated Restart condition was completed by the SSP module
- The initiated Acknowledge condition was completed by the SSP module
- A START condition occurred while the SSP module was idle (multi-master system)
- A STOP condition occurred while the SSP module was idle (multi-master system)
0 = No SSP interrupt condition has occurred
bit 2
CCP1IF: CCP1 Interrupt Flag bit
Capture mode:
1= A TMR1 register capture occurred (must be cleared in software)
0= No TMR1 register capture occurred
Compare mode:
1= A TMR1 register compare match occurred (must be cleared in software)
0= No TMR1 register compare match occurred
PWM mode: Unused in this mode
bit 1
bit 0
TMR2IF: TMR2 to PR2 Match Interrupt Flag bit
1= TMR2 to PR2 match occurred (must be cleared in software)
0= No TMR2 to PR2 match occurred
TMR1IF: TMR1 Overflow Interrupt Flag bit
1= TMR1 register overflowed (must be cleared in software)
0= TMR1 register did not overflow
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
’0’ = Bit is cleared x = Bit is unknown
- n = Value at POR
’1’ = Bit is set
DS30221B-page 16
2002 Microchip Technology Inc.
PIC16F872
2.2.2.6
PIE2 Register
The PIE2 register contains the individual enable bits for
the CCP2 peripheral interrupt, the SSP bus collision
interrupt, and the EEPROM write operation interrupt.
REGISTER 2-6:
PIE2 REGISTER (ADDRESS: 8Dh)
U-0
R/W-0
U-0
R/W-0
EEIE
R/W-0
BCLIE
U-0
U-0
R/W-0
reserved
bit 0
—
reserved
—
—
—
bit 7
bit 7
bit 6
bit 5
bit 4
Unimplemented: Read as '0'
Reserved: Always maintain this bit clear
Unimplemented: Read as '0'
EEIE: EEPROM Write Operation Interrupt Enable bit
1= Enable EEPROM write interrupt
0= Disable EEPROM write interrupt
bit 3
BCLIE: Bus Collision Interrupt Enable bit
1= Enable bus collision interrupt
0= Disable bus collision interrupt
bit 2-1
bit 0
Unimplemented: Read as '0'
Reserved: Always maintain this bit clear
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
’0’ = Bit is cleared x = Bit is unknown
- n = Value at POR
’1’ = Bit is set
2002 Microchip Technology Inc.
DS30221B-page 17
PIC16F872
2.2.2.7
PIR2 Register
Note: Interrupt flag bits are set when an interrupt
condition occurs, regardless of the state of
its corresponding enable bit or the global
enable bit, GIE (INTCON<7>). User soft-
ware should ensure the appropriate inter-
rupt flag bits are clear prior to enabling an
interrupt.
The PIR2 register contains the flag bits for the CCP2
interrupt, the SSP bus collision interrupt and the
EEPROM write operation interrupt.
.
REGISTER 2-7:
PIR2 REGISTER (ADDRESS: 0Dh)
U-0
R/W-0
U-0
R/W-0
EEIF
R/W-0
BCLIF
U-0
U-0
R/W-0
reserved
bit 0
—
reserved
—
—
—
bit 7
bit 7
bit 6
bit 5
bit 4
Unimplemented: Read as '0'
Reserved: Always maintain this bit clear
Unimplemented: Read as '0'
EEIF: EEPROM Write Operation Interrupt Flag bit
1= The write operation completed (must be cleared in software)
0= The write operation is not complete or has not been started
bit 3
BCLIF: Bus Collision Interrupt Flag bit
1= A bus collision has occurred in the SSP, when configured for I2C Master mode
0= No bus collision has occurred
bit 2-1
bit 0
Unimplemented: Read as '0'
Reserved: Always maintain this bit clear
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
’0’ = Bit is cleared x = Bit is unknown
- n = Value at POR
’1’ = Bit is set
DS30221B-page 18
2002 Microchip Technology Inc.
PIC16F872
2.2.2.8
PCON Register
Note: BOR is unknown on POR. It must be set by
the user and checked on subsequent
RESETS to see if BOR is clear, indicating
a brown-out has occurred. The BOR status
bit is a don’t care and is not predictable if
the brown-out circuit is disabled (by clear-
ing the BODEN bit in the Configuration
Word).
The Power Control (PCON) Register contains flag bits
to allow differentiation between a Power-on Reset
(POR), a Brown-out Reset (BOR), a Watchdog Reset
(WDT) and an external MCLR Reset.
REGISTER 2-8:
PCON REGISTER (ADDRESS: 8Eh)
U-0
U-0
U-0
U-0
U-0
U-0
R/W-0
POR
R/W-1
BOR
—
—
—
—
—
—
bit 7
bit 0
bit 7-2
bit 1
Unimplemented: Read as '0'
POR: Power-on Reset Status bit
1= No Power-on Reset occurred
0= A Power-on Reset occurred (must be set in software after a Power-on Reset occurs)
bit 0
BOR: Brown-out Reset Status bit
1= No Brown-out Reset occurred
0= A Brown-out Reset occurred (must be set in software after a Brown-out Reset occurs)
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
’0’ = Bit is cleared x = Bit is unknown
- n = Value at POR
’1’ = Bit is set
2002 Microchip Technology Inc.
DS30221B-page 19
PIC16F872
2.3.2
STACK
2.3
PCL and PCLATH
The PIC16FXXX family has an 8-level deep x 13-bit
wide hardware stack. The stack space is not part of
either program or data space and the stack pointer is
not readable or writable. The PC is PUSHed onto the
stack when a CALLinstruction is executed or an inter-
rupt causes a branch. The stack is POPed in the event
of a RETURN, RETLWor a RETFIEinstruction execu-
tion. PCLATH is not affected by a PUSH or POP oper-
ation.
The program counter (PC) is 13-bits wide. The low byte
comes from the PCL register, which is a readable and
writable register. The upper bits (PC<12:8>) are not
readable, but are indirectly writable through the
PCLATH register. On any RESET, the upper bits of the
PC will be cleared. Figure 2-3 shows the two situations
for the loading of the PC. The upper example in the fig-
ure shows how the PC is loaded on a write to PCL
(PCLATH<4:0> → PCH). The lower example in the fig-
ure shows how the PC is loaded during a CALLor GOTO
instruction (PCLATH<4:3> → PCH).
The stack operates as a circular buffer. This means that
after the stack has been PUSHed eight times, the ninth
push overwrites the value that was stored from the first
push. The tenth push overwrites the second push (and
so on).
FIGURE 2-3:
LOADING OF PC IN
DIFFERENT SITUATIONS
Note 1: There are no status bits to indicate stack
PCH
PCL
overflow or stack underflow conditions.
12
8
7
0
Instruction with
2: There are no instructions/mnemonics
called PUSH or POP. These are actions
that occur from the execution of the
CALL, RETURN, RETLW and RETFIE
instructions, or the vectoring to an inter-
rupt address.
PCL as
Destination
PC
8
PCLATH<4:0>
PCLATH
5
ALU
PCH
12 11 10
PC
PCL
2.4
Program Memory Paging
8
7
0
GOTO,CALL
All PIC16FXXX devices are capable of addressing a
continuous 8K word block of program memory. The
CALL and GOTO instructions provide only 11 bits of
address to allow branching within any 2K program
memory page. When doing a CALLor GOTOinstruction,
the upper 2 bits of the address are provided by
PCLATH<4:3>. Since the PIC16F872 has only 2K
words of program memory or one page, additional code
is not required to ensure that the correct page is
selected before a CALL or GOTO instruction is exe-
cuted. The PCLATH<4:3> bits should always be main-
tained as zeros. If a return from a CALLinstruction (or
interrupt) is executed, the entire 13-bit PC is popped off
PCLATH<4:3>
PCLATH
11
2
Opcode <10:0>
2.3.1
COMPUTED GOTO
A computed GOTOis accomplished by adding an offset
to the program counter (ADDWF PCL). When doing a
table read using a computed GOTO method, care
should be exercised if the table location crosses a PCL
memory boundary (each 256 byte block). Refer to the
the
stack. Therefore,
manipulation of
the
Application Note, “Implementing
(AN556).
a Table Read"
PCLATH<4:3> bits are not required for the return
instructions (which POPs the address from the stack).
Note: The contents of the PCLATH register are
unchanged after a RETURN or RETFIE
instruction is executed. The user must
rewrite the contents of the PCLATH regis-
ter for any subsequent subroutine calls or
GOTOinstructions.
DS30221B-page 20
2002 Microchip Technology Inc.
PIC16F872
A simple program to clear RAM locations 20h-2Fh
using indirect addressing is shown in Example 2-1.
2.5
Indirect Addressing, INDF and
FSR Registers
The INDF register is not a physical register. Addressing
the INDF register will cause indirect addressing.
EXAMPLE 2-1:
INDIRECT ADDRESSING
MOVLW 0x20
MOVWF FSR
;initialize pointer
;to RAM
;clear INDF register
;inc pointer
;all done?
;no clear next
Indirect addressing is possible by using the INDF reg-
ister. Any instruction using the INDF register actually
accesses the register pointed to by the File Select Reg-
ister, FSR. Reading the INDF register itself indirectly
(FSR = ’0’), will read 00h. Writing to the INDF register
indirectly results in a no operation (although status bits
may be affected). An effective 9-bit address is obtained
by concatenating the 8-bit FSR register and the IRP bit
(STATUS<7>), as shown in Figure 2-4.
NEXT
CLRF INDF
INCF FSR,F
BTFSS FSR,4
GOTO NEXT
CONTINUE
:
;yes continue
FIGURE 2-4:
DIRECT/INDIRECT ADDRESSING
Direct Addressing
From Opcode
Indirect Addressing
7
RP1:RP0
6
0
0
IRP
FSR Register
Bank Select
Location Select
Bank Select
Location Select
00
01
80h
10
100h
11
00h
180h
Data
Memory
(1)
7Fh
Bank 0
FFh
Bank 1
17Fh
Bank 2
1FFh
Bank 3
Note 1: For register file map detail, see Figure 2-2.
2002 Microchip Technology Inc.
DS30221B-page 21
PIC16F872
NOTES:
DS30221B-page 22
2002 Microchip Technology Inc.
PIC16F872
The EEPROM Data memory allows byte read and write
operations without interfering with the normal operation
of the microcontroller. When interfacing to EEPROM
Data memory, the EEADR register holds the address to
be accessed. Depending on the operation, the EEDATA
register holds the data to be written or the data read at
the address in EEADR. The PIC16F872 has 64 bytes of
EEPROM Data memory and therefore, requires that the
two Most Significant bits of EEADR remain clear.
EEPROM Data memory on these devices wraps around
to 0 (i.e., 40h in the EEADR maps to 00h).
3.0
DATA EEPROM AND FLASH
PROGRAM MEMORY
The Data EEPROM and FLASH Program Memory are
readable and writable during normal operation over the
entire VDD range. These operations take place on a sin-
gle byte for Data EEPROM memory and a single word
for Program memory. A write operation causes an
erase-then-write operation to take place on the speci-
fied byte or word. A bulk erase operation may not be
issued from user code (which includes removing code
protection).
The FLASH Program memory allows non-intrusive
read access, but write operations cause the device to
stop executing instructions until the write completes.
When interfacing to the Program memory, the
EEADRH:EEADR registers pair forms a two-byte word
which holds the 13-bit address of the memory location
being accessed. The EEDATH:EEDATA register pair
holds the 14-bit data for writes or reflects the value of
program memory after a read operation. Just as in
EEPROM Data memory accesses, the value of the
EEADRH:EEADR registers must be within the valid
range of program memory, depending on the device
(0000h to 07FFh). Addresses outside of this range
wrap around to 0000h (i.e., 0800h maps to 0000h).
Access to program memory allows for checksum calcu-
lation. The values written to Program memory do not
need to be valid instructions. Therefore, numbers of up
to 14 bits can be stored in memory for use as calibra-
tion parameters, serial numbers, packed 7-bit ASCII,
etc. Executing a program memory location, containing
data that forms an invalid instruction, results in the exe-
cution of a NOPinstruction.
The EEPROM Data memory is rated for high erase/
write cycles (specification #D120). The FLASH Pro-
gram memory is rated much lower (specification
#D130) because EEPROM Data memory can be used
to store frequently updated values. An on-chip timer
controls the write time and it will vary with voltage and
temperature, as well as from chip to chip. Please refer
to the specifications for exact limits (specifications
#D122 and #D133).
3.1
EECON1 and EECON2 Registers
The EECON1 register is the control register for config-
uring and initiating the access. The EECON2 register is
not a physically implemented register, but is used
exclusively in the memory write sequence to prevent
inadvertent writes.
A byte or word write automatically erases the location
and writes the new value (erase before write). Writing
to EEPROM Data memory does not impact the opera-
tion of the device. Writing to Program memory will
cease the execution of instructions until the write is
complete. The program memory cannot be accessed
during the write. During the write operation, the oscilla-
tor continues to run, the peripherals continue to func-
tion and interrupt events will be detected and
essentially “queued” until the write is complete. When
the write completes, the next instruction in the pipeline
is executed and the branch to the interrupt vector will
take place if the interrupt is enabled and occurred dur-
ing the write.
There are many bits used to control the read and write
operations to EEPROM Data and FLASH Program
memory. The EEPGD bit determines if the access will
be a program or data memory access. When clear, any
subsequent operations will work on the EEPROM Data
memory. When set, all subsequent operations will
operate in the Program memory.
Read operations only use one additional bit, RD, which
initiates the read operation from the desired memory
location. Once this bit is set, the value of the desired
memory location will be available in the data registers.
This bit cannot be cleared by firmware. It is automati-
cally cleared at the end of the read operation. For
EEPROM Data memory reads, the data will be avail-
able in the EEDATA register in the very next instruction
cycle after the RD bit is set. For program memory
reads, the data will be loaded into the
EEDATH:EEDATA registers, following the second
instruction after the RD bit is set.
Read and write access to both memories take place
indirectly through a set of Special Function Registers
(SFR). The six SFRs used are:
• EEDATA
• EEDATH
• EEADR
• EEADRH
• EECON1
• EECON2
2002 Microchip Technology Inc.
DS30221B-page 23
PIC16F872
Write operations have two control bits, WR and WREN,
and two status bits, WRERR and EEIF. The WREN bit
is used to enable or disable the write operation. When
WREN is clear, the write operation will be disabled.
Therefore, the WREN bit must be set before executing
a write operation. The WR bit is used to initiate the write
operation. It also is automatically cleared at the end of
the write operation. The interrupt flag EEIF (located in
register PIR2) is used to determine when the memory
write completes. This flag must be cleared in software
before setting the WR bit. For EEPROM Data memory,
once the WREN bit and the WR bit have been set, the
desired memory address in EEADR will be erased fol-
lowed by a write of the data in EEDATA. This operation
takes place in parallel with the microcontroller continu-
ing to execute normally. When the write is complete,
the EEIF flag bit will be set. For program memory, once
the WREN bit and the WR bit have been set, the micro-
controller will cease to execute instructions. The
desired
memory
location
pointed
to
by
EEADRH:EEADR will be erased. Then the data value
in EEDATH:EEDATA will be programmed. When com-
plete, the EEIF flag bit will be set and the microcontrol-
ler will continue to execute code.
The WRERR bit is used to indicate when the device
has been RESET during a write operation. WRERR
should be cleared after Power-on Reset. Thereafter, it
should be checked on any other RESET. The WRERR
bit is set when a write operation is interrupted by a
MCLR Reset or a WDT Time-out Reset during normal
operation. In these situations, following a RESET, the
user should check the WRERR bit and rewrite the
memory location if set. The contents of the data regis-
ters, address registers and EEPGD bit are not affected
by either MCLR Reset or WDT Time-out Reset during
normal operation.
REGISTER 3-1:
EECON1 REGISTER (ADDRESS 18Ch)
R/W-x
U-0
U-0
U-0
R/W-x
R/W-0
WREN
R/S-0
WR
R/S-0
RD
EEPGD
—
—
—
WRERR
bit 7
bit 0
bit 7
EEPGD: Program/Data EEPROM Select bit
1= Accesses Program memory
0= Accesses data memory
(This bit cannot be changed while a read or write operation is in progress.)
bit 6-4
bit 3
Unimplemented: Read as '0'
WRERR: EEPROM Error Flag bit
1= A write operation is prematurely terminated
(any MCLR Reset or any WDT Reset during normal operation)
0= The write operation completed
bit 2
bit 1
WREN: EEPROM Write Enable bit
1= Allows write cycles
0= Inhibits write to the EEPROM
WR: Write Control bit
1= Initiates a write cycle (The bit is cleared by hardware once write is complete. The WR bit
can only be set (not cleared) in software.)
0= Write cycle to the EEPROM is complete
bit 0
RD: Read Control bit
1= Initiates an EEPROM read RD is cleared in hardware. The RD bit can only be set (not
cleared) in software.
0= Does not initiate an EEPROM read
Legend:
S = Settable bit
U = Unimplemented bit, read as ‘0’
’1’ = Bit is set ’0’ = Bit is cleared
R = Readable bit
W = Writable bit
- n = Value at POR
x = Bit is unknown
DS30221B-page 24
2002 Microchip Technology Inc.
PIC16F872
should be kept clear at all times, except when writing to
the EEPROM Data. The WR bit can only be set if the
WREN bit was set in a previous operation, i.e., they
both cannot be set in the same operation. The WREN
bit should then be cleared by firmware after the write.
Clearing the WREN bit before the write actually com-
pletes will not terminate the write in progress.
3.2
Reading the EEPROM Data
Memory
Reading EEPROM Data memory only requires that the
desired address to access be written to the EEADR
register and clear the EEPGD bit. After the RD bit is set,
data will be available in the EEDATA register on the
very next instruction cycle. EEDATA will hold this value
until another read operation is initiated or until it is writ-
ten by firmware.
Writes to EEPROM Data memory must also be pref-
aced with a special sequence of instructions that pre-
vent inadvertent write operations. This is a sequence of
five instructions that must be executed without interrup-
tion for each byte written.
The steps to reading the EEPROM Data Memory are:
1. Write the address to EEDATA. Make sure that
the address is not larger than the memory size
of the device.
The steps to write to program memory are:
1. Write the address to EEADR. Make sure that the
address is not larger than the memory size of
the device.
2. Clear the EEPGD bit to point to EEPROM Data
memory.
3. Set the RD bit to start the read operation.
4. Read the data from the EEDATA register.
2. Write the 8-bit data value to be programmed in
the EEDATA registers.
3. Clear the EEPGD bit to point to EEPROM Data
memory.
EXAMPLE 3-1:
EEPROM DATA READ
BSF
BCF
STATUS, RP1
STATUS, RP0
ADDR, W
;
;Bank 2
;Write address
4. Set the WREN bit to enable program operations.
5. Disable interrupts (if enabled).
MOVF
MOVWF EEADR
6. Execute the special five instruction sequence:
;to read from
BSF
BCF
BSF
BCF
MOVF
STATUS, RP0
EECON1, EEPGD ;Point to Data memory
EECON1, RD
STATUS, RP0
EEDATA, W
;Bank 3
• Write 55h to EECON2 in two steps (first to W,
then to EECON2)
;Start read operation
;Bank 2
;W = EEDATA
• Write AAh to EECON2 in two steps (first to
W, then to EECON2)
• Set the WR bit
7. Enable interrupts (if using interrupts).
8. Clear the WREN bit to disable program operations.
3.3
Writing to the EEPROM Data
Memory
9. At the completion of the write cycle, the WR bit
is cleared and the EEIF interrupt flag bit is set.
(EEIF must be cleared by firmware). Firmware
may check for EEIF to be set or WR to clear to
indicate end of program cycle.
There are many steps in writing to the EEPROM Data
memory. Both address and data values must be written
to the SFRs. The EEPGD bit must be cleared and the
WREN bit must be set to enable writes. The WREN bit
EXAMPLE 3-2:
EEPROM DATA WRITE
BSF
BCF
STATUS, RP1
STATUS, RP0
ADDR, W
EEADR
VALUE, W
;
;Bank 2
;Address to
;write to
;Data to
;write
;Bank 3
;Point to Data memory
;Enable writes
MOVF
MOVWF
MOVF
MOVWF
BSF
EEDATA
STATUS, RP0
EECON1, EEPGD
EECON1, WREN
BCF
BSF
;Only disable interrupts
;if already enabled,
;otherwise discard
;Write 55h to
;EECON2
;Write AAh to
BCF
INTCON, GIE
MOVLW
MOVWF
MOVLW
MOVWF
BSF
0x55
EECON2
0xAA
EECON2
EECON1, WR
;EECON2
;Start write operation
;Only enable interrupts
;if using interrupts,
;otherwise discard
;Disable writes
BSF
BCF
INTCON, GIE
EECON1, WREN
2002 Microchip Technology Inc.
DS30221B-page 25
PIC16F872
The steps to reading the FLASH Program Memory are:
3.4
Reading the FLASH Program
Memory
1. Write the address to EEADRH:EEADR. Make
sure that the address is not larger than the mem-
ory size of the device.
Reading FLASH Program memory is much like that of
EEPROM Data memory, only two NOP instructions
must be inserted after the RD bit is set. These two
instruction cycles that the NOPinstructions execute will
be used by the microcontroller to read the data out of
program memory and insert the value into the
EEDATH:EEDATA registers. Data will be available fol-
lowing the second NOP instruction. EEDATH and
EEDATA will hold their value until another read opera-
tion is initiated, or until they are written by firmware.
2. Set the EEPGD bit to point to FLASH Program
memory.
3. Set the RD bit to start the read operation.
4. Execute two NOPinstructions to allow the micro-
controller to read out of program memory.
5. Read the data from the EEDATH:EEDATA
registers.
EXAMPLE 3-3:
BSF
FLASH PROGRAM READ
STATUS, RP1
STATUS, RP0
ADDRL, W
;
BCF
;Bank 2
MOVF
MOVWF
MOVF
MOVWF
BSF
;Write the
;address bytes
EEADR
ADDRH,W
;for the desired
EEADRH
;address to read
STATUS, RP0
EECON1, EEPGD
EECON1, RD
;Bank 3
BSF
;Point to Program memory
BSF
;Start read operation
NOP
;Required two NOPs
NOP
;
BCF
STATUS, RP0
EEDATA, W
DATAL
;Bank 2
MOVF
MOVWF
MOVF
MOVWF
;DATAL = EEDATA
;
EEDATH,W
DATAH
;DATAH = EEDATH
;
clear at all times, except when writing to the FLASH
Program memory. The WR bit can only be set if the
WREN bit was set in a previous operation, i.e., they
both cannot be set in the same operation. The WREN
bit should then be cleared by firmware after the write.
Clearing the WREN bit before the write actually com-
pletes will not terminate the write in progress.
3.5
Writing to the FLASH Program
Memory
Writing to FLASH Program memory is unique in that the
microcontroller does not execute instructions while pro-
gramming is taking place. The oscillator continues to
run and all peripherals continue to operate and queue
interrupts, if enabled. Once the write operation com-
pletes (specification #D133), the processor begins exe-
cuting code from where it left off. The other important
difference when writing to FLASH Program memory is
that the WRT configuration bit, when clear, prevents
any writes to program memory (see Table 3-1).
Writes to program memory must also be prefaced with
a special sequence of instructions that prevent inad-
vertent write operations. This is a sequence of five
instructions that must be executed without interruption
for each byte written. These instructions must then be
followed by two NOPinstructions to allow the microcon-
troller to setup for the write operation. Once the write is
complete, the execution of instructions starts with the
instruction after the second NOP.
Just like EEPROM Data memory, there are many steps
in writing to the FLASH Program memory. Both
address and data values must be written to the SFRs.
The EEPGD bit must be set and the WREN bit must be
set to enable writes. The WREN bit should be kept
DS30221B-page 26
2002 Microchip Technology Inc.
PIC16F872
The steps to write to program memory are:
• Write AAh to EECON2 in two steps (first to W,
then to EECON2)
1. Write the address to EEADRH:EEADR. Make
sure that the address is not larger than the mem-
ory size of the device.
• Set the WR bit
7. Execute two NOPinstructions to allow the micro-
controller to setup for write operation.
2. Write the 14-bit data value to be programmed in
the EEDATH:EEDATA registers.
8. Enable interrupts (if using interrupts).
3. Set the EEPGD bit to point to FLASH Program
memory.
9. Clear the WREN bit to disable program
operations.
4. Set the WREN bit to enable program operations.
5. Disable interrupts (if enabled).
At the completion of the write cycle, the WR bit is
cleared and the EEIF interrupt flag bit is set. (EEIF
must be cleared by firmware). Since the microcontroller
does not execute instructions during the write cycle, the
firmware does not necessarily have to check either
EEIF or WR to determine if the write had finished.
6. Execute the special five instruction sequence:
• Write 55h to EECON2 in two steps (first to W,
then to EECON2)
EXAMPLE 3-4:
FLASH PROGRAM WRITE
BSF
BCF
STATUS, RP1
STATUS, RP0
ADDRL, W
EEADR
ADDRH, W
EEADRH
VALUEL, W
EEDATA
VALUEH, W
EEDATH
STATUS, RP0
EECON1, EEPGD
EECON1, WREN
;
;Bank 2
;Write address
;of desired
;program memory
;location
;Write value to
;program at
;desired memory
;location
;Bank 3
;Point to Program memory
;Enable writes
MOVF
MOVWF
MOVF
MOVWF
MOVF
MOVWF
MOVF
MOVWF
BSF
BSF
BSF
;Only disable interrupts
;if already enabled,
;otherwise discard
;Write 55h to
;EECON2
;Write AAh to
BCF
INTCON, GIE
MOVLW
MOVWF
MOVLW
MOVWF
BSF
0x55
EECON2
0xAA
EECON2
EECON1, WR
;EECON2
;Start write operation
;Two NOPs to allow micro
;to setup for write
;Only enable interrupts
;if using interrupts,
;otherwise discard
;Disable writes
NOP
NOP
BSF
BCF
INTCON, GIE
EECON1, WREN
3.6
Write Verify
3.7
Protection Against Spurious Writes
The PIC16F87X devices do not automatically verify the
value written during a write operation. Depending on
the application, good programming practice may dic-
tate that the value written to memory be verified against
the original value. This should be used in applications
where excessive writes can stress bits near the speci-
fied endurance limits.
There are conditions when the device may not want to
write to the EEPROM Data memory or FLASH program
memory. To protect against these spurious write condi-
tions various mechanisms have been built into the
device. On power-up, the WREN bit is cleared and the
Power-up Timer (if enabled) prevents writes.
The write initiate sequence and the WREN bit together
help prevent any accidental writes during brown-out,
power glitches or firmware malfunction.
2002 Microchip Technology Inc.
DS30221B-page 27
PIC16F872
ent effects on writing to program memory. Table 4-1
shows the effect of the code protect bits and the WRT
bit on program memory.
3.8
Operation While Code Protected
The PIC16F872 has two code protect mechanisms,
one bit for EEPROM Data memory and two bits for
FLASH Program memory. Data can be read and written
to the EEPROM Data memory regardless of the state
of the code protection bit, CPD. When code protection
is enabled, CPD cleared, external access via ICSP is
disabled regardless of the state of the program memory
code protect bits. This prevents the contents of
EEPROM Data memory from being read out of the
device.
Once code protection has been enabled for either
EEPROM Data memory or FLASH Program memory,
only a full erase of the entire device will disable code
protection.
3.9
FLASH Program Memory Write
Protection
The configuration word contains a bit that write protects
the FLASH Program memory called WRT. This bit can
only be accessed when programming the device via
ICSP. Once write protection is enabled, only an erase
of the entire device will disable it. When enabled, write
protection prevents any writes to FLASH Program
memory. Write protection does not affect program
memory reads.
The state of the program memory code protect bits,
CP0 and CP1, do not affect the execution of instruc-
tions out of program memory. The PIC16F872 can
always read the values in program memory, regardless
of the state of the code protect bits. However, the state
of the code protect bits and the WRT bit will have differ-
TABLE 3-1:
READ/WRITE STATE OF INTERNAL FLASH PROGRAM MEMORY
Configuration Bits
Internal
Read
Internal
Write
Memory Location
ICSP Read
ICSP Write
CP1
CP0
WRT
0
0
1
1
0
0
1
1
0
1
0
1
All program memory
All program memory
All program memory
All program memory
Yes
Yes
Yes
Yes
No
Yes
No
No
No
No
No
Yes
Yes
Yes
Yes
Yes
TABLE 3-2:
REGISTERS ASSOCIATED WITH DATA EEPROM/PROGRAM FLASH
Value on:
POR,
BOR
Value on
all other
RESETS
Address
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
0Bh, 8Bh, INTCON
10Bh, 18Bh
GIE
PEIE
TMR0IE
INTE
RBIE
TMR0IF INTF
RBIF 0000 000x 0000 000u
10Dh
10Fh
10Ch
10Eh
18Ch
18Dh
8Dh
EEADR
EEPROM Address Register, Low Byte
EEPROM Address, High Byte
xxxx xxxx uuuu uuuu
xxxx xxxx uuuu uuuu
xxxx xxxx uuuu uuuu
xxxx xxxx uuuu uuuu
EEADRH
—
—
—
EEDATA EEPROM Data Register, Low Byte
EEDATH
—
—
—
EEPROM Data Register, High Byte
WRERR WREN
EECON1 EEPGD
—
—
WR
RD
x--- x000 x--- u000
EECON2 EEPROM Control Register2 (not a physical register)
—
—
PIE2
PIR2
—
—
(1)
(1)
—
—
EEIE
EEIF
BCLIE
BCLIF
—
—
—
—
(1)
(1)
-r-0 0--r -r-0 0--r
-r-0 0--r -r-0 0--r
0Dh
Legend: x= unknown, u= unchanged, r = reserved, -= unimplemented, read as '0'.
Shaded cells are not used during FLASH/EEPROM access.
Note 1: These bits are reserved; always maintain these bits clear.
DS30221B-page 28
2002 Microchip Technology Inc.
PIC16F872
FIGURE 4-1:
BLOCK DIAGRAM OF
RA3:RA0 AND RA5 PINS
4.0
I/O PORTS
The PIC16F872 provides three general purpose I/O
ports. Some pins for these ports are multiplexed with an
alternate function for the peripheral features on the
device. In general, when a peripheral is enabled, that
pin may not be used as a general purpose I/O pin.
Data
Bus
Data Latch
D
Q
VDD
WR
Port
Q
CK
P
I/O pin(1)
Additional information on I/O ports may be found in the
PICmicro™ Mid-Range Reference Manual (DS33023).
TRIS Latch
N
D
Q
4.1
PORTA and the TRISA Register
WR
PORTA is a 6-bit wide, bi-directional port. The corre-
sponding data direction register is TRISA. Setting a
TRISA bit (= ‘1’) will make the corresponding PORTA
pin an input (i.e., put the corresponding output driver in
a Hi-Impedance mode). Clearing a TRISA bit (= ‘0’) will
make the corresponding PORTA pin an output (i.e., put
the contents of the output latch on the selected pin).
TRIS
Q
CK
VSS
Analog
Input
Mode
RD
TRIS
TTL
Input
Buffer
Reading the PORTA register reads the status of the
pins, whereas writing to it will write to the port latch. All
write operations are read-modify-write operations.
Therefore, a write to a port implies that the port pins are
read, the value is modified and then written to the port
data latch.
Q
D
EN
RD PORT
Pin RA4 is multiplexed with the Timer0 module clock
input to become the RA4/T0CKI pin. The RA4/T0CKI
pin is a Schmitt Trigger input and an open drain output.
All other PORTA pins have TTL input levels and full
CMOS output drivers.
To A/D Converter
Note 1:
I/O pins have protection diodes to VDD and VSS.
Other PORTA pins are multiplexed with analog inputs
and analog VREF input. The operation of each pin is
selected by clearing/setting the control bits in the
ADCON1 register (A/D Control Register1).
FIGURE 4-2:
BLOCK DIAGRAM OF
RA4/T0CKI PIN
Data Latch
Data
Bus
Note: On a Power-on Reset, these pins are con-
D
Q
figured as analog inputs and read as '0'.
WR
PORT
Q
CK
I/O pin(1)
The TRISA register controls the direction of the RA
pins, even when they are being used as analog inputs.
The user must ensure the bits in the TRISA register are
maintained set when using them as analog inputs.
N
TRIS Latch
D
Q
VSS
WR
TRIS
Schmitt
Trigger
Input
Q
CK
EXAMPLE 4-1:
INITIALIZING PORTA
BCF
BCF
STATUS, RP0
STATUS, RP1 ; Bank0
;
Buffer
RD
TRIS
CLRF
PORTA
; Initialize PORTA by
; clearing output
; data latches
BSF
STATUS, RP0 ; Select Bank 1
Q
D
MOVLW
MOVWF
MOVLW
0x06
; Configure all pins
ADCON1
0xCF
; as digital inputs
; Value used to
EN
; initialize data
; direction
RD PORT
MOVWF
TRISA
; Set RA<3:0> as inputs
; RA<5:4> as outputs
; TRISA<7:6>are always
; read as ’0’.
TMR0 clock input
Note 1:
I/O pin has protection diodes to VSS only.
2002 Microchip Technology Inc.
DS30221B-page 29
PIC16F872
TABLE 4-1:
Name
PORTA FUNCTIONS
Bit#
Buffer
Function
RA0/AN0
bit0
bit1
bit2
bit3
bit4
TTL
TTL
TTL
TTL
ST
Input/output or analog input.
Input/output or analog input.
Input/output or analog input.
RA1/AN1
RA2/AN2
RA3/AN3/VREF
RA4/T0CKI
Input/output or analog input or VREF.
Input/output or external clock input for Timer0.
Output is open drain type.
RA5/SS/AN4
bit5
TTL
Input/output or slave select input for synchronous serial port or analog input.
Legend: TTL = TTL input, ST = Schmitt Trigger input
TABLE 4-2:
SUMMARY OF REGISTERS ASSOCIATED WITH PORTA
Value on: Value on all
Address Name
Bit 7 Bit 6 Bit 5 Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
POR,
BOR
other
RESETS
--0x 0000 --0u 0000
--11 1111 --11 1111
--0- 0000 --0- 0000
05h
85h
9Fh
PORTA
TRISA
—
—
—
—
—
RA5
RA4
RA3
RA2
RA1
RA0
PORTA Data Direction Register
PCFG3 PCFG2 PCFG1 PCFG0
ADCON1 ADFM
—
—
Legend: x= unknown, u= unchanged, -= unimplemented locations read as '0'.
Shaded cells are not used by PORTA.
Note: When using the SSP module in SPI Slave mode and SS enabled, the A/D converter must be set to one of
the following modes, where PCFG3:PCFG0 = 0100, 0101, 011x, 1101, 1110, 1111.
DS30221B-page 30
2002 Microchip Technology Inc.
PIC16F872
This interrupt can wake the device from SLEEP. The
user, in the Interrupt Service Routine, can clear the
interrupt in the following manner:
4.2
PORTB and the TRISB Register
PORTB is an 8-bit wide, bi-directional port. The corre-
sponding data direction register is TRISB. Setting a
TRISB bit (= ‘1’) will make the corresponding PORTB
pin an input (i.e., put the corresponding output driver in
a Hi-Impedance mode). Clearing a TRISB bit (= ‘0’) will
make the corresponding PORTB pin an output (i.e., put
the contents of the output latch on the selected pin).
a) Any read or write of PORTB. This will end the
mismatch condition.
b) Clear flag bit RBIF.
A mismatch condition will continue to set flag bit RBIF.
Reading PORTB will end the mismatch condition and
allow flag bit RBIF to be cleared.
Three pins of PORTB are multiplexed with the Low
Voltage Programming function; RB3/PGM, RB6/PGC
and RB7/PGD. The alternate functions of these pins
are described in the Special Features Section.
The interrupt-on-change feature is recommended for
wake-up on key depression operation and operations
where PORTB is only used for the interrupt-on-change
feature. Polling of PORTB is not recommended while
using the interrupt-on-change feature.
Each of the PORTB pins has a weak internal pull-up. A
single control bit can turn on all the pull-ups. This is per-
formed by clearing bit RBPU (OPTION_REG<7>). The
weak pull-up is automatically turned off when the port
pin is configured as an output. The pull-ups are dis-
abled on a Power-on Reset.
This interrupt on mismatch feature, together with soft-
ware configurable pull-ups on these four pins, allow
easy interface to a keypad and make it possible for
wake-up on key depression. Refer to the Embedded
Control Handbook, “Implementing Wake-Up on Key
Stroke” (AN552).
FIGURE 4-3:
BLOCK DIAGRAM OF
RB3:RB0 PINS
RB0/INT is an external interrupt input pin and is config-
ured using the INTEDG bit (OPTION_REG<6>).
VDD
RBPU(2)
Weak
Pull-up
RB0/INT is discussed in detail in Section 11.10.1.
P
Data Latch
Data Bus
WR Port
D
Q
FIGURE 4-4:
BLOCK DIAGRAM OF
RB7:RB4 PINS
VDD
I/O pin(1)
CK
TRIS Latch
RBPU(2)
Weak
P
Pull-up
D
Q
TTL
Input
Buffer
Data Latch
Data Bus
WR Port
WR TRIS
D
Q
CK
I/O pin(1)
CK
TRIS Latch
RD TRIS
RD Port
D
Q
Q
D
TTL
Input
Buffer
WR TRIS
RD TRIS
CK
EN
ST
Buffer
RB0/INT
RB3/PGM
Latch
Schmitt Trigger
Buffer
RD Port
Q
Q
D
RD Port
Note 1: I/O pins have diode protection to VDD and VSS.
EN
Q1
Set RBIF
2: To enable weak pull-ups, set the appropriate TRIS
bit(s) and clear the RBPU bit (OPTION_REG<7>).
D
Four of the PORTB pins, RB7:RB4, have an interrupt-
on-change feature. Only pins configured as inputs can
cause this interrupt to occur (i.e., any RB7:RB4 pin
configured as an output is excluded from the interrupt-
on-change comparison). The input pins (of RB7:RB4)
are compared with the old value latched on the last
read of PORTB. The “mismatch” outputs of RB7:RB4
are OR’ed together to generate the RB Port Change
Interrupt with flag bit RBIF (INTCON<0>).
RD Port
Q3
From other
RB7:RB4 pins
EN
RB7:RB6
In Serial Programming Mode
Note 1: I/O pins have diode protection to VDD and VSS.
2: To enable weak pull-ups, set the appropriate TRIS
bit(s) and clear the RBPU bit (OPTION_REG<7>).
2002 Microchip Technology Inc.
DS30221B-page 31
PIC16F872
TABLE 4-3:
PORTB FUNCTIONS
Name
Bit#
Buffer
Function
RB0/INT
bit0
TTL/ST(1)
Input/output pin or external interrupt input. Internal software
programmable weak pull-up.
RB1
bit1
bit2
bit3
TTL
TTL
TTL
Input/output pin. Internal software programmable weak pull-up.
Input/output pin. Internal software programmable weak pull-up.
RB2
RB3/PGM
Input/output pin or programming pin in LVP mode.
Internal software programmable weak pull-up.
RB4
bit4
bit5
bit6
bit7
TTL
Input/output pin (with interrupt-on-change).
Internal software programmable weak pull-up.
RB5
TTL
Input/output pin (with interrupt-on-change).
Internal software programmable weak pull-up.
RB6/PGC
RB7/PGD
TTL/ST(2)
TTL/ST(2)
Input/output pin (with interrupt-on-change) or In-Circuit Debugger pin.
Internal software programmable weak pull-up. Serial programming clock.
Input/output pin (with interrupt-on-change) or In-Circuit Debugger pin.
Internal software programmable weak pull-up. Serial programming data.
Legend: TTL = TTL input, ST = Schmitt Trigger input
Note 1: This buffer is a Schmitt Trigger input when configured as the external interrupt.
2: This buffer is a Schmitt Trigger input when used in Serial Programming mode.
TABLE 4-4:
Address
SUMMARY OF REGISTERS ASSOCIATED WITH PORTB
Value on: Value on
Name
Bit 7
Bit 6
Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
RB5 RB4 RB3 RB2 RB1 RB0
POR,
BOR
all other
RESETS
xxxx xxxx uuuu uuuu
1111 1111 1111 1111
1111 1111 1111 1111
06h, 106h PORTB
86h, 186h TRISB
RB7
RB6
PORTB Data Direction Register
81h, 181h OPTION_REG RBPU INTEDG T0CS T0SE PSA PS2 PS1 PS0
Legend: x= unknown, u= unchanged. Shaded cells are not used by PORTB.
DS30221B-page 32
2002 Microchip Technology Inc.
PIC16F872
FIGURE 4-6:
PORTC BLOCK DIAGRAM
(PERIPHERAL OUTPUT
OVERRIDE) RC<4:3>
4.3
PORTC and the TRISC Register
PORTC is an 8-bit wide, bi-directional port. The corre-
sponding data direction register is TRISC. Setting a
TRISC bit (= ‘1’) will make the corresponding PORTC
pin an input (i.e., put the corresponding output driver in
a Hi-Impedance mode). Clearing a TRISC bit (= ‘0’) will
make the corresponding PORTC pin an output (i.e., put
the contents of the output latch on the selected pin).
Port/Peripheral Select(2)
Peripheral Data Out
Data Bus
VDD
0
D
Q
Q
P
WR
PORT
I/O
1
pin(1)
CK
PORTC is multiplexed with several peripheral functions
(Table 4-5). PORTC pins have Schmitt Trigger input
buffers.
When the I2C module is enabled, the PORTC (4:3) pins
can be configured with normal I2C levels or with SMBus
levels by using the CKE bit (SSPSTAT<6>).
Data Latch
D
Q
Q
WR
TRIS
CK
N
TRIS Latch
Vss
RD
When enabling peripheral functions, care should be
taken in defining TRIS bits for each PORTC pin. Some
peripherals override the TRIS bit to make a pin an out-
put, while other peripherals override the TRIS bit to
make a pin an input. Since the TRIS bit override is in
effect while the peripheral is enabled, read-modify-
write instructions (BSF, BCF, XORWF) with TRISC as
the destination should be avoided. The user should
refer to the corresponding peripheral section for the
correct TRIS bit settings.
TRIS
Schmitt
Trigger
Peripheral
OE(3)
Q
D
Schmitt
Trigger
with
SMBus
Levels
EN
RD
PORT
SSPl Input
0
1
CKE
SSPSTAT<6>
FIGURE 4-5:
PORTC BLOCK DIAGRAM
(PERIPHERAL OUTPUT
OVERRIDE) RC<2:0>
RC<7:5>
Note 1: I/O pins have diode protection to VDD and VSS.
2: Port/Peripheral select signal selects between port data
and peripheral output.
3: Peripheral OE (output enable) is only activated if
peripheral select is active.
Port/Peripheral Select(2)
Peripheral Data Out
Data Bus
VDD
P
0
1
D
Q
Q
WR
PORT
CK
Data Latch
I/O pin(1)
D
Q
Q
WR
TRIS
CK
N
TRIS Latch
VSS
RD
TRIS
Schmitt
Trigger
Peripheral
OE(3)
Q
D
EN
RD
PORT
Peripheral Input
Note 1: I/O pins have diode protection to VDD and VSS.
2: Port/Peripheral select signal selects between port
data and peripheral output.
3: Peripheral OE (output enable) is only activated if
peripheral select is active.
2002 Microchip Technology Inc.
DS30221B-page 33
PIC16F872
TABLE 4-5:
PORTC FUNCTIONS
Name
Bit# Buffer Type
Function
RC0/T1OSO/T1CKI
RC1/T1OSI/CCP2
bit0
bit1
ST
ST
Input/output port pin or Timer1 oscillator output/Timer1 clock input.
Input/output port pin or Timer1 oscillator input or Capture2 input/
Compare2 output/PWM2 output.
RC2/CCP1
bit2
bit3
ST
ST
Input/output port pin or Capture1 input/Compare1 output/
PWM output.
RC3 can also be the synchronous serial clock for both SPI and I2C
RC3/SCK/SCL
modes.
RC4/SDI/SDA
RC5/SDO
bit4
bit5
ST
ST
RC4 can also be the SPI Data In (SPI mode) or Data I/O (I2C mode).
Input/output port pin or Synchronous Serial Port data output
(SPI mode).
RC6
RC7
bit6
bit7
ST
ST
Input/output port pin.
Input/output port pin.
Legend: ST = Schmitt Trigger input
TABLE 4-6:
SUMMARY OF REGISTERS ASSOCIATED WITH PORTC
Value on:
POR,
Value on
all other
RESETS
Address Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
BOR
xxxx xxxx uuuu uuuu
1111 1111 1111 1111
07h
87h
PORTC RC7
RC6
RC5
RC4
RC3
RC2
RC1
RC0
TRISC PORTC Data Direction Register
Legend: x= unknown, u= unchanged
DS30221B-page 34
2002 Microchip Technology Inc.
PIC16F872
Counter mode is selected by setting bit T0CS
(OPTION_REG<5>). In Counter mode, Timer0 will
increment either on every rising or falling edge of pin
RA4/T0CKI. The incrementing edge is determined by
the Timer0 Source Edge Select bit T0SE
(OPTION_REG<4>). Clearing bit T0SE selects the ris-
ing edge. Restrictions on the external clock input are
discussed in detail in Section 5.2.
5.0
TIMER0 MODULE
The Timer0 module timer/counter has the following
features:
• 8-bit timer/counter
• Readable and writable
• 8-bit software programmable prescaler
• Internal or external clock select
• Interrupt on overflow from FFh to 00h
• Edge select for external clock
The prescaler is mutually exclusively shared between
the Timer0 module and the Watchdog Timer. The pres-
caler is not readable or writable. Section 5.3 details the
operation of the prescaler.
Figure 5-1 is a block diagram of the Timer0 module and
the prescaler shared with the WDT.
5.1
Timer0 Interrupt
Additional information on the Timer0 module is avail-
able in the PICmicro™ Mid-Range MCU Family Refer-
ence Manual (DS33023).
The TMR0 interrupt is generated when the TMR0 reg-
ister overflows from FFh to 00h. This overflow sets bit
TMR0IF (INTCON<2>). The interrupt can be masked
by clearing bit TMR0IE (INTCON<5>). Bit TMR0IF
must be cleared in software by the Timer0 module
Interrupt Service Routine before re-enabling this inter-
rupt. The TMR0 interrupt cannot awaken the processor
from SLEEP, since the timer is shut-off during SLEEP.
Timer mode is selected by clearing bit T0CS
(OPTION_REG<5>). In Timer mode, the Timer0 mod-
ule will increment every instruction cycle (without pres-
caler). If the TMR0 register is written, the increment is
inhibited for the following two instruction cycles. The
user can work around this by writing an adjusted value
to the TMR0 register.
FIGURE 5-1:
BLOCK DIAGRAM OF THE TIMER0/WDT PRESCALER
Data Bus
CLKOUT (= FOSC/4)
8
M
U
X
1
0
0
1
M
U
X
RA4/T0CKI
Pin
SYNC
2
TMR0 reg
Cycles
T0SE
T0CS
Set Flag Bit TMR0IF
PSA
on Overflow
PRESCALER
0
1
8-bit Prescaler
M
U
X
Watchdog
Timer
8
8 - to - 1MUX
PS2:PS0
PSA
1
0
WDT Enable bit
M U X
PSA
WDT
Time-out
Note: T0CS, T0SE, PSA, PS2:PS0 are (OPTION_REG<5:0>).
2002 Microchip Technology Inc.
DS30221B-page 35
PIC16F872
Timer0 module means that there is no prescaler for the
Watchdog Timer, and vice-versa. This prescaler is not
readable or writable (see Figure 5-1).
5.2
Using Timer0 with an External
Clock
When no prescaler is used, the external clock input is
the same as the prescaler output. The synchronization
of T0CKI with the internal phase clocks is accom-
plished by sampling the prescaler output on the Q2 and
Q4 cycles of the internal phase clocks. Therefore, it is
necessary for T0CKI to be high for at least 2TOSC (and
a small RC delay of 20 ns) and low for at least 2TOSC
(and a small RC delay of 20 ns). Refer to the electrical
specification of the desired device.
The PSA and PS2:PS0 bits (OPTION_REG<3:0>)
determine the prescaler assignment and prescale ratio.
When assigned to the Timer0 module, all instructions
writing to the TMR0 register (e.g. CLRF1, MOVWF1,
BSF1,x....etc.) will clear the prescaler. When assigned
to WDT, a CLRWDT instruction will clear the prescaler
along with the Watchdog Timer. The prescaler is not
readable or writable.
Note: Writing to TMR0, when the prescaler is
assigned to Timer0, will clear the prescaler
count, but will not change the prescaler
assignment.
5.3
Prescaler
There is only one prescaler available, which is mutually
exclusively shared between the Timer0 module and the
Watchdog Timer. A prescaler assignment for the
REGISTER 5-1:
OPTION_REG REGISTER
R/W-1
RBPU
R/W-1
R/W-1
T0CS
R/W-1
T0SE
R/W-1
PSA
R/W-1
PS2
R/W-1
PS1
R/W-1
PS0
INTEDG
bit 7
bit 0
bit 7
bit 6
bit 5
RBPU
INTEDG
T0CS: TMR0 Clock Source Select bit
1= Transition on T0CKI pin
0= Internal instruction cycle clock (CLKOUT)
bit 4
T0SE: TMR0 Source Edge Select bit
1= Increment on high-to-low transition on T0CKI pin
0= Increment on low-to-high transition on T0CKI pin
bit 3
PSA: Prescaler Assignment bit
1= Prescaler is assigned to the WDT
0= Prescaler is assigned to the Timer0 module
bit 2-0
PS2:PS0: Prescaler Rate Select bits
Bit Value TMR0 Rate WDT Rate
000
001
010
011
100
101
110
111
1 : 2
1 : 4
1 : 8
1 : 16
1 : 32
1 : 64
1 : 128
1 : 256
1 : 1
1 : 2
1 : 4
1 : 8
1 : 16
1 : 32
1 : 64
1 : 128
Legend:
R = Readable bit
W = Writable bit
’1’ = Bit is set
U = Unimplemented bit, read as ‘0’
’0’ = Bit is cleared x = Bit is unknown
- n = Value at POR
Note: To avoid an unintended device RESET, the instruction sequence shown in the PICmicro™ Mid-Range MCU
Family Reference Manual (DS33023) must be executed when changing the prescaler assignment from
Timer0 to the WDT. This sequence must be followed even if the WDT is disabled.
DS30221B-page 36
2002 Microchip Technology Inc.
PIC16F872
TABLE 5-1:
Address
REGISTERS ASSOCIATED WITH TIMER0
Value on: Value on
Name
Bit 7
Bit 6
Bit 5 Bit 4 Bit 3
Bit 2
Bit 1 Bit 0
POR,
BOR
all other
resets
xxxx xxxx uuuu uuuu
0000 000x 0000 000u
01h,101h TMR0
Timer0 Module Register
GIE PEIE TMR0IE INTE RBIE TMR0IF INTF RBIF
0Bh,8Bh, INTCON
10Bh,18Bh
1111 1111 1111 1111
81h,181h OPTION_REG RBPU INTEDG T0CS T0SE PSA
PS2
PS1 PS0
Legend: x= unknown, u= unchanged, -= unimplemented locations read as ’0’.
Shaded cells are not used by Timer0.
2002 Microchip Technology Inc.
DS30221B-page 37
PIC16F872
NOTES:
DS30221B-page 38
2002 Microchip Technology Inc.
PIC16F872
In Timer mode, Timer1 increments every instruction
cycle. In Counter mode, it increments on every rising
edge of the external clock input.
6.0
TIMER1 MODULE
The Timer1 module is a 16-bit timer/counter consisting
of two 8-bit registers (TMR1H and TMR1L), which are
readable and writable. The TMR1 Register pair
(TMR1H:TMR1L) increments from 0000h to FFFFh
and rolls over to 0000h. The TMR1 Interrupt, if enabled,
is generated on overflow, which is latched in interrupt
flag bit TMR1IF (PIR1<0>). This interrupt can be
enabled/disabled by setting/clearing TMR1 interrupt
enable bit TMR1IE (PIE1<0>).
Timer1 can be enabled/disabled by setting/clearing
control bit TMR1ON (T1CON<0>).
Timer1 also has an internal “RESET input”. This
RESET can be generated by either of the two CCP
modules (Section 8.0). Register 6-1 shows the Timer1
control register.
When the Timer1 oscillator is enabled (T1OSCEN is
set), the RC1/T1OSI/CCP2 and RC0/T1OSO/T1CKI
pins become inputs. That is, the TRISC<1:0> value is
ignored, and these pins read as ‘0’.
Timer1 can operate in one of two modes:
• As a Timer
• As a Counter
Additional information on timer modules is available in
the PICmicro™ Mid-range MCU Family Reference
Manual (DS33023).
The operating mode is determined by the clock select
bit, TMR1CS (T1CON<1>).
REGISTER 6-1:
T1CON: TIMER1 CONTROL REGISTER (ADDRESS 10h)
U-0
U-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
—
—
T1CKPS1 T1CKPS0 T1OSCEN T1SYNC TMR1CS TMR1ON
bit 0
bit 7
bit 7-6
bit 5-4
Unimplemented: Read as '0'
T1CKPS1:T1CKPS0: Timer1 Input Clock Prescale Select bits
11= 1:8 Prescale value
10= 1:4 Prescale value
01= 1:2 Prescale value
00= 1:1 Prescale value
bit 3
bit 2
T1OSCEN: Timer1 Oscillator Enable Control bit
1= Oscillator is enabled
0= Oscillator is shut off (The oscillator inverter is turned off to eliminate power drain)
T1SYNC: Timer1 External Clock Input Synchronization Control bit
When TMR1CS = 1:
1= Do not synchronize external clock input
0= Synchronize external clock input
When TMR1CS = 0:
This bit is ignored. Timer1 uses the internal clock when TMR1CS = 0.
TMR1CS: Timer1 Clock Source Select bit
bit 1
bit 0
1= External clock from pin RC0/T1OSO/T1CKI (on the rising edge)
0= Internal clock (FOSC/4)
TMR1ON: Timer1 On bit
1= Enables Timer1
0= Stops Timer1
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
’0’ = Bit is cleared x = Bit is unknown
- n = Value at POR
’1’ = Bit is set
2002 Microchip Technology Inc.
DS30221B-page 39
PIC16F872
6.1
Timer1 Operation in Timer Mode
6.2
Timer1 Counter Operation
Timer mode is selected by clearing the TMR1CS
(T1CON<1>) bit. In this mode, the input clock to the
timer is FOSC/4. The synchronize control bit T1SYNC
(T1CON<2>) has no effect since the internal clock is
always in sync.
Timer1 may operate in either a Synchronous or an
Asynchronous mode, depending on the setting of the
TMR1CS bit.
When Timer1 is being incremented via an external
source, increments occur on a rising edge. After Timer1
is enabled in Counter mode, the module must first have
a falling edge before the counter begins to increment.
FIGURE 6-1:
TIMER1 INCREMENTING EDGE
T1CKI
(Default High)
T1CKI
(Default Low)
Note: Arrows indicate counter increments.
If T1SYNC is cleared, then the external clock input is
synchronized with internal phase clocks. The synchro-
nization is done after the prescaler stage. The pres-
caler stage is an asynchronous ripple counter.
6.3
Timer1 Operation in Synchronized
Counter Mode
Counter mode is selected by setting bit TMR1CS. In
this mode, the timer increments on every rising edge of
clock input on pin RC1/T1OSI/CCP2, when bit
T1OSCEN is set, or on pin RC0/T1OSO/T1CKI, when
bit T1OSCEN is cleared.
In this configuration, during SLEEP mode, Timer1 will
not increment even if the external clock is present,
since the synchronization circuit is shut-off. The pres-
caler, however, will continue to increment.
FIGURE 6-2:
TIMER1 BLOCK DIAGRAM
Set Flag bit
TMR1IF on
Overflow
Synchronized
0
TMR1
Clock Input
TMR1L
TMR1H
1
TMR1ON
On/Off
T1SYNC
T1OSC
RC0/T1OSO/T1CKI
1
Synchronize
det
Prescaler
1, 2, 4, 8
T1OSCEN
Enable
FOSC/4
Internal
Clock
0
(1)
(2)
Oscillator
RC1/T1OSI/CCP2
2
Q Clock
T1CKPS1:T1CKPS0
TMR1CS
Note 1: When the T1OSCEN bit is cleared, the inverter is turned off. This eliminates power drain.
DS30221B-page 40
2002 Microchip Technology Inc.
PIC16F872
TABLE 6-1:
CAPACITOR SELECTION FOR
THE TIMER1 OSCILLATOR
6.4
Timer1 Operation in
Asynchronous Counter Mode
If control bit T1SYNC (T1CON<2>) is set, the external
clock input is not synchronized. The timer continues to
increment asynchronous to the internal phase clocks.
The timer will continue to run during SLEEP and can
generate an interrupt on overflow, which will wake-up
the processor. However, special precautions in soft-
ware are needed to read/write the timer (Section 6.4.1).
Osc Type
Freq
C1
C2
LP
32 kHz
100 kHz
200 kHz
33 pF
15 pF
15 pF
33 pF
15 pF
15 pF
These values are for design guidance only.
Crystals Tested:
In Asynchronous Counter mode, Timer1 cannot be
used as a time-base for capture or compare opera-
tions.
32.768 kHz Epson C-001R32.768K-A ± 20 PPM
100 kHz
200 kHz
Epson C-2 100.00 KC-P ± 20 PPM
STD XTL 200.000 kHz ± 20 PPM
6.4.1
READING AND WRITING TIMER1 IN
ASYNCHRONOUS COUNTER
MODE
Note 1: Higher capacitance increases the stability
of oscillator, but also increases the start-up
time.
2: Since each resonator/crystal has its own
characteristics, the user should consult the
resonator/crystal manufacturer for appro-
priate values of external components.
Reading TMR1H or TMR1L while the timer is running
from an external asynchronous clock will guarantee a
valid read (taken care of in hardware). However, the
user should keep in mind that reading the 16-bit timer
in two 8-bit values itself, poses certain problems, since
the timer may overflow between the reads.
6.6
Resetting Timer1 using a CCP
Trigger Output
For writes, it is recommended that the user simply stop
the timer and write the desired values. A write conten-
tion may occur by writing to the timer registers while the
register is incrementing. This may produce an unpre-
dictable value in the timer register.
If the CCP1 or CCP2 module is configured in Compare
mode to generate “special event trigger”
(CCP1M3:CCP1M0 = 1011), this signal will reset
a
Timer1.
Note: The special event triggers from the CCP1
and CCP2 modules will not set interrupt
flag bit TMR1IF (PIR1<0>).
Reading the 16-bit value requires some care. Exam-
ples 12-2 and 12-3 in the PICmicro™ Mid-Range MCU
Family Reference Manual (DS33023) show how to
read and write Timer1 when it is running in Asynchro-
nous mode.
Timer1 must be configured for either Timer or Synchro-
nized Counter mode to take advantage of this feature.
If Timer1 is running in Asynchronous Counter mode,
this RESET operation may not work.
6.5
Timer1 Oscillator
A crystal oscillator circuit is built-in between pins T1OSI
(input) and T1OSO (amplifier output). It is enabled by
setting control bit T1OSCEN (T1CON<3>). The oscilla-
tor is a low power oscillator, rated up to 200 kHz. It will
continue to run during SLEEP. It is primarily intended
for use with a 32 kHz crystal. Table 6-1 shows the
capacitor selection for the Timer1 oscillator.
In the event that a write to Timer1 coincides with a spe-
cial event trigger from CCP1 or CCP2, the write will
take precedence.
In this mode of operation, the CCPRxH:CCPRxL regis-
ter pair effectively becomes the period register for
Timer1.
The Timer1 oscillator is identical to the LP oscillator.
The user must provide a software time delay to ensure
proper oscillator start-up.
6.7
Resetting of Timer1 Register Pair
(TMR1H, TMR1L)
TMR1H and TMR1L registers are not reset to 00h on a
POR or any other RESET, except by the CCP1 and
CCP2 special event triggers.
T1CON register is reset to 00h on a Power-on Reset or
a Brown-out Reset, which shuts off the timer and
leaves a 1:1 prescale. In all other RESETS, the register
is unaffected.
6.8
Timer1 Prescaler
The prescaler counter is cleared on writes to the
TMR1H or TMR1L registers.
2002 Microchip Technology Inc.
DS30221B-page 41
PIC16F872
TABLE 6-2:
REGISTERS ASSOCIATED WITH TIMER1 AS A TIMER/COUNTER
Value on:
POR,
BOR
Value on
all other
RESETS
Address
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
0Bh,8Bh,
INTCON GIE
PEIE TMR0IE
INTE
RBIE
TMR0IF
INTF
RBIF
0000 000x 0000 000u
10Bh, 18Bh
r0rr 0000
0Ch
8Ch
0Eh
0Fh
10h
PIR1
PIE1
(3)
(3)
ADIF
ADIE
(3)
(3)
(3)
(3)
SSPIF
SSPIE
CCP1IF TMR2IF TMR1IF
CCP1IE TMR2IE TMR1IE
0000 0000
r0rr 0000
0000 0000
TMR1L Holding Register for the Least Significant Byte of the 16-bit TMR1 Register
TMR1H Holding Register for the Most Significant Byte of the 16-bit TMR1 Register
xxxx xxxx uuuu uuuu
xxxx xxxx uuuu uuuu
T1CON
—
—
T1CKPS1 T1CKPS0 T1OSCEN T1SYNC TMR1CS TMR1ON --00 0000 --uu uuuu
Legend: x= unknown, u= unchanged, -= unimplemented, read as '0'. Shaded cells are not used by the Timer1 module.
DS30221B-page 42
2002 Microchip Technology Inc.
PIC16F872
Register 7-1 shows the Timer2 Control register.
7.0
TIMER2 MODULE
Additional information on timer modules is available in
the PICmicro™ Mid-Range MCU Family Reference
Manual (DS33023).
Timer2 is an 8-bit timer with a prescaler and a
postscaler. It can be used as the PWM time-base for
the PWM mode of the CCP module(s). The TMR2 reg-
ister is readable and writable, and is cleared on any
device RESET.
FIGURE 7-1:
TIMER2 BLOCK DIAGRAM
Sets Flag
bit TMR2IF
The input clock (FOSC/4) has a prescale option of 1:1,
TMR2
Output(1)
Reset
1:4
or
1:16,
selected
by
control
bits
T2CKPS1:T2CKPS0 (T2CON<1:0>).
Prescaler
1:1, 1:4, 1:16
TMR2 reg
FOSC/4
The Timer2 module has an 8-bit period register, PR2.
Timer2 increments from 00h until it matches PR2 and
then resets to 00h on the next increment cycle. PR2 is
a readable and writable register. The PR2 register is
initialized to FFh upon RESET.
Postscaler
1:1 to 1:16
2
Comparator
EQ
T2CKPS1:
T2CKPS0
4
PR2 reg
T2OUTPS3:
T2OUTPS0
The match output of TMR2 goes through a 4-bit
postscaler (which gives a 1:1 to 1:16 scaling inclusive)
to generate a TMR2 interrupt (latched in flag bit,
TMR2IF (PIR1<1>)).
Note 1: TMR2 register output can be software selected by the
SSP module as a baud clock.
Timer2 can be shut-off by clearing control bit TMR2ON
(T2CON<2>) to minimize power consumption.
REGISTER 7-1:
T2CON: TIMER2 CONTROL REGISTER (ADDRESS 12h)
U-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
—
TOUTPS3 TOUTPS2 TOUTPS1 TOUTPS0 TMR2ON T2CKPS1 T2CKPS0
bit 0
bit 7
bit 7
Unimplemented: Read as '0'
bit 6-3
TOUTPS3:TOUTPS0: Timer2 Output Postscale Select bits
0000= 1:1 Postscale
0001= 1:2 Postscale
0010= 1:3 Postscale
•
•
•
1111= 1:16 Postscale
TMR2ON: Timer2 On bit
bit 2
1= Timer2 is on
0= Timer2 is off
bit 1-0
T2CKPS1:T2CKPS0: Timer2 Clock Prescale Select bits
00= Prescaler is 1
01= Prescaler is 4
1x= Prescaler is 16
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
’0’ = Bit is cleared x = Bit is unknown
- n = Value at POR
’1’ = Bit is set
2002 Microchip Technology Inc.
DS30221B-page 43
PIC16F872
7.1
Timer2 Prescaler and Postscaler
7.2
Output of TMR2
The prescaler and postscaler counters are cleared
when any of the following occurs:
The output of TMR2 (before the postscaler) is fed to the
SSP module, which optionally uses it to generate shift
clock.
• a write to the TMR2 register
• a write to the T2CON register
• any device RESET (POR, MCLR Reset, WDT
Reset or BOR)
TMR2 is not cleared when T2CON is written.
TABLE 7-1:
REGISTERS ASSOCIATED WITH TIMER2 AS A TIMER/COUNTER
Value on:
POR,
BOR
Value on
all other
RESETS
Address
Name Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
0Bh,8Bh,
INTCON GIE
PEIE
TMR0IE
INTE
RBIE
TMR0IF
INTF
RBIF
0000 000x 0000 000u
10Bh, 18Bh
0Ch
8Ch
11h
12h
92h
PIR1
(3)
(3)
ADIF
ADIE
(3)
(3)
(3)
(3)
SSPIF
SSPIE
CCP1IF TMR2IF TMR1IF r0rr 0000 0000 0000
CCP1IE TMR2IE TMR1IE r0rr 0000 0000 0000
0000 0000 0000 0000
PIE1
TMR2
T2CON
PR2
Timer2 Module Register
—
TOUTPS3 TOUTPS2 TOUTPS1 TOUTPS0 TMR2ON T2CKPS1 T2CKPS0 -000 0000 -000 0000
Timer2 Period Register 1111 1111 1111 1111
Legend: x= unknown, u= unchanged, -= unimplemented, read as '0'. Shaded cells are not used by the Timer2 module.
DS30221B-page 44
2002 Microchip Technology Inc.
PIC16F872
Additional information on CCP modules is available in
the PICmicro™ Mid-Range MCU Family Reference
Manual (DS33023) and in Application Note (AN594),
“Using the CCP Modules” (DS00594).
8.0
CAPTURE/COMPARE/PWM
MODULE
The Capture/Compare/PWM (CCP) module contains a
16-bit register, which can operate as a:
TABLE 8-1:
CCP MODE - TIMER
RESOURCES REQUIRED
• 16-bit Capture register
• 16-bit Compare register
• PWM Master/Slave Duty Cycle register
CCP Mode
Capture
Compare
PWM
Timer Resource
The timer resources used by the module are shown in
Table 8-1.
Timer1
Timer1
Timer2
Capture/Compare/PWM Register 1 (CCPR1) is com-
prised of two 8-bit registers: CCPR1L (low byte) and
CCPR1H (high byte). The CCP1CON register controls
the operation of CCP1. The special event trigger is
generated by a compare match and will reset Timer1.
REGISTER 8-1:
CCP1CON REGISTER (ADDRESS: 17h)
U-0
U-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
—
—
CCP1X
CCP1Y
CCP1M3 CCP1M2 CCP1M1 CCP1M0
bit 0
bit 7
Unimplemented: Read as '0'
bit 7-6
bit 5-4
CCP1X:CCP1Y: PWM Least Significant bits
Capture mode:
Unused
Compare mode:
Unused
PWM mode:
These bits are the two LSbs of the PWM duty cycle. The eight MSbs are found in CCPR1L.
bit 3-0
CCP1M3:CCP1M0: CCP1 Mode Select bits
0000= Capture/Compare/PWM disabled (resets CCP module)
0100= Capture mode, every falling edge
0101= Capture mode, every rising edge
0110= Capture mode, every 4th rising edge
0111= Capture mode, every 16th rising edge
1000= Compare mode, set output on match (CCP1IF bit is set)
1001= Compare mode, clear output on match (CCP1IF bit is set)
1010= Compare mode, generate software interrupt on match (CCP1IF bit is set, CCP1 pin is
unaffected)
1011= Compare mode, trigger special event (CCP1IF bit is set, CCP1 pin is unaffected);
CCP1 resets TMR1 and starts an A/D conversion (if A/D module is enabled)
11xx= PWM mode
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
’0’ = Bit is cleared x = Bit is unknown
- n = Value at POR
’1’ = Bit is set
2002 Microchip Technology Inc.
DS30221B-page 45
PIC16F872
8.1.2
TIMER1 MODE SELECTION
8.1
Capture Mode
Timer1 must be running in Timer mode or Synchro-
nized Counter mode for the CCP module to use the
capture feature. In Asynchronous Counter mode, the
capture operation may not work.
In Capture mode, CCPR1H:CCPR1L captures the
16-bit value of the TMR1 register when an event occurs
on pin RC2/CCP1. An event is defined as one of the
following:
• Every falling edge
• Every rising edge
8.1.3
SOFTWARE INTERRUPT
When the Capture mode is changed, a false capture
interrupt may be generated. The user should keep bit
CCP1IE (PIE1<2>) clear to avoid false interrupts and
should clear the flag bit, CCP1IF, following any such
change in operating mode.
• Every 4th rising edge
• Every 16th rising edge
The type of event is configured by control bits
CCP1M3:CCP1M0 (CCP1CON<3:0>). When a cap-
ture is made, the interrupt request flag bit CCP1IF
(PIR1<2>) is set. The interrupt flag must be cleared in
software. If another capture occurs before the value in
register CCPR1 is read, the old captured value is over-
written by the new value.
8.1.4
CCP PRESCALER
There are four prescaler settings, specified by bits
CCP1M3:CCP1M0. Whenever the CCP module is
turned off, or the CCP module is not in Capture mode,
the prescaler counter is cleared. Any RESET will clear
the prescaler counter.
8.1.1
CCP PIN CONFIGURATION
In Capture mode, the RC2/CCP1 pin should be config-
ured as an input by setting the TRISC<2> bit.
Switching from one capture prescaler to another may
generate an interrupt. Also, the prescaler counter will
not be cleared, therefore, the first capture may be from
a non-zero prescaler. Example 8-1 shows the recom-
mended method for switching between capture pres-
calers. This example also clears the prescaler counter
and will not generate the “false” interrupt.
Note: If the RC2/CCP1 pin is configured as an
output, a write to the port can cause a cap-
ture condition.
FIGURE 8-1:
CAPTURE MODE
OPERATION BLOCK
DIAGRAM
EXAMPLE 8-1:
CHANGING BETWEEN
CAPTURE PRESCALERS
RC2/CCP1
Pin
Set Flag bit CCP1IF
(PIR1<2>)
CLRF
CCP1CON
; Turn CCP module off
Prescaler
MOVLW
NEW_CAPT_PS ; Load the W reg with
; the new prescaler
÷ 1, 4, 16
CCPR1H
CCPR1L
; move value and CCP ON
MOVWF
CCP1CON
; Load CCP1CON with this
; value
Capture
Enable
and
Edge Detect
TMR1H
TMR1L
CCP1CON<3:0>
Qs
DS30221B-page 46
2002 Microchip Technology Inc.
PIC16F872
8.2.1
CCP PIN CONFIGURATION
8.2
Compare Mode
The user must configure the RC2/CCP1 pin as an out-
put by clearing the TRISC<2> bit.
In Compare mode, the 16-bit CCPR1 register value is
constantly compared against the TMR1 register pair
value. When a match occurs, the RC2/CCP1 pin is:
Note: Clearing the CCP1CON register will force
the RC2/CCP1 compare output latch to the
default low level. This is not the PORTC
I/O data latch.
• Driven high
• Driven low
• Remains unchanged
The action on the pin is based on the value of control
bits, CCP1M3:CCP1M0 (CCP1CON<3:0>). At the
same time, interrupt flag bit CCP1IF is set.
8.2.2
TIMER1 MODE SELECTION
Timer1 must be running in Timer mode or Synchro-
nized Counter mode if the CCP module is using the
compare feature. In Asynchronous Counter mode, the
compare operation may not work.
FIGURE 8-2:
COMPARE MODE
OPERATION BLOCK
DIAGRAM
8.2.3
SOFTWARE INTERRUPT MODE
Special event trigger will:
reset Timer1, but not set interrupt flag bit TMR1IF (PIR1<0>),
and set bit GO/DONE (ADCON0<2>).
When Generate Software Interrupt mode is chosen, the
CCP1 pin is not affected. The CCPIF bit is set, causing
a CCP interrupt (if enabled).
Special Event Trigger
8.2.4
SPECIAL EVENT TRIGGER
Set Flag bit CCP1IF
(PIR1<2>)
RC2/CCP1
Pin
In this mode, an internal hardware trigger is generated,
which may be used to initiate an action.
CCPR1H CCPR1L
Q
S
R
Output
Logic
Comparator
The special event trigger output of CCP1 resets the
TMR1 register pair and starts an A/D conversion (if the
A/D module is enabled). This allows the CCPR1 regis-
ter to effectively be a 16-bit programmable period
register for Timer1.
Match
TRISC<2>
Output Enable
TMR1H TMR1L
CCP1CON<3:0>
Mode Select
Note: The special event trigger from the CCP
module will not set interrupt flag bit
TMR1IF (PIR1<0>).
TABLE 8-2:
REGISTERS ASSOCIATED WITH CAPTURE, COMPARE, AND TIMER1
Value on:
POR,
BOR
Value on
all other
RESETS
Address
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
0Bh,8Bh,
INTCON
GIE
PEIE TMR0IE
INTE
RBIE
TMR0IF
INTF
RBIF
0000 000x 0000 000u
10Bh, 18Bh
0Ch
8Ch
87h
0Eh
0Fh
10h
15h
16h
17h
PIR1
(1)
(1)
ADIF
ADIE
(1)
(1)
(1)
(1)
SSPIF
SSPIE
CCP1IF TMR2IF TMR1IF r0rr 0000 0000 0000
CCP1IE TMR2IE TMR1IE r0rr 0000 0000 0000
1111 1111 1111 1111
PIE1
TRISC
TMR1L
TMR1H
T1CON
PORTC Data Direction Register
Holding Register for the Least Significant Byte of the 16-bit TMR1 Register
Holding Register for the Most Significant Byte of the 16-bit TMR1 Register
xxxx xxxx uuuu uuuu
xxxx xxxx uuuu uuuu
—
—
T1CKPS1 T1CKPS0 T1OSCEN T1SYNC TMR1CS TMR1ON --00 0000 --uu uuuu
CCPR1L Capture/Compare/PWM Register1 (LSB)
CCPR1H Capture/Compare/PWM Register1 (MSB)
xxxx xxxx uuuu uuuu
xxxx xxxx uuuu uuuu
CCP1CON
—
—
CCP1X
CCP1Y CCP1M3 CCP1M2 CCP1M1 CCP1M0 --00 0000 --00 0000
Legend: x= unknown, u= unchanged, -= unimplemented, read as '0'. Shaded cells are not used by Capture and Timer1.
Note 1: These bits are reserved; always maintain clear.
2002 Microchip Technology Inc.
DS30221B-page 47
PIC16F872
8.3.1
PWM PERIOD
8.3
PWM Mode (PWM)
The PWM period is specified by writing to the PR2 reg-
ister. The PWM period can be calculated using the fol-
lowing formula:
In Pulse Width Modulation mode, the CCP1 pin pro-
duces up to a 10-bit resolution PWM output. Since the
CCP1 pin is multiplexed with the PORTC data latch, the
TRISC<2> bit must be cleared to make the CCP1 pin
an output.
PWM period = [(PR2) + 1] • 4 • TOSC •
(TMR2 prescale value)
Note: Clearing the CCP1CON register will force
the CCP1 PWM output latch to the default
low level. This is not the PORTC I/O data
latch.
PWM frequency is defined as 1 / [PWM period].
When TMR2 is equal to PR2, the following three events
occur on the next increment cycle:
• TMR2 is cleared
Figure 8-3 shows a simplified block diagram of the
CCP module in PWM mode.
• The CCP1 pin is set (exception: if PWM duty
cycle = 0%, the CCP1 pin will not be set)
For a step-by-step procedure on how to set up the CCP
module for PWM operation, see Section 8.3.3.
• The PWM duty cycle is latched from CCPR1L into
CCPR1H
FIGURE 8-3:
SIMPLIFIED PWM BLOCK
DIAGRAM
Note: The Timer2 postscaler (see Section 7.1) is
not used in the determination of the PWM
frequency. The postscaler could be used
to have a servo update rate at a different
frequency than the PWM output.
CCP1CON<5:4>
Duty Cycle Registers
CCPR1L
8.3.2
PWM DUTY CYCLE
The PWM duty cycle is specified by writing to the
CCPR1L register and to the CCP1CON<5:4> bits. Up
to 10-bit resolution is available. The CCPR1L contains
the eight MSbs and the CCP1CON<5:4> contains the
two LSbs. This 10-bit value is represented by
CCPR1L:CCP1CON<5:4>. The following equation is
used to calculate the PWM duty cycle in time:
CCPR1H (Slave)
Comparator
RC2/CCP1
Q
R
S
(Note 1)
TMR2
PWM duty cycle = (CCPR1L:CCP1CON<5:4>)•
TOSC • (TMR2 prescale value)
TRISC<2>
Comparator
PR2
Clear Timer,
CCP1 pin and
latch D.C.
CCPR1L and CCP1CON<5:4> can be written to at any
time, but the duty cycle value is not latched into
CCPR1H until after a match between PR2 and TMR2
occurs (i.e., the period is complete). In PWM mode,
CCPR1H is a read only register.
Note 1: The 8-bit timer is concatenated with 2-bit internal Q
clock, or 2 bits of the prescaler to create 10-bit time-base.
A PWM output (Figure 8-4) has a time-base (period)
and a time that the output stays high (duty cycle). The
frequency of the PWM is the inverse of the period
(1/period).
The CCPR1H register and a 2-bit internal latch are
used to double buffer the PWM duty cycle. This double
buffering is essential for glitch-free PWM operation.
When the CCPR1H and 2-bit latch match TMR2, con-
catenated with an internal 2-bit Q clock or 2 bits of the
TMR2 prescaler, the CCP1 pin is cleared.
FIGURE 8-4:
PWM OUTPUT
The maximum PWM resolution (bits) for a given PWM
frequency is given by the formula:
Period
FOSC
log( )
FPWM
Resolution
bits
=
Duty Cycle
log(2)
TMR2 = PR2
Note: If the PWM duty cycle value is longer than
the PWM period, the CCP1 pin will not be
cleared.
TMR2 = Duty Cycle
TMR2 = PR2
DS30221B-page 48
2002 Microchip Technology Inc.
PIC16F872
3. Make the CCP1 pin an output by clearing the
TRISC<2> bit.
8.3.3
SETUP FOR PWM OPERATION
The following steps should be taken when configuring
the CCP module for PWM operation:
4. Set the TMR2 prescale value and enable Timer2
by writing to T2CON.
1. Set the PWM period by writing to the PR2
register.
5. Configure the CCP1 module for PWM operation.
2. Set the PWM duty cycle by writing to the
CCPR1L register and CCP1CON<5:4> bits.
TABLE 8-3:
EXAMPLE PWM FREQUENCIES AND RESOLUTIONS AT 20 MHz
PWM Frequency
1.22 kHz 4.88 kHz 19.53 kHz
78.12kHz
156.3 kHz 208.3 kHz
Timer Prescaler (1, 4, 16)
PR2 Value
16
FFh
10
4
1
1
3Fh
8
1
1Fh
7
1
FFh
10
FFh
10
17h
5.5
Maximum Resolution (bits)
TABLE 8-4:
REGISTERS ASSOCIATED WITH PWM AND TIMER2
Value on: Value on
Address
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
POR,
BOR
all other
RESETS
0Bh,8Bh,
INTCON
GIE
PEIE
TMR0IE
INTE
RBIE
TMR0IF
INTF
RBIF
0000 000x 0000 000u
10Bh, 18Bh
0Ch
8Ch
87h
11h
92h
12h
15h
16h
17h
PIR1
(1)
(1)
ADIF
ADIE
(1)
(1)
(1)
(1)
SSPIF
SSPIE
CCP1IF TMR2IF TMR1IF 0000 0000 0000 0000
CCP1IE TMR2IE TMR1IE r0rr 0000 0000 0000
1111 1111 1111 1111
PIE1
TRISC
TMR2
PR2
PORTC Data Direction Register
Timer2 Modules Register
0000 0000 0000 0000
Timer2 Module Period Register
1111 1111 1111 1111
T2CON
—
TOUTPS3 TOUTPS2 TOUTPS1 TOUTPS0 TMR2ON T2CKPS1 T2CKPS0 -000 0000 -000 0000
CCPR1L Capture/Compare/PWM Register1 (LSB)
CCPR1H Capture/Compare/PWM Register1 (MSB)
xxxx xxxx uuuu uuuu
xxxx xxxx uuuu uuuu
CCP1CON
—
—
CCP1X
CCP1Y CCP1M3 CCP1M2 CCP1M1 CCP1M0 --00 0000 --00 0000
Legend: x= unknown, u= unchanged, -= unimplemented read as '0'. Shaded cells are not used by PWM and Timer2.
Note 1: These bits are reserved; always maintain clear.
2002 Microchip Technology Inc.
DS30221B-page 49
PIC16F872
NOTES:
DS30221B-page 50
2002 Microchip Technology Inc.
PIC16F872
The MSSP module is controlled by three special func-
tion registers:
9.0
MASTER SYNCHRONOUS
SERIAL PORT (MSSP)
MODULE
• SSPSTAT
• SSPCON
• SSPCON2
The Master Synchronous Serial Port (MSSP) module is
a serial interface useful for communicating with other
peripheral or microcontroller devices. These peripheral
devices may be serial EEPROMs, shift registers, dis-
play drivers, A/D converters, etc. The MSSP module
can operate in one of two modes:
The SSPSTAT and SSPCON registers are used in both
SPI and I2C modes; their individual bits take on differ-
ent functions depending on the mode selected. The
SSPCON2 register, on the other hand, is associated
only with I2C operations. The registers are detailed in
Registers 9-1 through 9-3 on the following pages.
• Serial Peripheral Interface (SPI)
• Inter-Integrated Circuit (I2C)
The operation of the module in SPI mode is discussed
in greater detail in Section 9.1. The operations of the
module in the the various I2C modes are covered in
Section 9.2, while special considerations for connect-
ing the I2C bus are discussed in Section 9.3.
2002 Microchip Technology Inc.
DS30221B-page 51
PIC16F872
REGISTER 9-1:
SSPSTAT: SYNC SERIAL PORT STATUS REGISTER (ADDRESS: 94h)
R/W-0
SMP
R/W-0
CKE
R-0
D/A
R-0
P
R-0
S
R-0
R-0
UA
R-0
BF
R/W
bit 7
bit 0
bit 7
SMP: Sample bit
SPI Master mode:
1= Input data sampled at end of data output time
0= Input data sampled at middle of data output time
SPI Slave mode:
SMP must be cleared when SPI is used in Slave mode
2
In I C Master or Slave mode:
1= Slew rate control disabled for Standard Speed mode (100 kHz and 1 MHz)
0= Slew rate control enabled for High Speed mode (400 kHz)
bit 6
CKE: SPI Clock Edge Select bit (Figure 9-2, Figure 9-3 and Figure 9-4)
SPI mode:
For CKP = 0
1= Transmit happens on transition from active clock state to idle clock state
0= Transmit happens on transition from idle clock state to active clock state
For CKP = 1
1= Data transmitted on falling edge of SCK
0= Data transmitted on rising edge of SCK
2
In I C Master or Slave mode:
1= Input levels conform to SMBus spec
2
0= Input levels conform to I C specs
2
bit 5
bit 4
D/A: Data/Address bit (I C mode only)
1= Indicates that the last byte received or transmitted was data
0= Indicates that the last byte received or transmitted was address
P: STOP bit
2
(I C mode only. This bit is cleared when the MSSP module is disabled, SSPEN is cleared.)
1= Indicates that a STOP bit has been detected last (this bit is ’0’ on RESET)
0= STOP bit was not detected last
bit 3
bit 2
S: START bit
2
(I C mode only. This bit is cleared when the MSSP module is disabled, SSPEN is cleared.)
1= Indicates that a START bit has been detected last (this bit is ’0’ on RESET)
0= START bit was not detected last
2
R/W: Read/Write bit information (I C mode only)
This bit holds the R/W bit information following the last address match. This bit is only valid from the
address match to the next START bit, STOP bit or not ACK bit.
2
In I C Slave mode:
1= Read
0= Write
2
In I C Master mode:
1= Transmit is in progress
0= Transmit is not in progress.
Logical OR of this bit with SEN, RSEN, PEN, RCEN or ACKEN will indicate if the MSSP is in IDLE
mode.
2
bit 1
bit 0
UA: Update Address bit (10-bit I C mode only)
1= Indicates that the user needs to update the address in the SSPADD register
0= Address does not need to be updated
BF: Buffer Full Status bit
2
Receive (SPI and I C modes):
1= Receive complete, SSPBUF is full
0= Receive not complete, SSPBUF is empty
2
Transmit (I C mode only):
1= Data Transmit in progress (does not include the ACK and STOP bits), SSPBUF is full
0= Data Transmit complete (does not include the ACK and STOP bits), SSPBUF is empty
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
’0’ = Bit is cleared x = Bit is unknown
- n = Value at POR
’1’ = Bit is set
DS30221B-page 52
2002 Microchip Technology Inc.
PIC16F872
REGISTER 9-2:
SSPCON: SYNC SERIAL PORT CONTROL REGISTER (ADDRESS: 14h)
R/W-0
WCOL
R/W-0
R/W-0
R/W-0
CKP
R/W-0
R/W-0
R/W-0
R/W-0
SSPOV
SSPEN
SSPM3
SSPM2
SSPM1
SSPM0
bit 7
bit 0
bit 7
WCOL: Write Collision Detect bit
Master mode:
2
1= A write to SSPBUF was attempted while the I C conditions were not valid
0= No collision
Slave mode:
1= SSPBUF register is written while still transmitting the previous word (must be cleared in software)
0= No collision
bit 6
SSPOV: Receive Overflow Indicator bit
In SPI mode:
1= A new byte is received while SSPBUF holds previous data. Data in SSPSR is lost on overflow.
In Slave mode, the user must read the SSPBUF, even if only transmitting data, to avoid over-
flows. In Master mode, the overflow bit is not set since each operation is initiated by writing to
the SSPBUF register. (Must be cleared in software.)
0= No overflow
2
In I C mode:
1= A byte is received while the SSPBUF is holding the previous byte. SSPOV is a "don’t care" in
Transmit mode. (Must be cleared in software.)
0= No overflow
bit 5
SSPEN: Synchronous Serial Port Enable bit
In SPI mode:
When enabled, these pins must be properly configured as input or output.
1= Enables serial port and configures SCK, SDO, SDI, and SS as the source of the serial port pins
0= Disables serial port and configures these pins as I/O port pins
2
In I C mode:
When enabled, these pins must be properly configured as input or output.
1= Enables the serial port and configures the SDA and SCL pins as the source of the serial port pins
0= Disables serial port and configures these pins as I/O port pins
bit 4
CKP: Clock Polarity Select bit
In SPI mode:
1= IDLE state for clock is a high level
0= IDLE state for clock is a low level
2
In I C slave mode:
SCK release control
1= Enable clock
0= Holds clock low (clock stretch). (Used to ensure data setup time.)
2
In I C master mode:
Unused in this mode
bit 3-0
SSPM3:SSPM0: Synchronous Serial Port Mode Select bits
0000= SPI Master mode, clock = FOSC/4
0001= SPI Master mode, clock = FOSC/16
0010= SPI Master mode, clock = FOSC/64
0011= SPI Master mode, clock = TMR2 output/2
0100= SPI Slave mode, clock = SCK pin. SS pin control enabled.
0101= SPI Slave mode, clock = SCK pin. SS pin control disabled. SS can be used as I/O pin.
2
0110= I C Slave mode, 7-bit address
2
0111= I C Slave mode, 10-bit address
2
1000= I C Master mode, clock = FOSC / (4 * (SSPADD+1)
2
1011= I C Firmware Controlled Master mode (slave idle)
2
1110= I C Firmware Controlled Master mode, 7-bit address with START and STOP bit interrupts
enabled
2
1111= I C Firmware Controlled Master mode, 10-bit address with START and STOP bit interrupts
enabled
1001, 1010, 1100, 1101= reserved
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
’0’ = Bit is cleared x = Bit is unknown
- n = Value at POR
’1’ = Bit is set
2002 Microchip Technology Inc.
DS30221B-page 53
PIC16F872
REGISTER 9-3:
SSPCON2: SYNC SERIAL PORT CONTROL REGISTER2 (ADDRESS: 91h)
R/W-0
GCEN
R/W-0
R/W-0
R/W-0
R/W-0
RCEN
R/W-0
PEN
R/W-0
RSEN
R/W-0
SEN
ACKSTAT ACKDT
ACKEN
bit 7
bit 0
bit 7
bit 6
GCEN: General Call Enable bit (In I2C Slave mode only)
1= Enable interrupt when a general call address (0000h) is received in the SSPSR
0= General call address disabled
ACKSTAT: Acknowledge Status bit (In I2C Master mode only)
In Master Transmit mode:
1= Acknowledge was not received from slave
0= Acknowledge was received from slave
bit 5
bit 4
ACKDT: Acknowledge Data bit (In I2C Master mode only)
In Master Receive mode:
Value that will be transmitted when the user initiates an Acknowledge sequence at the end of
a receive.
1= Not Acknowledge
0= Acknowledge
ACKEN: Acknowledge Sequence Enable bit (In I2C Master mode only)
In Master Receive mode:
1= Initiate Acknowledge sequence on SDA and SCL pins, and transmit ACKDT data bit. Auto-
matically cleared by hardware.
0= Acknowledge sequence IDLE
bit 3
bit 2
RCEN: Receive Enable bit (In I2C Master mode only).
1= Enables Receive mode for I2C
0= Receive IDLE
PEN: STOP Condition Enable bit (In I2C Master mode only)
SCK Release Control:
1= Initiate STOP condition on SDA and SCL pins. Automatically cleared by hardware.
0= STOP condition IDLE
bit 1
bit 0
RSEN: Repeated START Condition Enabled bit (In I2C Master mode only)
1= Initiate Repeated START condition on SDA and SCL pins. Automatically cleared by
hardware.
0= Repeated START condition IDLE
SEN: START Condition Enabled bit (In I2C Master mode only)
1= Initiate START condition on SDA and SCL pins. Automatically cleared by hardware.
0= START condition IDLE
Note:
For bits ACKEN, RCEN, PEN, RSEN, SEN: If the I2C module is not in the IDLE
mode, this bit may not be set (no spooling), and the SSPBUF may not be written (or
writes to the SSPBUF are disabled).
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
’0’ = Bit is cleared x = Bit is unknown
- n = Value at POR
’1’ = Bit is set
DS30221B-page 54
2002 Microchip Technology Inc.
PIC16F872
FIGURE 9-1:
MSSP BLOCK DIAGRAM
(SPI MODE)
9.1
SPI Mode
The SPI mode allows 8 bits of data to be synchronously
transmitted and received, simultaneously. All four
modes of SPI are supported. To accomplish communi-
cation, typically three pins are used:
Internal
Data Bus
Read
Write
• Serial Data Out (SDO)
• Serial Data In (SDI)
• Serial Clock (SCK)
SSPBUF reg
Additionally, a fourth pin may be used when in a Slave
mode of operation:
SSPSR reg
Shift
Clock
SDI
bit0
• Slave Select (SS)
When initializing the SPI, several options need to be
specified. This is done by programming the appropriate
control bits (SSPCON<5:0> and SSPSTAT<7:6>).
These control bits allow the following to be specified:
SDO
Control
Enable
SS
• Master mode (SCK is the clock output)
• Slave mode (SCK is the clock input)
• Clock Polarity (IDLE state of SCK)
SS
Edge
Select
• Data input sample phase
(middle or end of data output time)
2
Clock Select
• Clock edge
(output data on rising/falling edge of SCK)
SSPM3:SSPM0
SMP:CKE
• Clock Rate (Master mode only)
4
TMR2 Output
2
2
• Slave Select mode (Slave mode only)
Edge
Select
Figure 9-4 shows the block diagram of the MSSP mod-
ule when in SPI mode.
TOSC
Prescaler
4, 16, 64
SCK
To enable the serial port, MSSP Enable bit, SSPEN
(SSPCON<5>) must be set. To reset or reconfigure SPI
mode, clear bit SSPEN, re-initialize the SSPCON reg-
isters, and then set bit SSPEN. This configures the
SDI, SDO, SCK and SS pins as serial port pins. For the
pins to behave as the serial port function, some must
have their data direction bits (in the TRIS register)
appropriately programmed. That is:
Data to TX/RX in SSPSR
Data Direction bit
9.1.1
MASTER MODE
The master can initiate the data transfer at any time
because it controls the SCK. The master determines
when the slave (Processor 2, Figure 9-5) is to broad-
cast data by the software protocol.
• SDI is automatically controlled by the SPI module
• SDO must have TRISC<5> cleared
• SCK (Master mode) must have TRISC<3>
In Master mode, the data is transmitted/received as
soon as the SSPBUF register is written to. If the SPI
module is only going to receive, the SDO output could
be disabled (programmed as an input). The SSPSR
register will continue to shift in the signal present on the
SDI pin at the programmed clock rate. As each byte is
received, it will be loaded into the SSPBUF register as
if a normal received byte (interrupts and status bits
appropriately set). This could be useful in receiver
applications as a “line activity monitor”.
cleared
• SCK (Slave mode) must have TRISC<3> set
• SS must have TRISA<5> set, and
• Register ADCON1 must be set in a way that pin
RA5 is configured as a digital I/O
Any serial port function that is not desired may be over-
ridden by programming the corresponding data direc-
tion (TRIS) register to the opposite value.
2002 Microchip Technology Inc.
DS30221B-page 55
PIC16F872
The clock polarity is selected by appropriately program-
ming bit CKP (SSPCON<4>). This, then, would give
waveforms for SPI communication as shown in
Figure 9-6, Figure 9-8 and Figure 9-9, where the MSb is
transmitted first. In Master mode, the SPI clock rate (bit
rate) is user programmable to be one of the following:
This allows a maximum bit clock frequency (at 20 MHz)
of 5.0 MHz.
Figure 9-6 shows the waveforms for Master mode.
When CKE = 1, the SDO data is valid before there is a
clock edge on SCK. The change of the input sample is
shown based on the state of the SMP bit. The time
when the SSPBUF is loaded with the received data is
shown.
• FOSC/4 (or TCY)
• FOSC/16 (or 4 • TCY)
• FOSC/64 (or 16 • TCY)
• Timer2 Output/2
FIGURE 9-2:
SPI MODE TIMING, MASTER MODE
SCK (CKP = 0,
CKE = 0)
SCK (CKP = 0,
CKE = 1)
SCK (CKP = 1,
CKE = 0)
SCK (CKP = 1,
CKE = 1)
bit2
bit7
bit6
bit5
bit3
bit1
bit0
bit4
SDO
SDI (SMP = 0)
bit7
bit0
SDI (SMP = 1)
SSPIF
bit7
bit0
While in SLEEP mode, the slave can transmit/receive
data. When a byte is received, the device will wake-up
from SLEEP.
9.1.2
SLAVE MODE
In Slave mode, the data is transmitted and received as
the external clock pulses appear on SCK. When the
last bit is latched, the interrupt flag bit SSPIF (PIR1<3>)
is set.
Note 1: When the SPI module is in Slave mode
with
SS
pin
control
enabled
(SSPCON<3:0> = 0100), the SPI module
will reset if the SS pin is set to VDD.
While in Slave mode, the external clock is supplied by
the external clock source on the SCK pin. This external
clock must meet the minimum high and low times, as
specified in the electrical specifications.
2: If the SPI is used in Slave mode with
CKE = '1', then SS pin control must be
enabled.
DS30221B-page 56
2002 Microchip Technology Inc.
PIC16F872
FIGURE 9-3:
SPI MODE TIMING (SLAVE MODE WITH CKE = 0)
SS (optional)
SCK (CKP = 0)
SCK (CKP = 1)
bit2
bit7
bit6
bit5
bit3
bit1
bit0
bit4
SDO
SDI (SMP = 0)
bit7
bit0
SSPIF
FIGURE 9-4:
SPI MODE TIMING (SLAVE MODE WITH CKE = 1)
SS
SCK (CKP = 0)
SCK (CKP = 1)
bit2
SDO
bit7
bit6
bit5
bit3
bit1
bit0
bit4
SDI (SMP = 0)
SSPIF
bit7
bit0
TABLE 9-1:
REGISTERS ASSOCIATED WITH SPI OPERATION
Value on:
POR,
BOR
Value on
all other
RESETS
Address
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
0Bh, 8Bh,
INTCON
GIE
PEIE TMR0IE INTE RBIE TMR0IF
INTF
RBIF
0000 000x 0000 000u
10Bh, 18Bh
0Ch
8Ch
13h
14h
PIR1
(1)
(1)
ADIF
ADIE
(1)
(1)
(1)
(1)
SSPIF CCP1IF TMR2IF TMR1IF r0rr 0000 0000 0000
SSPIE CCP1IE TMR2IE TMR1IE r0rr 0000 0000 0000
PIE1
SSPBUF
SSPCON
Synchronous Serial Port Receive Buffer/Transmit Register
WCOL SSPOV SSPEN CKP SSPM3 SSPM2 SSPM1 SSPM0 0000 0000 0000 0000
SMP CKE D/A R/W UA BF 0000 0000 0000 0000
xxxx xxxx uuuu uuuu
94h
SSPSTAT
P
S
Legend: x= unknown, u= unchanged, -= unimplemented, read as ’0’. Shaded cells are not used by the SSP in SPI mode.
Note 1: These bits are reserved; always maintain these bits clear.
2002 Microchip Technology Inc.
DS30221B-page 57
PIC16F872
The SSPCON register allows control of the I2C opera-
tion. Four mode selection bits (SSPCON<3:0>) allow
one of the following I2C modes to be selected:
• I2C Slave mode (7-bit address)
• I2C Slave mode (10-bit address)
• I2C Master mode, clock = OSC/4 (SSPADD +1)
Before selecting any I2C mode, the SCL and SDA pins
must be programmed to inputs by setting the appropri-
ate TRIS bits. Selecting an I2C mode by setting the
SSPEN bit, enables the SCL and SDA pins to be used
as the clock and data lines in I2C mode. Pull-up resis-
tors must be provided externally to the SCL and SDA
pins for the proper operation of the I2C module.
2
9.2
MSSP I C Operation
The MSSP module in I2C mode, fully implements all
master and slave functions (including general call sup-
port) and provides interrupts on START and STOP bits
in hardware to determine a free bus (multi-master func-
tion). The MSSP module implements the standard
mode specifications, as well as 7-bit and 10-bit
addressing.
Refer to Application Note (AN578), "Use of the SSP
Module in the I 2C Multi-Master Environment."
A "glitch" filter is on the SCL and SDA pins when the pin
is an input. This filter operates in both the 100 kHz and
400 kHz modes. In the 100 kHz mode, when these pins
are an output, there is a slew rate control of the pin that
is independent of device frequency.
The CKE bit (SSPSTAT<6:7>) sets the levels of the
SDA and SCL pins in either Master or Slave mode.
When CKE = 1, the levels will conform to the SMBus
specification. When CKE = 0, the levels will conform to
the I2C specification.
FIGURE 9-5:
I2C SLAVE MODE BLOCK
DIAGRAM
The SSPSTAT register gives the status of the data
transfer. This information includes detection of a
START (S) or STOP (P) bit, specifies if the received
byte was data or address, if the next byte is the com-
pletion of 10-bit address, and if this will be a read or
write data transfer.
Internal
Data Bus
Read
Write
SSPBUF reg
SCL
SDA
Shift
Clock
SSPBUF is the register to which the transfer data is
written to or read from. The SSPSR register shifts the
data in or out of the device. In receive operations, the
SSPBUF and SSPSR create a doubled buffered
receiver. This allows reception of the next byte to begin
before reading the last byte of received data. When the
complete byte is received, it is transferred to the
SSPBUF register and flag bit SSPIF is set. If another
complete byte is received before the SSPBUF register
is read, a receiver overflow has occurred and bit
SSPOV (SSPCON<6>) is set and the byte in the
SSPSR is lost.
SSPSR reg
MSb
LSb
Addr Match
Match Detect
SSPADD reg
START and
Set, Reset
S, P bits
(SSPSTAT reg)
STOP bit Detect
The SSPADD register holds the slave address. In
10-bit mode, the user needs to write the high byte of the
address (1111 0 A9 A8 0). Following the high byte
address match, the low byte of the address needs to be
loaded (A7:A0).
Two pins are used for data transfer. These are the SCL
pin, which is the clock, and the SDA pin, which is the
data. The SDA and SCL pins are automatically config-
ured when the I2C mode is enabled. The SSP module
functions are enabled by setting SSP Enable bit
SSPEN (SSPCON<5>).
9.2.1
SLAVE MODE
In Slave mode, the SCL and SDA pins must be config-
ured as inputs. The MSSP module will override the
input state with the output data when required (slave-
transmitter).
The MSSP module has six registers for I2C operation.
They are the:
• SSP Control Register (SSPCON)
• SSP Control Register2 (SSPCON2)
• SSP Status Register (SSPSTAT)
• Serial Receive/Transmit Buffer (SSPBUF)
When an address is matched, or the data transfer after
an address match is received, the hardware automati-
cally will generate the Acknowledge (ACK) pulse, and
then load the SSPBUF register with the received value
currently in the SSPSR register.
• SSP Shift Register (SSPSR) - Not directly
accessible
• SSP Address Register (SSPADD)
DS30221B-page 58
2002 Microchip Technology Inc.
PIC16F872
There are certain conditions that will cause the MSSP
module not to give this ACK pulse. These are if either
(or both):
1. Receive first (high) byte of Address (bits SSPIF,
BF and UA (SSPSTAT<1>) are set).
2. Update the SSPADD register with the second
(low) byte of Address (clears bit UA and
releases the SCL line).
a) The buffer full bit BF (SSPSTAT<0>) was set
before the transfer was received.
3. Read the SSPBUF register (clears bit BF) and
clear flag bit SSPIF.
b) The overflow bit SSPOV (SSPCON<6>) was set
before the transfer was received.
4. Receive second (low) byte of Address (bits
SSPIF, BF and UA are set).
If the BF bit is set, the SSPSR register value is not
loaded into the SSPBUF, but bit SSPIF and SSPOV are
set. Table 9-2 shows what happens when a data trans-
fer byte is received, given the status of bits BF and
SSPOV. The shaded cells show the condition where
user software did not properly clear the overflow condi-
tion. Flag bit BF is cleared by reading the SSPBUF reg-
ister, while bit SSPOV is cleared through software.
5. Update the SSPADD register with the first (high)
byte of Address. This will clear bit UA and
release the SCL line.
6. Read the SSPBUF register (clears bit BF) and
clear flag bit SSPIF.
7. Receive Repeated START condition.
The SCL clock input must have a minimum high and
low time for proper operation. The high and low times
of the I2C specification, as well as the requirement of
the MSSP module, is shown in timing parameter #100
and parameter #101 of the electrical specifications.
8. Receive first (high) byte of Address (bits SSPIF
and BF are set).
9. Read the SSPBUF register (clears bit BF) and
clear flag bit SSPIF.
Note: Following the Repeated START condition
(step 7) in 10-bit mode, the user only
needs to match the first 7-bit address. The
user does not update the SSPADD for the
second half of the address.
9.2.1.1
Addressing
Once the MSSP module has been enabled, it waits for
a START condition to occur. Following the START con-
dition, the 8-bits are shifted into the SSPSR register. All
incoming bits are sampled with the rising edge of the
clock (SCL) line. The value of register SSPSR<7:1> is
compared to the value of the SSPADD register. The
address is compared on the falling edge of the eighth
clock (SCL) pulse. If the addresses match, and the BF
and SSPOV bits are clear, the following events occur:
9.2.1.2
Slave Reception
When the R/W bit of the address byte is clear and an
address match occurs, the R/W bit of the SSPSTAT
register is cleared. The received address is loaded into
the SSPBUF register.
When the address byte overflow condition exists, then
no Acknowledge (ACK) pulse is given. An overflow
condition is defined as either bit BF (SSPSTAT<0>) is
set, or bit SSPOV (SSPCON<6>) is set. This is an error
condition due to user firmware.
a) The SSPSR register value is loaded into the
SSPBUF register on the falling edge of the 8th
SCL pulse.
b) The buffer full bit, BF, is set on the falling edge
of the 8th SCL pulse.
An SSP interrupt is generated for each data transfer
byte. Flag bit SSPIF (PIR1<3>) must be cleared in soft-
ware. The SSPSTAT register is used to determine the
status of the received byte.
c) An ACK pulse is generated.
d) SSP interrupt flag bit, SSPIF (PIR1<3>), is set
(interrupt is generated if enabled) on the falling
edge of the 9th SCL pulse.
In 10-bit Address mode, two address bytes need to be
received by the slave. The five Most Significant bits
(MSbs) of the first address byte specify if this is a 10-bit
address. Bit R/W (SSPSTAT<2>) must specify a write,
so the slave device will receive the second address
byte. For a 10-bit address the first byte would equal
‘1111 0 A9 A8 0’, where A9 and A8 are the two
MSbs of the address. The sequence of events for a
10-bit address is as follows, with steps 7-9 for slave
transmitter:
Note: The SSPBUF will be loaded if the SSPOV
bit is set and the BF flag is cleared. If a
read of the SSPBUF was performed, but
the user did not clear the state of the
SSPOV bit before the next receive
occurred, the ACK is not sent and the
SSPBUF is updated.
2002 Microchip Technology Inc.
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TABLE 9-2:
DATA TRANSFER RECEIVED BYTE ACTIONS
Status Bits as Data
Transfer is Received
Set bit SSPIF
(SSP Interrupt occurs
if enabled)
Generate ACK
Pulse
BF
SSPOV
SSPSR → SSPBUF
0
1
1
0
0
0
1
1
Yes
No
Yes
No
No
No
Yes
Yes
Yes
Yes
No
Yes
Note: Shaded cells show the conditions where the user software did not properly clear the overflow condition.
An SSP interrupt is generated for each data transfer
byte. The SSPIF flag bit must be cleared in software
and the SSPSTAT register is used to determine the sta-
tus of the byte transfer. The SSPIF flag bit is set on the
falling edge of the ninth clock pulse.
9.2.1.3
Slave Transmission
When the R/W bit of the incoming address byte is set
and an address match occurs, the R/W bit of the
SSPSTAT register is set. The received address is
loaded into the SSPBUF register. The ACK pulse will
be sent on the ninth bit, and the SCL pin is held low.
The transmit data must be loaded into the SSPBUF
register, which also loads the SSPSR register. Then the
SCL pin should be enabled by setting bit CKP
(SSPCON<4>). The master must monitor the SCL pin
prior to asserting another clock pulse. The slave
devices may be holding off the master by stretching the
clock. The eight data bits are shifted out on the falling
edge of the SCL input. This ensures that the SDA sig-
nal is valid during the SCL high time (Figure 9-7).
As a slave-transmitter, the ACK pulse from the master
receiver is latched on the rising edge of the ninth SCL
input pulse. If the SDA line is high (Not ACK), then the
data transfer is complete. When the Not ACK is latched
by the slave, the slave logic is reset and the slave then
monitors for another occurrence of the START bit. If the
SDA line was low (ACK), the transmit data must be
loaded into the SSPBUF register, which also loads the
SSPSR register. Then, the SCL pin should be enabled
by setting the CKP bit.
FIGURE 9-6:
I2C WAVEFORMS FOR RECEPTION (7-BIT ADDRESS)
R/W=0
ACK
Not
ACK
Receiving Address
A7 A6 A5 A4
Receiving Data
Receiving Data
ACK
SDA
A3 A2 A1
D5
D2
D0
8
D5
D2
D0
8
D7 D6
D4 D3
D7 D6
D4 D3
D1
7
D1
7
3
9
7
1
2
4
9
5
4
3
6
9
5
6
1
2
3
6
1
2
4
8
5
P
SCL
S
SSPIF
Bus Master
terminates
transfer
BF (SSPSTAT<0>)
Cleared in software
SSPBUF register is read
SSPOV (SSPCON<6>)
Bit SSPOV is set because the SSPBUF register is still full
ACK is not sent
DS30221B-page 60
2002 Microchip Technology Inc.
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FIGURE 9-7:
I2C WAVEFORMS FOR TRANSMISSION (7-BIT ADDRESS)
R/W = 0
Transmitting Data Not ACK
R/W = 1
ACK
Receiving Address
SDA
A7 A6 A5 A4 A3 A2 A1
D7 D6 D5 D4 D3 D2 D1 D0
SCL
S
1
2
3
4
5
6
7
8
9
1
2
3
4
5
6
7
8
9
P
SCL held low
while CPU
responds to SSPIF
Data in
sampled
SSPIF
BF (SSPSTAT<0>)
Cleared in software
SSPBUF is written in software
From SSP Interrupt
Service Routine
CKP (SSPCON<4>)
Set bit after writing to SSPBUF
(the SSPBUF must be written to
before the CKP bit can be set)
If the general call address matches, the SSPSR is
transferred to the SSPBUF, the BF flag is set (eighth
bit), and on the falling edge of the ninth bit (ACK bit),
the SSPIF flag is set.
9.2.2
GENERAL CALL ADDRESS
SUPPORT
The addressing procedure for the I2C bus is such that
the first byte after the START condition usually deter-
mines which device will be the slave addressed by the
master. The exception is the general call address,
which can address all devices. When this address is
used, all devices should, in theory, respond with an
Acknowledge.
When the interrupt is serviced, the source for the inter-
rupt can be checked by reading the contents of the
SSPBUF, to determine if the address was device spe-
cific or a general call address.
In 10-bit mode, the SSPADD is required to be updated
for the second half of the address to match, and the UA
bit is set (SSPSTAT<1>). If the general call address is
sampled when GCEN is set while the slave is config-
ured in 10-bit Address mode, then the second half of
the address is not necessary, the UA bit will not be set,
and the slave will begin receiving data after the
Acknowledge (Figure 9-8).
The general call address is one of eight addresses
reserved for specific purposes by the I2C protocol. It
consists of all 0’s with R/W = 0.
The general call address is recognized when the Gen-
eral Call Enable bit (GCEN) is enabled (SSPCON2<7>
is set). Following a START bit detect, 8-bits are shifted
into SSPSR and the address is compared against
SSPADD. It is also compared to the general call
address and fixed in hardware.
FIGURE 9-8:
SLAVE MODE GENERAL CALL ADDRESS SEQUENCE (7 OR 10-BIT MODE)
Address is compared to General Call Address
after ACK, set interrupt flag
Receiving Data
D5 D4 D3 D2 D1
ACK
R/W = 0
ACK
General Call Address
SDA
SCL
D7 D6
D0
8
1
2
3
4
5
6
7
8
9
1
2
3
4
5
6
7
9
S
SSPIF
BF
(SSPSTAT<0>)
Cleared in software
SSPBUF is read
SSPOV
(SSPCON<6>)
’0’
’1’
GCEN
(SSPCON2<7>)
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9.2.3
SLEEP OPERATION
9.2.4
EFFECTS OF A RESET
While in SLEEP mode, the I2C module can receive
addresses or data. When an address match or com-
plete byte transfer occurs, wake the processor from
SLEEP (if the SSP interrupt is enabled).
A RESET disables the SSP module and terminates the
current transfer.
TABLE 9-3:
REGISTERS ASSOCIATED WITH I2C OPERATION
Value on:
POR,
BOR
Value on
all other
RESETS
Address
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
0Bh, 8Bh, INTCON
10Bh,18Bh
GIE
PEIE
TMR0IE INTE
RBIE TMR0IF INTF
RBIF 0000 000x 0000 000u
0Ch
8Ch
0Dh
8Dh
13h
14h
91h
94h
PIR1
(1)
(1)
—
ADIF
ADIE
(1)
(1)
(1)
—
(1)
(1)
SSPIF CCP1IF TMR2IF TMR1IF 0000 0000 0000 0000
SSPIE CCP1IE TMR2IE TMR1IE r0rr 0000 0000 0000
PIE1
PIR2
EEIF
BCLIF
—
—
(1)
(1)
CCP2IF -r-0 0--0 -r-0 0--0
CCP2IE -r-0 0--r -r-0 0--r
xxxx xxxx uuuu uuuu
PIE2
—
(1)
—
EEIE BCLIE
SSPBUF
SSPCON
SSPCON2
SSPSTAT
Synchronous Serial Port Receive Buffer/Transmit Register
WCOL SSPOV SSPEN
GCEN ACKSTAT ACKDT ACKEN RCEN
SMP CKE D/A
CKP SSPM3 SSPM2 SSPM1 SSPM0 0000 0000 0000 0000
PEN
R/W
RSEN
UA
SEN 0000 0000 0000 0000
P
S
BF
0000 0000 0000 0000
2
Legend: x= unknown, u= unchanged, -= unimplemented, read as '0'. Shaded cells are not used by the SSP in I C mode.
Note 1: These bits are reserved; always maintain these bits clear.
DS30221B-page 62
2002 Microchip Technology Inc.
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The following events will cause the SSP Interrupt Flag
bit, SSPIF, to be set (an SSP Interrupt will occur if
enabled):
9.2.5
MASTER MODE
Master mode of operation is supported by interrupt
generation on the detection of the START and STOP
conditions. The STOP (P) and START (S) bits are
cleared from a RESET or when the MSSP module is
disabled. Control of the I2C bus may be taken when the
P bit is set, or the bus is IDLE, with both the S and P
bits clear.
• START condition
• STOP condition
• Data transfer byte transmitted/received
• Acknowledge transmit
• Repeated START
In Master mode, the SCL and SDA lines are manipu-
lated by the MSSP hardware.
2
FIGURE 9-9:
SSP BLOCK DIAGRAM (I C MASTER MODE)
Internal
Data Bus
SSPM3:SSPM0,
SSPADD<6:0>
Read
Write
SSPBUF
SSPSR
Baud
Rate
Generator
SDA
Shift
Clock
SDA In
MSb
LSb
START bit, STOP bit,
Acknowledge
Generate
SCL
START bit Detect,
STOP bit Detect
Write Collision Detect
Clock Arbitration
SCL In
Bus Collision
Set/Reset, S, P, WCOL (SSPSTAT)
Set SSPIF, BCLIF
Reset ACKSTAT, PEN (SSPCON2)
State Counter for
End of XMIT/RCV
The states where arbitration can be lost are:
9.2.6
MULTI-MASTER MODE
• Address Transfer
In Multi-Master mode, the interrupt generation on the
detection of the START and STOP conditions allows
the determination of when the bus is free. The STOP
(P) and START (S) bits are cleared from a RESET or
when the MSSP module is disabled. Control of the I2C
bus may be taken when bit P (SSPSTAT<4>) is set, or
the bus is IDLE with both the S and P bits clear. When
the bus is busy, enabling the SSP interrupt will gener-
ate the interrupt when the STOP condition occurs.
• Data Transfer
• A START Condition
• A Repeated START Condition
• An Acknowledge Condition
In Multi-Master operation, the SDA line must be moni-
tored for arbitration to see if the signal level is the
expected output level. This check is performed in hard-
ware, with the result placed in the BCLIF bit.
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I2C MASTER MODE SUPPORT
will automatically begin counting on a write to the
SSPBUF. Once the given operation is complete (i.e.,
transmission of the last data bit is followed by ACK) the
internal clock will automatically stop counting and the
SCL pin will remain in its last state
9.2.7
Master mode is enabled by setting and clearing the
appropriate SSPM bits in SSPCON and by setting the
SSPEN bit. Once Master mode is enabled, the user
has six options.
A typical transmit sequence would go as follows:
• Assert a START condition on SDA and SCL.
a) The user generates a Start Condition by setting
the START enable bit (SEN) in SSPCON2.
• Assert a Repeated START condition on SDA and
SCL.
b) SSPIF is set. The module will wait the required
start time before any other operation takes place.
• Write to the SSPBUF register, initiating transmis-
sion of data/address.
c) The user loads the SSPBUF with address to
transmit.
• Generate a STOP condition on SDA and SCL.
• Configure the I2C port to receive data.
d) Address is shifted out the SDA pin until all 8 bits
are transmitted.
• Generate an Acknowledge condition at the end of
a received byte of data.
e) The MSSP module shifts in the ACK bit from the
slave device and writes its value into the
SSPCON2 register (SSPCON2<6>).
Note: The MSSP module, when configured in I2C
Master mode, does not allow queueing of
events. For instance, the user is not
allowed to initiate a START condition and
immediately write the SSPBUF register to
initiate transmission, before the START
condition is complete. In this case, the
SSPBUF will not be written to and the
WCOL bit will be set, indicating that a write
to the SSPBUF did not occur.
f) The module generates an interrupt at the end of
the ninth clock cycle by setting SSPIF.
g) The user loads the SSPBUF with eight bits of data.
h) DATA is shifted out the SDA pin until all 8 bits are
transmitted.
i) The MSSP module shifts in the ACK bit from the
slave device, and writes its value into the
SSPCON2 register (SSPCON2<6>).
j) The MSSP module generates an interrupt at the
end of the ninth clock cycle by setting the SSPIF bit.
9.2.7.1
I2C Master Mode Operation
The master device generates all of the serial clock
pulses and the START and STOP conditions. A trans-
fer is ended with a STOP condition or with a Repeated
START condition. Since the Repeated START condi-
tion is also the beginning of the next serial transfer, the
I2C bus will not be released.
k) The user generates a STOP condition by setting
the STOP enable bit PEN in SSPCON2.
l) Interrupt is generated once the STOP condition
is complete.
9.2.8
BAUD RATE GENERATOR
In Master Transmitter mode, serial data is output
through SDA, while SCL outputs the serial clock. The
first byte transmitted contains the slave address of the
receiving device (7 bits) and the Read/Write (R/W) bit.
In this case, the R/W bit will be logic '0'. Serial data is
transmitted 8 bits at a time. After each byte is transmit-
ted, an Acknowledge bit is received. START and STOP
conditions are output to indicate the beginning and the
end of a serial transfer.
In I2C Master mode, the reload value for the BRG is
located in the lower 7 bits of the SSPADD register
(Figure 9-10). When the BRG is loaded with this value,
the BRG counts down to 0 and stops until another reload
has taken place. The BRG count is decremented twice
per instruction cycle (TCY), on the Q2 and Q4 clock.
In I2C Master mode, the BRG is reloaded automatically.
If Clock Arbitration is taking place, for instance, the
BRG will be reloaded when the SCL pin is sampled
high (Figure 9-11).
In Master Receive mode, the first byte transmitted con-
tains the slave address of the transmitting device
(7 bits) and the R/W bit. In this case, the R/W bit will be
logic '1'. Thus, the first byte transmitted is a 7-bit slave
address followed by a '1' to indicate receive bit. Serial
data is received via SDA, while SCL outputs the serial
clock. Serial data is received 8 bits at a time. After each
byte is received, an Acknowledge bit is transmitted.
START and STOP conditions indicate the beginning
and end of transmission.
FIGURE 9-10:
BAUD RATE GENERATOR
BLOCK DIAGRAM
SSPM3:SSPM0
SSPADD<6:0>
Reload
Reload
SSPM3:SSPM0
SCL
The baud rate generator used for SPI mode operation
is now used to set the SCL clock frequency for either
100 kHz, 400 kHz or 1 MHz I2C operation. The baud
rate generator reload value is contained in the lower 7
bits of the SSPADD register. The baud rate generator
Control
FOSC/4
BRG Down Counter
CLKOUT
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2002 Microchip Technology Inc.
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FIGURE 9-11:
BAUD RATE GENERATOR TIMING WITH CLOCK ARBITRATION
SDA
DX
DX-1
SCL allowed to transition high
SCL de-asserted but slave holds
SCL low (clock arbitration)
SCL
BRG decrements
(on Q2 and Q4 cycles)
BRG
Value
03h
02h
01h
00h (hold off)
03h
02h
SCL is sampled high, reload takes
place, and BRG starts its count.
BRG
Reload
9.2.9
I2C MASTER MODE START
CONDITION TIMING
Note: If, at the beginning of START condition, the
SDA and SCL pins are already sampled
low, or if during the START condition, the
SCL line is sampled low before the SDA
line is driven low, a bus collision occurs,
the Bus Collision Interrupt Flag (BCLIF) is
set, the START condition is aborted, and
the I2C module is reset into its IDLE state.
To initiate a START condition, the user sets the START
condition enable bit, SEN (SSPCON2<0>). If the SDA
and SCL pins are sampled high, the baud rate genera-
tor is reloaded with the contents of SSPADD<6:0> and
starts its count. If SCL and SDA are both sampled high
when the baud rate generator times out (TBRG), the
SDA pin is driven low. The action of the SDA being
driven low while SCL is high is the START condition,
and causes the S bit (SSPSTAT<3>) to be set. Follow-
ing this, the baud rate generator is reloaded with the
contents of SSPADD<6:0> and resumes its count.
When the baud rate generator times out (TBRG), the
SEN bit (SSPCON2<0>) will be automatically cleared
by hardware. The baud rate generator is suspended,
leaving the SDA line held low, and the START condition
is complete.
9.2.9.1
WCOL Status Flag
If the user writes the SSPBUF when a START
sequence is in progress, then WCOL is set and the
contents of the buffer are unchanged (the write doesn’t
occur).
Note: Because queueing of events is not
allowed, writing to the lower 5 bits of
SSPCON2 is disabled until the START
condition is complete.
FIGURE 9-12:
FIRST START BIT TIMING
Set S bit (SSPSTAT<3>)
Write to SEN bit occurs here
SDA = 1,
At completion of START bit,
hardware clears SEN bit
and sets SSPIF bit
SCL = 1
TBRG
TBRG
Write to SSPBUF occurs here
2nd Bit
1st Bit
SDA
TBRG
SCL
TBRG
S
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I2C MASTER MODE REPEATED
START CONDITION TIMING
Immediately following the SSPIF bit getting set, the
user may write the SSPBUF with the 7-bit address in
7-bit mode, or the default first address in 10-bit mode.
After the first eight bits are transmitted and an ACK is
received, the user may then transmit an additional eight
bits of address (10-bit mode), or eight bits of data (7-bit
mode).
9.2.10
A Repeated START condition occurs when the RSEN
bit (SSPCON2<1>) is programmed high and the I2C
module is in the IDLE state. When the RSEN bit is set,
the SCL pin is asserted low. When the SCL pin is sam-
pled low, the baud rate generator is loaded with the
contents of SSPADD<6:0> and begins counting. The
SDA pin is released (brought high) for one baud rate
generator count (TBRG). When the baud rate generator
times out if SDA is sampled high, the SCL pin will be
de-asserted (brought high). When SCL is sampled
high, the baud rate generator is reloaded with the con-
tents of SSPADD<6:0> and begins counting. SDA and
SCL must be sampled high for one TBRG. This action is
then followed by assertion of the SDA pin (SDA is low)
for one TBRG, while SCL is high. Following this, the
RSEN bit in the SSPCON2 register will be automati-
cally cleared and the baud rate generator will not be
reloaded, leaving the SDA pin held low. As soon as a
START condition is detected on the SDA and SCL pins,
the S bit (SSPSTAT<3>) will be set. The SSPIF bit will
notbesetuntilthebaudrategeneratorhastimedout.
9.2.10.1
WCOL Status Flag
If the user writes the SSPBUF when a Repeated
START sequence is in progress, then WCOL is set and
the contents of the buffer are unchanged (the write
doesn’t occur).
Note: Because queueing of events is not
allowed, writing of the lower 5 bits of
SSPCON2 is disabled until the Repeated
START condition is complete.
Note 1: If RSEN is programmed while any other
event is in progress, it will not take effect.
2: A bus collision during the Repeated
START condition occurs if:
•
SDA is sampled low when SCL
goes from low to high.
•
SCL goes low before SDA is
asserted low. This may indicate that
another master is attempting to
transmit a data "1".
FIGURE 9-13:
REPEAT START CONDITION WAVEFORM
Set S (SSPSTAT<3>)
Write to SSPCON2
SDA = 1,
SCL = 1
occurs here.
At completion of START bit,
hardware clear RSEN bit
and set SSPIF
SDA = 1,
SCL(no change).
TBRG TBRG
TBRG
1st Bit
SDA
Write to SSPBUF occurs here
TBRG
Falling edge of ninth clock
End of Xmit
SCL
TBRG
Sr = Repeated START
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9.2.11
I2C MASTER MODE
TRANSMISSION
9.2.11.1
BF Status Flag
In Transmit mode, the BF bit (SSPSTAT<0>) is set
when the CPU writes to SSPBUF and is cleared when
all 8 bits are shifted out.
Transmission of a data byte, a 7-bit address, or either
half of a 10-bit address, is accomplished by simply writ-
ing a value to SSPBUF register. This action will set the
buffer full flag (BF) and allow the baud rate generator to
begin counting and start the next transmission. Each bit
of address/data will be shifted out onto the SDA pin
after the falling edge of SCL is asserted (see data hold
time spec). SCL is held low for one baud rate gener-
ator rollover count (TBRG). Data should be valid before
SCL is released high (see data setup time spec). When
the SCL pin is released high, it is held that way for
TBRG. The data on the SDA pin must remain stable for
that duration and some hold time after the next falling
edge of SCL. After the eighth bit is shifted out (the fall-
ing edge of the eighth clock), the BF flag is cleared and
the master releases SDA, allowing the slave device
being addressed to respond with an ACK bit during the
ninth bit time, if an address match occurs or if data was
received properly. The status of ACK is read into the
ACKDT on the falling edge of the ninth clock. If the
master receives an Acknowledge, the Acknowledge
status bit (ACKSTAT) is cleared. If not, the bit is set.
After the ninth clock, the SSPIF is set and the master
clock (baud rate generator) is suspended until the next
data byte is loaded into the SSPBUF, leaving SCL low
and SDA unchanged (Figure 9-14).
9.2.11.2
WCOL Status Flag
If the user writes the SSPBUF when a transmit is
already in progress (i.e., SSPSR is still shifting out a
data byte), then WCOL is set and the contents of the
buffer are unchanged (the write doesn’t occur).
WCOL must be cleared in software.
9.2.11.3
ACKSTAT Status Flag
In Transmit mode, the ACKSTAT bit (SSPCON2<6>) is
cleared when the slave has sent an Acknowledge
(ACK = 0), and is set when the slave does Not
Acknowledge (ACK = 1). A slave sends an Acknowl-
edge when it has recognized its address (including a
general call), or when the slave has properly received
its data.
After the write to the SSPBUF, each bit of address will
be shifted out on the falling edge of SCL, until all seven
address bits and the R/W bit are completed. On the fall-
ing edge of the eighth clock, the master will de-assert
the SDA pin allowing the slave to respond with an
Acknowledge. On the falling edge of the ninth clock, the
master will sample the SDA pin to see if the address
was recognized by a slave. The status of the ACK bit is
loaded into the ACKSTAT status bit (SSPCON2<6>).
Following the falling edge of the ninth clock transmis-
sion of the address, the SSPIF is set, the BF flag is
cleared, and the baud rate generator is turned off until
another write to the SSPBUF takes place, holding SCL
low and allowing SDA to float.
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FIGURE 9-14:
I C MASTER MODE TIMING (TRANSMISSION, 7 OR 10-BIT ADDRESS)
DS30221B-page 68
2002 Microchip Technology Inc.
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9.2.12
I2C MASTER MODE RECEPTION
9.2.12.1
BF Status Flag
In receive operation, BF is set when an address or data
byte is loaded into SSPBUF from SSPSR. It is cleared
when SSPBUF is read.
Master mode reception is enabled by programming the
receive enable bit, RCEN (SSPCON2<3>).
Note: The SSP module must be in an IDLE state
before the RCEN bit is set, or the RCEN bit
will be disregarded.
9.2.12.2
SSPOV Status Flag
In receive operation, SSPOV is set when 8 bits are
received into the SSPSR, and the BF flag is already set
from a previous reception.
The baud rate generator begins counting, and on each
rollover, the state of the SCL pin changes (high to low/
low to high), and data is shifted into the SSPSR. After
the falling edge of the eighth clock, the receive enable
flag is automatically cleared, the contents of the
SSPSR are loaded into the SSPBUF, the BF flag is set,
the SSPIF is set, and the baud rate generator is sus-
pended from counting, holding SCL low. The SSP is
now in IDLE state, awaiting the next command. When
the buffer is read by the CPU, the BF flag is automati-
cally cleared. The user can then send an Acknowledge
bit at the end of reception, by setting the Acknowledge
sequence enable bit, ACKEN (SSPCON2<4>).
9.2.12.3
WCOL Status Flag
If the user writes the SSPBUF when a receive is
already in progress (i.e., SSPSR is still shifting in a data
byte), then WCOL is set and the contents of the buffer
are unchanged (the write doesn’t occur).
2002 Microchip Technology Inc.
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FIGURE 9-15:
I C MASTER MODE TIMING (RECEPTION, 7-BIT ADDRESS)
DS30221B-page 70
2002 Microchip Technology Inc.
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sampled high (clock arbitration), the baud rate genera-
tor counts for TBRG. The SCL pin is then pulled low. Fol-
lowing this, the ACKEN bit is automatically cleared, the
baud rate generator is turned off, and the SSP module
then goes into IDLE mode (Figure 9-16).
9.2.13
ACKNOWLEDGE SEQUENCE
TIMING
An Acknowledge sequence is enabled by setting the
Acknowledge sequence enable bit, ACKEN
(SSPCON2<4>). When this bit is set, the SCL pin is
pulled low and the contents of the Acknowledge data bit
are presented on the SDA pin. If the user wishes to gen-
erate an Acknowledge, the ACKDT bit should be
cleared. If not, the user should set the ACKDT bit before
starting an Acknowledge sequence. The baud rate gen-
erator then counts for one rollover period (TBRG), and
the SCL pin is de-asserted high). When the SCL pin is
9.2.13.1
WCOL Status Flag
If the user writes the SSPBUF when an acknowledge
sequence is in progress, the WCOL is set and the con-
tents of the buffer are unchanged (the write doesn’t
occur).
FIGURE 9-16:
ACKNOWLEDGE SEQUENCE WAVEFORM
Acknowledge sequence starts here.
Write to SSPCON2,
ACKEN automatically cleared
ACKEN = 1, ACKDT = 0
TBRG
TBRG
SDA
SCL
D0
ACK
8
9
SSPIF
Cleared in
software
Set SSPIF at the end
of receive
Cleared in
software
Set SSPIF at the end
of Acknowledge sequence
Note: TBRG = one baud rate generator period.
Whenever the firmware decides to take control of the
bus, it will first determine if the bus is busy by checking
the S and P bits in the SSPSTAT register. If the bus is
busy, then the CPU can be interrupted (notified) when
a STOP bit is detected (i.e., bus is free).
9.2.14
STOP CONDITION TIMING
A STOP bit is asserted on the SDA pin at the end of a
receive/transmit, by setting the Stop Sequence Enable
bit PEN (SSPCON2<2>). At the end of a receive/
transmit, the SCL line is held low after the falling edge
of the ninth clock. When the PEN bit is set, the master
will assert the SDA line low. When the SDA line is sam-
pled low, the baud rate generator is reloaded and
counts down to 0. When the baud rate generator times
out, the SCL pin will be brought high, and one TBRG
(baud rate generator rollover count) later, the SDA pin
will be de-asserted. When the SDA pin is sampled high
while SCL is high, the P bit (SSPSTAT<4>) is set. A
TBRG later, the PEN bit is cleared and the SSPIF bit is
set (Figure 9-17).
9.2.14.1
WCOL Status Flag
If the user writes the SSPBUF when a STOP sequence
is in progress, then WCOL is set and the contents of the
buffer are unchanged (the write doesn’t occur).
2002 Microchip Technology Inc.
DS30221B-page 71
PIC16F872
FIGURE 9-17:
STOP CONDITION RECEIVE OR TRANSMIT MODE
SCL = 1 for TBRG, followed by SDA = 1 for TBRG
after SDA sampled high. P bit (SSPSTAT<4>) is set.
Write to SSPCON2,
set PEN
PEN bit (SSPCON2<2>) is cleared by
hardware and the SSPIF bit is set
Falling edge of
9th clock
TBRG
TBRG
SCL
ACK
SDA
P
TBRG
TBRG
SCL brought high after TBRG
SDA asserted low before rising edge of clock
to setup STOP condition.
Note: TBRG = one baud rate generator period.
9.2.15
CLOCK ARBITRATION
9.2.16
SLEEP OPERATION
Clock arbitration occurs when the master, during any
receive, transmit, or Repeated START/STOP condi-
tion, de-asserts the SCL pin (SCL allowed to float high).
When the SCL pin is allowed to float high, the baud rate
generator (BRG) is suspended from counting until the
SCL pin is actually sampled high. When the SCL pin is
sampled high, the baud rate generator is reloaded with
the contents of SSPADD<6:0> and begins counting.
This ensures that the SCL high time will always be at
least one BRG rollover count, in the event that the clock
is held low by an external device (Figure 9-18).
While in SLEEP mode, the I2C module can receive
addresses or data, and when an address match or
complete byte transfer occurs, wake the processor
from SLEEP (if the SSP interrupt is enabled).
9.2.17
EFFECTS OF A RESET
A RESET disables the SSP module and terminates the
current transfer.
FIGURE 9-18:
CLOCK ARBITRATION TIMING IN MASTER TRANSMIT MODE
BRG overflow,
release SCL.
If SCL = 1, load BRG with
SSPADD<6:0> and start count
to measure high time interval.
BRG overflow occurs,
release SCL. Slave device holds SCL low.
SCL = 1, BRG starts counting
clock high interval
SCL
SDA
SCL line sampled once every machine cycle (TOSC • 4).
Hold off BRG until SCL is sampled high.
TBRG
TBRG
TBRG
DS30221B-page 72
2002 Microchip Technology Inc.
PIC16F872
If a START, Repeated START, STOP or Acknowledge
condition was in progress when the bus collision
occurred, the condition is aborted, the SDA and SCL
lines are de-asserted, and the respective control bits in
the SSPCON2 register are cleared. When the user ser-
vices the bus collision Interrupt Service Routine, and if
the I2C bus is free, the user can resume communication
by asserting a START condition.
9.2.18
MULTI -MASTER
COMMUNICATION,
BUS COLLISION, AND
BUS ARBITRATION
Multi-Master mode support is achieved by bus arbitra-
tion. When the master outputs address/data bits onto
the SDA pin, arbitration takes place when the master
outputs a ’1’ on SDA, by letting SDA float high and
another master asserts a ’0’. When the SCL pin floats
high, data should be stable. If the expected data on
SDA is a ’1’ and the data sampled on the SDA pin = ’0’,
a bus collision has taken place. The master will set the
Bus Collision Interrupt Flag, BCLIF and reset the I2C
port to its IDLE state. (Figure 9-19).
The master will continue to monitor the SDA and SCL
pins, and if a STOP condition occurs, the SSPIF bit will
be set.
A write to the SSPBUF will start the transmission of
data at the first data bit, regardless of where the trans-
mitter left off when the bus collision occurred.
In Multi-Master mode, the interrupt generation on the
detection of START and STOP conditions allows the
determination of when the bus is free. Control of the I2C
bus can be taken when the P bit is set in the SSPSTAT
register, or the bus is IDLE and the S and P bits are
cleared.
If a transmit was in progress when the bus collision
occurred, the transmission is halted, the BF flag is
cleared, the SDA and SCL lines are de-asserted, and
the SSPBUF can be written to. When the user services
the bus collision Interrupt Service Routine, and if the
I2C bus is free, the user can resume communication by
asserting a START condition.
FIGURE 9-19:
BUS COLLISION TIMING FOR TRANSMIT AND ACKNOWLEDGE
Sample SDA. While SCL is high,
data doesn’t match what is driven
by the master.
SDA line pulled low
by another source
Data changes
while SCL = 0
Bus collision has occurred.
SDA released
by master
SDA
SCL
Set bus collision
interrupt
BCLIF
2002 Microchip Technology Inc.
DS30221B-page 73
PIC16F872
If the SDA pin is sampled low during this count, the
BRG is reset and the SDA line is asserted early
(Figure 9-22). If, however, a '1' is sampled on the SDA
pin, the SDA pin is asserted low at the end of the BRG
count. The baud rate generator is then reloaded and
counts down to 0. During this time, if the SCL pins are
sampled as '0', a bus collision does not occur. At the
end of the BRG count, the SCL pin is asserted low.
9.2.18.1
Bus Collision During a START
Condition
During a START condition, a bus collision occurs if:
a) SDA or SCL are sampled low at the beginning of
the START condition (Figure 9-20).
b) SCL is sampled low before SDA is asserted low.
(Figure 9-21).
During a START condition, both the SDA and the SCL
pins are monitored. If either the SDA pin or the SCL pin
is already low, then these events all occur:
Note: The reason that bus collision is not a factor
during a START condition, is that no two
bus masters can assert a START condition
at the exact same time. Therefore, one
master will always assert SDA before the
other. This condition does not cause a bus
collision, because the two masters must be
allowed to arbitrate the first address follow-
ing the START condition. If the address is
the same, arbitration must be allowed to
continue into the data portion, Repeated
START or STOP conditions.
• the START condition is aborted,
• and the BCLIF flag is set
• and the SSP module is reset to its IDLE state
(Figure 9-20).
The START condition begins with the SDA and SCL
pins de-asserted. When the SDA pin is sampled high,
the baud rate generator is loaded from SSPADD<6:0>
and counts down to 0. If the SCL pin is sampled low
while SDA is high, a bus collision occurs, because it is
assumed that another master is attempting to drive a
data '1' during the START condition.
FIGURE 9-20:
BUS COLLISION DURING START CONDITION (SDA ONLY)
SDA goes low before the SEN bit is set.
Set BCLIF,
S bit and SSPIF set because
SDA = 0, SCL = 1.
SDA
SCL
SEN
Set SEN, enable START
condition if SDA = 1, SCL=1
SEN cleared automatically because of bus collision.
SSP module reset into IDLE state.
SDA sampled low before
START condition.
Set BCLIF.
S bit and SSPIF set because
SDA = 0, SCL = 1.
BCLIF
SSPIF and BCLIF are
cleared in software
S
SSPIF
SSPIF and BCLIF are
cleared in software
DS30221B-page 74
2002 Microchip Technology Inc.
PIC16F872
FIGURE 9-21:
BUS COLLISION DURING START CONDITION (SCL = 0)
SDA = 0, SCL = 1
TBRG
TBRG
SDA
Set SEN, enable START
sequence if SDA = 1, SCL = 1
SCL
SEN
SCL = 0 before SDA = 0,
bus collision occurs. Set BCLIF.
SCL = 0 before BRG time-out,
Bus collision occurs. Set BCLIF.
BCLIF
Interrupts cleared
in software
S
’0’
’0’
’0’
’0’
SSPIF
FIGURE 9-22:
BRG RESET DUE TO SDA COLLISION DURING START CONDITION
SDA = 0, SCL = 1
Set S
Set SSPIF
Less than TBRG
TBRG
SDA pulled low by other master.
Reset BRG and assert SDA.
SDA
SCL
s
SCL pulled low after BRG
Time-out
SEN
Set SEN, enable START
sequence if SDA = 1, SCL = 1
’0’
BCLIF
S
SSPIF
Interrupts cleared
in software.
SDA = 0, SCL = 1
Set SSPIF
2002 Microchip Technology Inc.
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SDA is sampled high, the BRG is reloaded and begins
counting. If SDA goes from high to low before the BRG
times out, no bus collision occurs, because no two
masters can assert SDA at exactly the same time.
9.2.18.2
Bus Collision During a Repeated
START Condition
During a Repeated START condition, a bus collision
occurs if:
If, however, SCL goes from high to low before the BRG
times out and SDA has not already been asserted, a
bus collision occurs. In this case, another master is
attempting to transmit a data’1’ during the Repeated
START condition.
a) A low level is sampled on SDA when SCL goes
from low level to high level.
b) SCL goes low before SDA is asserted low, indi-
cating that another master is attempting to trans-
mit a data ’1’.
If, at the end of the BRG time-out, both SCL and SDA
are still high, the SDA pin is driven low, the BRG is
reloaded and begins counting. At the end of the count,
regardless of the status of the SCL pin, the SCL pin is
driven low and the Repeated START condition is com-
plete (Figure 9-23).
When the user de-asserts SDA and the pin is allowed
to float high, the BRG is loaded with SSPADD<6:0>
and counts down to 0. The SCL pin is then de-asserted,
and when sampled high, the SDA pin is sampled. If
SDA is low, a bus collision has occurred (i.e., another
master is attempting to transmit a data’0’). If, however,
FIGURE 9-23:
BUS COLLISION DURING A REPEATED START CONDITION (CASE 1)
SDA
SCL
Sample SDA when SCL goes high.
If SDA = 0, set BCLIF and release SDA and SCL.
RSEN
BCLIF
Cleared in software
’0’
’0’
’0’
S
’0’
SSPIF
FIGURE 9-24:
BUS COLLISION DURING REPEATED START CONDITION (CASE 2)
TBRG
TBRG
SDA
SCL
SCL goes low before SDA,
set BCLIF. Release SDA and SCL.
BCLIF
RSEN
Interrupt cleared
in software
’0’
’0’
’0’
’0’
S
SSPIF
DS30221B-page 76
2002 Microchip Technology Inc.
PIC16F872
The STOP condition begins with SDA asserted low.
When SDA is sampled low, the SCL pin is allowed to
float. When the pin is sampled high (clock arbitration),
the baud rate generator is loaded with SSPADD<6:0>
and counts down to 0. After the BRG times out, SDA is
sampled. If SDA is sampled low, a bus collision has
occurred. This is due to another master attempting to
drive a data ’0’. If the SCL pin is sampled low before
SDA is allowed to float high, a bus collision occurs. This
is a case of another master attempting to drive a data
’0’ (Figure 9-25).
9.2.18.3
Bus Collision During a STOP
Condition
Bus collision occurs during a STOP condition if:
a) After the SDA pin has been de-asserted and
allowed to float high, SDA is sampled low after
the BRG has timed out.
b) After the SCL pin is de-asserted, SCL is sam-
pled low before SDA goes high.
FIGURE 9-25:
BUS COLLISION DURING A STOP CONDITION (CASE 1)
SDA sampled
low after TBRG,
set BCLIF
TBRG
TBRG
TBRG
SDA
SDA asserted low
SCL
PEN
BCLIF
P
’0’
’0’
’0’
’0’
SSPIF
FIGURE 9-26:
BUS COLLISION DURING A STOP CONDITION (CASE 2)
TBRG
TBRG
TBRG
SDA
SCL goes low before SDA goes high,
set BCLIF
Assert SDA
SCL
PEN
BCLIF
P
’0’
’0’
SSPIF
2002 Microchip Technology Inc.
DS30221B-page 77
PIC16F872
2
VOL max = 0.4V at 3 mA, Rp min = (5.5-0.4)/0.003 =
1.7 kΩ. VDD, as a function of Rp, is shown in
Figure 9-27. The desired noise margin of 0.1 VDD for
the low level limits the maximum value of Rs. Series
resistors are optional and used to improve ESD
susceptibility.
9.3
Connection Considerations for I C
Bus
For standard mode I2C bus devices, the values of
resistors Rp and Rs in Figure 9-27 depend on the fol-
lowing parameters:
• Supply voltage
The bus capacitance is the total capacitance of wire,
connections, and pins. This capacitance limits the max-
imum value of Rp, due to the specified rise time
(Figure 9-27).
• Bus capacitance
• Number of connected devices
(input current + leakage current).
The SMP bit is the slew rate control enabled bit. This bit
is in the SSPSTAT register, and controls the slew rate
of the I/O pins when in I2C mode (master or slave).
The supply voltage limits the minimum value of resistor
Rp, due to the specified minimum sink current of 3 mA
at VOL max = 0.4V, for the specified output stages. For
example, with a supply voltage of VDD = 5V+10% and
FIGURE 9-27:
SAMPLE DEVICE CONFIGURATION FOR I2C BUS
VDD + 10%
DEVICE
Rp
Rp
Rs
Rs
SDA
SCL
C =10 - 400 pF
b
2
Note: I C devices with input levels related to VDD must have one common supply line to which the pull-up resistor is
also connected.
DS30221B-page 78
2002 Microchip Technology Inc.
PIC16F872
The A/D module has four registers. These registers
are:
10.0 ANALOG-TO-DIGITAL
CONVERTER (A/D) MODULE
• A/D Result High Register (ADRESH)
• A/D Result Low Register (ADRESL)
• A/D Control Register0 (ADCON0)
• A/D Control Register1 (ADCON1)
The Analog-to-Digital (A/D) Converter module has five
input channels. The analog input charges a sample and
hold capacitor. The output of the sample and hold
capacitor is the input into the converter. The converter
then generates a digital result of this analog level via
successive approximation. The A/D conversion of the
analog input signal results in a corresponding 10-bit
digital number. The A/D module has high and low volt-
age reference input that is software selectable to some
combination of VDD, VSS, RA2 or RA3.
The ADCON0 register, shown in Register 10-1, con-
trols the operation of the A/D module. The ADCON1
register, shown in Register 10-2, configures the func-
tions of the port pins. The port pins can be configured
as analog inputs (RA3 can also be the voltage refer-
ence), or as digital I/O.
The A/D converter has a unique feature of being able
to operate while the device is in SLEEP mode. To oper-
ate in SLEEP, the A/D clock must be derived from the
A/D’s internal RC oscillator.
Additional information on using the A/D module can be
found in the PICmicro™ Mid-Range MCU Family Ref-
erence Manual (DS33023).
REGISTER 10-1: ADCON0 REGISTER (ADDRESS: 1Fh)
R/W-0
R/W-0
R/W-0
CHS2
R/W-0
CHS1
R/W-0
CHS0
R/W-0
U-0
R/W-0
ADON
ADCS1
ADCS0
GO/DONE
—
bit 7
bit 0
bit 7-6
bit 5-3
ADCS1:ADCS0: A/D Conversion Clock Select bits
00= FOSC/2
01= FOSC/8
10= FOSC/32
11= FRC (clock derived from the internal A/D module RC oscillator)
CHS2:CHS0: Analog Channel Select bits
000= Channel 0 (RA0/AN0)
001= Channel 1 (RA1/AN1)
010= Channel 2 (RA2/AN2)
011= Channel 3 (RA3/AN3)
100= Channel 4 (RA5/AN4)
bit 2
GO/DONE: A/D Conversion Status bit
If ADON = 1:
1= A/D conversion in progress (setting this bit starts the A/D conversion)
0= A/D conversion not in progress (this bit is automatically cleared by hardware when the A/D
conversion is complete)
bit 1
bit 0
Unimplemented: Read as '0'
ADON: A/D On bit
1= A/D converter module is operating
0= A/D converter module is shut-off and consumes no operating current
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
’0’ = Bit is cleared x = Bit is unknown
- n = Value at POR
’1’ = Bit is set
2002 Microchip Technology Inc.
DS30221B-page 79
PIC16F872
REGISTER 10-2: ADCON1 REGISTER (ADDRESS: 9Fh)
U-0
U-0
R/W-0
U-0
R/W-0
R/W-0
R/W-0
R/W-0
ADFM
—
—
—
PCFG3
PCFG2
PCFG1
PCFG0
bit 7
bit 0
bit 7
ADFM: A/D Result Format Select bit
1= Right justified. Six Most Significant bits of ADRESH are read as ‘0’.
0= Left justified. Six Least Significant bits of ADRESL are read as ‘0’.
bit 6-4
bit 3-0
Unimplemented: Read as '0'
PCFG3:PCFG0: A/D Port Configuration Control bits:
PCFG3:
PCFG0
AN4
RA5
AN3
RA3
AN2
RA2
AN1
RA1
AN0
RA0
CHAN/
Refs
VREF+
VREF-
(1)
0000
0001
0010
0011
0100
0101
011x
1000
1001
1010
1011
1100
1101
1110
1111
A
A
A
A
D
D
D
A
A
A
A
A
D
D
D
A
A
A
A
A
A
A
A
A
D
A
A
A
A
A
A
D
D
A
A
A
A
A
A
D
A
A
A
A
A
A
A
A
VDD
RA3
VDD
RA3
VDD
RA3
VDD
RA3
VDD
RA3
RA3
RA3
RA3
VDD
RA3
VSS
VSS
VSS
VSS
VSS
VSS
VSS
RA2
VSS
VSS
RA2
RA2
RA2
VSS
RA2
8/0
7/1
5/0
4/1
3/0
2/1
0/0
6/2
6/0
5/1
4/2
3/2
2/2
1/0
1/2
VREF+
A
A
VREF+
A
A
D
VREF+
D
D
D
VREF+
A
VREF-
A
VREF+
VREF+
VREF+
VREF+
D
A
VREF-
VREF-
VREF-
D
VREF+
VREF-
A = Analog input
D = Digital I/O
Note 1: This column indicates the number of analog channels available as A/D inputs and
the number of analog channels used as voltage reference inputs.
Legend:
R = Readable bit
- n = Value at POR
W = Writable bit
U = Unimplemented bit, read as ‘0’
’0’ = Bit is cleared x = Bit is unknown
’1’ = Bit is set
DS30221B-page 80
2002 Microchip Technology Inc.
PIC16F872
The ADRESH:ADRESL registers contain the 10-bit
result of the A/D conversion. When the A/D conversion
is complete, the result is loaded into this A/D result reg-
ister pair, the GO/DONE bit (ADCON0<2>) is cleared
and the A/D interrupt flag bit ADIF is set. The block dia-
gram of the A/D module is shown in Figure 10-1.
2. Configure A/D interrupt (if desired):
• Clear ADIF bit
• Set ADIE bit
• Set PEIE bit
• Set GIE bit
3. Wait the required acquisition time.
4. Start conversion:
After the A/D module has been configured as desired,
the selected channel must be acquired before the con-
version is started. The analog input channels must
have their corresponding TRIS bits selected as inputs.
• Set GO/DONE bit (ADCON0)
5. Wait for A/D conversion to complete, by either:
• Polling for the GO/DONE bit to be cleared
To determine sample time, see Section 10.1. After this
acquisition time has elapsed, the A/D conversion can
be started.
(with interrupts enabled); OR
• Waiting for the A/D interrupt
6. Read
A/D
Result
register
pair
These steps should be followed for doing an A/D
conversion:
(ADRESH:ADRESL), clear bit ADIF if required.
7. For the next conversion, go to step 1 or step 2,
as required. The A/D conversion time per bit is
defined as TAD.
1. Configure the A/D module:
• Configure analog pins/voltage reference and
digital I/O (ADCON1)
• Select A/D input channel (ADCON0)
• Select A/D conversion clock (ADCON0)
• Turn on A/D module (ADCON0)
FIGURE 10-1:
A/D BLOCK DIAGRAM
CHS2:CHS0
100
RA5/AN4
011
RA3/AN3/VREF+
VAIN
010
RA2/AN2/VREF-
(Input Voltage)
001
RA1/AN1
000
RA0/AN0
VDD
A/D
Converter
VREF+
(Reference
Voltage)
PCFG3:PCFG0
VREF-
(Reference
Voltage)
VSS
PCFG3:PCFG0
2002 Microchip Technology Inc.
DS30221B-page 81
PIC16F872
decreased. After the analog input channel is selected
(changed), this acquisition must be done before the
conversion can be started.
10.1 A/D Acquisition Requirements
For the A/D converter to meet its specified accuracy,
the charge holding capacitor (CHOLD) must be allowed
to fully charge to the input channel voltage level. The
analog input model is shown in Figure 10-2. The
source impedance (RS) and the internal sampling
switch (RSS) impedance directly affect the time
required to charge the capacitor CHOLD. The sampling
switch (RSS) impedance varies over the device voltage
(VDD), Figure 10-2. The maximum recommended
impedance for analog sources is 10 kΩ. As the
impedance is decreased, the acquisition time may be
Equation 10-1 may be used to calculate the minimum
acquisition time. This equation assumes that 1/2 LSb
error is used (1024 steps for the A/D). The 1/2 LSb
error is the maximum error allowed for the A/D to meet
its specified resolution.
To calculate the minimum acquisition time, TACQ, see
the PICmicro™ Mid-Range Reference Manual
(DS33023).
EQUATION 10-1: ACQUISITION TIME
TACQ
= Amplifier Settling Time + Hold Capacitor Charging Time + Temperature Coefficient
= TAMP + TC + TCOFF
= 2 µs + TC + [(Temperature -25°C)(0.05 µs/°C)]
TC
= CHOLD (RIC + RSS + RS) In(1/2047) - 120 pF (1 kΩ + 7 kΩ + 10 kΩ) In(0.0004885)
= 16.47 µs
TACQ
= 2 µs + 16.47 µs + [(50°C -25°C)(0.05 µs/°C)
= 19.72 µs
Note 1: The reference voltage (VREF) has no effect on the equation, since it cancels itself out.
2: The charge holding capacitor (CHOLD) is not discharged after each conversion.
3: The maximum recommended impedance for analog sources is 10 kΩ. This is required to meet the pin
leakage specification.
FIGURE 10-2:
ANALOG INPUT MODEL
VDD
Sampling
Switch
VT = 0.6V
ANx
SS
RIC ≤ 1k
RSS
RS
CHOLD
= DAC capacitance
= 120 pF
CPIN
5 pF
VA
I LEAKAGE
± 500 nA
VT = 0.6V
VSS
Legend CPIN
VT
= input capacitance
= threshold voltage
6V
5V
I LEAKAGE = leakage current at the pin due to
VDD 4V
3V
various junctions
= interconnect resistance
= sampling switch
2V
RIC
SS
CHOLD
= sample/hold capacitance (from DAC)
5 6 7 8 9 1011
Sampling Switch
(kΩ)
DS30221B-page 82
2002 Microchip Technology Inc.
PIC16F872
10.2 Selecting the A/D Conversion
Clock
10.3 Configuring Analog Port Pins
The ADCON1, and TRIS registers control the operation
of the A/D port pins. The port pins that are desired as
analog inputs must have their corresponding TRIS bits
set (input). If the TRIS bit is cleared (output), the digital
output level (VOH or VOL) will be converted.
The A/D conversion time per bit is defined as TAD. The
A/D conversion requires a minimum 12TAD per 10-bit
conversion. The source of the A/D conversion clock is
software selected. The four possible options for TAD
are:
The A/D operation is independent of the state of the
CHS2:CHS0 bits and the TRIS bits.
• 2TOSC
• 8TOSC
Note 1: When reading the port register, any pin
configured as an analog input channel will
read as cleared (a low level). Pins config-
ured as digital inputs will convert an ana-
log input. Analog levels on a digitally
configured input will not affect the conver-
sion accuracy.
• 32TOSC
• Internal A/D module RC oscillator (2-6 µs)
For correct A/D conversions, the A/D conversion clock
(TAD) must be selected to ensure a minimum TAD time
of 1.6 µs.
Table 10-1shows the resultant TAD times derived from
the device operating frequencies and the A/D clock
source selected.
2: Analog levels on any pin that is defined as
a digital input (including the AN7:AN0
pins), may cause the input buffer to con-
sume current that is out of the device
specifications.
TABLE 10-1: TAD vs. MAXIMUM DEVICE OPERATING FREQUENCIES (STANDARD DEVICES (C))
AD Clock Source (TAD)
Maximum Device Frequency
Operation
ADCS1:ADCS0
2TOSC
8TOSC
00
01
10
11
1.25 MHz
5 MHz
32TOSC
RC(1, 2, 3)
20 MHz
(Note 1)
Note 1: The RC source has a typical TAD time of 4 µs, but can vary between 2-6 µs.
2: When the device frequencies are greater than 1 MHz, the RC A/D conversion clock source is only recom-
mended for SLEEP operation.
3: For extended voltage devices (LC), please refer to the Electrical Characteristics (Sections 14.1 and 14.2).
2002 Microchip Technology Inc.
DS30221B-page 83
PIC16F872
In Figure 10-3, after the GO bit is set, the first time seg-
ment has a minimum of TCY and a maximum of TAD.
10.4 A/D Conversions
Clearing the GO/DONE bit during a conversion will
abort the current conversion. The A/D result register
pair will NOT be updated with the partially completed
Note: The GO/DONE bit should NOT be set in
the same instruction that turns on the A/D.
A/D
conversion
sample.
That
is,
the
ADRESH:ADRESL registers will continue to contain
the value of the last completed conversion (or the last
value written to the ADRESH:ADRESL registers). After
the A/D conversion is aborted, acquisition on the
selected channel is automatically started. The
GO/DONE bit can then be set to start the conversion.
FIGURE 10-3:
A/D CONVERSION TAD CYCLES
TCY to TAD TAD1 TAD2 TAD3
TAD5 TAD6
b6 b5
T
AD
7
T
AD
8
T
AD
9
TAD10 TAD11
b1 b0
TAD4
b9
b8
b7
b4
b3
b2
Conversion Starts
Holding capacitor is disconnected from analog input (typically 100 ns)
Set GO bit
ADRES is loaded
GO bit is cleared
ADIF bit is set
Holding capacitor is connected to analog input
Format Select bit (ADFM) controls this justification.
Figure 10-4 shows the operation of the A/D result justi-
fication. The extra bits are loaded with ’0’s’. When an
A/D result will not overwrite these locations (A/D
disable), these registers may be used as two general
purpose 8-bit registers.
10.4.1
A/D RESULT REGISTERS
The ADRESH:ADRESL register pair is the location
where the 10-bit A/D result is loaded at the completion
of the A/D conversion. This register pair is 16-bits wide.
The A/D module gives the flexibility to left or right justify
the 10-bit result in the 16-bit result register. The A/D
FIGURE 10-4:
A/D RESULT JUSTIFICATION
10-Bit Result
ADFM = 0
ADFM = 1
0
7
7
2 1 0 7
0 7 6 5
0
0000 00
0000 00
ADRESH
ADRESL
ADRESH
ADRESL
10-bit Result
10-bit Result
Left Justified
Right Justified
DS30221B-page 84
2002 Microchip Technology Inc.
PIC16F872
Turning off the A/D places the A/D module in its lowest
current consumption state.
10.5 A/D Operation During SLEEP
The A/D module can operate during SLEEP mode. This
requires that the A/D clock source be set to RC
(ADCS1:ADCS0 = 11). When the RC clock source is
selected, the A/D module waits one instruction cycle
before starting the conversion. This allows the SLEEP
instruction to be executed, which eliminates all digital
switching noise from the conversion. When the conver-
sion is completed, the GO/DONE bit will be cleared and
the result loaded into the ADRES register. If the A/D
interrupt is enabled, the device will wake-up from
SLEEP. If the A/D interrupt is not enabled, the A/D mod-
ule will then be turned off, although the ADON bit will
remain set.
Note: For the A/D module to operate in SLEEP,
the A/D clock source must be set to RC
(ADCS1:ADCS0 = 11). To allow the con-
version to occur during SLEEP, ensure the
SLEEPinstruction immediately follows the
instruction that sets the GO/DONE bit.
10.6 Effects of a RESET
A device RESET forces all registers to their RESET
state. This forces the A/D module to be turned off, and
any conversion is aborted. All A/D input pins are con-
figured as analog inputs.
When the A/D clock source is another clock option (not
RC), a SLEEPinstruction will cause the present conver-
sion to be aborted and the A/D module to be turned off,
though the ADON bit will remain set.
The value that is in the ADRESH:ADRESL registers is
not modified for
a
Power-on Reset. The
ADRESH:ADRESL registers will contain unknown data
after a Power-on Reset.
TABLE 10-2: REGISTERS/BITS ASSOCIATED WITH A/D
POR,
BOR
MCLR,
WDT
Address
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
0Bh,8Bh,
INTCON
GIE
PEIE TMR0IE
INTE
RBIE
TMR0IF
INTF
RBIF 0000 000x 0000 000u
10Bh, 18Bh
0Ch
8Ch
1Eh
9Eh
1Fh
9Fh
85h
05h
PIR1
PIE1
(1)
(1)
ADIF
ADIE
(1)
(1)
(1)
(1)
SSPIF
CCP1IF TMR2IF TMR1IF r0rr 0000 0000 0000
SSPIE CCP1IE TMR2IE TMR1IE r0rr 0000 0000 0000
xxxx xxxx uuuu uuuu
ADRESH A/D Result Register High Byte
ADRESL A/D Result Register Low Byte
ADCON0 ADCS1 ADCS0 CHS2
xxxx xxxx uuuu uuuu
CHS1
CHS0 GO/DONE
—
ADON 0000 00-0 0000 00-0
ADCON1 ADFM
—
—
—
—
—
PCFG3 PCFG2 PCFG1 PCFG0 --0- 0000 --0- 0000
TRISA
—
—
PORTA Data Direction Register
--11 1111 --11 1111
--0x 0000 --0u 0000
PORTA
PORTA Data Latch when written: PORTA pins when read
Legend: x= unknown, u= unchanged, -= unimplemented, read as '0'. Shaded cells are not used for A/D conversion.
Note 1: These bits are reserved; always maintain clear.
2002 Microchip Technology Inc.
DS30221B-page 85
PIC16F872
NOTES:
DS30221B-page 86
2002 Microchip Technology Inc.
PIC16F872
11.1 Configuration Bits
11.0 SPECIAL FEATURES OF THE
CPU
The configuration bits can be programmed (read as '0'),
or left unprogrammed (read as '1'), to select various
device configurations. The erased, or unprogrammed,
value of the configuration word is 3FFFh. These bits
are mapped in program memory location 2007h.
The PIC16F872 microcontroller has a host of features
intended to maximize system reliability, minimize cost
through elimination of external components, provide
power saving operating modes and offer code protec-
tion. These are:
It is important to note that address 2007h is beyond the
user program memory space, which can be accessed
only during programming.
• Oscillator Selection
• RESET
- Power-on Reset (POR)
- Power-up Timer (PWRT)
- Oscillator Start-up Timer (OST)
- Brown-out Reset (BOR)
• Interrupts
• Watchdog Timer (WDT)
• SLEEP
• Code Protection
• ID Locations
• In-Circuit Serial Programming
• Low Voltage In-Circuit Serial Programming
• In-Circuit Debugger
The microcontrollers have a Watchdog Timer, which
can be shut-off only through configuration bits. It runs
off its own RC oscillator for added reliability.
There are two timers that offer necessary delays on
power-up. One is the Oscillator Start-up Timer (OST),
intended to keep the chip in RESET until the crystal
oscillator is stable. The other is the Power-up Timer
(PWRT), which provides a fixed delay of 72 ms (nomi-
nal) on power-up only. It is designed to keep the part in
RESET while the power supply stabilizes. With these
two timers on-chip, most applications need no external
RESET circuitry.
SLEEP mode is designed to offer a very low current
power-down mode. The user can wake-up from SLEEP
through external RESET, Watchdog Timer Wake-up, or
through an interrupt.
Several oscillator options are also made available to
allow the part to fit the application. The RC oscillator
option saves system cost, while the LP crystal option
saves power. A set of configuration bits is used to
select various options.
Additional information on special features is available
in the PICmicro™ Mid-Range Reference Manual,
(DS33023).
2002 Microchip Technology Inc.
DS30221B-page 87
PIC16F872
REGISTER 11-1: CONFIGURATION WORD (ADDRESS: 2007h)(1)
R/P-1 R/P-1 R/P-1
U-0 R/P-1 R/P-1 R/P-1 R/P-1 R/P-1 R/P-1 R/P-1 R/P-1 R/P-1 R/P-1
CP1
CP0 DEBUG
—
WRT CPD LVP BODEN CP1
CP0 PWRTE WDTE F0SC1 F0SC0
bit0
bit13
bit 13-12
bit 5-4
CP1:CP0: FLASH Program Memory Code Protection bits(2)
11= Code protection off
10= Not supported
01= Not supported
00= All memory code protected
bit 11
DEBUG: In-Circuit Debugger Mode bit
1= In-Circuit Debugger disabled, RB6 and RB7 are general purpose I/O pins
0= In-Circuit Debugger enabled, RB6 and RB7 are dedicated to the debugger
bit 10
bit 9
Unimplemented: Read as ‘1’
WRT: FLASH Program Memory Write Enable bit
1= Unprotected program memory may be written to by EECON control
0= Unprotected program memory may not be written to by EECON control
bit 8
bit 7
bit 6
bit 3
bit 2
bit 1-0
CPD: Data EEPROM Memory Code Protection bit
1= Code protection off
0= Data EEPROM memory code protected
LVP: Low Voltage In-Circuit Serial Programming Enable bit
1= RB3/PGM pin has PGM function, low voltage programming enabled
0= RB3 is digital I/O, HV on MCLR must be used for programming
BODEN: Brown-out Reset Enable bit(3)
1= BOR enabled
0= BOR disabled
PWRTE: Power-up Timer Enable bit(3)
1= PWRT disabled
0= PWRT enabled
WDTE: Watchdog Timer Enable bit
1= WDT enabled
0= WDT disabled
FOSC1:FOSC0: Oscillator Selection bits
11= RC oscillator
10= HS oscillator
01= XT oscillator
00= LP oscillator
Note 1: The erased (unprogrammed) value of the configuration word is 3FFFh.
2: All of the CP1:CP0 pairs have to be given the same value to enable the code protection
scheme listed.
3: Enabling Brown-out Reset automatically enables Power-up Timer (PWRT), regardless of
the value of bit PWRTE. Ensure the Power-up Timer is enabled any time Brown-out Reset
is enabled.
Legend:
R = Readable bit
P = Programmable bit
U = Unimplemented bit, read as ‘0’
- n = Value when device is unprogrammed
u = Unchanged from programmed state
DS30221B-page 88
2002 Microchip Technology Inc.
PIC16F872
FIGURE 11-2:
EXTERNAL CLOCK INPUT
OPERATION (HS, XT OR
LP OSC
11.2 Oscillator Configurations
11.2.1 OSCILLATOR TYPES
CONFIGURATION)
The PIC16F872 can be operated in four different oscil-
lator modes. The user can program two configuration
bits (FOSC1 and FOSC0) to select one of these four
modes:
OSC1
Clock from
Ext. System
• LP
• XT
• HS
• RC
Low Power Crystal
PIC16F87X
OSC2
Crystal/Resonator
Open
High Speed Crystal/Resonator
Resistor/Capacitor
11.2.2
CRYSTAL OSCILLATOR/CERAMIC
RESONATORS
In XT, LP or HS modes, a crystal or ceramic resonator
is connected to the OSC1/CLKIN and OSC2/CLKOUT
pins to establish oscillation (Figure 11-1). The
PIC16F872 oscillator design requires the use of a par-
allel cut crystal. Use of a series cut crystal may give a
frequency out of the crystal manufacturers specifica-
tions. When in XT, LP or HS modes, the device can
have an external clock source to drive the OSC1/
CLKIN pin (Figure 11-2).
TABLE 11-1: CERAMIC RESONATORS
Ranges Tested:
Mode
Freq
OSC1
OSC2
XT
455 kHz
2.0 MHz
4.0 MHz
68 - 100 pF 68 - 100 pF
15 - 68 pF
15 - 68 pF
15 - 68 pF
15 - 68 pF
HS
8.0 MHz
16.0 MHz
10 - 68 pF
10 - 22 pF
10 - 68 pF
10 - 22 pF
FIGURE 11-1:
CRYSTAL/CERAMIC
RESONATOROPERATION
(HS, XT OR LP
These values are for design guidance only.
See notes following Table 11-2.
Resonators Used:
OSC CONFIGURATION)
455 kHz Panasonic EFO-A455K04B
0.3%
(1)
C1
OSC1
2.0 MHz
4.0 MHz
8.0 MHz
Murata Erie CSA2.00MG
Murata Erie CSA4.00MG
Murata Erie CSA8.00MT
0.5%
0.5%
0.5%
0.5%
To
Internal
Logic
XTAL
(3)
RF
OSC2
16.0 MHz Murata Erie CSA16.00MX
SLEEP
PIC16F87X
(2)
RS
All resonators used did not have built-in capacitors.
(1)
C2
Note 1: See Table 11-1 and Table 11-2 for recom-
mended values of C1 and C2.
2: A series resistor (RS) may be required for
AT strip cut crystals.
3: RF varies with the crystal chosen.
2002 Microchip Technology Inc.
DS30221B-page 89
PIC16F872
TABLE 11-2: CAPACITOR SELECTION FOR
CRYSTAL OSCILLATOR
11.2.3
RC OSCILLATOR
For timing insensitive applications, the “RC” device
option offers additional cost savings. The RC oscillator
frequency is a function of the supply voltage, the resis-
tor (REXT) and capacitor (CEXT) values, and the operat-
ing temperature. In addition to this, the oscillator
frequency will vary from unit to unit due to normal pro-
cess parameter variation. Furthermore, the difference
in lead frame capacitance between package types will
also affect the oscillation frequency, especially for low
CEXT values. The user also needs to take into account
variation due to tolerance of external R and C compo-
nents used. Figure 11-3 shows how the R/C combina-
tion is connected to the PIC16F872.
Cap.
Range
C2
Crystal
Freq
Cap. Range
C1
Osc Type
LP
32 kHz
200 kHz
200 kHz
1 MHz
33 pF
15 pF
33 pF
15 pF
XT
47-68 pF
15 pF
47-68 pF
15 pF
4 MHz
15 pF
15 pF
HS
4 MHz
15 pF
15 pF
8 MHz
15-33 pF
15-33 pF
15-33 pF
15-33 pF
20 MHz
FIGURE 11-3:
RC OSCILLATOR MODE
These values are for design guidance only.
See notes following this table.
VDD
Crystals Used
REXT
Internal
OSC1
32 kHz
200 kHz
1 MHz
4 MHz
8 MHz
Epson C-001R32.768K-A
STD XTL 200.000KHz
ECS ECS-10-13-1
± 20 PPM
± 20 PPM
± 50 PPM
± 50 PPM
Clock
CEXT
VSS
PIC16F87X
ECS ECS-40-20-1
OSC2/CLKOUT
EPSON CA-301 8.000M-C ± 30 PPM
FOSC/4
Recommended values:
20 MHz EPSON CA-301 20.000M-C ± 30 PPM
3 kΩ ≤ REXT ≤ 100 kΩ
CEXT > 20pF
Note 1: Higher capacitance increases the stability
of oscillator, but also increases the start-
up time.
2: Since each resonator/crystal has its own
characteristics, the user should consult
the resonator/crystal manufacturer for
appropriate values of external compo-
nents.
3: Rs may be required in HS mode, as well
as XT mode, to avoid overdriving crystals
with low drive level specification.
4: When migrating from other PICmicro®
devices, oscillator performance should be
verified.
DS30221B-page 90
2002 Microchip Technology Inc.
PIC16F872
SLEEP, and Brown-out Reset (BOR). They are not
affected by a WDT Wake-up, which is viewed as the
resumption of normal operation. The TO and PD bits
are set or cleared differently in different RESET situa-
tions, as indicated in Table 11-4. These bits are used in
software to determine the nature of the RESET. See
Table 11-6 for a full description of RESET states of all
registers.
11.3 Reset
The PIC16F872 differentiates between various kinds of
RESET:
• Power-on Reset (POR)
• MCLR Reset during normal operation
• MCLR Reset during SLEEP
• WDT Reset (during normal operation)
• WDT Wake-up (during SLEEP)
• Brown-out Reset (BOR)
A simplified block diagram of the On-Chip Reset circuit
is shown in Figure 11-4.
These devices have a MCLR noise filter in the MCLR
Reset path. The filter will detect and ignore small
pulses.
Some registers are not affected in any RESET condi-
tion. Their status is unknown on POR and unchanged
in any other RESET. Most other registers are reset to a
“RESET state” on Power-on Reset (POR), on the
MCLR and WDT Reset, on MCLR Reset during
It should be noted that a WDT Reset does not drive
MCLR pin low.
FIGURE 11-4:
SIMPLIFIED BLOCK DIAGRAM OF ON-CHIP RESET CIRCUIT
External
RESET
MCLR
SLEEP
WDT
WDT
Module
Time-out
Reset
VDD Rise
Detect
Power-on Reset
VDD
Brown-out
Reset
S
BODEN
OST/PWRT
OST
Chip_Reset
10-bit Ripple Counter
R
Q
OSC1
(1)
On-Chip
RC OSC
PWRT
10-bit Ripple Counter
Enable PWRT
Enable OST
Note 1: This is a separate oscillator from the RC oscillator of the CLKIN pin.
2002 Microchip Technology Inc.
DS30221B-page 91
PIC16F872
11.4 Power-on Reset (POR)
11.7 Brown-out Reset (BOR)
A Power-on Reset pulse is generated on-chip when
VDD rise is detected (in the range of 1.2V - 1.7V). To
take advantage of the POR, tie the MCLR pin directly
(or through a resistor) to VDD. This will eliminate exter-
nal RC components usually needed to create a Power-
on Reset. A maximum rise time for VDD is specified.
See Electrical Specifications for details.
The configuration bit, BODEN, can enable or disable
the Brown-out Reset circuit. If VDD falls below VBOR
(parameter #D005, about 4V) for longer than TBOR
(parameter #35, about 100 µS), the brown-out situation
will reset the device. If VDD falls below VBOR for less
than TBOR, a RESET may not occur.
Once the brown-out occurs, the device will remain in
Brown-out Reset until VDD rises above VBOR. The
Power-up Timer then keeps the device in RESET for
TPWRT (parameter #33, about 72 mS). If VDD should fall
below VBOR during TPWRT, the Brown-out Reset pro-
cess will restart when VDD rises above VBOR with the
Power-up Timer Reset. The Power-up Timer is always
enabled when the Brown-out Reset circuit is enabled,
regardless of the state of the PWRT configuration bit.
When the device starts normal operation (exits the
RESET condition), device operating parameters (volt-
age, frequency, temperature,...) must be met to ensure
operation. If these conditions are not met, the device
must be held in RESET until the operating conditions
are met. Brown-out Reset may be used to meet the
start-up conditions. For additional information, refer to
Application Note (AN007), “Power-up Trouble
Shooting”, (DS00007).
11.8 Time-out Sequence
11.5 Power-up Timer (PWRT)
On power-up, the time-out sequence is as follows: the
PWRT delay starts (if enabled) when a POR Reset
occurs. Then, OST starts counting 1024 oscillator
cycles when PWRT ends (LP, XT, HS). When the OST
ends, the device comes out of RESET.
The Power-up Timer provides a fixed 72 ms nominal
time-out on power-up only from the POR. The Power-
up Timer operates on an internal RC oscillator. The
chip is kept in RESET as long as the PWRT is active.
The PWRT’s time delay allows VDD to rise to an accept-
able level. A configuration bit is provided to enable/dis-
able the PWRT.
If MCLR is kept low long enough, the time-outs will
expire. Bringing MCLR high will begin execution imme-
diately. This is useful for testing purposes or to synchro-
nize more than one PIC16F872 device operating in
parallel.
The power-up time delay will vary from chip to chip due
to VDD, temperature and process variation. See DC
parameters for details (TPWRT, parameter #33).
Table 11-5 shows the RESET conditions for the
STATUS, PCON and PC registers, while Table 11-6
shows the RESET conditions for all the registers.
11.6 Oscillator Start-up Timer (OST)
The Oscillator Start-up Timer (OST) provides a delay of
1024 oscillator cycles (from OSC1 input) after the
PWRT delay is over (if PWRT is enabled). This helps to
ensure that the crystal oscillator or resonator has
started and stabilized.
11.9 Power Control/Status Register
(PCON)
The Power Control/Status Register, PCON, has two bits.
Bit 0 is the Brown-out Reset Status bit (BOR). Bit BOR
is unknown on a Power-on Reset. It must then be set
by the user and checked on subsequent RESETS to
see if bit BOR cleared, indicating a BOR occurred.
When the Brown-out Reset is disabled, the state of the
BOR bit is unpredictable and is, therefore, not valid at
any time.
The OST time-out is invoked only for XT, LP and HS
modes and only on Power-on Reset or wake-up from
SLEEP.
Bit 1 is the Power-on Reset Status bit (POR). It is
cleared on a Power-on Reset and unaffected other-
wise. The user must set this bit following a Power-on
Reset.
TABLE 11-3: TIME-OUT IN VARIOUS SITUATIONS
Power-up
Wake-up from
Oscillator Configuration
Brown-out
SLEEP
PWRTE = 0
PWRTE = 1
XT, HS, LP
RC
72 ms + 1024TOSC
72 ms
1024TOSC
72 ms + 1024TOSC
72 ms
1024TOSC
—
—
DS30221B-page 92
2002 Microchip Technology Inc.
PIC16F872
TABLE 11-4: STATUS BITS AND THEIR SIGNIFICANCE
POR
BOR
TO
PD
0
0
0
1
1
1
1
1
x
x
x
0
1
1
1
1
1
0
x
1
0
0
u
1
1
x
0
1
1
0
u
0
Power-on Reset
Illegal, TO is set on POR
Illegal, PD is set on POR
Brown-out Reset
WDT Reset
WDT Wake-up
MCLR Reset during normal operation
MCLR Reset during SLEEP or interrupt wake-up from SLEEP
TABLE 11-5: RESET CONDITION FOR SPECIAL REGISTERS
Program
STATUS
Register
PCON
Register
Condition
Counter
Power-on Reset
000h
000h
0001 1xxx
000u uuuu
0001 0uuu
0000 1uuu
uuu0 0uuu
0001 1uuu
uuu1 0uuu
---- --0x
---- --uu
---- --uu
---- --uu
---- --uu
---- --u0
---- --uu
MCLR Reset during normal operation
MCLR Reset during SLEEP
WDT Reset
000h
000h
WDT Wake-up
PC + 1
Brown-out Reset
000h
PC + 1(1)
Interrupt wake-up from SLEEP
Legend: u= unchanged, x= unknown, -= unimplemented bit, read as ’0’
Note 1: When the wake-up is due to an interrupt and the GIE bit is set, the PC is loaded with the interrupt vector
(0004h).
TABLE 11-6: INITIALIZATION CONDITIONS FOR ALL REGISTERS
Power-on Reset,
Brown-out Reset
MCLR Resets
WDT Reset
Wake-up via WDT or
Interrupt
Register
W
xxxx xxxx
N/A
uuuu uuuu
N/A
uuuu uuuu
N/A
INDF
TMR0
PCL
xxxx xxxx
0000h
uuuu uuuu
uuuu uuuu
PC + 1(2)
0000h
STATUS
FSR
0001 1xxx
xxxx xxxx
--0x 0000
xxxx xxxx
xxxx xxxx
---0 0000
0000 000x
r0rr 0000
-r-0 0--r
000q quuu(3)
uuuu uuuu
--0u 0000
uuuu uuuu
uuuu uuuu
---0 0000
0000 000u
r0rr 0000
-r-0 0--r
uuuq quuu(3)
uuuu uuuu
--uu uuuu
uuuu uuuu
uuuu uuuu
---u uuuu
uuuu uuuu(1)
rurr uuuu(1)
-r-u u--r(1)
PORTA
PORTB
PORTC
PCLATH
INTCON
PIR1
PIR2
Legend: u= unchanged, x= unknown, -= unimplemented bit, read as ’0’, q= value depends on condition,
r= reserved, maintain clear
Note 1: One or more bits in INTCON, PIR1 and/or PIR2 will be affected (to cause wake-up).
2: When the wake-up is due to an interrupt and the GIE bit is set, the PC is loaded with the interrupt vector
(0004h).
3: See Table 11-5 for RESET value for specific condition.
2002 Microchip Technology Inc.
DS30221B-page 93
PIC16F872
TABLE 11-6: INITIALIZATION CONDITIONS FOR ALL REGISTERS (CONTINUED)
Power-on Reset,
Brown-out Reset
MCLR Resets
WDT Reset
Wake-up via WDT or
Interrupt
Register
TMR1L
xxxx xxxx
xxxx xxxx
--00 0000
0000 0000
-000 0000
xxxx xxxx
0000 0000
xxxx xxxx
xxxx xxxx
--00 0000
xxxx xxxx
0000 00-0
1111 1111
--11 1111
1111 1111
1111 1111
r0rr 0000
-r-0 0--r
---- --qq
0000 0000
1111 1111
0000 0000
--00 0000
xxxx xxxx
0--- 0000
0--- 0000
xxxx xxxx
xxxx xxxx
xxxx xxxx
x--- x000
---- ----
uuuu uuuu
uuuu uuuu
--uu uuuu
0000 0000
-000 0000
uuuu uuuu
0000 0000
uuuu uuuu
uuuu uuuu
--00 0000
uuuu uuuu
0000 00-0
1111 1111
--11 1111
1111 1111
1111 1111
r0rr 0000
-r-0 0--r
---- --uu
0000 0000
1111 1111
0000 0000
--00 0000
uuuu uuuu
0--- 0000
0--- 0000
uuuu uuuu
uuuu uuuu
uuuu uuuu
u--- u000
---- ----
uuuu uuuu
uuuu uuuu
--uu uuuu
uuuu uuuu
-uuu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
--uu uuuu
uuuu uuuu
uuuu uu-u
uuuu uuuu
--uu uuuu
uuuu uuuu
uuuu uuuu
rurr uuuu
-r-u u--r
---- --uu
uuuu uuuu
1111 1111
uuuu uuuu
--uu uuuu
uuuu uuuu
u--- uuuu
u--- uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
u--- uuuu
---- ----
TMR1H
T1CON
TMR2
T2CON
SSPBUF
SSPCON
CCPR1L
CCPR1H
CCP1CON
ADRESH
ADCON0
OPTION_REG
TRISA
TRISB
TRISC
PIE1
PIE2
PCON
SSPCON2
PR2
SSPADD
SSPSTAT
ADRESL
ADCON1
EEDATA
EEADR
EEDATH
EEADRH
EECON1
EECON2
Legend: u= unchanged, x= unknown, -= unimplemented bit, read as ’0’, q= value depends on condition,
r= reserved, maintain clear
Note 1: One or more bits in INTCON, PIR1 and/or PIR2 will be affected (to cause wake-up).
2: When the wake-up is due to an interrupt and the GIE bit is set, the PC is loaded with the interrupt vector
(0004h).
3: See Table 11-5 for RESET value for specific condition.
DS30221B-page 94
2002 Microchip Technology Inc.
PIC16F872
FIGURE 11-5:
TIME-OUT SEQUENCE ON POWER-UP (MCLR TIED TO VDD VIA RC NETWORK)
VDD
MCLR
INTERNAL POR
TPWRT
PWRT TIME-OUT
OST TIME-OUT
TOST
INTERNAL RESET
FIGURE 11-6:
TIME-OUT SEQUENCE ON POWER-UP (MCLR NOT TIED TO VDD): CASE 1
VDD
MCLR
INTERNAL POR
TPWRT
PWRT TIME-OUT
OST TIME-OUT
TOST
INTERNAL RESET
2002 Microchip Technology Inc.
DS30221B-page 95
PIC16F872
FIGURE 11-7:
TIME-OUT SEQUENCE ON POWER-UP (MCLR NOT TIED TO VDD): CASE 2
VDD
MCLR
INTERNAL POR
TPWRT
PWRT TIME-OUT
OST TIME-OUT
TOST
INTERNAL RESET
FIGURE 11-8:
SLOW RISETIME (MCLR TIED TO VDD VIA RC NETWORK)
5V
1V
VDD
MCLR
0V
INTERNAL POR
TPWRT
PWRT TIME-OUT
TOST
OST TIME-OUT
INTERNAL RESET
DS30221B-page 96
2002 Microchip Technology Inc.
PIC16F872
The RB0/INT pin interrupt, the RB port change interrupt
and the TMR0 overflow interrupt flags are contained in
the INTCON register.
11.10 Interrupts
The PIC16F872 has 10 sources of interrupt. The inter-
rupt control register (INTCON) records individual inter-
rupt requests in flag bits. It also has individual and
global interrupt enable bits.
The peripheral interrupt flags are contained in the spe-
cial function registers, PIR1 and PIR2. The correspond-
ing interrupt enable bits are contained in special
function registers, PIE1 and PIE2, and the peripheral
interrupt enable bit is contained in special function
register, INTCON.
Note: Individual interrupt flag bits are set, regard-
less of the status of their corresponding
mask bit or the GIE bit.
A global interrupt enable bit, GIE (INTCON<7>),
enables (if set) all unmasked interrupts or disables (if
cleared) all interrupts. When bit GIE is enabled, and an
interrupt’s flag bit and mask bit are set, the interrupt will
vector immediately. Individual interrupts can be dis-
abled through their corresponding enable bits in vari-
ous registers. Individual interrupt bits are set,
regardless of the status of the GIE bit. The GIE bit is
cleared on RESET.
When an interrupt is responded to, the GIE bit is
cleared to disable any further interrupt, the return
address is pushed onto the stack and the PC is loaded
with 0004h. Once in the Interrupt Service Routine, the
source(s) of the interrupt can be determined by polling
the interrupt flag bits. The interrupt flag bit(s) must be
cleared in software before re-enabling interrupts to
avoid recursive interrupts.
For external interrupt events, such as the INT pin or
PORTB change interrupt, the interrupt latency will be
three or four instruction cycles. The exact latency
depends when the interrupt event occurs. The latency
is the same for one or two-cycle instructions. Individual
interrupt flag bits are set, regardless of the status of
their corresponding mask bit, PEIE bit, or GIE bit
The “return from interrupt” instruction, RETFIE, exits
the interrupt routine, as well as sets the GIE bit, which
re-enables interrupts.
FIGURE 11-9:
INTERRUPT LOGIC
EEIF
EEIE
Wake-up (If in SLEEP mode)
ADIF
ADIE
TMR0IF
TMR0IE
INTF
INTE
SSPIF
SSPIE
Interrupt to CPU
RBIF
RBIE
CCP1IF
CCP1IE
PEIE
GIE
TMR2IF
TMR2IE
TMR1IF
TMR1IE
BCLIF
BCLIE
2002 Microchip Technology Inc.
DS30221B-page 97
PIC16F872
11.10.1 INT INTERRUPT
11.10.3 PORTB INTCON CHANGE
External interrupt on the RB0/INT pin is edge triggered,
either rising if bit INTEDG (OPTION_REG<6>) is set,
or falling if the INTEDG bit is clear. When a valid edge
appears on the RB0/INT pin, flag bit INTF
(INTCON<1>) is set. This interrupt can be disabled by
clearing enable bit INTE (INTCON<4>). Flag bit INTF
must be cleared in software in the Interrupt Service
Routine before re-enabling this interrupt. The INT inter-
rupt can wake-up the processor from SLEEP, if bit INTE
was set prior to going into SLEEP. The status of global
interrupt enable bit GIE, decides whether or not the
processor branches to the interrupt vector following
wake-up. See Section 11.13 for details on SLEEP
mode.
An input change on PORTB<7:4> sets flag bit RBIF
(INTCON<0>). The interrupt can be enabled/disabled
by setting/clearing enable bit RBIE (INTCON<4>), see
Section 4.2.
11.11 Context Saving During Interrupts
During an interrupt, only the return PC value is saved
on the stack. Typically, users may wish to save key reg-
isters during an interrupt, (i.e., W register and STATUS
register). This will have to be implemented in software.
Since the upper 16 bytes of each bank are common in
PIC16F872 devices, temporary holding registers,
W_TEMP, STATUS_TEMP and PCLATH_TEMP,
should be placed in here. These 16 locations don’t
require banking and therefore, make it easier for con-
text save and restore. The same code shown in
Example 11-1 can be used.
11.10.2 TMR0 INTERRUPT
An overflow (FFh → 00h) in the TMR0 register will set
flag bit TMR0IF (INTCON<2>). The interrupt can be
enabled/disabled by setting/clearing enable bit
TMR0IE (INTCON<5>), see Section 5.0.
EXAMPLE 11-1:
SAVING STATUS, W, AND PCLATH REGISTERS IN RAM
MOVWF
SWAPF
CLRF
MOVWF
MOVF
MOVWF
CLRF
:
W_TEMP
STATUS,W
STATUS
STATUS_TEMP
PCLATH, W
PCLATH_TEMP
PCLATH
;Copy W to TEMP register
;Swap status to be saved into W
;bank 0, regardless of current bank, Clears IRP,RP1,RP0
;Save status to bank zero STATUS_TEMP register
;Only required if using pages 1, 2 and/or 3
;Save PCLATH into W
;Page zero, regardless of current page
:(ISR)
:
;(Insert user code here)
MOVF
MOVWF
SWAPF
PCLATH_TEMP, W
PCLATH
STATUS_TEMP,W
;Restore PCLATH
;Move W into PCLATH
;Swap STATUS_TEMP register into W
;(sets bank to original state)
;Move W into STATUS register
;Swap W_TEMP
MOVWF
SWAPF
SWAPF
STATUS
W_TEMP,F
W_TEMP,W
;Swap W_TEMP into W
DS30221B-page 98
2002 Microchip Technology Inc.
PIC16F872
WDT time-out period values may be found in the Elec-
trical Specifications section under parameter #31. Val-
ues for the WDT prescaler (actually a postscaler, but
shared with the Timer0 prescaler) may be assigned
using the OPTION_REG register.
11.12 Watchdog Timer (WDT)
The Watchdog Timer is a free running on-chip RC oscil-
lator, which does not require any external components.
This RC oscillator is separate from the RC oscillator of
the OSC1/CLKI pin. That means that the WDT will run,
even if the clock on the OSC1/CLKI and OSC2/CLKO
pins of the device has been stopped, for example, by
execution of a SLEEPinstruction.
Note 1: The CLRWDT and SLEEP instructions
clear the WDT and the postscaler, if
assigned to the WDT, and prevent it from
timing out and generating
RESET condition.
a device
During normal operation, a WDT time-out generates a
device RESET (Watchdog Timer Reset). If the device is
in SLEEP mode, a WDT time-out causes the device to
wake-up and continue with normal operation (Watch-
dog Timer Wake-up). The TO bit in the STATUS regis-
ter will be cleared upon a Watchdog Timer time-out.
2: When a CLRWDT instruction is executed
and the prescaler is assigned to the WDT,
the prescaler count will be cleared, but
the prescaler assignment is not changed.
The WDT can be permanently disabled by clearing
configuration bit WDTE (Section 11.1).
FIGURE 11-10:
WATCHDOG TIMER BLOCK DIAGRAM
From TMR0 Clock Source
(Figure 5-1)
0
Postscaler
M
1
U
WDT Timer
X
8
8 - to - 1 MUX
PS2:PS0
PSA
WDT
Enable Bit
To TMR0 (Figure 5-1)
0
1
MUX
PSA
WDT
Time-out
Note:
PSA and PS2:PS0 are bits in the OPTION_REG register.
TABLE 11-7: SUMMARY OF WATCHDOG TIMER REGISTERS
Address
Name
Bit 7
(1)
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
2007h
Config. bits
BODEN(1)
INTEDG
CP1
CP0
PWRTE(1)
PSA
WDTE
PS2
FOSC1
PS1
FOSC0
PS0
81h,181h OPTION_REG RBPU
T0CS
T0SE
Legend: Shaded cells are not used by the Watchdog Timer.
Note 1: See Register 11-1 for operation of these bits.
2002 Microchip Technology Inc.
DS30221B-page 99
PIC16F872
Other peripherals cannot generate interrupts, since
during SLEEP, no on-chip clocks are present.
11.13 Power-down Mode (SLEEP)
Power-down mode is entered by executing a SLEEP
When the SLEEPinstruction is being executed, the next
instruction (PC + 1) is pre-fetched. For the device to
wake-up through an interrupt event, the corresponding
interrupt enable bit must be set (enabled). Wake-up is
regardless of the state of the GIE bit. If the GIE bit is
clear (disabled), the device continues execution at the
instruction after the SLEEPinstruction. If the GIE bit is
set (enabled), the device executes the instruction after
the SLEEP instruction and then branches to the inter-
rupt address (0004h). In cases where the execution of
the instruction following SLEEP is not desirable, the
user should have a NOPafter the SLEEPinstruction.
instruction.
If enabled, the Watchdog Timer will be cleared but
keeps running, the PD bit (STATUS<3>) is cleared, the
TO (STATUS<4>) bit is set, and the oscillator driver is
turned off. The I/O ports maintain the status they had
before the SLEEP instruction was executed (driving
high, low, or hi-impedance).
For lowest current consumption in this mode, place all
I/O pins at either VDD or VSS, ensure no external cir-
cuitry is drawing current from the I/O pin, power-down
the A/D and disable external clocks. Pull all I/O pins
that are hi-impedance inputs, high or low externally, to
avoid switching currents caused by floating inputs. The
T0CKI input should also be at VDD or VSS for lowest
current consumption. The contribution from on-chip
pull-ups on PORTB should also be considered.
11.13.2 WAKE-UP USING INTERRUPTS
When global interrupts are disabled (GIE cleared) and
any interrupt source has both its interrupt enable bit
and interrupt flag bit set, one of the following will occur:
The MCLR pin must be at a logic high level (VIHMC).
• If the interrupt occurs before the execution of a
SLEEPinstruction, the SLEEPinstruction will com-
plete as a NOP. Therefore, the WDT and WDT
postscaler will not be cleared, the TO bit will not
be set and PD bits will not be cleared.
11.13.1 WAKE-UP FROM SLEEP
The device can wake-up from SLEEP through one of
the following events:
• If the interrupt occurs during or after the execu-
tion of a SLEEPinstruction, the device will imme-
diately wake-up from SLEEP. The SLEEP
instruction will be completely executed before the
wake-up. Therefore, the WDT and WDT
postscaler will be cleared, the TO bit will be set
and the PD bit will be cleared.
1. External RESET input on MCLR pin.
2. Watchdog Timer wake-up (if WDT was
enabled).
3. Interrupt from INT pin, RB port change or
Peripheral Interrupt.
External MCLR Reset will cause a device RESET. All
other events are considered a continuation of program
execution and cause a “wake-up”. The TO and PD bits
in the STATUS register can be used to determine the
cause of device RESET. The PD bit, which is set on
power-up, is cleared when SLEEP is invoked. The TO
bit is cleared if a WDT time-out occurred and caused
wake-up.
Even if the flag bits were checked before executing a
SLEEP instruction, it may be possible for flag bits to
become set before the SLEEPinstruction completes. To
determine whether a SLEEPinstruction executed, test
the PD bit. If the PD bit is set, the SLEEP instruction
was executed as a NOP.
To ensure that the WDT is cleared, a CLRWDTinstruc-
tion should be executed before a SLEEPinstruction.
The following peripheral interrupts can wake the device
from SLEEP:
1. PSP read or write.
2. TMR1 interrupt. Timer1 must be operating as an
asynchronous counter.
3. CCP Capture mode interrupt.
4. Special event trigger (Timer1 in Asynchronous
mode using an external clock).
5. SSP (START/STOP) bit detect interrupt.
6. SSP transmit or receive in Slave mode
(SPI/I2C).
7. USART RX or TX (Synchronous Slave mode).
8. A/D conversion (when A/D clock source is RC).
9. EEPROM write operation completion.
DS30221B-page 100
2002 Microchip Technology Inc.
PIC16F872
FIGURE 11-11:
WAKE-UP FROM SLEEP THROUGH INTERRUPT
Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1
Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4
OSC1
(2)
CLKOUT(4)
TOST
INT pin
INTF Flag
Interrupt Latency
(INTCON<1>)
(Note 2)
GIE bit
Processor in
SLEEP
(INTCON<7>)
INSTRUCTION FLOW
PC
PC
PC+1
PC+2
PC+2
PC + 2
0004h
0005h
Instruction
Inst(0004h)
Inst(PC + 1)
Inst(PC + 2)
Inst(0005h)
Inst(PC) = SLEEP
Fetched
Instruction
Executed
Dummy cycle
Dummy cycle
SLEEP
Inst(PC + 1)
Inst(PC - 1)
Inst(0004h)
Note 1: XT, HS or LP oscillator mode assumed.
2: TOST = 1024TOSC (drawing not to scale). This delay will not be there for RC osc mode.
3: GIE = ’1’ assumed. In this case, after wake- up, the processor jumps to the interrupt routine.
If GIE = ’0’, execution will continue in-line.
4: CLKOUT is not available in these osc modes, but shown here for timing reference.
11.14 In-Circuit Debugger
11.15 Program Verification/Code
Protection
When the DEBUG bit in the configuration word is
programmed to a ’0’, the In-Circuit Debugger function-
ality is enabled. This function allows simple debugging
functions when used with MPLAB® IDE. When the
microcontroller has this feature enabled, some of the
resources are not available for general use. Table 11-8
shows which features are consumed by the back-
ground debugger.
If the code protection bit(s) have not been pro-
grammed, the on-chip program memory can be read
out for verification purposes.
11.16 ID Locations
Four memory locations (2000h - 2003h) are designated
as ID locations, where the user can store checksum or
other code identification numbers. These locations are
not accessible during normal execution, but are read-
able and writable during program/verify. It is recom-
mended that only the 4 Least Significant bits of the ID
location are used.
TABLE 11-8: DEBUGGER RESOURCES
I/O pins
RB6, RB7
1 level
Stack
Program Memory
Address 0000h must be NOP
Last 100h words
Data Memory
0x070 (0x0F0, 0x170, 0x1F0)
0x1EB - 0x1EF
To use the In-Circuit Debugger function of the micro-
controller, the design must implement In-Circuit Serial
Programming connections to MCLR/VPP, VDD, GND,
RB7 and RB6. This will interface to the In-Circuit
Debugger module available from Microchip or one of
the third party development tool companies.
2002 Microchip Technology Inc.
DS30221B-page 101
PIC16F872
If Low Voltage Programming mode is not used, the LVP
bit can be programmed to a '0' and RB3/PGM becomes
a digital I/O pin. However, the LVP bit may only be pro-
grammed when programming is entered with VIHH on
MCLR. The LVP bit can only be charged when using
high voltage on MCLR.
11.17 In-Circuit Serial Programming
PIC16F872 microcontrollers can be serially pro-
grammed while in the end application circuit. This is
simply done with two lines for clock and data and three
other lines for power, ground, and the programming
voltage. This allows customers to manufacture boards
with unprogrammed devices, and then program the
microcontroller just before shipping the product. This
also allows the most recent firmware or a custom firm-
ware to be programmed.
It should be noted that once the LVP bit is programmed
to 0, only the High Voltage Programming mode is avail-
able and only High Voltage Programming mode can be
used to program the device.
When using low voltage ICSP, the part must be sup-
plied 4.5V to 5.5V if a bulk erase will be executed. This
includes reprogramming of the code protect bits from
an on-state to off-state. For all other cases of low volt-
age ICSP, the part may be programmed at the normal
operating voltage. This means calibration values,
unique user IDs, or user code can be reprogrammed or
added.
When using ICSP, the part must be supplied 4.5V to
5.5V if a bulk erase will be executed. This includes
reprogramming of the code protect, both from an on-
state to off-state. For all other cases of ICSP, the part
may be programmed at the normal operating voltages.
This means calibration values, unique user IDs or user
code can be reprogrammed or added.
For complete details of serial programming, please
refer to the EEPROM Memory Programming Specifica-
tion for the PIC16F87X (DS39025).
11.18 Low Voltage ICSP Programming
The LVP bit of the configuration word enables low volt-
age ICSP programming. This mode allows the micro-
controller to be programmed via ICSP, using a VDD
source in the operating voltage range. This only means
that VPP does not have to be brought to VIHH, but can
instead be left at the normal operating voltage. In this
mode, the RB3/PGM pin is dedicated to the program-
ming function and ceases to be a general purpose I/O
pin. During programming, VDD is applied to the MCLR
pin. To enter Programming mode, VDD must be applied
to the RB3/PGM pin, provided the LVP bit is set. The
LVP bit defaults to on (‘1’) from the factory.
Note 1: The High Voltage Programming mode is
always available, regardless of the state
of the LVP bit, by applying VIHH to the
MCLR pin.
2: While in low voltage ICSP mode, the RB3
pin can no longer be used as a general
purpose I/O pin.
3: When using low voltage ICSP program-
ming (LVP) and the pull-ups on PORTB
are enabled, bit 3 in the TRISB register
must be cleared to disable the pull-up on
RB3 and ensure the proper operation of
the device.
DS30221B-page 102
2002 Microchip Technology Inc.
PIC16F872
For example, a “CLRF PORTB” instruction will read
PORTB, clear all the data bits, then write the result
back to PORTB. This example would have the unin-
tended result that the condition that sets the RBIF flag
would be cleared.
12.0 INSTRUCTION SET SUMMARY
The PIC16 instruction set is highly orthogonal and is
comprised of three basic categories:
• Byte-oriented operations
• Bit-oriented operations
TABLE 12-1: OPCODE FIELD
DESCRIPTIONS
• Literal and control operations
Each PIC16 instruction is a 14-bit word divided into an
opcode which specifies the instruction type, and one or
more operands which further specify the operation of
the instruction. The formats for each of the categories
is presented in Figure 12-1, while the various opcode
fields are summarized in Table 12-1.
Field
Description
f
W
b
k
x
Register file address (0x00 to 0x7F)
Working register (accumulator)
Bit address within an 8-bit file register
Literal field, constant data or label
Table 13-2 lists the instructions recognized by the
MPASMTM Assembler. A complete description of each
instruction is also available in the PICmicro™ Mid-
Range Reference Manual (DS33023).
Don't care location (= 0or 1).
The assembler will generate code with x = 0.
It is the recommended form of use for
compatibility with all Microchip software tools.
For byte-oriented instructions, ‘f’ represents a file reg-
ister designator and ‘d’ represents a destination desig-
nator. The file register designator specifies which file
register is to be used by the instruction.
d
Destination select; d = 0: store result in W,
d = 1: store result in file register f.
Default is d = 1.
PC
TO
PD
Program Counter
Time-out bit
The destination designator specifies where the result of
the operation is to be placed. If ‘d’ is zero, the result is
placed in the W register. If ‘d’ is one, the result is placed
in the file register specified in the instruction.
Power-down bit
For bit-oriented instructions, ‘b’ represents a bit field
designator, which selects the bit affected by the opera-
tion, while ‘f’ represents the address of the file in which
the bit is located.
FIGURE 12-1:
GENERAL FORMAT FOR
INSTRUCTIONS
Byte-oriented file register operations
13
8
7
6
0
For literal and control operations, ‘k’ represents an
eight- or eleven-bit constant or literal value
OPCODE
d
f (FILE #)
d = 0 for destination W
d = 1 for destination f
f = 7-bit file register address
One instruction cycle consists of four oscillator periods;
for an oscillator frequency of 4 MHz, this gives a normal
instruction execution time of 1 µs. All instructions are
executed within a single instruction cycle, unless a con-
ditional test is true or the program counter is changed
as a result of an instruction. When this occurs, the exe-
cution takes two instruction cycles with the second
cycle executed as a NOP.
Bit-oriented file register operations
13 10 9
b (BIT #)
7
6
0
OPCODE
f (FILE #)
b = 3-bit bit address
f = 7-bit file register address
Note: To maintain upward compatibility with
future PIC16F872 products, do not use the
OPTIONand TRISinstructions.
Literal and control operations
General
All instruction examples use the format ‘0xhh’ to repre-
sent a hexadecimal number, where ‘h’ signifies a hexa-
decimal digit.
13
8
7
0
0
OPCODE
k (literal)
k = 8-bit immediate value
12.1 READ-MODIFY-WRITE
OPERATIONS
CALLand GOTOinstructions only
13 11 10
OPCODE
k = 11-bit immediate value
Any instruction that specifies a file register as part of
the instruction performs a Read-Modify-Write (R-M-W)
operation. The register is read, the data is modified,
and the result is stored according to either the instruc-
tion or the destination designator ‘d’. A read operation
is performed on a register even if the instruction writes
to that register.
k (literal)
2002 Microchip Technology Inc.
DS30221B-page 103
PIC16F872
TABLE 12-2: PIC16F872 INSTRUCTION SET
14-Bit Opcode
Mnemonic,
Description
Operands
Status
Affected
Cycles
Notes
MSb
LSb
BYTE-ORIENTED FILE REGISTER OPERATIONS
ADDWF
ANDWF
CLRF
CLRW
COMF
DECF
f, d
f, d
f
Add W and f
AND W with f
Clear f
Clear W
Complement f
Decrement f
Decrement f, Skip if 0
Increment f
Increment f, Skip if 0
Inclusive OR W with f
Move f
1
1
1
1
1
1
1(2)
1
1(2)
1
1
1
1
1
1
1
1
1
00 0111 dfff ffff C,DC,Z
1,2
1,2
2
00 0101 dfff ffff
00 0001 lfff ffff
00 0001 0xxx xxxx
00 1001 dfff ffff
00 0011 dfff ffff
00 1011 dfff ffff
00 1010 dfff ffff
00 1111 dfff ffff
00 0100 dfff ffff
00 1000 dfff ffff
00 0000 lfff ffff
00 0000 0xx0 0000
00 1101 dfff ffff
00 1100 dfff ffff
Z
Z
Z
Z
Z
-
f, d
f, d
f, d
f, d
f, d
f, d
f, d
f
1,2
1,2
1,2,3
1,2
1,2,3
1,2
1,2
DECFSZ
INCF
Z
INCFSZ
IORWF
MOVF
MOVWF
NOP
RLF
RRF
SUBWF
SWAPF
XORWF
Z
Z
Move W to f
No Operation
-
f, d
f, d
f, d
f, d
f, d
Rotate Left f through Carry
Rotate Right f through Carry
Subtract W from f
Swap nibbles in f
Exclusive OR W with f
C
C
1,2
1,2
1,2
1,2
1,2
00 0010 dfff ffff C,DC,Z
00 1110 dfff ffff
00 0110 dfff ffff
Z
BIT-ORIENTED FILE REGISTER OPERATIONS
BCF
BSF
BTFSC
BTFSS
f, b
f, b
f, b
f, b
Bit Clear f
Bit Set f
Bit Test f, Skip if Clear
Bit Test f, Skip if Set
1
1
1 (2)
1 (2)
01 00bb bfff ffff
1,2
1,2
3
01 01bb bfff ffff
01 10bb bfff ffff
01 11bb bfff ffff
3
LITERAL AND CONTROL OPERATIONS
ADDLW
ANDLW
CALL
CLRWDT
GOTO
IORLW
MOVLW
RETFIE
RETLW
RETURN
SLEEP
SUBLW
XORLW
k
k
k
-
k
k
k
-
k
-
-
k
k
Add literal and W
AND literal with W
Call subroutine
Clear Watchdog Timer
Go to address
1
1
2
1
2
1
1
2
2
2
1
1
1
11 111x kkkk kkkk C,DC,Z
11 1001 kkkk kkkk
10 0kkk kkkk kkkk
00 0000 0110 0100
10 1kkk kkkk kkkk
11 1000 kkkk kkkk
11 00xx kkkk kkkk
00 0000 0000 1001
11 01xx kkkk kkkk
00 0000 0000 1000
00 0000 0110 0011
Z
TO,PD
Z
Inclusive OR literal with W
Move literal to W
Return from interrupt
Return with literal in W
Return from Subroutine
Go into Standby mode
Subtract W from literal
Exclusive OR literal with W
TO,PD
11 110x kkkk kkkk C,DC,Z
11 1010 kkkk kkkk
Z
Note 1: When an I/O register is modified as a function of itself ( e.g., MOVF PORTB, 1), the value used will be that value present
on the pins themselves. For example, if the data latch is ’1’ for a pin configured as input and is driven low by an external
device, the data will be written back with a ’0’.
2: If this instruction is executed on the TMR0 register (and, where applicable, d = 1), the prescaler will be cleared if
assigned to the Timer0 module.
3: If Program Counter (PC) is modified, or a conditional test is true, the instruction requires two cycles. The second cycle is
executed as a NOP.
Note: Additional information on the mid-range instruction set is available in the PICmicro™ Mid-Range MCU
Family Reference Manual (DS33023).
DS30221B-page 104
2002 Microchip Technology Inc.
PIC16F872
12.2 Instruction Descriptions
ADDLW
Add Literal and W
BCF
Bit Clear f
Syntax:
[ label ] ADDLW
0 ≤ k ≤ 255
k
Syntax:
[ label ] BCF f,b
Operands:
Operation:
Status Affected:
Description:
Operands:
0 ≤ f ≤ 127
0 ≤ b ≤ 7
(W) + k → (W)
C, DC, Z
Operation:
0 → (f<b>)
Status Affected:
Description:
None
The contents of the W register
are added to the eight-bit literal ’k’
and the result is placed in the W
register.
Bit 'b' in register 'f' is cleared.
BSF
Bit Set f
ADDWF
Add W and f
Syntax:
[ label ] BSF f,b
Syntax:
[ label ] ADDWF f,d
Operands:
0 ≤ f ≤ 127
0 ≤ b ≤ 7
Operands:
0 ≤ f ≤ 127
d ∈ [0,1]
Operation:
1 → (f<b>)
Operation:
(W) + (f) → (destination)
Status Affected:
Description:
None
Status Affected: C, DC, Z
Bit 'b' in register 'f' is set.
Description:
Add the contents of the W register
with register ’f’. If ’d’ is 0, the result
is stored in the W register. If ’d’ is
1, the result is stored back in
register ’f’.
BTFSS
Bit Test f, Skip if Set
ANDLW
AND Literal with W
Syntax:
[ label ] BTFSS f,b
Syntax:
[ label ] ANDLW
0 ≤ k ≤ 255
k
Operands:
0 ≤ f ≤ 127
0 ≤ b < 7
Operands:
Operation:
Status Affected:
Description:
(W) .AND. (k) → (W)
Operation:
skip if (f<b>) = 1
Z
Status Affected: None
The contents of W register are
AND’ed with the eight-bit literal
'k'. The result is placed in the W
register.
Description:
If bit 'b' in register 'f' is '0', the next
instruction is executed.
If bit 'b' is '1', then the next instruc-
tion is discarded and a NOPis
executed instead, making this a
2TCY instruction.
BTFSC
Bit Test, Skip if Clear
ANDWF
AND W with f
Syntax:
[ label ] BTFSC f,b
Syntax:
[ label ] ANDWF f,d
Operands:
0 ≤ f ≤ 127
0 ≤ b ≤ 7
Operands:
0 ≤ f ≤ 127
d ∈ [0,1]
Operation:
skip if (f<b>) = 0
Operation:
(W) .AND. (f) → (destination)
Status Affected: None
Status Affected:
Description:
Z
Description: If bit 'b' in register 'f' is '1', the next
AND the W register with register
'f'. If 'd' is 0, the result is stored in
the W register. If 'd' is 1, the result
is stored back in register 'f'.
instruction is executed.
If bit 'b', in register 'f', is '0', the
next instruction is discarded, and
a NOPis executed instead, making
this a 2TCY instruction.
2002 Microchip Technology Inc.
DS30221B-page 105
PIC16F872
CALL
Call Subroutine
CLRWDT
Clear Watchdog Timer
Syntax:
[ label ] CALL k
0 ≤ k ≤ 2047
Syntax:
[ label ] CLRWDT
Operands:
Operation:
Operands:
Operation:
None
(PC)+ 1→ TOS,
k → PC<10:0>,
(PCLATH<4:3>) → PC<12:11>
00h → WDT
0 → WDT prescaler,
1 → TO
1 → PD
Status Affected: None
Status Affected: TO, PD
Description:
Call Subroutine. First, return
address (PC+1) is pushed onto
the stack. The eleven-bit immedi-
ate address is loaded into PC bits
<10:0>. The upper bits of the PC
are loaded from PCLATH. CALLis
a two-cycle instruction.
Description:
CLRWDTinstruction resets the
Watchdog Timer. It also resets
the prescaler of the WDT. Status
bits TO and PD are set.
CLRF
Clear f
COMF
Complement f
Syntax:
[ label ] CLRF
0 ≤ f ≤ 127
f
Syntax:
[ label ] COMF f,d
Operands:
Operation:
Operands:
0 ≤ f ≤ 127
d ∈ [0,1]
00h → (f)
1 → Z
Operation:
(f) → (destination)
Status Affected:
Description:
Z
Status Affected:
Description:
Z
The contents of register ’f’ are
cleared and the Z bit is set.
The contents of register ’f’ are
complemented. If ’d’ is 0, the
result is stored in W. If ’d’ is 1, the
result is stored back in register ’f’.
CLRW
Clear W
DECF
Decrement f
Syntax:
[ label ] CLRW
Syntax:
[ label ] DECF f,d
Operands:
Operation:
None
Operands:
0 ≤ f ≤ 127
d ∈ [0,1]
00h → (W)
1 → Z
Operation:
(f) - 1 → (destination)
Status Affected:
Description:
Z
Status Affected:
Description:
Z
W register is cleared. Zero bit (Z)
is set.
Decrement register ’f’. If ’d’ is 0,
the result is stored in the W
register. If ’d’ is 1, the result is
stored back in register ’f’.
DS30221B-page 106
2002 Microchip Technology Inc.
PIC16F872
DECFSZ
Decrement f, Skip if 0
INCFSZ
Increment f, Skip if 0
Syntax:
[ label ] DECFSZ f,d
Syntax:
[ label ] INCFSZ f,d
Operands:
0 ≤ f ≤ 127
d ∈ [0,1]
Operands:
0 ≤ f ≤ 127
d ∈ [0,1]
Operation:
(f) - 1 → (destination);
skip if result = 0
Operation:
(f) + 1 → (destination),
skip if result = 0
Status Affected: None
Status Affected: None
Description:
The contents of register ’f’ are
Description:
The contents of register ’f’ are
decremented. If ’d’ is 0, the result
is placed in the W register. If ’d’ is
1, the result is placed back in
register ’f’.
incremented. If ’d’ is 0, the result is
placed in the W register. If ’d’ is 1,
the result is placed back in
register ’f’.
If the result is 1, the next instruc-
tion is executed. If the result is 0,
then a NOPis executed instead,
making it a 2TCY instruction.
If the result is 1, the next instruc-
tion is executed. If the result is 0,
a NOPis executed instead, making
it a 2TCY instruction.
GOTO
Unconditional Branch
IORLW
Inclusive OR Literal with W
Syntax:
[ label ] GOTO k
0 ≤ k ≤ 2047
Syntax:
[ label ] IORLW k
0 ≤ k ≤ 255
Operands:
Operation:
Operands:
Operation:
Status Affected:
Description:
k → PC<10:0>
PCLATH<4:3> → PC<12:11>
(W) .OR. k → (W)
Z
Status Affected: None
The contents of the W register are
OR’ed with the eight-bit literal 'k'.
The result is placed in the W
register.
Description:
GOTOis an unconditional branch.
The eleven-bit immediate value is
loaded into PC bits <10:0>. The
upper bits of PC are loaded from
PCLATH<4:3>. GOTOis a two-
cycle instruction.
IORWF
Inclusive OR W with f
INCF
Increment f
Syntax:
[ label ] IORWF f,d
Syntax:
[ label ] INCF f,d
Operands:
0 ≤ f ≤ 127
d ∈ [0,1]
Operands:
0 ≤ f ≤ 127
d ∈ [0,1]
Operation:
(W) .OR. (f) → (destination)
Operation:
(f) + 1 → (destination)
Status Affected:
Description:
Z
Status Affected:
Description:
Z
Inclusive OR the W register with
register 'f'. If 'd' is 0, the result is
placed in the W register. If 'd' is 1,
the result is placed back in
register 'f'.
The contents of register ’f’ are
incremented. If ’d’ is 0, the result
is placed in the W register. If ’d’ is
1, the result is placed back in
register ’f’.
2002 Microchip Technology Inc.
DS30221B-page 107
PIC16F872
MOVF
Move f
NOP
No Operation
Syntax:
[ label ] MOVF f,d
Syntax:
[ label ] NOP
None
Operands:
0 ≤ f ≤ 127
d ∈ [0,1]
Operands:
Operation:
No operation
Operation:
(f) → (destination)
Status Affected: None
Status Affected:
Description:
Z
Description:
No operation.
The contents of register f are
moved to a destination dependant
upon the status of d. If d = 0,
destination is W register. If d = 1,
the destination is file register f itself.
d = 1 is useful to test a file register,
since status flag Z is affected.
MOVLW
Move Literal to W
RETFIE
Return from Interrupt
Syntax:
[ label ] MOVLW k
0 ≤ k ≤ 255
k → (W)
Syntax:
[ label ] RETFIE
Operands:
Operation:
Status Affected:
Description:
Operands:
Operation:
None
TOS → PC,
1 → GIE
None
Status Affected: None
The eight-bit literal ’k’ is loaded
into W register. The don’t cares
will assemble as 0’s.
MOVWF
Move W to f
RETLW
Return with Literal in W
Syntax:
[ label ] MOVWF
0 ≤ f ≤ 127
(W) → (f)
f
Syntax:
[ label ] RETLW k
0 ≤ k ≤ 255
Operands:
Operation:
Status Affected:
Description:
Operands:
Operation:
k → (W);
TOS → PC
None
Status Affected: None
Move data from W register to
register 'f'.
Description: The W register is loaded with the
eight-bit literal 'k'. The program
counter is loaded from the top of
the stack (the return address).
This is a two-cycle instruction.
DS30221B-page 108
2002 Microchip Technology Inc.
PIC16F872
RLF
Rotate Left f through Carry
SLEEP
Syntax:
[ label ] RLF f,d
Syntax:
[ label ] SLEEP
Operands:
0 ≤ f ≤ 127
d ∈ [0,1]
Operands:
Operation:
None
00h → WDT,
0 → WDT prescaler,
1 → TO,
Operation:
See description below
C
Status Affected:
Description:
0 → PD
The contents of register ’f’are rotated
one bit to the left through the Carry
Flag. If ’d’ is 0, the result is placed in
the W register. If ’d’ is 1, the result is
stored back in register ’f’.
Status Affected:
Description:
TO, PD
The power-down status bit, PD is
cleared. Time-out status bit, TO
is set. Watchdog Timer and its
prescaler are cleared.
C
Register f
The processor is put into SLEEP
mode with the oscillator stopped.
RETURN
Return from Subroutine
SUBLW
Subtract W from Literal
Syntax:
[ label ] RETURN
None
Syntax:
[ label ] SUBLW k
0 ≤ k ≤ 255
Operands:
Operation:
Operands:
Operation:
TOS → PC
k - (W) → (W)
Status Affected: None
Status Affected: C, DC, Z
Description:
Return from subroutine. The stack
Description:
The W register is subtracted (2’s
is POPed and the top of the stack
(TOS) is loaded into the program
counter. This is a two-cycle
instruction.
complement method) from the
eight-bit literal 'k'. The result is
placed in the W register.
RRF
Rotate Right f through Carry
SUBWF
Subtract W from f
Syntax:
[ label ] RRF f,d
Syntax:
[ label ] SUBWF f,d
Operands:
0 ≤ f ≤ 127
d ∈ [0,1]
Operands:
0 ≤ f ≤ 127
d ∈ [0,1]
Operation:
See description below
C
Operation:
(f) - (W) → (destination)
Status Affected:
Description:
Status
Affected:
C, DC, Z
The contents of register ’f’ are
rotated one bit to the right through
the Carry Flag. If ’d’ is 0, the result
is placed in the W register. If ’d’ is
1, the result is placed back in
register ’f’.
Description:
Subtract (2’s complement method)
W register from register 'f'. If 'd' is 0,
the result is stored in the W
register. If 'd' is 1, the result is
stored back in register 'f'.
C
Register f
2002 Microchip Technology Inc.
DS30221B-page 109
PIC16F872
SWAPF
Swap Nibbles in f
XORWF
Exclusive OR W with f
Syntax:
[ label ] SWAPF f,d
Syntax:
[ label ] XORWF f,d
Operands:
0 ≤ f ≤ 127
d ∈ [0,1]
Operands:
0 ≤ f ≤ 127
d ∈ [0,1]
Operation:
(f<3:0>) → (destination<7:4>),
(f<7:4>) → (destination<3:0>)
Operation:
(W) .XOR. (f) → (destination)
Status Affected:
Description:
Z
Status Affected: None
Exclusive OR the contents of the
W register with register 'f'. If 'd' is
0, the result is stored in the W
register. If 'd' is 1, the result is
stored back in register 'f'.
Description:
The upper and lower nibbles of
register ’f’ are exchanged. If ’d’ is
0, the result is placed in the W
register. If ’d’ is 1, the result is
placed in register ’f’.
XORLW
Exclusive OR Literal with W
Syntax:
[label] XORLW k
0 ≤ k ≤ 255
Operands:
Operation:
Status Affected:
Description:
(W) .XOR. k → (W)
Z
The contents of the W register
are XOR’ed with the eight-bit lit-
eral 'k'. The result is placed in
the W register.
DS30221B-page 110
2002 Microchip Technology Inc.
PIC16F872
The MPLAB IDE allows you to:
13.0 DEVELOPMENT SUPPORT
• Edit your source files (either assembly or ‘C’)
The PICmicro® microcontrollers are supported with a
full range of hardware and software development tools:
• One touch assemble (or compile) and download
to PICmicro emulator and simulator tools (auto-
matically updates all project information)
• Integrated Development Environment
- MPLAB® IDE Software
• Debug using:
- source files
• Assemblers/Compilers/Linkers
- MPASMTM Assembler
- absolute listing file
- machine code
- MPLAB C17 and MPLAB C18 C Compilers
- MPLINKTM Object Linker/
MPLIBTM Object Librarian
The ability to use MPLAB IDE with multiple debugging
tools allows users to easily switch from the cost-
effective simulator to a full-featured emulator with
minimal retraining.
• Simulators
- MPLAB SIM Software Simulator
• Emulators
13.2 MPASM Assembler
- MPLAB ICE 2000 In-Circuit Emulator
- ICEPIC™ In-Circuit Emulator
• In-Circuit Debugger
The MPASM assembler is a full-featured universal
macro assembler for all PICmicro MCU’s.
- MPLAB ICD
The MPASM assembler has a command line interface
and a Windows shell. It can be used as a stand-alone
application on a Windows 3.x or greater system, or it
can be used through MPLAB IDE. The MPASM assem-
bler generates relocatable object files for the MPLINK
object linker, Intel® standard HEX files, MAP files to
detail memory usage and symbol reference, an abso-
lute LST file that contains source lines and generated
machine code, and a COD file for debugging.
• Device Programmers
- PRO MATE® II Universal Device Programmer
- PICSTART® Plus Entry-Level Development
Programmer
• Low Cost Demonstration Boards
- PICDEMTM 1 Demonstration Board
- PICDEM 2 Demonstration Board
- PICDEM 3 Demonstration Board
- PICDEM 17 Demonstration Board
- KEELOQ® Demonstration Board
The MPASM assembler features include:
• Integration into MPLAB IDE projects.
• User-defined macros to streamline assembly
code.
13.1 MPLAB Integrated Development
Environment Software
• Conditional assembly for multi-purpose source
files.
The MPLAB IDE software brings an ease of software
development previously unseen in the 8-bit microcon-
troller market. The MPLAB IDE is a Windows®-based
application that contains:
• Directives that allow complete control over the
assembly process.
13.3 MPLAB C17 and MPLAB C18
C Compilers
• An interface to debugging tools
- simulator
The MPLAB C17 and MPLAB C18 Code Development
Systems are complete ANSI ‘C’ compilers for
Microchip’s PIC17CXXX and PIC18CXXX family of
microcontrollers, respectively. These compilers provide
powerful integration capabilities and ease of use not
found with other compilers.
- programmer (sold separately)
- emulator (sold separately)
- in-circuit debugger (sold separately)
• A full-featured editor
• A project manager
For easier source level debugging, the compilers pro-
vide symbol information that is compatible with the
MPLAB IDE memory display.
• Customizable toolbar and key mapping
• A status bar
• On-line help
2002 Microchip Technology Inc.
DS30221B-page 111
PIC16F872
13.4 MPLINK Object Linker/
MPLIB Object Librarian
13.6 MPLAB ICE High Performance
Universal In-Circuit Emulator with
MPLAB IDE
The MPLINK object linker combines relocatable
objects created by the MPASM assembler and the
MPLAB C17 and MPLAB C18 C compilers. It can also
link relocatable objects from pre-compiled libraries,
using directives from a linker script.
The MPLAB ICE universal in-circuit emulator is intended
to provide the product development engineer with a
complete microcontroller design tool set for PICmicro
microcontrollers (MCUs). Software control of the
MPLAB ICE in-circuit emulator is provided by the
MPLAB Integrated Development Environment (IDE),
which allows editing, building, downloading and source
debugging from a single environment.
The MPLIB object librarian is a librarian for pre-
compiled code to be used with the MPLINK object
linker. When a routine from a library is called from
another source file, only the modules that contain that
routine will be linked in with the application. This allows
large libraries to be used efficiently in many different
applications. The MPLIB object librarian manages the
creation and modification of library files.
The MPLAB ICE 2000 is a full-featured emulator sys-
tem with enhanced trace, trigger and data monitoring
features. Interchangeable processor modules allow the
system to be easily reconfigured for emulation of differ-
ent processors. The universal architecture of the
MPLAB ICE in-circuit emulator allows expansion to
support new PICmicro microcontrollers.
The MPLINK object linker features include:
• Integration with MPASM assembler and MPLAB
C17 and MPLAB C18 C compilers.
The MPLAB ICE in-circuit emulator system has been
designed as a real-time emulation system, with
advanced features that are generally found on more
expensive development tools. The PC platform and
Microsoft® Windows environment were chosen to best
make these features available to you, the end user.
• Allows all memory areas to be defined as sections
to provide link-time flexibility.
The MPLIB object librarian features include:
• Easier linking because single libraries can be
included instead of many smaller files.
• Helps keep code maintainable by grouping
related modules together.
13.7 ICEPIC In-Circuit Emulator
• Allows libraries to be created and modules to be
added, listed, replaced, deleted or extracted.
The ICEPIC low cost, in-circuit emulator is a solution
for the Microchip Technology PIC16C5X, PIC16C6X,
PIC16C7X and PIC16CXXX families of 8-bit One-
Time-Programmable (OTP) microcontrollers. The mod-
ular system can support different subsets of PIC16C5X
or PIC16CXXX products through the use of inter-
changeable personality modules, or daughter boards.
The emulator is capable of emulating without target
application circuitry being present.
13.5 MPLAB SIM Software Simulator
The MPLAB SIM software simulator allows code devel-
opment in a PC-hosted environment by simulating the
PICmicro series microcontrollers on an instruction
level. On any given instruction, the data areas can be
examined or modified and stimuli can be applied from
a file, or user-defined key press, to any of the pins. The
execution can be performed in single step, execute
until break, or trace mode.
The MPLAB SIM simulator fully supports symbolic debug-
ging using the MPLAB C17 and the MPLAB C18 C com-
pilers and the MPASM assembler. The software simulator
offers the flexibility to develop and debug code outside of
the laboratory environment, making it an excellent multi-
project software development tool.
DS30221B-page 112
2002 Microchip Technology Inc.
PIC16F872
13.8 MPLAB ICD In-Circuit Debugger
13.11 PICDEM 1 Low Cost PICmicro
Demonstration Board
Microchip’s In-Circuit Debugger, MPLAB ICD, is a pow-
erful, low cost, run-time development tool. This tool is
based on the FLASH PICmicro MCUs and can be used
to develop for this and other PICmicro microcontrollers.
The MPLAB ICD utilizes the in-circuit debugging capa-
bility built into the FLASH devices. This feature, along
with Microchip’s In-Circuit Serial ProgrammingTM proto-
col, offers cost-effective in-circuit FLASH debugging
from the graphical user interface of the MPLAB
Integrated Development Environment. This enables a
designer to develop and debug source code by watch-
ing variables, single-stepping and setting break points.
Running at full speed enables testing hardware in real-
time.
The PICDEM 1 demonstration board is a simple board
which demonstrates the capabilities of several of
Microchip’s microcontrollers. The microcontrollers sup-
ported are: PIC16C5X (PIC16C54 to PIC16C58A),
PIC16C61, PIC16C62X, PIC16C71, PIC16C8X,
PIC17C42, PIC17C43 and PIC17C44. All necessary
hardware and software is included to run basic demo
programs. The user can program the sample microcon-
trollers provided with the PICDEM 1 demonstration
board on a PRO MATE II device programmer, or a
PICSTART Plus development programmer, and easily
test firmware. The user can also connect the
PICDEM 1 demonstration board to the MPLAB ICE in-
circuit emulator and download the firmware to the emu-
lator for testing. A prototype area is available for the
user to build some additional hardware and connect it
to the microcontroller socket(s). Some of the features
include an RS-232 interface, a potentiometer for simu-
lated analog input, push button switches and eight
LEDs connected to PORTB.
13.9 PRO MATE II Universal Device
Programmer
The PRO MATE II universal device programmer is a
full-featured programmer, capable of operating in
stand-alone mode, as well as PC-hosted mode. The
PRO MATE II device programmer is CE compliant.
The PRO MATE II device programmer has program-
mable VDD and VPP supplies, which allow it to verify
programmed memory at VDD min and VDD max for max-
imum reliability. It has an LCD display for instructions
and error messages, keys to enter commands and a
modular detachable socket assembly to support various
package types. In stand-alone mode, the PRO MATE II
device programmer can read, verify, or program
PICmicro devices. It can also set code protection in this
mode.
13.12 PICDEM 2 Low Cost PIC16CXX
Demonstration Board
The PICDEM 2 demonstration board is a simple dem-
onstration board that supports the PIC16C62,
PIC16C64, PIC16C65, PIC16C73 and PIC16C74
microcontrollers. All the necessary hardware and soft-
ware is included to run the basic demonstration pro-
grams. The user can program the sample
microcontrollers provided with the PICDEM 2 demon-
stration board on a PRO MATE II device programmer,
or a PICSTART Plus development programmer, and
easily test firmware. The MPLAB ICE in-circuit emula-
tor may also be used with the PICDEM 2 demonstration
board to test firmware. A prototype area has been pro-
vided to the user for adding additional hardware and
connecting it to the microcontroller socket(s). Some of
the features include a RS-232 interface, push button
switches, a potentiometer for simulated analog input, a
serial EEPROM to demonstrate usage of the I2CTM bus
and separate headers for connection to an LCD
module and a keypad.
13.10 PICSTART Plus Entry Level
Development Programmer
The PICSTART Plus development programmer is an
easy-to-use, low cost, prototype programmer. It con-
nects to the PC via a COM (RS-232) port. MPLAB
Integrated Development Environment software makes
using the programmer simple and efficient.
The PICSTART Plus development programmer sup-
ports all PICmicro devices with up to 40 pins. Larger pin
count devices, such as the PIC16C92X and
PIC17C76X, may be supported with an adapter socket.
The PICSTART Plus development programmer is CE
compliant.
2002 Microchip Technology Inc.
DS30221B-page 113
PIC16F872
13.13 PICDEM 3 Low Cost PIC16CXXX
Demonstration Board
13.14 PICDEM 17 Demonstration Board
The PICDEM 17 demonstration board is an evaluation
board that demonstrates the capabilities of several
Microchip microcontrollers, including PIC17C752,
PIC17C756A, PIC17C762 and PIC17C766. All neces-
sary hardware is included to run basic demo programs,
which are supplied on a 3.5-inch disk. A programmed
sample is included and the user may erase it and
program it with the other sample programs using the
PRO MATE II device programmer, or the PICSTART
Plus development programmer, and easily debug and
test the sample code. In addition, the PICDEM 17 dem-
onstration board supports downloading of programs to
and executing out of external FLASH memory on board.
The PICDEM 17 demonstration board is also usable
with the MPLAB ICE in-circuit emulator, or the
PICMASTER emulator and all of the sample programs
can be run and modified using either emulator. Addition-
ally, a generous prototype area is available for user
hardware.
The PICDEM 3 demonstration board is a simple dem-
onstration board that supports the PIC16C923 and
PIC16C924 in the PLCC package. It will also support
future 44-pin PLCC microcontrollers with an LCD Mod-
ule. All the necessary hardware and software is
included to run the basic demonstration programs. The
user can program the sample microcontrollers pro-
vided with the PICDEM 3 demonstration board on a
PRO MATE II device programmer, or a PICSTART Plus
development programmer with an adapter socket, and
easily test firmware. The MPLAB ICE in-circuit emula-
tor may also be used with the PICDEM 3 demonstration
board to test firmware. A prototype area has been pro-
vided to the user for adding hardware and connecting it
to the microcontroller socket(s). Some of the features
include a RS-232 interface, push button switches, a
potentiometer for simulated analog input, a thermistor
and separate headers for connection to an external
LCD module and a keypad. Also provided on the
PICDEM 3 demonstration board is a LCD panel, with 4
commons and 12 segments, that is capable of display-
ing time, temperature and day of the week. The
PICDEM 3 demonstration board provides an additional
RS-232 interface and Windows software for showing
the demultiplexed LCD signals on a PC. A simple serial
interface allows the user to construct a hardware
demultiplexer for the LCD signals.
13.15 KEELOQ Evaluation and
Programming Tools
KEELOQ evaluation and programming tools support
Microchip’s HCS Secure Data Products. The HCS eval-
uation kit includes a LCD display to show changing
codes, a decoder to decode transmissions and a pro-
gramming interface to program test transmitters.
DS30221B-page 114
2002 Microchip Technology Inc.
PIC16F872
TABLE 13-1: DEVELOPMENT TOOLS FROM MICROCHIP
0 1 5 2 P M C
X X X C R M F
H C S X X X
X X C 9 3
/ X X C 2 5
/ X X C 2 4
X X X F 8 C 1 P I
X X C 8 2 C 1 P I
X 7 X 7 C 1 C I P
X 4 1 7 C I C P
X 9 X 6 C 1 C I P
X 8 X 6 F 1 C I P
X 8 1 6 C I C P
X 7 X 6 C 1 C I P
X 7 1 6 C I C P
X 6 2 1 6 C I F P
X
X X C 6 C 1 P I
X 6 1 6 C I C P
X 5 1 6 C I C P
0 0 1 4 C I 0 P
X
X X C 2 C 1 P I
s o l T e o r a w f t S o s r o t a u l E m e r u b g e g D s m e a r m o g P r r
s t K l a i E d v n a s d r a B o o m D e
2002 Microchip Technology Inc.
DS30221B-page 115
PIC16F872
NOTES:
DS30221B-page 116
2002 Microchip Technology Inc.
PIC16F872
14.0 ELECTRICAL CHARACTERISTICS
Absolute Maximum Ratings †
Ambient temperature under bias.................................................................................................................-55 to +125°C
Storage temperature .............................................................................................................................. -65°C to +150°C
Voltage on any pin with respect to VSS (except VDD, MCLR. and RA4) ......................................... -0.3V to (VDD + 0.3V)
Voltage on VDD with respect to VSS ............................................................................................................ -0.3 to +7.5V
Voltage on MCLR with respect to VSS (Note 2) .................................................................................................0 to +14V
Voltage on RA4 with respect to Vss..................................................................................................................0 to +8.5V
Total power dissipation (Note 1) ...............................................................................................................................1.0W
Maximum current out of VSS pin ...........................................................................................................................300 mA
Maximum current into VDD pin ..............................................................................................................................250 mA
Input clamp current, IIK (VI < 0 or VI > VDD)..................................................................................................................... 20 mA
Output clamp current, IOK (VO < 0 or VO > VDD) ............................................................................................................. 20 mA
Maximum output current sunk by any I/O pin..........................................................................................................25 mA
Maximum output current sourced by any I/O pin ....................................................................................................25 mA
Maximum current sunk by PORTA and PORTB....................................................................................................200 mA
Maximum current sourced by PORTA and PORTB ..............................................................................................200 mA
Maximum current sunk by PORTC .......................................................................................................................200 mA
Maximum current sourced by PORTC ..................................................................................................................200 mA
Note 1: Power dissipation is calculated as follows: Pdis = VDD x {IDD - ∑ IOH} + ∑ {(VDD - VOH) x IOH} + ∑(VOl x IOL)
2: Voltage spikes below VSS at the MCLR pin, inducing currents greater than 80 mA, may cause latchup. Thus,
a series resistor of 50-100Ω should be used when applying a “low” level to the MCLR pin, rather than pulling
this pin directly to VSS.
† NOTICE: Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to the
device. This is a stress rating only and functional operation of the device at those or any other conditions above those
indicated in the operation listings of this specification is not implied. Exposure to maximum rating conditions for
extended periods may affect device reliability.
2002 Microchip Technology Inc.
DS30221B-page 117
PIC16F872
FIGURE 14-1:
PIC16F872 VOLTAGE-FREQUENCY GRAPH
6.0 V
5.5 V
5.0 V
4.5 V
4.0 V
3.5 V
3.0 V
2.5 V
2.0 V
20 MHz
Frequency
FIGURE 14-2:
PIC16LF872 VOLTAGE-FREQUENCY GRAPH
6.0 V
5.5 V
5.0 V
4.5 V
4.0 V
3.5 V
3.0 V
2.5 V
2.0 V
Equation 2
2.2 V
Equation 1
4 MHz
10 MHz
20 MHz
Frequency
Equation 1: FMAX = (6.0 MHz/V) (VDDAPPMIN - 2.0V) + 4 MHz; VDDAPPMIN = 2.2V - 3.0V
Equation 2: FMAX = (10.0 MHz/V) (VDDAPPMIN - 3.0V) + 10 MHz; VDDAPPMIN = 3.0V - 4.0V
Note 1: VDDAPPMIN is the minimum voltage of the PICmicro® device in the application.
Note 2: FMAX has a maximum frequency of 10 MHz.
DS30221B-page 118
2002 Microchip Technology Inc.
PIC16F872
14.1 DC Characteristics: PIC16F872 (Commercial, Industrial)
PIC16LF872 (Commercial, Industrial)
Standard Operating Conditions (unless otherwise stated)
PIC16LF872 (Commercial, Industrial)
Operating temperature -40°C ≤ TA ≤ +85°C for industrial
0°C ≤ TA ≤ +70°C for commercial
Standard Operating Conditions (unless otherwise stated)
Operating temperature -40°C ≤ TA ≤ +85°C for industrial
0°C ≤ TA ≤ +70°C for commercial
PIC16F872 (Commercial, Industrial)
Param Symbol
No.
Characteristic/
Device
Min Typ† Max Units
Conditions
VDD
Supply Voltage
PIC16LF872
D001
2.2
—
—
5.5
V
LP,XT,RC osc configuration
(DC to 4 MHz)
D001
PIC16F872
4.0
4.5
5.5
5.5
5.5
—
V
V
V
V
LP, XT, RC osc configuration
HS osc configuration
BOR enabled, FMAX = 14 MHz(7)
D001A
D001A
PIC16LF872
PIC16F872 VBOR
D002
VDR
RAM Data Retention
—
1.5
Voltage(1)
D003
VPOR
VDD Start Voltage to
ensure internal Power-on
Reset signal
—
VSS
—
—
V
See section on Power-on Reset for details
D004
D005
SVDD
VDD Rise Rate to ensure
internal Power-on Reset
signal
0.05
3.7
—
V/ms See section on Power-on Reset for details
VBOR
IDD
Brown-out Reset
Voltage
Supply Current(2,5)
4.0
4.35
V
BODEN bit in configuration word enabled
D010
D010
D010A
D013
PIC16LF872
—
—
—
—
0.6
1.6
20
7
2.0
4
mA XT, RC osc configuration
FOSC = 4 MHz, VDD = 3.0V
PIC16F872
PIC16LF872
PIC16F872
mA RC osc configurations
FOSC = 4 MHz, VDD = 5.5V
35
15
µA LP osc configuration
FOSC = 32 kHz, VDD = 3.0V, WDT disabled
mA HS osc configuration,
FOSC = 20 MHz, VDD = 5.5V
Legend: Rows with standard voltage device data only are shaded for improved readability.
†
Data is “Typ” column is at 5V, 25°C, unless otherwise stated. These parameters are for design guidance only,
and are not tested.
Note 1: This is the limit to which VDD can be lowered without losing RAM data.
2: The supply current is mainly a function of the operating voltage and frequency. Other factors, such as I/O pin
loading and switching rate, oscillator type, internal code execution pattern and temperature, also have an
impact on the current consumption.
The test conditions for all IDD measurements in active operation mode are:
OSC1 = external square wave, from rail-to-rail; all I/O pins tri-stated, pulled to VDD
MCLR = VDD; WDT enabled/disabled as specified.
3: The power-down current in SLEEP mode does not depend on the oscillator type. Power-down current is mea-
sured with the part in SLEEP mode, with all I/O pins in hi-impedance state and tied to VDD and VSS.
4: For RC osc configuration, current through REXT is not included. The current through the resistor can be esti-
mated by the formula Ir = VDD/2REXT (mA) with REXT in kOhm.
5: Timer1 oscillator (when enabled) adds approximately 20 µA to the specification. This value is from character-
ization and is for design guidance only. This is not tested.
6: The ∆ current is the additional current consumed when this peripheral is enabled. This current should be
added to the base IDD or IPD measurement.
7: When BOR is enabled, the device will operate correctly until the VBOR voltage trip point is reached.
2002 Microchip Technology Inc.
DS30221B-page 119
PIC16F872
14.1 DC Characteristics: PIC16F872 (Commercial, Industrial)
PIC16LF872 (Commercial, Industrial) (Continued)
Standard Operating Conditions (unless otherwise stated)
Operating temperature -40°C ≤ TA ≤ +85°C for industrial
0°C ≤ TA ≤ +70°C for commercial
PIC16LF872 (Commercial, Industrial)
PIC16F872 (Commercial, Industrial)
Standard Operating Conditions (unless otherwise stated)
Operating temperature -40°C ≤ TA ≤ +85°C for industrial
0°C ≤ TA ≤ +70°C for commercial
Param Symbol
No.
Characteristic/
Device
Min Typ† Max Units
Conditions
D015
∆IBOR
Brown-out
—
85
200
µA BOR enabled, VDD = 5.0V
Reset Current(6)
Power-down Current(3,5)
PIC16LF872
IPD
D020
D020
D021
D021
D021A
D021A
D023
—
—
—
—
7.5
10.5
0.9
1.5
0.9
1.5
85
30
42
5
µA VDD = 3.0V, WDT enabled,
-40°C to +85°C
µA VDD = 4.0V, WDT enabled,
-40°C to +85°C
PIC16F872
PIC16LF872
PIC16F872
PIC16LF872
PIC16F872
µA VDD = 3.0V, WDT disabled,
0°C to +70°C
16
5
µA VDD = 4.0V, WDT disabled,
-40°C to +85°C
µA VDD = 3.0V, WDT disabled,
-40°C to +85°C
19
200
µA VDD = 4.0V, WDT disabled,
-40°C to +85°C
∆IBOR
Brown-out
—
µA BOR enabled, VDD = 5.0V
Reset Current(6)
Legend: Rows with standard voltage device data only are shaded for improved readability.
†
Data is “Typ” column is at 5V, 25°C, unless otherwise stated. These parameters are for design guidance only,
and are not tested.
Note 1: This is the limit to which VDD can be lowered without losing RAM data.
2: The supply current is mainly a function of the operating voltage and frequency. Other factors, such as I/O pin
loading and switching rate, oscillator type, internal code execution pattern and temperature, also have an
impact on the current consumption.
The test conditions for all IDD measurements in active operation mode are:
OSC1 = external square wave, from rail-to-rail; all I/O pins tri-stated, pulled to VDD
MCLR = VDD; WDT enabled/disabled as specified.
3: The power-down current in SLEEP mode does not depend on the oscillator type. Power-down current is mea-
sured with the part in SLEEP mode, with all I/O pins in hi-impedance state and tied to VDD and VSS.
4: For RC osc configuration, current through REXT is not included. The current through the resistor can be esti-
mated by the formula Ir = VDD/2REXT (mA) with REXT in kOhm.
5: Timer1 oscillator (when enabled) adds approximately 20 µA to the specification. This value is from character-
ization and is for design guidance only. This is not tested.
6: The ∆ current is the additional current consumed when this peripheral is enabled. This current should be
added to the base IDD or IPD measurement.
7: When BOR is enabled, the device will operate correctly until the VBOR voltage trip point is reached.
DS30221B-page 120
2002 Microchip Technology Inc.
PIC16F872
14.2 DC Characteristics: PIC16F872 (Commercial, Industrial)
PIC16LF872 (Commercial, Industrial)
Standard Operating Conditions (unless otherwise stated)
Operating temperature -40°C ≤ TA ≤ +85°C for industrial
0°C ≤ TA ≤ +70°C for commercial
DC CHARACTERISTICS
Operating voltage VDD range as described in DC specification
(Section 14.1)
Param
Sym
No.
Characteristic
Min
Typ† Max Units
Conditions
VIL
Input Low Voltage
I/O ports:
with TTL buffer
D030
D030A
D031
D032
D033
VSS
VSS
VSS
VSS
VSS
-
-
-
-
-
0.15VDD
0.8V
V
V
V
V
V
For entire VDD range
4.5V ≤ VDD ≤ 5.5V
with Schmitt Trigger buffer
MCLR, OSC1 (in RC mode)
OSC1 (in XT, HS and LP modes)
Ports RC3 and RC4:
with Schmitt Trigger buffer
with SMBus
0.2VDD
0.2VDD
0.3VDD
(Note 1)
D034
VSS
-0.5
-
-
0.3VDD
0.6
V
V
For entire VDD range
for VDD = 4.5 to 5.5V
D034A
VIH
Input High Voltage
I/O ports:
-
-
-
D040
with TTL buffer
2.0
VDD
VDD
V
V
4.5V ≤ VDD ≤ 5.5V
For entire VDD range
D040A
0.25VDD
+ 0.8V
D041
D042
D042A
D043
with Schmitt Trigger buffer
MCLR
0.8VDD
0.8VDD
0.7VDD
0.9VDD
-
-
-
-
VDD
VDD
VDD
VDD
V
V
V
V
For entire VDD range
OSC1 (XT, HS and LP modes)
OSC1 (in RC mode)
Ports RC3 and RC4:
with Schmitt Trigger buffer
with SMBus
(Note 1)
D044
D044A
D070
0.7VDD
1.4
-
-
VDD
5.5
V
V
For entire VDD range
for VDD = 4.5 to 5.5V
IPURB PORTB Weak Pull-up Current
50
250
400
µA VDD = 5V, VPIN = VSS,
-40°C TO +85°C
Input Leakage Current(2, 3)
IIL
D060
I/O ports
-
-
1
µA Vss ≤ VPIN ≤ VDD,
Pin at hi-impedance
D061
D063
MCLR, RA4/T0CKI
OSC1
-
-
-
-
5
5
µA Vss ≤ VPIN ≤ VDD
µA Vss ≤ VPIN ≤ VDD, XT, HS
and LP osc configuration
*
These parameters are characterized but not tested.
†
Data in "Typ" column is at 5V, 25°C unless otherwise stated. These parameters are for design guidance
only and are not tested.
Note 1: In RC oscillator configuration, the OSC1/CLKIN pin is a Schmitt Trigger input. It is not recommended that the
PIC16F872 be driven with external clock in RC mode.
2: The leakage current on the MCLR pin is strongly dependent on the applied voltage level. The specified levels
represent normal operating conditions. Higher leakage current may be measured at different input voltages.
3: Negative current is defined as current sourced by the pin.
2002 Microchip Technology Inc.
DS30221B-page 121
PIC16F872
14.2 DC Characteristics: PIC16F872 (Commercial, Industrial)
PIC16LF872 (Commercial, Industrial) (Continued)
Standard Operating Conditions (unless otherwise stated)
Operating temperature -40°C ≤ TA ≤ +85°C for industrial
0°C ≤ TA ≤ +70°C for commercial
DC CHARACTERISTICS
Operating voltage VDD range as described in DC specification
(Section 14.1)
Param
Sym
No.
Characteristic
Min
Typ† Max Units
Conditions
VOL
VOH
Output Low Voltage
D080
D083
I/O ports
-
-
-
-
0.6
0.6
V
V
IOL = 8.5 mA, VDD = 4.5V,
-40°C to +85°C
IOL = 1.6 mA, VDD = 4.5V,
-40°C to +85°C
OSC2/CLKOUT (RC osc config)
Output High Voltage
I/O ports(3)
D090
D092
VDD - 0.7
-
-
-
-
-
V
V
V
IOH = -3.0 mA, VDD = 4.5V,
-40°C to +85°C
IOH = -1.3 mA, VDD = 4.5V,
-40°C to +85°C
OSC2/CLKOUT (RC osc config) VDD - 0.7
D150* VOD
Open Drain High Voltage
-
-
8.5
RA4 pin
Capacitive Loading Specs on
Output Pins
D100
COSC2 OSC2 pin
-
15
pF In XT, HS and LP modes when
external clock is used to drive
OSC1
D101
D102
CIO
CB
All I/O pins and OSC2 (RC
mode) SCL, SDA (I2C mode)
-
-
-
-
50
400
pF
pF
Data EEPROM Memory
D120
D121
ED
Endurance
100K
VMIN
-
-
-
E/W 25°C at 5V
VDRW VDD for read/write
5.5
V
Using EECON to read/write
VMIN = min. operating voltage
D122
TDEW Erase/write cycle time
-
4
8
ms
Program FLASH Memory
D130
D131
D132A
EP
Endurance
1000
VMIN
VMIN
-
-
-
-
E/W 25°C at 5V
VPR
VDD for read
5.5
5.5
V
Vmin = min operating voltage
VDD for erase/write
V
Using EECON to read/write,
VMIN = min. operating voltage
D133
TPEW Erase/Write cycle time
-
4
8
ms
*
These parameters are characterized but not tested.
†
Data in "Typ" column is at 5V, 25°C unless otherwise stated. These parameters are for design guidance
only and are not tested.
Note 1: In RC oscillator configuration, the OSC1/CLKIN pin is a Schmitt Trigger input. It is not recommended that the
PIC16F872 be driven with external clock in RC mode.
2: The leakage current on the MCLR pin is strongly dependent on the applied voltage level. The specified levels
represent normal operating conditions. Higher leakage current may be measured at different input voltages.
3: Negative current is defined as current sourced by the pin.
DS30221B-page 122
2002 Microchip Technology Inc.
PIC16F872
14.3 DC Characteristics: PIC16F872 (Extended)
Standard Operating Conditions (unless otherwise stated)
Operating temperature -40°C ≤ TA ≤ +125°C
PIC16F872 (Extended)
Param Symbol
No.
Characteristic/
Device
Min
Typ† Max Units
Conditions
VDD
Supply Voltage
D001
4.0
4.5
—
5.5
5.5
5.5
—
V
V
V
V
LP, XT, RC osc configuration
HS osc configuration
BOR enabled, FMAX = 14 MHz(7)
D001A
D001A
D002
VBOR
—
VDR
RAM Data Retention
Voltage(1)
1.5
D003
D004
D005
VPOR
VDD Start Voltage to
ensure internal Power-on
Reset signal
—
VSS
—
—
V
See section on Power-on Reset for
details
SVDD
VDD Rise Rate to ensure 0.05
internal Power-on Reset
signal
—
V/ms See section on Power-on Reset for
details
VBOR
IDD
Brown-out Reset
Voltage
Supply Current(2,5)
3.7
4.0
4.35
V
BODEN bit in configuration word
enabled
D010
D013
D015
—
—
—
1.6
7
4
mA RC osc configurations
FOSC = 4 MHz, VDD = 5.5V
15
mA HS osc configuration,
FOSC = 20 MHZ, VDD = 5.5V
∆IBOR
Brown-out
85
200
µA BOR enabled, VDD = 5.0V
Reset Current(6)
IPD
Power-down
Current(3,5)
D020A
D021B
D023
10.5
1.5
85
60
30
µA VDD = 4.0V, WDT enabled
µA VDD = 4.0V, WDT disabled
µA BOR enabled, VDD = 5.0V
∆IBOR
Brown-out
—
200
Reset Current(6)
†
Data in “Typ” column is at 5V, 25°C, unless otherwise stated. These parameters are for design guidance only,
and are not tested.
Note 1: This is the limit to which VDD can be lowered without losing RAM data.
2: The supply current is mainly a function of the operating voltage and frequency. Other factors, such as I/O pin
loading and switching rate, oscillator type, internal code execution pattern and temperature also have an
impact on the current consumption.
The test conditions for all IDD measurements in active operation mode are:
OSC1 = external square wave, from rail-to-rail; all I/O pins tri-stated, pulled to VDD
MCLR = VDD; WDT enabled/disabled as specified.
3: The power-down current in SLEEP mode does not depend on the oscillator type. Power-down current is
measured with the part in SLEEP mode, with all I/O pins in hi-impedance state and tied to VDD and VSS.
4: For RC osc configuration, current through REXT is not included. The current through the resistor can be esti-
mated by the formula Ir = VDD/2REXT (mA) with REXT in kOhm.
5: Timer1 oscillator (when enabled) adds approximately 20 µA to the specification. This value is from charac-
terization and is for design guidance only. This is not tested.
6: The ∆ current is the additional current consumed when this peripheral is enabled. This current should be
added to the base IDD or IPD measurement.
7: When BOR is enabled, the device will operate correctly until the VBOR voltage trip point is reached.
2002 Microchip Technology Inc.
DS30221B-page 123
PIC16F872
14.4 DC Characteristics: PIC16F872 (Extended)
Standard Operating Conditions (unless otherwise stated)
Operating temperature -40°C ≤ TA ≤ +125°C
Operating voltage VDD range as described in DC specification
(Section 14.1)
DC CHARACTERISTICS
Param
Sym
No.
Characteristic
Min
Typ†
Max Units
Conditions
VIL
Input Low Voltage
I/O ports:
with TTL buffer
D030
D030A
D031
D032
D033
Vss
Vss
Vss
VSS
VSS
-
-
-
-
-
0.15VDD
0.8V
V
V
V
V
V
For entire VDD range
4.5V ≤ VDD ≤ 5.5V
with Schmitt Trigger buffer
MCLR, OSC1 (in RC mode)
OSC1 (in XT, HS and LP modes)
Ports RC3 and RC4:
with Schmitt Trigger buffer
with SMBus
0.2VDD
0.2VDD
0.3VDD
(Note1)
D034
Vss
-0.5
-
-
0.3VDD
0.6
V
V
For entire VDD range
for VDD = 4.5 to 5.5V
D034A
VIH
Input High Voltage
I/O ports:
-
-
-
D040
with TTL buffer
2.0
VDD
VDD
V
V
4.5V ≤ VDD ≤ 5.5V
For entire VDD range
D040A
0.25VDD
+ 0.8V
D041
D042
D042A
D043
with Schmitt Trigger buffer
MCLR
0.8VDD
0.8VDD
0.7VDD
0.9VDD
-
-
-
-
VDD
VDD
VDD
VDD
V
V
V
V
For entire VDD range
OSC1 (XT, HS and LP modes)
OSC1 (in RC mode)
Ports RC3 and RC4:
with Schmitt Trigger buffer
with SMBus
(Note1)
D044
0.7VDD
1.4
-
-
VDD
5.5
V
V
For entire VDD range
for VDD = 4.5 to 5.5V
D044A
D070A IPURB PORTB Weak Pull-up Current
50
300
500
µA VDD = 5V, VPIN = VSS,
Input Leakage Current(2, 3)
IIL
D060
I/O ports
-
-
1
µA Vss ≤ VPIN ≤ VDD,
Pin at hi-impedance
D061
D063
MCLR, RA4/T0CKI
OSC1
-
-
-
-
5
5
µA Vss ≤ VPIN ≤ VDD
µA Vss ≤ VPIN ≤ VDD, XT, HS
and LP osc configuration
*
These parameters are characterized but not tested.
†
Data in "Typ" column is at 5V, 25°C unless otherwise stated. These parameters are for design guidance
only and are not tested.
Note 1: In RC oscillator configuration, the OSC1/CLKIN pin is a Schmitt Trigger input. It is not recommended that the
PIC16F872 be driven with external clock in RC mode.
2: The leakage current on the MCLR pin is strongly dependent on the applied voltage level. The specified levels
represent normal operating conditions. Higher leakage current may be measured at different input voltages.
3: Negative current is defined as current sourced by the pin.
DS30221B-page 124
2002 Microchip Technology Inc.
PIC16F872
14.4 DC Characteristics: PIC16F872 (Extended) (Continued)
Standard Operating Conditions (unless otherwise stated)
Operating temperature -40°C ≤ TA ≤ +125°C
Operating voltage VDD range as described in DC specification
(Section 14.1)
DC CHARACTERISTICS
Param
Sym
No.
Characteristic
Min
Typ†
Max Units
Conditions
VOL
Output Low Voltage
I/O Ports
D080A
D083A
0.6
0.6
V
V
IOL =2.5 mA, VDD = 4.5V
IOL = 1.2 mA, VDD = 4.5V
OSC2/CLKOUT (RC osc config)
Output High Voltage
I/O ports(3)
VOH
D090A
D092A
VDD - 0.7
-
-
-
-
-
V
V
V
IOH = -2.5 mA, VDD = 4.5V
IOH = -1.0 mA, VDD = 4.5V
RA4 pin
OSC2/CLKOUT (RC osc config) VDD - 0.7
D150* VOD
Open Drain High Voltage
-
8.5
Capacitive Loading Specs on
Output Pins
D100
COSC2 OSC2 pin
-
-
15
pF In XT, HS and LP modes when
external clock is used to drive
OSC1
D101
D102
CIO
CB
All I/O pins and OSC2
(RC mode)
-
-
-
-
50
pF
SCL, SDA (I2C mode)
400
pF
Data EEPROM Memory
D120
D121
ED
Endurance
100K
VMIN
-
-
-
E/W 25°C at 5V
VDRW VDD for read/write
5.5
V
Using EECON to read/write
VMIN = min. operating voltage
D122
TDEW Erase/write cycle time
-
4
8
ms
Program FLASH Memory
D130
D131
D132A
EP
Endurance
1000
VMIN
VMIN
-
-
-
-
E/W 25°C at 5V
VPR
VDD for read
5.5
5.5
V
VMIN = min. operating voltage
VDD for erase/write
V
Using EECON to read/write,
VMIN = min. operating voltage
D133
TPEW Erase/Write cycle time
-
4
8
ms
*
These parameters are characterized but not tested.
†
Data in "Typ" column is at 5V, 25°C unless otherwise stated. These parameters are for design guidance
only and are not tested.
Note 1: In RC oscillator configuration, the OSC1/CLKIN pin is a Schmitt Trigger input. It is not recommended that the
PIC16F872 be driven with external clock in RC mode.
2: The leakage current on the MCLR pin is strongly dependent on the applied voltage level. The specified levels
represent normal operating conditions. Higher leakage current may be measured at different input voltages.
3: Negative current is defined as current sourced by the pin.
2002 Microchip Technology Inc.
DS30221B-page 125
PIC16F872
14.5 Timing Parameter Symbology
The timing parameter symbols have been created fol-
lowing one of the following formats:
(I2C specifications only)
(I2C specifications only)
1. TppS2ppS
2. TppS
T
3. TCC:ST
4. Ts
F
Frequency
Lowercase letters (pp) and their meanings:
pp
cc
T
Time
CCP1
CLKOUT
CS
osc
rd
OSC1
RD
ck
cs
di
rw
sc
ss
t0
RD or WR
SCK
SDI
do
dt
SDO
SS
Data in
I/O port
MCLR
T0CKI
T1CKI
WR
io
t1
mc
wr
Uppercase letters and their meanings:
S
F
H
I
Fall
P
R
V
Z
Period
High
Rise
Invalid (Hi-impedance)
Low
Valid
L
Hi-impedance
I2C only
AA
output access
Bus free
High
Low
High
Low
BUF
TCC:ST (I2C specifications only)
CC
HD
ST
DAT
STA
Hold
SU
Setup
DATA input hold
START condition
STO
STOP condition
FIGURE 14-3:
LOAD CONDITIONS
Load Condition 1
Load Condition 2
VDD/2
RL
CL
CL
Pin
Pin
VSS
VSS
RL = 464 Ω
CL = 50 pF for all pins except OSC2, but including PORTD and PORTE outputs as ports
15 pF for OSC2 output
DS30221B-page 126
2002 Microchip Technology Inc.
PIC16F872
FIGURE 14-4:
EXTERNAL CLOCK TIMING
Q4
Q1
Q2
Q3
Q4
4
Q1
OSC1
1
3
4
3
2
CLKOUT
TABLE 14-1: EXTERNAL CLOCK TIMING REQUIREMENTS
Parameter
Sym
Characteristic
Min Typ†
Max
Units
Conditions
No.
FOSC External CLKIN Frequency
DC
DC
DC
DC
DC
0.1
—
—
—
—
—
—
4
4
MHz XT and RC osc mode
MHz HS osc mode (-04)
MHz HS osc mode (-20)
kHz LP osc mode
(Note 1)
20
200
4
Oscillator Frequency
(Note 1)
MHz RC osc mode
4
MHz XT osc mode
4
5
—
—
20
200
MHz HS osc mode
kHz LP osc mode
1
TOSC
External CLKIN Period
(Note 1)
250
250
50
—
—
—
—
—
—
—
—
—
TCY
—
—
ns XT and RC osc mode
ns HS osc mode (-04)
ns HS osc mode (-20)
µs LP osc mode
—
5
—
Oscillator Period
(Note 1)
250
250
250
50
—
ns RC osc mode
10,000
250
250
—
ns XT osc mode
ns HS osc mode (-04)
ns HS osc mode (-20)
µs LP osc mode
5
2
3
TCY
Instruction Cycle Time
(Note 1)
200
DC
ns TCY = 4/FOSC
TosL, External Clock in (OSC1) High or 100
TosH Low Time
—
—
—
—
—
—
—
—
—
25
50
15
ns XT oscillator
µs LP oscillator
ns HS oscillator
ns XT oscillator
ns LP oscillator
ns HS oscillator
2.5
15
4
TosR, External Clock in (OSC1) Rise or
TosF Fall Time
—
—
—
†
Data in "Typ" column is at 5V, 25°C unless otherwise stated. These parameters are for design guidance
only and are not tested.
Note 1: Instruction cycle period (TCY) equals four times the input oscillator time-base period. All specified values are
based on characterization data for that particular oscillator type under standard operating conditions with
the device executing code. Exceeding these specified limits may result in an unstable oscillator operation
and/or higher than expected current consumption. All devices are tested to operate at "Min." values with an
external clock applied to the OSC1/CLKIN pin. When an external clock input is used, the "Max." cycle time
limit is "DC" (no clock) for all devices.
2002 Microchip Technology Inc.
DS30221B-page 127
PIC16F872
FIGURE 14-5:
CLKOUT AND I/O TIMING
Q1
Q2
Q3
Q4
OSC1
11
10
CLKOUT
13
12
18
19
14
16
I/O Pin
(input)
15
17
I/O Pin
(output)
new value
old value
20, 21
Note: Refer to Figure 14-3 for load conditions.
TABLE 14-2: CLKOUT AND I/O TIMING REQUIREMENTS
Param
No.
Symbol
Characteristic
Min
Typ†
Max
Units Conditions
10*
11*
12*
13*
14*
15*
16*
17*
TosH2ckL OSC1↑ to CLKOUT↓
TosH2ckH OSC1↑ to CLKOUT↑
—
75
75
35
35
—
200
200
ns
ns
ns
ns
ns
ns
ns
ns
(Note 1)
(Note 1)
(Note 1)
(Note 1)
(Note 1)
(Note 1)
(Note 1)
—
TckR
TckF
CLKOUT rise time
CLKOUT fall time
—
100
—
100
TckL2ioV CLKOUT↓ to Port out valid
TioV2ckH Port in valid before CLKOUT↑
TckH2ioI Port in hold after CLKOUT↑
—
0.5TCY + 20
—
TOSC + 200
—
0
—
—
TosH2ioV OSC1↑ (Q1 cycle) to
—
100
255
Port out valid
18*
TosH2ioI OSC1↑ (Q2 cycle) to Port
Standard (F)
100
200
0
—
—
—
10
—
10
—
—
—
—
—
ns
ns
ns
ns
ns
ns
ns
ns
ns
input invalid (I/O in hold time)
Extended (LF)
19*
20*
TioV2osH Port input valid to OSC1↑ (I/O in setup time)
—
TIOR
Port output rise time
Port output fall time
INT pin high or low time
Standard (F)
Extended (LF)
Standard (F)
Extended (LF)
—
40
145
40
145
—
—
21*
TIOF
—
—
22††* TINP
23††* TRBP
TCY
TCY
RB7:RB4 change INT high or low time
—
*
These parameters are characterized but not tested.
†
Data in "Typ" column is at 5V, 25°C unless otherwise stated. These parameters are for design guidance only and are
not tested.
†† These parameters are asynchronous events not related to any internal clock edges.
Note 1: Measurements are taken in RC mode, where CLKOUT output is 4 x TOSC.
DS30221B-page 128
2002 Microchip Technology Inc.
PIC16F872
FIGURE 14-6:
RESET, WATCHDOG TIMER, OSCILLATOR START-UP TIMER AND
POWER-UP TIMER TIMING
VDD
MCLR
30
Internal
POR
33
PWRT
Time-out
32
OSC
Time-out
Internal
Reset
Watchdog
Timer
Reset
31
34
34
I/O Pins
Note: Refer to Figure 14-3 for load conditions.
FIGURE 14-7:
BROWN-OUT RESET TIMING
VBOR
VDD
35
TABLE 14-3: RESET, WATCHDOG TIMER, OSCILLATOR START-UP TIMER, POWER-UP TIMER,
AND BROWN-OUT RESET REQUIREMENTS
Parameter
Symbol
Characteristic
Min
Typ†
Max
Units
Conditions
No.
30
TMCL
TWDT
MCLR Pulse Width (Low)
2
7
—
—
µs
VDD = 5V, -40°C to +85°C
31*
Watchdog Timer Time-out Period
(No Prescaler)
18
33
ms VDD = 5V, -40°C to +85°C
32
33*
34
TOST
TPWRT
TIOZ
Oscillation Start-up Timer Period
Power up Timer Period
—
28
—
1024 TOSC
—
132
2.1
—
TOSC = OSC1 period
72
ms VDD = 5V, -40°C to +85°C
µs
I/O Hi-Impedance from MCLR Low
or Watchdog Timer Reset
—
35
TBOR
Brown-out Reset Pulse Width
100
—
—
µs
VDD ≤ VBOR (D005)
*
These parameters are characterized but not tested.
†
Data in "Typ" column is at 5V, 25°C unless otherwise stated. These parameters are for design guidance only and are
not tested.
2002 Microchip Technology Inc.
DS30221B-page 129
PIC16F872
FIGURE 14-8:
TIMER0 AND TIMER1 EXTERNAL CLOCK TIMINGS
RA4/T0CKI
41
40
42
RC0/T1OSO/T1CKI
46
45
47
48
TMR0 or
TMR1
Note: Refer to Figure 14-3 for load conditions.
TABLE 14-4: TIMER0 AND TIMER1 EXTERNAL CLOCK REQUIREMENTS
Param
No.
Symbol
Tt0H
Characteristic
T0CKI High Pulse Width
Min
Typ† Max Units
Conditions
40*
No Prescaler
With Prescaler
No Prescaler
With Prescaler
No Prescaler
With Prescaler
0.5TCY + 20
10
—
—
—
—
—
—
—
—
—
—
—
—
ns Must also meet
parameter 42
ns
ns Must also meet
41*
42*
Tt0L
Tt0P
T0CKI Low Pulse Width
T0CKI Period
0.5TCY + 20
10
parameter 42
ns
ns
TCY + 40
Greater of:
20 or TCY + 40
N
ns N = prescale
value (2, 4,...,
256)
45*
46*
47*
Tt1H
Tt1L
Tt1P
T1CKI High Time Synchronous, Prescaler = 1
0.5TCY + 20
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
ns Must also meet
parameter 47
Synchronous,
Prescaler = 2,4,8
Standard(F)
Extended(LF)
Standard(F)
Extended(LF)
15
ns
ns
ns
ns
25
Asynchronous
30
50
T1CKI Low Time Synchronous, Prescaler = 1
0.5TCY + 20
ns Must also meet
parameter 47
Synchronous,
Prescaler = 2,4,8
Standard(F)
Extended(LF)
Standard(F)
Extended(LF)
Standard(F)
15
25
30
50
ns
ns
ns
ns
Asynchronous
Synchronous
T1CKI Input
Period
Greater of:
30 OR TCY + 40
N
ns N = prescale
value (1, 2, 4, 8)
Extended(LF)
Greater of:
50 OR TCY + 40
N
N = prescale
value (1, 2, 4, 8)
Asynchronous
Standard(F)
60
100
DC
—
—
—
—
—
ns
ns
Extended(LF)
Ft1
Timer1 Oscillator Input Frequency Range
(oscillator enabled by setting bit T1OSCEN)
200
kHz
48
TCKEZtmr1 Delay from External Clock Edge to Timer Increment
These parameters are characterized but not tested.
2TOSC
—
7TOSC
—
*
†
Data in "Typ" column is at 5V, 25°C unless otherwise stated. These parameters are for design guidance only and are not tested.
DS30221B-page 130
2002 Microchip Technology Inc.
PIC16F872
FIGURE 14-9:
CAPTURE/COMPARE/PWM TIMINGS
RC1/T1OSI/CCP2
and RC2/CCP1
(Capture Mode)
50
51
52
RC1/T1OSI/CCP2
and RC2/CCP1
(Compare or PWM Mode)
53
Note: Refer to Figure 14-3 for load conditions.
54
TABLE 14-5: CAPTURE/COMPARE/PWM REQUIREMENTS
Param
No.
Sym
Characteristic
No Prescaler
With Prescaler
Min
Typ† Max Units
Conditions
50*
TccL CCP1 Input Low Time
0.5TCY + 20
—
—
—
—
—
—
—
—
—
—
—
—
—
—
ns
ns
ns
ns
ns
ns
Standard(F)
10
Extended(LF)
20
0.5TCY + 20
10
51*
TccH CCP1 Input High Time No Prescaler
With Prescaler
Standard(F)
Extended(LF)
20
52*
53*
TccP CCP1 Input Period
3TCY + 40
N
ns N = prescale
value (1,4 or 16)
TccR CCP1 Output Rise Time
TccF CCP1 Output Fall Time
Standard(F)
Extended(LF)
Standard(F)
Extended(LF)
—
—
—
—
10
25
10
25
25
50
25
45
ns
ns
ns
ns
54*
* These parameters are characterized but not tested.
† Data in "Typ" column is at 5V, 25°C unless otherwise stated. These parameters are for design guidance only and are not tested.
2002 Microchip Technology Inc.
DS30221B-page 131
PIC16F872
FIGURE 14-10:
SPI MASTER MODE TIMING (CKE = 0, SMP = 0)
SS
70
SCK
(CKP = 0)
71
72
78
79
79
SCK
(CKP = 1)
78
80
MSb
BIT6 - - - - - -1
LSb
SDO
SDI
75, 76
MSb IN
74
BIT6 - - - -1
LSb IN
73
Note: Refer to Figure 14-3 for load conditions.
FIGURE 14-11:
SPI MASTER MODE TIMING (CKE = 1, SMP = 1)
SS
81
SCK
(CKP = 0)
71
72
79
78
73
SCK
(CKP = 1)
80
LSb
MSb
BIT6 - - - - - -1
BIT6 - - - -1
SDO
SDI
75, 76
MSb IN
74
LSb IN
Note: Refer to Figure 14-3 for load conditions.
DS30221B-page 132
2002 Microchip Technology Inc.
PIC16F872
FIGURE 14-12:
SPI SLAVE MODE TIMING (CKE = 0)
SS
70
SCK
(CKP = 0)
83
71
72
78
79
79
SCK
(CKP = 1)
78
80
MSb
LSb
SDO
SDI
BIT6 - - - - - -1
77
75, 76
MSb IN
74
BIT6 - - - -1
LSb IN
73
Note: Refer to Figure 14-3 for load conditions.
FIGURE 14-13:
SPI SLAVE MODE TIMING (CKE = 1)
82
SS
70
SCK
83
(CKP = 0)
71
72
SCK
(CKP = 1)
80
MSb
BIT6 - - - - - -1
BIT6 - - - -1
LSb
SDO
SDI
75, 76
77
MSb IN
74
LSb IN
Note: Refer to Figure 14-3 for load conditions.
2002 Microchip Technology Inc.
DS30221B-page 133
PIC16F872
TABLE 14-6: SPI MODE REQUIREMENTS
Param
No.
Symbol
Characteristic
SS↓ to SCK↓ or SCK↑ Input
Min
Typ†
Max Units Conditions
70*
TssL2scH,
TssL2scL
TCY
—
—
ns
71*
72*
73*
TscH
TscL
SCK Input High Time (Slave mode)
SCK Input Low Time (Slave mode)
Setup Time of SDI Data Input to SCK Edge
TCY + 20
TCY + 20
100
—
—
—
—
—
—
ns
ns
ns
TdiV2scH,
TdiV2scL
74*
75*
TscH2diL,
TscL2diL
Hold Time of SDI Data Input to SCK Edge
100
—
—
ns
TdoR
SDO Data Output Rise Time
Standard(F)
Extended(LF)
—
—
10
25
25
50
ns
ns
76*
77*
78*
TdoF
SDO Data Output Fall Time
—
10
25
50
ns
ns
TssH2doZ
TscR
SS↑ to SDO Output Hi-Impedance
10
—
SCK Output Rise Time (Master mode) Standard(F)
Extended(LF)
—
—
10
25
25
50
ns
ns
79*
80*
TscF
SCK Output Fall Time (Master mode)
—
10
25
ns
ns
TscH2doV, SDO Data Output Valid after SCK
TscL2doV Edge
Standard(F)
Extended(LF)
—
—
—
—
50
145
81*
TdoV2scH, SDO Data Output Setup to SCK Edge
TdoV2scL
TCY
—
—
ns
82*
83*
TssL2doV
SDO Data Output Valid after SS↓ Edge
—
—
—
50
ns
ns
TscH2ssH, SS↑ after SCK Edge
1.5TCY + 40
—
TscL2ssH
*
These parameters are characterized but not tested.
†
Data in "Typ" column is at 5V, 25°C unless otherwise stated. These parameters are for design guidance only and are not tested.
FIGURE 14-14:
I2C BUS START/STOP BITS TIMING
SCL
SDA
93
91
90
92
STOP
Condition
START
Condition
Note: Refer to Figure 14-3 for load conditions.
TABLE 14-7: I2C BUS START/STOP BITS REQUIREMENTS
Parameter
Symbol
Characteristic
START condition
Min Typ Max Units
Conditions
No.
90
TSU:STA
100 kHz mode
400 kHz mode
100 kHz mode
400 kHz mode
100 kHz mode
400 kHz mode
100 kHz mode
400 kHz mode
4700
600
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
ns
ns
ns
ns
Only relevant for Repeated
START condition
Setup time
91
92
93
THD:STA
TSU:STO
THD:STO
START condition
Hold time
4000
600
After this period, the first clock
pulse is generated
STOP condition
Setup time
4700
600
STOP condition
Hold time
4000
600
DS30221B-page 134
2002 Microchip Technology Inc.
PIC16F872
FIGURE 14-15:
I2C BUS DATA TIMING
103
102
100
101
SCL
90
106
107
91
92
SDA
In
110
109
109
SDA
Out
Note: Refer to Figure 14-3 for load conditions.
TABLE 14-8: I2C BUS DATA REQUIREMENTS
Param
No.
Sym
Characteristic
100 kHz mode
Min
Max
Units
Conditions
100
THIGH
Clock High Time
4.0
—
µs
Device must operate at a mini-
mum of 1.5 MHz
400 kHz mode
0.6
—
µs
Device must operate at a mini-
mum of 10 MHz
SSP Module
1.5TCY
4.7
—
—
101
TLOW
Clock Low Time
100 kHz mode
µs
µs
Device must operate at a mini-
mum of 1.5 MHz
400 kHz mode
1.3
—
Device must operate at a mini-
mum of 10 MHz
SSP Module
1.5TCY
—
102
103
TR
TF
SDA and SCL Rise
Time
100 kHz mode
400 kHz mode
—
1000
300
ns
ns
20 + 0.1CB
CB is specified to be from
10 to 400 pF
SDA and SCL Fall
Time
100 kHz mode
400 kHz mode
—
300
300
ns
ns
20 + 0.1CB
CB is specified to be from
10 to 400 pF
90
91
TSU:STA START Condition
Setup Time
100 kHz mode
400 kHz mode
4.7
0.6
4.0
0.6
0
—
—
µs
µs
µs
µs
ns
µs
ns
ns
µs
µs
ns
ns
µs
µs
pF
Only relevant for Repeated
START condition
THD:STA START Condition Hold 100 kHz mode
—
After this period, the first clock
pulse is generated
Time
400 kHz mode
—
106
107
92
THD:DAT Data Input Hold Time 100 kHz mode
400 kHz mode
—
0
0.9
—
TSU:DAT Data Input Setup Time 100 kHz mode
400 kHz mode
250
100
4.7
0.6
—
(Note 2)
—
TSU:STO STOP Condition
Setup Time
100 kHz mode
400 kHz mode
100 kHz mode
400 kHz mode
100 kHz mode
400 kHz mode
—
—
109
110
TAA
TBUF
CB
Output Valid From
Clock
3500
—
(Note 1)
—
Bus Free Time
4.7
1.3
—
—
Time the bus must be free before
a new transmission can start
—
Bus Capacitive Loading
400
Note 1: As a transmitter, the device must provide this internal minimum delay time to bridge the undefined region (min. 300 ns) of
the falling edge of SCL to avoid unintended generation of START or STOP conditions.
2
2
2: A fast mode (400 kHz) I C bus device can be used in a standard mode (100 kHz) I C bus system, but the requirement
that TSU:DAT ≥ 250 ns must then be met. This will automatically be the case if the device does not stretch the LOW period
of the SCL signal. If such a device does stretch the LOW period of the SCL signal, it must output the next data bit to the
SDA line:
2
TR max.+ TSU:DAT = 1000 + 250 = 1250 ns (according to the standard mode I C bus specification) before the SCL line is
released.
2002 Microchip Technology Inc.
DS30221B-page 135
PIC16F872
TABLE 14-9: A/D CONVERTER CHARACTERISTICS:
PIC16F872 (COMMERCIAL, INDUSTRIAL, EXTENDED)
PIC16LF872 (COMMERCIAL, INDUSTRIAL)
Param
No.
Sym
Characteristic
Resolution
Min
Typ†
Max
Units
Conditions
A01 NR
A03 EIL
A04 EDL
—
—
10-bits
bit VREF = VDD = 5.12V,
VSS ≤ VAIN ≤ VREF
Integral Linearity Error
—
—
—
—
—
—
—
—
< ± 1
< ± 1
< ± 2
< ± 1
LSb VREF = VDD = 5.12V,
VSS ≤ VAIN ≤ VREF
Differential Linearity Error
LSb VREF = VDD = 5.12V,
VSS ≤ VAIN ≤ VREF
A06 EOFF Offset Error
LSb VREF = VDD = 5.12V,
VSS ≤ VAIN ≤ VREF
A07 EGN
Gain Error
LSb VREF = VDD = 5.12V,
VSS ≤ VAIN ≤ VREF
(3)
A10
—
Monotonicity
—
guaranteed
—
—
VSS ≤ VAIN ≤ VREF
A20 VREF Reference Voltage (VREF+ - VREF-)
2.0
—
VDD + 0.3
V
Absolute minimum electrical
spec. to ensure 10-bit
accuracy.
A21 VREF+ Reference Voltage High
A22 VREF- Reference Voltage Low
AVDD - 2.5V
AVSS - 0.3V
VSS - 0.3V
—
AVDD + 0.3V
VREF+ - 2.0V
VREF + 0.3V
10.0
V
V
A25 VAIN
A30 ZAIN
Analog Input Voltage
—
—
V
Recommended Impedance of
Analog Voltage Source
kΩ
A40 IAD
A/D Conversion
Current (VDD)
Standard
Extended
—
—
10
220
90
—
—
µA Average current consumption
when A/D is on (Note 1).
µA
A50 IREF
VREF Input Current (Note 2)
—
1000
µA During VAIN acquisition,
based on differential of VHOLD
to VAIN to charge CHOLD, see
Section 10.1.
—
—
10
µA During A/D conversion cycle.
* These parameters are characterized but not tested.
† Data in "Typ" column is at 5V, 25°C unless otherwise stated. These parameters are for design guidance only and are not
tested.
Note 1: When A/D is off, it will not consume any current other than minor leakage current.
The power-down current spec includes any such leakage from the A/D module.
2: VREF current is from RA3 pin or VDD pin, whichever is selected as reference input.
3: The A/D conversion result never decreases with an increase in the input voltage, and has no missing codes.
DS30221B-page 136
2002 Microchip Technology Inc.
PIC16F872
FIGURE 14-16:
A/D CONVERSION TIMING
BSF ADCON0, GO
1 TCY
(1)
(TOSC/2)
131
130
Q4
132
A/D CLK
. . .
. . .
9
8
7
2
1
0
A/D DATA
NEW_DATA
DONE
OLD_DATA
ADRES
ADIF
GO
SAMPLING STOPPED
SAMPLE
Note:
If the A/D clock source is selected as RC, a time of TCY is added before the A/D clock starts. This allows the
SLEEPinstruction to be executed.
TABLE 14-10: A/D CONVERSION REQUIREMENTS
Param
No.
Sym
Characteristic
A/D Clock Period Standard(F)
Min
Typ†
Max
Units
Conditions
130 TAD
1.6
3.0
2.0
3.0
—
—
—
—
µs TOSC based, VREF ≥ 3.0V
µs TOSC based, VREF ≥ 2.0V
µs A/D RC mode
µs A/D RC mode
TAD
Extended(LF)
Standard(F)
4.0
6.0
—
6.0
9.0
12
Extended(LF)
131 TCNV Conversion Time (not including S/H time)
(Note 1)
132 TACQ Acquisition Time
(Note 2)
40
—
—
µs
10*
—
µs The minimum time is the
amplifier settling time. This may
be used if the "new" input volt-
age has not changed by more
than 1 LSb (i.e., 20.0 mV @
5.12V) from the last sampled
voltage (as stated on CHOLD).
134 TGO
Q4 to A/D Clock Start
—
TOSC/2 §
—
—
If the A/D clock source is
selected as RC, a time of TCY is
added before the A/D clock
starts. This allows the SLEEP
instruction to be executed.
* These parameters are characterized but not tested.
† Data in "Typ" column is at 5V, 25°C unless otherwise stated. These parameters are for design guidance only and are not
tested.
§ This specification ensured by design.
Note 1: ADRES register may be read on the following TCY cycle.
2: See Section 10.1 for min. conditions.
2002 Microchip Technology Inc.
DS30221B-page 137
PIC16F872
NOTES:
DS30221B-page 138
2002 Microchip Technology Inc.
PIC16F872
15.0 DC AND AC CHARACTERISTICS GRAPHS AND TABLES
Note: The graphs and tables provided following this note are a statistical summary based on a limited number of
samples and are provided for informational purposes only. The performance characteristics listed herein are
not tested or guaranteed. In some graphs or tables, the data presented may be outside the specified oper-
ating range (e.g., outside specified power supply range) and therefore, outside the warranted range.
“Typical” represents the mean of the distribution at 25°C. “Maximum” or “minimum” represents (mean + 3σ) or (mean - 3σ)
respectively, where σ is a standard deviation, over the whole temperature range.
FIGURE 15-1:
TYPICAL IDD vs. FOSC OVER VDD (HS MODE)
7
Typical: statistical mean @ 25°C
Maximum: mean + 3σ (-40°C to 125°C)
Minimum: mean – 3σ (-40°C to 125°C)
6
5
4
3
2
1
5.5V
5.0V
4.5V
4.0V
3.5V
3.0V
2.5V
2.2V
0
4
6
8
10
12
14
16
18
20
FOSC (M Hz)
FIGURE 15-2:
MAXIMUM IDD vs. FOSC OVER VDD (HS MODE)
8
Typical: statistical mean @ 25°C
7
6
5
4
3
2
1
Maximum: mean + 3σ (-40°C to 125°C)
Minimum: mean – 3σ (-40°C to 125°C)
5.5V
5.0V
4.5V
4.0V
3.5V
3.0V
2.5V
2.2V
0
4
6
8
10
12
14
16
18
20
FOSC (M Hz)
2002 Microchip Technology Inc.
DS30221B-page 139
PIC16F872
FIGURE 15-3:
TYPICAL IDD vs. FOSC OVER VDD (XT MODE)
1.6
Typical: statistical mean @ 25°C
1.4
1.2
1.0
0.8
0.6
0.4
0.2
Maximum: mean + 3σ (-40°C to 125°C)
Minimum: mean – 3σ (-40°C to 125°C)
5.5V
5.0V
4.5V
4.0V
3.5V
3.0V
2.5V
2.2V
0.0
0.0
0.5
1.0
1.5
2.0
2.5
3.0
3.5
4.0
FOSC (MHz)
FIGURE 15-4:
MAXIMUM IDD vs. FOSC OVER VDD (XT MODE)
2.0
1.8
1.6
1.4
1.2
1.0
0.8
0.6
0.4
0.2
Typical: statistical mean @ 25°C
Maximum: mean + 3σ (-40°C to 125°C)
Minimum: mean – 3σ (-40°C to 125°C)
5.5V
5.0V
4.5V
4.0V
3.5V
3.0V
2.5V
2.2V
0.0
0.0
0.5
1.0
1.5
2.0
2.5
3.0
3.5
4.0
FOSC (MHz)
DS30221B-page 140
2002 Microchip Technology Inc.
PIC16F872
FIGURE 15-5:
TYPICAL IDD vs. FOSC OVER VDD (LP MODE)
80
5.5V
Typical: statistical mean @ 25°C
Maximum: mean + 3σ (-40°C to 125°C)
Minimum: mean – 3σ (-40°C to 125°C)
70
60
50
40
30
20
10
5.0V
4.5V
4.0V
3.5V
3.0V
2.5V
2.2V
0
20
30
40
50
60
70
80
90
100
FOSC (kHz)
FIGURE 15-6:
MAXIMUM IDD vs. FOSC OVER VDD (LP MODE)
120
110
100
90
Typical: statistical mean @ 25°C
Maximum: mean + 3σ (-40°C to 125°C)
Minimum: mean – 3σ (-40°C to 125°C)
5.5V
5.0V
80
4.5V
70
4.0V
60
3.5V
3.0V
50
40
2.5V
2.2V
30
20
10
0
20
30
40
50
60
70
80
90
100
FOSC (kHz)
2002 Microchip Technology Inc.
DS30221B-page 141
PIC16F872
FIGURE 15-7:
AVERAGE FOSC vs. VDD FOR VARIOUS VALUES OF R
(RC MODE, C = 20 pF, 25°C)
4.0
3.5
3.0
2.5
2.0
1.5
1.0
0.5
3.3kΩ
Ω
5.1k
10kΩ
Ω
100k
0.0
2.0
2.5
3.0
3.5
4.0
4.5
5.0
5.5
VDD (V)
FIGURE 15-8:
AVERAGE FOSC vs. VDD FOR VARIOUS VALUES OF R
(RC MODE, C = 100 pF, 25°C)
2.0
1.8
1.6
1.4
1.2
1.0
0.8
0.6
0.4
0.2
Ω
Ω
3.3k
5.1k
10kΩ
100kΩ
0.0
2.0
2.5
3.0
3.5
4.0
4.5
5.0
5.5
VDD (V)
DS30221B-page 142
2002 Microchip Technology Inc.
PIC16F872
FIGURE 15-9:
AVERAGE FOSC vs. VDD FOR VARIOUS VALUES OF R
(RC MODE, C = 300 pF, 25°C)
1.0
0.9
0.8
0.7
0.6
0.5
0.4
0.3
0.2
0.1
Ω
Ω
3.3k
5.1k
Ω
10k
Ω
100k
0.0
2.0
2.5
3.0
3.5
4.0
4.5
5.0
5.5
VDD (V)
FIGURE 15-10:
IPD vs. VDD (SLEEP MODE, ALL PERIPHERALS DISABLED)
100
Typical: statistical mean @ 25°C
Maximum: mean + 3σ (-40°C to 125°C)
Minimum: mean – 3σ (-40°C to 125°C)
MMax ((1255C°C))
10
Max (85°C)
Max (85C)
1
0.1
Typ (25°C)
Tp (25C)
0.01
2.0
2.5
3.0
3.5
4.0
4.5
5.0
5.5
VDD (V)
2002 Microchip Technology Inc.
DS30221B-page 143
PIC16F872
FIGURE 15-11:
∆IBOR vs. VDD OVER TEMPERATURE
1.2
Note: Device current in RESET
depends on oscillator mode,
frequency and circuit.
Typical: statistical mean @ 25°C
Maximum: mean + 3σ (-40°C to 125°C)
Minimum: mean – 3σ (-40°C to 125°C)
1.0
0.8
0.6
0.4
0.2
0.0
Max RESET
Max Reset
Typ RESET
(25°C)
Indeterminate
State
Device in SLEEP
Device in RESET
Max SLEEP
Ml
Typ SLEEP (25°C)
2.2
2.0
2.5
3.0
3.5
4.0
4.5
5.0
5.5
VDD (V)
FIGURE 15-12:
TYPICAL AND MAXIMUM ∆ITMR1 vs. VDD OVER TEMPERATURE
(-10°C TO +70°C, TIMER1 WITH OSCILLATOR, XTAL=32 kHZ, C1 AND C2=50 pF)
90
80
Typical: statistical mean @ 25°C
Maximum: mean + 3σ (-40°C to 125°C)
Minimum: mean – 3σ (-40°C to 125°C)
70
60
50
40
30
20
10
0
Max (-10°C)
Typ (25°C)
2.0
2.5
3.0
3.5
4.0
4.5
5.0
5.5
VDD (V)
DS30221B-page 144
2002 Microchip Technology Inc.
PIC16F872
FIGURE 15-13:
TYPICAL AND MAXIMUM ∆IWDT vs. VDD OVER TEMPERATURE
14
Typical: statistical mean @ 25°C
Maximum: mean + 3σ (-40°C to 125°C)
Minimum: mean – 3σ (-40°C to 125°C)
12
10
8
Max (125°C)
Typ (25°C)
6
4
2
0
2.0
2.5
3.0
3.5
4.0
4.5
5.0
5.5
VDD(V)
FIGURE 15-14:
TYPICAL, MINIMUM AND MAXIMUM WDT PERIOD vs. VDD (-40°C TO +125°C)
50
45
40
35
30
25
20
15
10
5
Typical: statistical mean @ 25°C
Maximum: mean + 3σ (-40°C to 125°C)
Minimum: mean – 3σ (-40°C to 125°C)
Max (85°C)
Typ (25°C)
Min (-40°C)
0
2.0
2.5
3.0
3.5
4.0
4.5
5.0
5.5
VDD (V)
2002 Microchip Technology Inc.
DS30221B-page 145
PIC16F872
FIGURE 15-15:
AVERAGE WDT PERIOD vs. VDD OVER TEMPERATURE (-40°C TO +125°C)
50
45
40
35
30
25
20
15
10
5
Typical: statistical mean @ 25°C
Maximum: mean + 3σ (-40°C to 125°C)
Minimum: mean – 3σ (-40°C to 125°C)
125°C
85°C
85C
25°C
25C
-40°C
-40C
0
2.2
2.0
2.5
3.0
3.5
4.0
4.5
5.0
5.5
VDD (V)
FIGURE 15-16:
TYPICAL, MINIMUM AND MAXIMUM VOH vs. IOH (VDD=5V, -40°C TO +125°C)
5.0
Max (-40°C)
Max (-40C)
4.5
4.0
3.5
3.0
Typ (25°C)
Typ (25C)
Min (125°C)
Min (125C)
Typical: statistical mean @ 25°C
Maximum: mean + 3σ (-40°C to 125°C)
Minimum: mean – 3σ (-40°C to 125°C)
2.5
2.0
0
5
10
15
20
25
IOH (-mA)
DS30221B-page 146
2002 Microchip Technology Inc.
PIC16F872
FIGURE 15-17:
TYPICAL, MINIMUM AND MAXIMUM VOH vs. IOH (VDD=3V, -40°C TO +125°C)
3.0
Max (-40°C)
Max (-40C)
Typical: statistical mean @ 25°C
2.5
2.0
1.5
1.0
0.5
Maximum: mean + 3σ (-40°C to 125°C)
Minimum: mean – 3σ (-40°C to 125°C)
Typ (25°C)
Typ (25C)
Min (125°C)
Min (125C)
0.0
0
5
10
15
20
25
IOH (-mA)
FIGURE 15-18:
TYPICAL, MINIMUM AND MAXIMUM VOL vs. IOL (VDD=5V, -40°C TO 125°C)
2.0
1.8
Typical: statistical mean @ 25°C
Maximum: mean + 3σ (-40°C to 125°C)
Minimum: mean – 3σ (-40°C to 125°C)
1.6
1.4
1.2
1.0
0.8
0.6
0.4
0.2
0.0
Max (125°C)
Ma(125)
Typ (25°C)
Typ (25C)
MMinn ((--4400°CC))
0
5
10
15
20
25
IOL (-mA)
2002 Microchip Technology Inc.
DS30221B-page 147
PIC16F872
FIGURE 15-19:
TYPICAL, MINIMUM AND MAXIMUM VOL vs. IOL (VDD=3V, -40°C TO +125°C)
3.0
Typical: statistical mean @ 25°C
Maximum: mean + 3σ (-40°C to 125°C)
Minimum: mean – 3σ (-40°C to 125°C)
2.5
2.0
1.5
1.0
0.5
0.0
Max (125°C)
Max (125C)
Typ (25°C)
Typ (25C)
Min (-40°C)
Min (-40C)
0
5
10
15
20
25
IOL (-mA)
FIGURE 15-20:
MINIMUM AND MAXIMUM VIN vs. VDD, (TTL INPUT, -40°C TO +125°C)
1.8
Typical: statistical mean @ 25°C
Maximum: mean + 3σ (-40°C to 125°C)
Minimum: mean – 3σ (-40°C to 125°C)
1.6
1.4
1.2
1.0
0.8
0.6
0.4
0.2
0.0
Max
Min
2.0
2.5
3.0
3.5
4.0
4.5
5.0
5.5
VDD (V)
DS30221B-page 148
2002 Microchip Technology Inc.
PIC16F872
FIGURE 15-21:
MINIMUM AND MAXIMUM VIN vs. VDD (ST INPUT, -40°C TO +125°C)
4.5
4.0
Typical: statistical mean @ 25°C
Maximum: mean + 3σ (-40°C to 125°C)
Minimum: mean – 3σ (-40°C to 125°C)
3.5
3.0
2.5
2.0
1.5
1.0
0.5
0.0
Max High
Min High
Max Low
Min Low
2.0
2.5
3.0
3.5
4.0
4.5
5.0
5.5
VDD (V)
FIGURE 15-22:
MINIMUM AND MAXIMUM VIN vs. VDD (I2C INPUT, -40°C TO +125°C)
3.5
Typical: statistical mean @ 25°C
Maximum: mean + 3σ (-40°C to 125°C)
Minimum: mean – 3σ (-40°C to 125°C)
Max High
3.0
2.5
2.0
1.5
1.0
0.5
0.0
Min High
Max Low
Min Low
2.0
2.5
3.0
3.5
4.0
4.5
5.0
5.5
VDD (V)
2002 Microchip Technology Inc.
DS30221B-page 149
PIC16F872
NOTES:
DS30221B-page 150
2002 Microchip Technology Inc.
PIC16F872
16.0 PACKAGING INFORMATION
16.1 Package Marking Information
28-Lead PDIP (Skinny DIP)
Example
XXXXXXXXXXXXXXXXX
XXXXXXXXXXXXXXXXX
YYWWNNN
PIC16F872/SP
0117017
28-Lead SOIC
Example
XXXXXXXXXXXXXXXXX
XXXXXXXXXXXXXXXXX
XXXXXXXXXXXXXXXXX
PIC16F872-I/SO
YYWWNNN
0110017
28-Lead SSOP
Example
XXXXXXXXXXXX
XXXXXXXXXXXX
PIC16LF872
-I/SS
YYWWNNN
0120017
Legend: XX...X Customer specific information*
Y
YY
Year code (last digit of calendar year)
Year code (last 2 digits of calendar year)
WW
NNN
Week code (week of January 1 is week ‘01’)
Alphanumeric traceability code
Note: In the event the full Microchip part number cannot be marked on one line, it will
be carried over to the next line thus limiting the number of available characters
for customer specific information.
*
Standard PICmicro device marking consists of Microchip part number, year code, week code, and
traceability code. For PICmicro device marking beyond this, certain price adders apply. Please check
with your Microchip Sales Office. For QTP devices, any special marking adders are included in QTP
price.
2002 Microchip Technology Inc.
DS30221B-page 151
PIC16F872
28-Lead Skinny Plastic Dual In-line (SP) – 300 mil (PDIP)
E1
D
2
n
1
α
E
A2
L
A
c
B1
β
A1
eB
B
p
Units
INCHES*
NOM
MILLIMETERS
Dimension Limits
MIN
MAX
MIN
NOM
28
MAX
n
p
Number of Pins
Pitch
28
.100
.150
.130
2.54
3.81
3.30
Top to Seating Plane
Molded Package Thickness
Base to Seating Plane
Shoulder to Shoulder Width
Molded Package Width
Overall Length
A
A2
A1
E
.140
.160
3.56
4.06
.125
.015
.300
.275
1.345
.125
.008
.040
.016
.320
.135
3.18
0.38
7.62
6.99
34.16
3.18
0.20
1.02
3.43
.310
.285
1.365
.130
.012
.053
.019
.350
10
.325
.295
1.385
.135
.015
.065
.022
.430
15
7.87
7.24
8.26
7.49
35.18
3.43
0.38
1.65
0.56
10.92
15
E1
D
34.67
3.30
Tip to Seating Plane
Lead Thickness
L
c
0.29
Upper Lead Width
B1
B
1.33
Lower Lead Width
0.41
8.13
5
0.48
8.89
10
Overall Row Spacing
Mold Draft Angle Top
Mold Draft Angle Bottom
§
eB
α
5
β
5
10
15
5
10
15
* Controlling Parameter
§ Significant Characteristic
Notes:
Dimension D and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed
.010” (0.254mm) per side.
JEDEC Equivalent: MO-095
Drawing No. C04-070
DS30221B-page 152
2002 Microchip Technology Inc.
PIC16F872
28-Lead Plastic Small Outline (SO) – Wide, 300 mil (SOIC)
E
E1
p
D
B
2
n
1
h
α
45°
c
A2
A
φ
β
L
A1
Units
INCHES*
NOM
MILLIMETERS
NOM
Dimension Limits
MIN
MAX
MIN
MAX
n
p
Number of Pins
Pitch
28
28
1.27
2.50
2.31
0.20
10.34
7.49
17.87
0.50
0.84
4
.050
.099
.091
.008
.407
.295
.704
.020
.033
4
Overall Height
A
.093
.104
2.36
2.64
Molded Package Thickness
Standoff
A2
A1
E
.088
.004
.394
.288
.695
.010
.016
0
.094
.012
.420
.299
.712
.029
.050
8
2.24
0.10
10.01
7.32
17.65
0.25
0.41
0
2.39
0.30
10.67
7.59
18.08
0.74
1.27
8
§
Overall Width
Molded Package Width
Overall Length
E1
D
Chamfer Distance
Foot Length
h
L
φ
Foot Angle Top
c
Lead Thickness
Lead Width
.009
.014
0
.011
.017
12
.013
.020
15
0.23
0.36
0
0.28
0.42
12
0.33
0.51
15
B
α
β
Mold Draft Angle Top
Mold Draft Angle Bottom
0
12
15
0
12
15
* Controlling Parameter
§ Significant Characteristic
Notes:
Dimensions D and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed
.010” (0.254mm) per side.
JEDEC Equivalent: MS-013
Drawing No. C04-052
2002 Microchip Technology Inc.
DS30221B-page 153
PIC16F872
28-Lead Plastic Shrink Small Outline (SS) – 209 mil, 5.30 mm (SSOP)
E
E1
p
D
B
2
n
1
α
A
c
A2
A1
φ
L
β
Units
INCHES
NOM
MILLIMETERS*
Dimension Limits
MIN
MAX
MIN
NOM
28
MAX
n
p
Number of Pins
Pitch
28
.026
.073
.068
.006
.309
.207
.402
.030
.007
4
0.65
Overall Height
A
.068
.078
1.73
1.63
1.85
1.73
0.15
7.85
5.25
10.20
0.75
0.18
101.60
0.32
5
1.98
Molded Package Thickness
Standoff
A2
A1
E
.064
.002
.299
.201
.396
.022
.004
0
.072
.010
.319
.212
.407
.037
.010
8
1.83
0.25
8.10
5.38
10.34
0.94
0.25
203.20
0.38
10
§
0.05
7.59
5.11
10.06
0.56
0.10
0.00
0.25
0
Overall Width
Molded Package Width
Overall Length
E1
D
Foot Length
L
c
Lead Thickness
Foot Angle
φ
Lead Width
B
α
β
.010
0
.013
5
.015
10
Mold Draft Angle Top
Mold Draft Angle Bottom
0
5
10
0
5
10
* Controlling Parameter
§ Significant Characteristic
Notes:
Dimensions D and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed
.010” (0.254mm) per side.
JEDEC Equivalent: MS-150
Drawing No. C04-073
DS30221B-page 154
2002 Microchip Technology Inc.
PIC16F872
APPENDIX A: REVISION HISTORY
APPENDIX B: CONVERSION
CONSIDERATIONS
Version
Date
Revision Description
Considerations for converting from previous versions
of devices to the ones listed in this data sheet are listed
in Table B-1.
A
11/99
This is a new data sheet (Pre-
liminary). However, these
devices are similar to the
PIC16C72A devices found in
the PIC16C62B/72A Data
Sheet (DS35008).
TABLE B-1:
CONVERSION
CONSIDERATIONS
B
12/01
Final version of data sheet.
Includes DC and AC charac-
teristics graphs and updated
electrical specifications.
Characteristic
PIC16C72A
PIC16F872
Pins
Timers
28
3
28
3
Interrupts
7
10
Communication
Basic SSP
(SPI, I2C
Slave)
SSP (SPI, I2C
Master/Slave)
Frequency
A/D
20 MHz
20 MHz
8-bit,
10-bit
5 channels
5 channels
CCP
1
1
Program
Memory
2K EPROM
2K FLASH
RAM
EEPROM Data
Other
128 bytes
None
128 bytes
64 bytes
In-Circuit
Debugger,
Low Voltage
Programming
2002 Microchip Technology Inc.
DS30221B-page 155
PIC16F872
NOTES:
DS30221B-page 156
2002 Microchip Technology Inc.
PIC16F872
INDEX
PWM Mode ............................................................... 48
RA3:RA0 and RA5 Pins ............................................ 29
RA4/T0CKI Pin .......................................................... 29
RB3:RB0 Pins ........................................................... 31
RB7:RB4 Pins ........................................................... 31
RC Oscillator Mode ................................................... 90
A
A/D ..................................................................................... 79
Acquisition Requirements .......................................... 82
ADCON0 Register ..................................................... 79
ADCON1 Register ..................................................... 79
ADIF Bit ..................................................................... 81
ADRESH Register ..................................................... 79
ADRESL Register ...................................................... 79
Associated Registers and Bits ................................... 85
Configuring Analog Port Pins .................................... 83
Configuring the Interrupt ............................................ 81
Configuring the Module ............................................. 81
Conversion Clock ...................................................... 83
Conversions ............................................................... 84
Effects of a RESET .................................................... 85
GO/DONE Bit ............................................................ 81
Internal Sampling Switch (Rss) Impedance ............... 82
Operation During SLEEP ........................................... 85
Result Registers ........................................................ 84
Source Impedance .................................................... 82
TAD ............................................................................ 83
Absolute Maximum Ratings ............................................. 117
ACK pulse .......................................................................... 59
ACKDT Bit
Acknowledge Data Bit (ACKDT) ................................ 54
ACKEN Bit
Acknowledge Sequence Enable Bit (ACKEN) ........... 54
Acknowledge Pulse (ACK) ................................................. 59
ACKSTAT Bit
Acknowledge Status Bit (ACKSTAT) ......................... 54
ACKSTAT Status Flag ....................................................... 67
ADCON0 Register ............................................................... 9
ADCON1 Register ............................................................. 10
ADRESH Register ............................................................... 9
ADRESL Register .............................................................. 10
Analog-to-Digital Converter. See A/D
2
SSP (I C Master Mode) ............................................ 63
Timer0/WDT Prescaler .............................................. 35
Timer1 ....................................................................... 40
Timer2 ....................................................................... 43
Watchdog Timer ........................................................ 99
BOR. See Brown-out Reset
Brown-out Reset (BOR) ................................ 87, 91, 92, 93
Bus Arbitration ................................................................... 73
Bus Collision
Section ...................................................................... 73
Bus Collision During a Repeated START Condition ......... 76
Bus Collision During a START Condition .......................... 74
Bus Collision During a STOP Condition ............................ 77
Bus Collision Interrupt Flag (BCLIF) .................................. 18
C
Capture Mode
CCP Pin Configuration .............................................. 46
Software Interrupt ...................................................... 46
Timer1 Mode Selection ............................................. 46
Capture/Compare/PWM (CCP) ......................................... 45
Associated Registers ................................................ 47
PWM and Timer2 .............................................. 49
Capture Mode ........................................................... 46
CCP1IF ............................................................. 46
Prescaler ........................................................... 46
CCP Timer Resources .............................................. 45
Compare Mode ......................................................... 47
Software Interrupt Mode .................................... 47
Special Event Trigger ........................................ 47
PWM Mode ............................................................... 48
Duty Cycle ......................................................... 48
Example Frequencies/
Application Notes
AN552 (Implementing Wake-up on Key Stroke) ........ 31
AN556 (Implementing a Table Read) ........................ 20
AN578 (Use of the SSP Module in the I C
Resolutions (Table) ........................... 49
2
PWM Period ...................................................... 48
Special Event Trigger and A/D Conversions ............. 47
CCP. See Capture/Compare/PWM
Multi-Master Environment) ........................ 58
Assembler
MPASM Assembler ................................................. 111
CCP1CON Register ............................................................ 9
CCP1M3:CCP1M0 bits ...................................................... 45
CCP1X bit .......................................................................... 45
CCP1Y bit .......................................................................... 45
CCPR1H Register .........................................................9, 45
CCPR1L Register ..........................................................9, 45
CKE Bit .............................................................................. 52
CKP Bit .............................................................................. 53
Clock Polarity Select Bit (CKP) ......................................... 53
Code Examples
Changing Between Capture Prescalers .................... 46
EEPROM Data Read ................................................ 25
EEPROM Data Write ................................................. 25
FLASH Program Read .............................................. 26
FLASH Program Write .............................................. 27
Indirect Addressing ................................................... 21
Initializing PORTA ..................................................... 29
Saving STATUS, W and PCLATH Registers ............ 98
Code Protected Operation
B
Banking, Data Memory ........................................................ 7
BCLIF Bit ........................................................................... 18
BF Bit
Buffer Full Status Bit (BF) .......................................... 52
BF Status Flag ............................................................ 67, 69
Block Diagrams
A/D Converter ............................................................ 81
Analog Input Model .................................................... 82
Baud Rate Generator ................................................ 64
Capture Mode ............................................................ 46
Compare Mode .......................................................... 47
2
I C Slave Mode ......................................................... 58
Interrupt Logic ............................................................ 97
MSSP (SPI Mode) ..................................................... 55
On-Chip Reset Circuit ................................................ 91
Peripheral Output Override (RC 2:0, 7:5) .................. 33
Peripheral Output Override (RC 4:3) ......................... 33
PIC16F872 .................................................................. 4
Data EEPROM and FLASH Program Memory .......... 28
2002 Microchip Technology Inc.
DS30221B-page 157
PIC16F872
Code Protection ........................................................ 87, 101
Compare Mode
I
I/O Ports ............................................................................ 29
CCP Pin Configuration ...............................................47
Timer1 Mode Selection ..............................................47
Computed GOTO ...............................................................20
Configuration Bits ..............................................................87
Configuration Word ............................................................88
Conversion Considerations ..............................................155
2
I C Bus
Connection Considerations ....................................... 78
Sample Device Configuration .................................... 78
2
I C Mode
Acknowledge Sequence Timing ................................ 71
Addressing ................................................................ 59
Associated Registers ................................................. 62
Baud Rate Generator (BRG) ..................................... 64
Bus Arbitration ........................................................... 73
Bus Collision .............................................................. 73
Repeated START Condition .............................. 76
D
D/A Bit ................................................................................52
Data EEPROM ...................................................................23
Associated Registers .................................................28
Code Protection .........................................................28
Reading .....................................................................25
Special Functions Registers ......................................23
Spurious Write Protection ..........................................27
Write Verify ................................................................27
Writing to ....................................................................25
Data Memory .......................................................................7
Bank Select (RP1:RP0 Bits) ........................................7
General Purpose Register File ....................................7
Register File Map .........................................................8
Special Function Registers ..........................................9
Data/Address Bit (D/A) ......................................................52
DC and AC Characteristics Graphs and Tables ..............139
DC Characteristics
START Condition .............................................. 74
STOP Condition ................................................ 77
Clock Arbitration ........................................................ 72
Conditions to not give ACK Pulse ............................. 59
Effects of a RESET .............................................62, 72
General Call Address Support ................................... 61
Master Mode ............................................................. 63
Master Mode Operation ............................................. 64
Master Mode Reception ............................................ 69
Master Mode Repeated START Condition ................ 66
Master Mode START Condition ................................ 65
Master Mode Transmission ....................................... 67
Master Mode Transmit Sequence ............................. 64
Multi-Master Communication ..................................... 73
Multi-Master Mode ..................................................... 63
Operation ................................................................... 58
Slave Mode ............................................................... 58
Slave Reception ........................................................ 59
Slave Transmission ................................................... 60
SLEEP Operation ................................................62, 72
SSPADD Address Register ....................................... 58
SSPBUF Register ...................................................... 58
STOP Condition Timing ............................................. 71
ICEPIC In-Circuit Emulator .............................................. 112
ID Locations ..............................................................87, 101
In-Circuit Debugger ...................................................87, 101
In-Circuit Serial Programming (ICSP) .......................87, 102
INDF Register ...................................................................... 9
Indirect Addressing ............................................................ 21
FSR Register .........................................................7, 21
Instruction Format ........................................................... 103
Instruction Set ................................................................. 103
ADDLW ................................................................... 105
ADDWF ................................................................... 105
ANDLW ................................................................... 105
ANDWF ................................................................... 105
BCF ......................................................................... 105
BSF ......................................................................... 105
BTFSC ..................................................................... 105
BTFSS ..................................................................... 105
CALL ....................................................................... 106
CLRF ....................................................................... 106
CLRW ...................................................................... 106
CLRWDT ................................................................. 106
COMF ...................................................................... 106
DECF ....................................................................... 106
DECFSZ .................................................................. 107
GOTO ...................................................................... 107
INCF ........................................................................ 107
INCFSZ ................................................................... 107
IORLW ..................................................................... 107
IORWF .................................................................... 107
Commercial and Industrial ............................... 119–122
Extended ............................................................ 123–52
Development Support ......................................................111
Device Overview ..................................................................3
Direct Addressing ..............................................................21
E
EECON1 and EECON2 Registers .....................................23
EECON1 Register ..............................................................11
EECON2 Register ..............................................................11
Electrical Characteristics .................................................117
Equations
A/D
Calculating Acquisition Time .............................82
Errata ...................................................................................2
External Clock Timing Requirements ..............................127
F
Firmware Instructions ......................................................103
FLASH Program Memory ..................................................23
Associated Registers .................................................28
Code Protection .........................................................28
Configuration Bits and Read/Write State ...................28
Reading .....................................................................26
Special Function Registers ........................................23
Spurious Write Protection ..........................................27
Write Protection .........................................................28
Write Verify ................................................................27
Writing to ....................................................................26
FSR Register ................................................................ 9, 21
G
GCEN Bit
General Call Enable Bit (GCEN) ................................54
General Call Address Support ...........................................61
DS30221B-page 158
2002 Microchip Technology Inc.
PIC16F872
MOVF ...................................................................... 108
MOVLW ................................................................... 108
MOVWF ................................................................... 108
NOP ......................................................................... 108
RETFIE .................................................................... 108
RETLW .................................................................... 108
RETURN .................................................................. 109
RLF .......................................................................... 109
RRF ......................................................................... 109
SLEEP ..................................................................... 109
SUBLW .................................................................... 109
SUBWF .................................................................... 109
SWAPF .................................................................... 110
XORLW ................................................................... 110
XORWF ................................................................... 110
Summary Table ....................................................... 104
INT Interrupt (RB0/INT). See Interrupt Sources
M
Master Clear (MCLR)
MCLR Reset, Normal Operation .........................91, 93
MCLR Reset, SLEEP ..........................................91, 93
Master Synchronous Serial Port. See MSSP
MCLR/VPP Pin ..................................................................... 5
Memory Organization .......................................................... 7
Data Memory ............................................................... 7
Program Memory ........................................................ 7
MPLAB C17 and MPLAB C18 C Compilers .................... 111
MPLAB ICD In-Circuit Debugger ..................................... 113
MPLAB ICE High Performance Universal In-Circuit
Emulator with MPLAB IDE ...................................... 112
MPLAB Integrated Development
Environment Software ............................................. 111
MPLINK Object Linker/MPLIB Object Librarian ............... 112
MSSP ................................................................................ 51
INTCON Register .......................................................... 9, 14
GIE Bit ....................................................................... 14
INTE Bit ..................................................................... 14
INTF Bit ..................................................................... 14
PEIE Bit ..................................................................... 14
RBIE Bit ..................................................................... 14
RBIF Bit .............................................................. 14, 31
TMR0IE Bit ................................................................ 14
TMR0IF Bit ................................................................ 14
2
I C Operation ............................................................ 58
Overflow Detect Bit (SSPOV) .................................... 59
Special Function Registers
SSPCON ........................................................... 51
SSPCON2 ......................................................... 51
SSPSTAT .......................................................... 51
SPI Master Mode ...................................................... 55
SPI Mode .................................................................. 55
SPI Slave Mode ........................................................ 56
SSPADD ................................................................... 59
SSPADD Register ..................................................... 58
SSPBUF .................................................................... 55
SSPBUF Register ..................................................... 58
SSPSR ................................................................55, 59
SSPSTAT Register ................................................... 58
Multi-Master Communication ............................................. 73
2
Inter-Integrated Circuit (I C) .............................................. 51
Internal Sampling Switch (Rss) Impedance ....................... 82
Interrupt Sources ........................................................ 87, 97
Interrupt-on-Change (RB7:RB4 ) ............................... 31
RB0/INT Pin, External ............................................... 98
TMR0 Overflow .......................................................... 98
Interrupts
Bus Collision Interrupt ............................................... 18
Synchronous Serial Port Interrupt ............................. 16
Interrupts, Context Saving During ...................................... 98
Interrupts, Enable Bits
O
OPCODE Field Descriptions ........................................... 103
OPTION_REG Register ..............................................10, 13
INTEDG Bit ............................................................... 13
PS2:PS0 Bits ............................................................. 13
PSA Bit ...................................................................... 13
RBPU Bit ................................................................... 13
T0CS Bit .................................................................... 13
T0SE Bit .................................................................... 13
OSC1/CLKI Pin ................................................................... 5
OSC2/CLKO Pin .................................................................. 5
Oscillator Configuration
HS .......................................................................89, 92
LP ........................................................................89, 92
RC ................................................................ 89, 90, 92
XT ........................................................................89, 92
Oscillator Selection ............................................................ 87
Oscillator, WDT ................................................................. 99
Oscillators
Global Interrupt Enable (GIE Bit) ............................... 97
Interrupt-on-Change (RB7:RB4) Enable
(RBIE Bit) .................................................. 98
Interrupts, Flag Bits
Interrupt-on-Change (RB7:RB4) Flag
(RBIF Bit) ............................................ 31, 98
TMR0 Overflow Flag (TMR0IF Bit) ............................ 98
K
KEELOQ Evaluation and Programming Tools ................... 114
L
Load Conditions ............................................................... 126
Loading of PC .................................................................... 20
Low Voltage ICSP Programming ..................................... 102
Low Voltage In-Circuit Serial Programming ....................... 87
Capacitor Selection ................................................... 90
Crystal and Ceramic Resonators .............................. 89
RC ............................................................................. 90
2002 Microchip Technology Inc.
DS30221B-page 159
PIC16F872
Program Memory
Interrupt Vector ............................................................ 7
P
P Bit
Paging ....................................................................... 20
Program Memory Map and Stack ................................ 7
RESET Vector ............................................................. 7
Program Verification ........................................................ 101
Programming, Device Instructions .................................. 103
Pulse Width Modulation.See Capture/Compare/PWM,
PWM Mode.
STOP Bit (P) ..............................................................52
Packaging ............................................................... 151–154
PCL Register ..........................................................9, 10, 20
PCLATH Register ......................................................... 9, 20
PCON Register .....................................................10, 19, 92
BOR Bit ......................................................................19
POR Bit ......................................................................19
PEN Bit
PUSH ................................................................................ 20
PWM Mode
STOP Condition Enable Bit (PEN) .............................54
PICDEM 1 Low Cost PICmicro
Setup ......................................................................... 49
Demonstration Board ...............................................113
PICDEM 17 Demonstration Board ...................................114
PICDEM 2 Low Cost PIC16CXX
Demonstration Board ...............................................113
PICDEM 3 Low Cost PIC16CXXX
R
R/W Bit .............................................................................. 59
Read/Write Bit Information (R/W) .............................. 52
R/W Bit .............................................................................. 59
RA0/AN0 Pin ....................................................................... 5
RA1/AN1 Pin ....................................................................... 5
RA2/AN2/VREF- Pin ............................................................. 5
RA3/AN3/VREF+ Pin ............................................................ 5
RA4/T0CKI Pin .................................................................... 5
RA5/SS/AN4 Pin ................................................................. 5
RAM. See Data Memory
RB0/INT Pin ........................................................................ 6
RB1 Pin ............................................................................... 6
RB2 Pin ............................................................................... 6
RB3/PGM Pin ...................................................................... 6
RB4 Pin ............................................................................... 6
RB5 Pin ............................................................................... 6
RB6/PGC Pin ...................................................................... 6
RB7/PGD Pin ...................................................................... 6
RC0/T1OSO/T1CKI Pin ....................................................... 6
RC1/T1OSI Pin .................................................................... 6
RC2/CCP1 Pin .................................................................... 6
RC3/SCK/SCL Pin ............................................................... 6
RC4/SDI/SDA Pin ................................................................ 6
RC5/SDO Pin ...................................................................... 6
RC6 Pin ............................................................................... 6
RC7 Pin ............................................................................... 6
RCEN Bit
Demonstration Board ...............................................114
PICSTART Plus Entry Level Development
Programmer .............................................................113
PIE1 Register .............................................................. 10, 15
PIE2 Register .............................................................. 10, 17
Pinout Descriptions ......................................................... 5–6
PIR1 Register ............................................................... 9, 16
PIR2 Register ............................................................... 9, 18
POP ...................................................................................20
POR. See Power-on Reset
PORTA ................................................................................5
Associated Registers .................................................30
Functions ...................................................................30
PORTA Register ................................................... 9, 29
RA3
RA0 and RA5 Port Pins .....................................29
TRISA Register ..........................................................29
PORTB ................................................................................6
Associated Registers .................................................32
Functions ...................................................................32
PORTB Register ................................................... 9, 31
RB0/INT Pin, External ................................................98
RB7:RB4 Interrupt-on-Change ..................................98
RB7:RB4 Interrupt-on-Change Enable
Receive Enable Bit (RCEN) ...................................... 54
Receive Overflow Indicator Bit (SSPOV) .......................... 53
Registers
(RBIE Bit) ...................................................98
RB7:RB4 Interrupt-on-Change Flag
(RBIF Bit) ............................................ 31, 98
ADCON0 (A/D Control 0) Register ............................ 79
ADCON1 (A/D Control 1) Register ............................ 80
CCP1CON (CCP Control 1) Register ........................ 45
EECON1 (EEPROM Control) Register ...................... 24
INTCON Register ...................................................... 14
OPTION_REG Register ......................................13, 36
PCON (Power Control) Register ............................... 19
PIE1 (Peripheral Interrupt Enable 1) Register ........... 15
PIE2 (Peripheral Interrupt Enable 2) Register ........... 17
PIR1 (Peripheral Interrupt Request 1) Register ........ 16
PIR2 (Peripheral Interrupt Request 2) Register ........ 18
Special Function, Summary ........................................ 9
SSPCON (Sync Serial Port Control) Register ........... 53
SSPCON2 (Sync Serial Port Control 2) Register ...... 54
SSPSTAT (Sync Serial Port Status) Register ........... 52
STATUS Register ...................................................... 12
T1CON (Timer1 Control) Register ............................. 39
T2CON (Timer 2 Control) Register ............................ 43
TRISB Register ................................................... 11, 31
PORTC ................................................................................6
Associated Registers .................................................34
Functions ...................................................................34
PORTC Register ................................................... 9, 33
TRISC Register ..........................................................33
Power-down Mode. See SLEEP
Power-on Reset (POR) ..................................87, 91, 92, 93
Oscillator Start-up Timer (OST) .......................... 87, 92
Power Control (PCON) Register ................................92
Power-down (PD Bit) .................................................91
Power-up Timer (PWRT) .................................... 87, 92
Time-out (TO Bit) .......................................................91
Time-out Sequence on Power-up ..............................96
PR2 Register .............................................................. 10, 43
PRO MATE II Universal Device Programmer ..................113
Program Counter
RESET Conditions .....................................................93
DS30221B-page 160
2002 Microchip Technology Inc.
PIC16F872
RESET ........................................................................ 87, 91
RESET Conditions for All Registers .......................... 93
RESET Conditions for PCON Register ...................... 93
RESET Conditions for Program Counter ................... 93
RESET Conditions for Special Registers .................. 93
RESET Conditions for STATUS Register .................. 93
RESET
STATUS Register ..........................................................9, 12
C Bit .......................................................................... 12
DC Bit ........................................................................ 12
IRP Bit ....................................................................... 12
PD Bit ..................................................................12, 91
RP1:RP0 Bits ............................................................ 12
TO Bit ..................................................................12, 91
Z Bit ........................................................................... 12
Synchronous Serial Port Enable Bit (SSPEN) ................... 53
Synchronous Serial Port Interrupt ..................................... 16
Synchronous Serial Port Mode Select Bits
Brown-out Reset (BOR). See Brown-out Reset (BOR)
MCLR Reset. See MCLR
Power-on Reset (POR). See Power-on Reset (POR)
WDT Reset. See Watchdog Timer (WDT)
Revision History ............................................................... 155
RSEN Bit
(SSPM3:SSPM0) ...................................................... 53
T
Repeated START Condition Enabled Bit (RSEN) ..... 54
T1CKPS0 bit ...................................................................... 39
T1CKPS1 bit ...................................................................... 39
T1CON Register .................................................................. 9
T1OSCEN bit ..................................................................... 39
T1SYNC bit ....................................................................... 39
T2CON Register .................................................................. 9
Time-out Sequence ........................................................... 92
Timer0 ............................................................................... 35
Associated Registers ................................................ 37
External Clock ........................................................... 36
Interrupt ..................................................................... 35
Overflow Flag (TMR0IF Bit) ...................................... 98
Overflow Interrupt ...................................................... 98
Prescaler ................................................................... 36
T0CKI ........................................................................ 36
Timer1 ............................................................................... 39
Associated Registers ................................................ 42
Asynchronous Counter Mode .................................... 41
Counter Operation ..................................................... 40
Operation in Timer Mode .......................................... 40
Oscillator ................................................................... 41
Capacitor Selection ........................................... 41
Prescaler ................................................................... 41
Reading and Writing in Asynchronous
S
S Bit
START Bit (S) ............................................................ 52
Sample Bit (SMP) .............................................................. 52
SCK Pin ............................................................................. 55
SCL Pin .............................................................................. 58
SDA Pin ............................................................................. 58
SDI Pin ............................................................................... 55
SDO Pin ............................................................................. 55
SEN Bit
START Condition Enabled Bit (SEN) ........................ 54
Serial Clock (SCK) ............................................................. 55
Serial Clock (SCL) ............................................................. 58
Serial Data Address (SDA) ................................................ 58
Serial Data In (SDI) ............................................................ 55
Serial Data Out (SDO) ....................................................... 55
Slave Select (SS) ............................................................... 55
SLEEP ................................................................87, 91, 100
SMP Bit .............................................................................. 52
Software Simulator (MPLAB SIM) ................................... 112
Special Features of the CPU ............................................. 87
Special Function Registers (SFRs) ...................................... 9
Data EEPROM and FLASH Program Memory .......... 23
Speed, Operating ................................................................. 1
SPI Clock Edge Select Bit (CKE) ....................................... 52
SPI Mode
Associated Registers ................................................. 57
Master Mode .............................................................. 56
Serial Clock ............................................................... 55
Serial Data In ............................................................. 55
Serial Data Out .......................................................... 55
Slave Select ............................................................... 55
SPI Clock ................................................................... 56
SS Pin ................................................................................ 55
SSBUF Register .................................................................. 9
MSSP
Counter Mode ........................................... 41
Resetting of Timer1 Registers ................................... 41
Resetting Timer1 using a CCP Trigger Output ......... 41
Synchronized Counter Mode ..................................... 40
Timer2 ............................................................................... 43
Associated Registers ................................................ 44
Output ....................................................................... 44
Postscaler ................................................................. 43
Prescaler ................................................................... 43
Prescaler and Postscaler .......................................... 44
Timing Diagrams
A/D Conversion ....................................................... 137
Acknowledge Sequence ............................................ 71
Baud Rate Generator with Clock Arbitration ............. 65
BRG Reset Due to SDA Collision During
START Condition ...................................... 75
Brown-out Reset ..................................................... 129
Bus Collision
Transmit and Acknowledge ............................... 73
Bus Collision During a Repeated START
Condition (Case 1) .................................... 76
Bus Collision During a Repeated START
2
See also I C Mode and SPI Mode.
SSPADD Register .............................................................. 10
SSPBUF register ............................................................... 58
SSPCON Register ............................................................... 9
SSPCON2 Register ........................................................... 10
SSPEN Bit ......................................................................... 53
SSPIF ......................................................................... 16, 59
SSPM3:SSPM0 Bits .......................................................... 53
SSPOV Bit .................................................................. 53, 59
SSPOV Status Flag ........................................................... 69
SSPSTAT Register ..................................................... 10, 58
Stack .................................................................................. 20
Overflows ................................................................... 20
Underflow .................................................................. 20
Condition (Case2) ..................................... 76
Bus Collision During a STOP Condition
(Case 1) .................................................... 77
Bus Collision During a STOP Condition
(Case 2) .................................................... 77
2002 Microchip Technology Inc.
DS30221B-page 161
PIC16F872
Bus Collision During START Condition
U
UA Bit
(SCL = 0) ...................................................75
Bus Collision During START Condition
(SDA Only) ................................................74
Update Address Bit (UA) ........................................... 52
Capture/Compare/PWM ..........................................131
CLKOUT and I/O .....................................................128
External Clock ..........................................................127
First START Bit Timing ..............................................65
W
Wake-up from SLEEP ...............................................87, 100
Interrupts ................................................................... 93
MCLR Reset .............................................................. 93
WDT Reset ................................................................ 93
Wake-Up Using Interrupts ............................................... 100
Watchdog Timer (WDT) ..............................................87, 99
Enable (WDTE Bit) .................................................... 99
Postscaler. See Postscaler, WDT
2
I C Bus Data ............................................................135
2
I C Bus START/STOP Bits ......................................134
2
I C Master Mode Transmission .................................68
2
I C Mode (7-bit Reception) ................................. 60, 70
2
I C Mode (7-bit Transmission) ...................................61
Master Mode Transmit Clock Arbitration ...................72
Power-up Timer .......................................................129
Repeat START Condition ..........................................66
RESET .....................................................................129
Slave Mode General Call Address Sequence
Programming Considerations .................................... 99
RC Oscillator ............................................................. 99
Time-out Period ......................................................... 99
WDT Reset, Normal Operation ...........................91, 93
WDT Reset, SLEEP ............................................91, 93
WDT Reset, Wake-up ............................................... 93
WCOL ................................................................................ 65
WCOL Bit .......................................................................... 53
WCOL Status Flag ........................................ 65, 67, 69, 71
Write Collision Detect Bit (WCOL) ..................................... 53
Write Verify
(7 or 10-bit Mode) ......................................61
Slow Rise Time (MCLR Tied to VDD
Via RC Network) ........................................96
SPI Master Mode .......................................................56
SPI Master Mode (CKE = 0, SMP = 0) ....................132
SPI Master Mode (CKE = 1, SMP = 1) ....................132
SPI Slave Mode (CKE = 0) ............................... 57, 133
SPI Slave Mode (CKE = 1) ............................... 57, 133
Start-up Timer ..........................................................129
STOP Condition Receive or Transmit Mode ..............72
Time-out Sequence on Power-up ..............................96
Time-out Sequence on Power-up
Data EEPROM and FLASH Program Memory .......... 27
WWW, On-Line Support ...................................................... 2
(MCLR Not Tied to VDD)
Case 1 ...............................................................95
Case 2 ...............................................................96
Time-out Sequence on Power-up
(MCLR Tied to VDD Via RC Network) ........95
Timer0 ......................................................................130
Timer1 ......................................................................130
Wake-up from SLEEP via Interrupt ..........................101
Watchdog Timer ......................................................129
Timing Parameter Symbology .........................................126
TMR0 Register .............................................................. 9, 11
TMR1CS bit .......................................................................39
TMR1H Register ..................................................................9
TMR1L Register ...................................................................9
TMR1ON bit .......................................................................39
TMR2 Register .....................................................................9
TOUTPS3:TOUTPS0 bits ..................................................43
TRISA Register ..................................................................10
TRISB Register ..................................................................10
TRISC Register ..................................................................10
DS30221B-page 162
2002 Microchip Technology Inc.
PIC16F872
Systems Information and Upgrade Hot Line
ON-LINE SUPPORT
The Systems Information and Upgrade Line provides
system users a listing of the latest versions of all of
Microchip's development systems software products.
Plus, this line provides information on how customers
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Microchip provides on-line support on the Microchip
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The web site is used by Microchip as a means to make
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Explorer. Files are also available for FTP download
from our FTP site.
1-800-755-2345 for U.S. and most of Canada, and
1-480-792-7302 for the rest of the world.
ConnectingtotheMicrochipInternetWebSite
013001
The Microchip web site is available by using your
favorite Internet browser to attach to:
www.microchip.com
The file transfer site is available by using an FTP ser-
vice to connect to:
ftp://ftp.microchip.com
The web site and file transfer site provide a variety of
services. Users may download files for the latest
Development Tools, Data Sheets, Application Notes,
User’s Guides, Articles and Sample Programs. A vari-
ety of Microchip specific business information is also
available, including listings of Microchip sales offices,
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available for consideration is:
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Questions
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• Microchip Consultant Program Member Listing
• Links to other useful web sites related to
Microchip Products
• Conferences for products, Development Systems,
technical information and more
• Listing of seminars and events
2002 Microchip Technology Inc.
DS30221B-page 163
PIC16F872
READER RESPONSE
It is our intention to provide you with the best documentation possible to ensure successful use of your Microchip prod-
uct. If you wish to provide your comments on organization, clarity, subject matter, and ways in which our documentation
can better serve you, please FAX your comments to the Technical Publications Manager at (480) 792-4150.
Please list the following information, and use this outline to provide us with your comments about this Data Sheet.
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Literature Number:
DS30221B
Device:
PIC16F872
Questions:
1. What are the best features of this document?
2. How does this document meet your hardware and software development needs?
3. Do you find the organization of this data sheet easy to follow? If not, why?
4. What additions to the data sheet do you think would enhance the structure and subject?
5. What deletions from the data sheet could be made without affecting the overall usefulness?
6. Is there any incorrect or misleading information (what and where)?
7. How would you improve this document?
8. How would you improve our software, systems, and silicon products?
DS30221B-page 164
2002 Microchip Technology Inc.
PIC16F872
PIC16F872 PRODUCT IDENTIFICATION SYSTEM
To order or obtain information, e.g., on pricing or delivery, refer to the factory or the listed sales office.
PART NO.
Device
X
/XX
XXX
Examples:
Temperature
Range
Package
Pattern
a)
PIC16F872 - I/P 301 = Industrial temp., skinny
PDIP package, normal VDD limits, QTP pattern
#301.
b)
c)
PIC16F872 - E/SO = Extended temp., SOIC
package, normal VDD limits.
PIC16LF872 - /SS = Commercial temp., SSOP
package, extended VDD limits.
Device
PIC16F87X(1), PIC16F87XT(2);VDD range 4.0V to 5.5V
PIC16LF87X(1), PIC16LF87XT(2 );VDD range 2.0V to 5.5V
Temperature Range
blank =
0°C to +70°C (Commercial)
-40°C to +85°C (Industrial)
-40°C to +125°C (Extended)
I
=
=
E
Package
SO
SP
SS
=
=
=
SOIC
Skinny Plastic DIP
SSOP
Note 1:
2:
F
LF
T
=
=
=
CMOS FLASH
Low Power CMOS FLASH
in tape and reel - SOIC, PLCC,
MQFP, TQFP packages only.
Sales and Support
Data Sheets
Products supported by a preliminary Data Sheet may have an errata sheet describing minor operational differences and recom-
mended workarounds. To determine if an errata sheet exists for a particular device, please contact one of the following:
1. Your local Microchip sales office
2. The Microchip Corporate Literature Center U.S. FAX: (480) 792-7277
3. The Microchip Worldwide Site (www.microchip.com)
Please specify which device, revision of silicon and Data Sheet (include Literature #) you are using.
New Customer Notification System
Register on our web site (www.microchip.com/cn) to receive the most current information on our products.
2002 Microchip Technology Inc.
DS30221B-page 165
M
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10/01/01
DS30221B-page 166
2002 Microchip Technology Inc.
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