PJ3843 [ETC]
High Performance Current Mode Controller; 高性能电流模式控制器
| 型号： | PJ3843 |
| 厂家： | 
ETC |
| 描述： | High Performance Current Mode Controller |
| 文件： | 总14页 (文件大小：845K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
PJ3842B / PJ3843B
High Performance Current Mode Controller
he PJ3842B and PJ3843B series are high performance
fixed frequency current mode controllers. This is
cycle-by-cycle current limiting, programmable output
deadtime, and a latch for single pulse metering.
T
specifically designed for Off-Line and DC-to-DC converter
applications offering the designer a cost effective solution
with minimal external components.This integrated circuits
feature a trimmed oscillator for precise duty cycle control, a
temperature compensated reference, high gain error amplifier,
current sensing comparator,and a high current totem pole
output ideally suited for driving a power MOSFET.
This device is available in 8-pin dual-in-line plastic
packages as well as the 8-pin plastic surface mount (SOP-8).
The SOP-8 package has separate power and ground pins for
the totem pole output stage.
The PJ3842B has UVLO thresholds of 16V (on) and 10V
(off), ideally suited for off-line converters. The PJ3843B is
tailored for lowervoltage applications having UVLO
thresholds of 8.5V (on) and 7.6V (off).
Also included are protective features consisting of input
and reference undervoltage lockouts each with hysteresis,
FEATURES
DIP-8
SOP-8
•
Trimmed Oscillator Discharge Current for Precise Duty
Cycle Control
•
•
•
•
Current Mode Operation to 500KHz
Automatic Feed Forward Compensation
Latching PWM for Cycle-By-Cycle Current Limiting
Internally Trimmed Reference with Undervoltage
Lockout
Pin：1. Compensation
Pin：2. Voltage Feedback
Pin：3. Current Sense
Pin：4. RT/CT
5. Gnd
6. Output
7. Vcc
8. Vref
•
•
•
High Current Totem Pole Output
ORDERING INFORMATION
Undervoltage Lockout with Hystersis
Low Start-Up and Operating Current
Operating Temperature
(Ambient)
Device
Package
DIP-8
SOP-8
PJ3842/3843BCD
PJ3842/3843BCS
-20℃ TO +85℃
SIMPLIFIED BLOCK DIAGRAM
The document contains information on a new product.Specifications and information herein are subject to change without notice.
1-14
2004/11.Rev B
PJ3842B / PJ3843B
High Performance Current Mode Controller
MAXIMUM RATING
Parameter
Supply Voltage (low impedance source)
Supply Voltage (Ii<30mA)
Output Current
Output Energy (capacitive load )
Analog Inputs (pins 2,3 )
Error Amplifier Output Sink Current
Storage Temperature Range
Symbol
Vi
Vi
IO
EO
Value
Unit
V
30
Self Limiting
±1
A
V
mJ
mA
℃
5
-0.3 to 6.3
10
-65 to +150
Tstg
* All voltages are with respect to pin 5,all currents are positive into the specified terminal.
ELECTRICAL CHARACTERISTICS
(Unless otherwise stated , these specifications apply for 0<Tamb<70℃；Vi = 15V (Note 5), RT=10K, CT=3.3nF )
PJ3842B / PJ3843B
Parameter
Symbol
Test Conditions
Unit
Min
Typ
Max
REFERENCE SECTION
Io=1mA,TJ = 25℃
Output Voltage
VREF
△VREF
4.90
5.00
6
5.10
20
V
mV
Line Regulation
12V<Vi<25V
1<Io<20mA
-
△VREF
Load Regulation
-
-
6
25
mV
△VREF /△T
mV/℃
V
Temperature Stability (Note2)
Total Output Variantion
0.2
-
0.4
5.18
Line,Load, Temperature(2)
4.82
10Hz<f<10kHz
mV
Output Noise Voltage
Vn
-
50
-
TJ=25℃ (2)
Tamb=125℃, 1000Hrs(2)
Long Term Stability
-
5
25
mV
mA
Output Short Circuit
OSCILLATOR SECTION
Initial Accuracy
Isc
fs
-30
-100
-180
TJ=25℃
47
-
52
0.5
5
57
3
-
KHz
%
Voltage Stability
12<Vi<25V
Temperature Stability
TMIN <Tamb<TMAX (2)
-
%
Amplitude VPIN4 Peak to Peak
ERROR AMPLIFIER SECTION
Input Voltage (Vo=2.5V)
V4
-
1.7
-
V
V2
IB
VPIN1=2.5V
2<Vo<4V
2.42
-
2.50
-0.3
90
2.58
V
mΑ
dB
Input Bias Current
-2.0
AVOL
B
65
0.7
60
-
-
-
Unity Gain Bandwidth (2)
Supply Voltage Rejection
Output Current
Sink
1.0
70
MHz
dB
SVR
V
Isink
VPIN2=2.7V, VPIN1=1.1V
VPIN2=2.3V, VPIN1=5V
2.0
6
-
-
Source
ISource
-0.5
-0.8
VPIN2=2.3V,
Output Voltage Swing
VOH
VOL
4.55
-
4.85
0.7
-
V
V
RL=15KΩ to Ground
VPIN2=2.7V,
High State
Output Voltage Swing
Low State
1.1
RL=15KΩ to Pin8
2-14
2004/11.Rev B
PJ3842B / PJ3843B
High Performance Current Mode Controller
PJ3842B / PJ3843B
Parameter
Symbol
Test Conditions
Unit
Min
Typ
Max
CURRENT SENSE SECTION
Current Sense Input Voltage
Gain (Note 3 &4 )
Gv
2.8
3.0
3.2
V/V
Maximum Input Signal
Supply VoltageRejection
Input Bias Current
Delay to Output
V3
SVR
IB
VPIN1=5V(Note 3 )
0.9
1.0
70
1.1
-
V
dB
mΑ
ns
12<Vi<25V(Note 3 )
-
-
-
-2.0
150
-10
300
Td
OUTPUT SECTION
Output Voltage
Low State
VOL
VOH
Isink=20mA
-
-
0.1
1.5
0.4
2.2
-
V
Isink=200mA
High State
Isource=20mA
13
12
-
13.5
13.5
50
Isource=200mA
-
Output Voltage Rise Time
Output Voltage Fall Time
tr
tf
TJ=25℃, CL=1.0nF (Note2 )
TJ=25℃, CL=1.0nF (Note2 )
150
150
ns
ns
-
50
UNDER-VOLTAGE LOCKOUT SECTION
Start-Up Threshold
Vth
V
PJ3842B
PJ3843B
14.5
7.8
16
17.5
9.0
8.4
Minimum Operating Voltage
After Turn-On
VCC(min)
DCmax
V
PJ3842B
8.5
7.0
10
11.5
8.2
PJ3843B
PWM SECTION
Max. Duty Cycle
7.6
93
97
100
%
TOTAL STANDBY CURRENT
Start-Up Current
Operating Supply Current
Zener Voltage
Ist
Ii
Viz
-
-
30
0.1
11
34
0.5
20
-
mA
mA
V
VPIN2=VPIN3=0V
Ii=25mA
Note:
1. Toggle flip flop used only in PJ3844 and PJ3845.
2. These parameters, although guaranteed, are not 100% tested in production.
3. Parameter measured at trip point of latch with VPIN2=0
∆VPIN1
∆VPIN3
4. Gain defined as : A =
；0≦VPIN3 ≦0.8V.
5. Adjust Vi above the start threshold before setting at 15V.
3-14
2004/11.Rev B
PJ3842B / PJ3843B
High Performance Current Mode Controller
FIGURE 1- OUTPUT DEAD TIME versus
OSCILLATOR FREQUENCY
FIGURE 2- TIMING RESISTOR versus OSCILLATOR
FREQUENCY
FIGURE 4-MAXIMUM OUTPUT DUTY CYCLE versus
TIMING RESISTOR
FIGURE 3-OSCILLATOR DISCHARGE CURRENT
versus TEMPERATURE
FIGURE 5-ERROR AMP SMALL SIGNAL TRANSIENT FIGURE 6-ERROR AMP LARGE SIGNAL TRANSIENT
RESPONSE RESPONSE
4-14
2004/11.Rev B
PJ3842B / PJ3843B
High Performance Current Mode Controller
FIGURE 7-ERROR AMP OPEN-LOOP GAIN AND FIGURE 8-CURRENT SENSE INPUT THRESHOLD
PHASE versus FREQUENCY
versus ERROR AMP OUTPUT VOLTAGE
FIGURE 9-REFERENCE VOLTAGE CHANGE versus FIGURE 10-REFERENCE SHORT CIRCUIT CURRENT
SOURCE CURRENT
versus TEMPERATURE
FIGURE 11- REFERENCE LOAD REGULATION
FIGURE 12-REFERENCE LINE REGULATION
5-14
2004/11.Rev B
PJ3842B / PJ3843B
High Performance Current Mode Controller
FIGURE 13-OUTPUT SATURATION VOLTAGE FIGURE 14-OUTPUT WAVEFORM
versus LOAD CURRENT
FIGURE 15-OUTPUT CROSS CONDUCTION
FIGURE 16-SUPPLY CURRENT versus SUPPLY
VOLTAGE
FIGURE 17-REPRESENTATIVE BLOCK DIAGRAM
Pin numbers adjacent to terminals are for the 8 pin dual-in-line package.
Pin numbers in parenthesis are for the SOP-14 package.
6-14
2004/11.Rev B
PJ3842B / PJ3843B
High Performance Current Mode Controller
FIGURE 18-TIMING DIAGRAM
UNDERVOLTAGE LOCKOUT
Two undervoltage lockout comparators have been
incorporated to guarantee that the IC is fully functional before
the output stage is enabled. The positive power supply
terminal (VCC) and the reference output (Vref) are each
monitored by separate comparators.Each has built-in
hysteresis to prevent erratic output behavior as their respective
thresholds are crossed. The large hysteresis and low start-up
current of the PJ3842B makes it ideally suited in off-line
converter applications where efficient bootstrap start-up
technique (Figure 33). 36 V zener is connected as a shunt
regulator from VCC to ground.Its purpose is to protect the IC
from excessive voltage that can occur during system start-up.
The minimum operating voltage for the PJ3842B is 11V.
is active.This characteristic eliminates the need for an external
pull-down resistor.
The SOP-8 surface mount package provides separate pins
for Vc(output supply) and Power Ground.Proper
implementation will significantly reduce the level of
switching transient noise imposed on the control circuitry.
This becomes particularly useful when reducing the Ipk(max)
clamp level.The separate Vc supply input allows the designer
added fiexlbility in tailoring the drive voltage independent of
Vcc.A zener clamp is typically connected to this input when
driving power MOSFETs in systems where Vcc is greater
than 20V. Figure 25 shows proper power and control ground
connections in a current sensing power MOSFET application.
Output
Reference
These devices contain a single totem pole output stage
that was specifically designed for direct drive of power
MOSFET’s. It is capable of up to ±1.0A peak drive current
and has a typical rise and fall time of 50 ns with a 1.0nF load.
Additional internal circuitry has been added to keep the
Output in a sinking mode whenever an undervoltage lockout
The 5.0V bandgap reference is trimmed to±2.0% on the
PJ3842B.Its promary purpose to supply charging current to
the oscillator timing capacitor.The reference has short circuit
protection and is capable of providing in excess of 20mA for
powering additional control system circuitry.
7-14
2004/11.Rev B
PJ3842B / PJ3843B
High Performance Current Mode Controller
Design Considerations
Current mode converters can exhibit subharmonic
Do not attempt to construct the converter on wirewrap or
plug-in prototype boards. High frequency circuit layout
techniques are imperative to prevent pulsewidth jitter.This is
usually caused by excessive noise pick-up imposed on the
Current Sense or Voltage Feedback inputs.Noise immunity
can be improved by lowering circuit impedances at these
points.The printed circuit layout should contain a ground
plane with lowcurrent signal and high-current switch and
output grounds returning separate paths back to the input filter
capacitor.Ceramic bypass capacitors(0.1 μ F) connected
directly to Vcc,Vc, and Vref may be required depending upon
circuit layout . This provides a low impedance path for
filtering the high frequency noised. All high current loops
should be kept as short as possible using heavy copper runs to
minimize radiated EMI. The Error Amp compensation
circuitry and the converter output voltage divider should be
located close to the IC and as far as possible from the power
switch and other noise generating components.
oscillations when operating at a duty cycle greater than 50%
with continuous inductor current,This instability is
independent of the regulators closed loop characteristics and
is caused by the simultaneous operating conditions of fixed
frequency and peak current detecting. Figure 19A shows the
phenomenon graphically, At t0 , switch conduction begins ,
causing the inductor current to rise at a slope of m1. This
slope is a function of the input voltage divided by the
inductance. At t1, the Current Sense Input reaches the
threshold established by the control voltage. This causes the
switch to turn off and the current to decay at a slope of m2,
until the next oscillator cycle. This unstable condition can be
shown if a perturbation is added to the control voltage ,
resulting in a small Δl (dashed line). With a fixed oscillator
period, the current decay time is reduced, and the minimum
current at switch turn-on(t2) is increased by Δl+Δl m2/m1.
The minimum current at the next cycle (t3) decreases to (Δl+
Δl m2/m1)(m2/m1). This perturbation is multiplied by m2/m1
on each succeeding cycle , alternately increasing and
decreasing the inductor current at switch turn-on, Several
oscillator cycles may be required before the inductor current
reaches zero causing the process to commence again. If m2/m1
is greater than 1, the converter will be unstable . Figure 19B
shows that by adding an artificial ramp that is synchronized
with the PWM clock to the control voltage . the Δ l
perturbation will decrease to zero on succeeding cycles. This
compensating ramp (m3) must have a slope equal to or slightly
FIGURE 19-CONTINUOUS CURRENT WAVEFROMS
greater than m2/2 for stability
.
With m2/2 slope
compensation , the average inductor current follows the
control voltage yielding true current mode operation. The
compensating ramp can be derived from the oscillator and
added to either the Voltage Feedback or Current Sense inputs
(Figure 32).
8-14
2004/11.Rev B
PJ3842B / PJ3843B
High Performance Current Mode Controller
FIGURE 20-EXTERNAL CLOCK
SYNCHRONIZATION
FIGURE 21-EXTERNAL DUTY CYCLE CLAMP AND
MULTI UNIT SYNCHRONIZATION
The diode clamp is required if the Sync amplitude is large enough
to the cause the bottom side of CT to go more than 300mV below
ground.
1.44
RA + RB
RB
RA + 2RB
f =
DMAX
=
(
)
FIGURE 22-ADJUSTABLE REDUCTION OF CLAMP FIGURE 23-SOFT-START CIRCUIT
LEVEL
Vclmap
Rs
1.67
Ipk (max) =
Vclamp =
Where：≤ Vclmap ≤ 1.0V
R1 R2
+ 0.33×10−3
R2
R1
Isoft-Start=3600c in µF
R1 + R2
+ 1
FIGURE 24-ADJUSTABLE BUFFERED REDUCTION FIGURE 25-CURRENT SENSING POWER MOSFET
OF CLAMP LEVEL WITH SOFT-STAR
Virtually lossless current sensing can be achieved with the
implementation of a SENSEFET power switch.For proper operation
during over current conditions.a reduction of the Ipk(max) clamp level
must be implemented.Refer to Figure 22 and 24
9-14
2004/11.Rev B
PJ3842B / PJ3843B
High Performance Current Mode Controller
FIGURE 26-CURRENT WAVEFORM SPIKE
FIGURE 27-MOSFET PARASITIC OSCILLATIONS
SUPPRESSION
The addition of RC filter will eliminate instability caused by the
leading edge splik on the current waveform.
FIGURE 28-BIPOLAR TRANSISTOR DRIVE
FIGURE 29-ISOLATED MOSFET DRIVE
The totem-pole output can furnish negative base current for enhanced
transistor turn-off,with the additions of capacitor C1.
FIGURE 30-LATCHED SHUTDOWN
FIGURE 31-ERROR AMPLIFIER COMPENSATION
Error Amp compensation circuit for stabilizing any currentmode
topology except for boost and flyback converters operating with
continuous inductor current.
The MCR101 SCR must be selected for a holding of less than 0.5mA
at TA (min). The simple two transistor circuit can be used in place of
the SCR as shown.All resistors are 10K
Error Amp compensation circuit for stabilizing any currentmode
topology except for boost and flyback converters operating with
continuous inductor current.
10-14
2004/11.Rev B
PJ3842B / PJ3843B
High Performance Current Mode Controller
FIGURE 32-SLOPE COMPENSATION
The buffered oscillator ramp can resistively summed with either the voltage
feedback or current sense inputs to provide slope compensation.
FIGURE 33-27 WATT OFF-LINE REGULATION
T1-Primary:45 Turns #26 AWG
Secondary ±12V :9 Turns #30 AWG (2 strands ) Bifiliar Wound
L1-15μH at 5.0A, Coilcraft 27156.
L2.L3-25μH at 1.0A, Coilcraft 27157.
Secondary 5.0V: 4 Turns (six strands) #26 Hexfiliar Wound
Secondary Feedback : 10 Turns #30 AWG (2 strands) Bifiliar Wound
Core: Ferroxcube EC35-3C8
Bobbin : Ferroxcube EC35PCB1
Gap： ≅ 0.10 ” for a primary inductance of 1.0mH
Line Regulation：5.0V
Line Regulation：±12V
Load Regulation：5.0V
Load Regulation：±12V
Output Ripple：5.0V
Output Ripple：±12V
Efficiency
ꢀ =50mV or ±0.5%
ꢀ =24mV or ±0.1%
ꢀ =300mV or ±3.0%
ꢀ =60mV or ±0.25%
40mVp-p
Vin=95 to 130 Vac
Vin=115Vac, Iout =1.0A to 4.0A
Vin=115Vac,Iout=100mA to 300mA
Vin=115Vac
80 Vp-p
70%
Vin=115Vac
All outputs are at nominal load currents unless otherwise noted.
11-14
2004/11.Rev B
PJ3842B / PJ3843B
High Performance Current Mode Controller
FIGURE 21-33 WATT OFF-LINE FLYBACK CONVERTER
WITH SOFT-START AND PRIMARY POWER LIMITING
T1
Coilcraft 11-464-16, 0.025” gap in each
leg
Baobbin：
Coilcraft 37-573
TEST
CONDITIONS
RESULTS
Windings：
Line Regulation 5.0V
Vin=95 to 135 Vac, Io=3.0A
20mV
0.40%
0.26%
9.5%
Primary, 2 each:
75 turns #26 Awg Bifilar wound
Line Regulation± 12V Vin=95 to 135 Vac, Io=±0.75A
Line Regulation 5.0V Vin=115 Vac, Io=1.0 to 4.0A
Line Regulation± 12V Vin=115 Vac, Io=±0.4 to ±0.9A
Line Regulation 5.0V Vin=115 Vac, Io=3.0A
52mV
476mV
300mV
Feedback：
15 turns #26 Awg
2.5%
Secondary , 5.0V：
45 mVp-p P.A.R.D.
75 mV p-p P.A.R.D.
6 turns #22 Awg Bifiar wound
Line Regulation± 12V Vin=115 Vac, Io=±0.75A
Secondary , 5.0V：
Vin=115 Vac, Io 5.0V=3.0A
14 turns #24 Awg Bifiar wound
Efficiency
74%
Vin=115 Vac, Io ±12=±0.75A
L1
Coilcraft Z7156. 15μF @ 5.0A
L2,L3
Coilcraft Z7157. 25μF @ 1.0A
PIN FUNCTION DESCRIPTION
Pin No.
Function
Description
1
Compensation
This pin is the Error Amplifier output and is made available for loop compensation
This is the inverting input of the Error Amplifier. It is normally connected to the
switching power supply output through a resistor divider.
2
Voltage Feedback
A voltage proportional to inductor current is connected to this input.
The PWM uses this information to terminate the output switch conduction.
The Oscillator Frequency and maximum Output duty are programmed by connecting
resistor RT to Vref and capacitor CT to ground operation to 500kHz is possible.
This pin is the combined control circuitry and power ground (8-pin package only).
This output directly drives the gate of a power MOSFET.Peak current up to 1.0A are
soured and sunk by this pin.
3
Current Sense
4
5
6
7
8
RT/CT
Gnd
Output
Vcc
This pin is the positive supply of the control IC.
This pin is the reference output . It provides charging current for capacitor CT
through resistor RT.
Vref
12-14
2004/11.Rev B
PJ3842B / PJ3843B
High Performance Current Mode Controller
OPERATING DESCRIPTION
The PJ3842B series are high performance, fixed frequency, current mode controllers, They are specifically designed for Off-Line
and DC-to-DC converter applications offering the designer a cost effective solution with minimal external components . A
representative block diagram is shown in Figure 17.
OSCILLATOR
The oscillator frequency is programmed by the values selected for the timing components RT and CT . Capacitor CT is charged
from the 5.0V reference through resistor RT to approximately 2.8V and discharge to 1.2V by an internal current sink.During the
discharge of CT , the oscillator generates an internal blanking pulse that holds the center input of the NOR gate high. This causes
the Output to be in a low state, thus producing a controlled amount of output deadtime. Figure 1 shows RT versus Oscillator
Frequency and Figure 2, Output Deadtime versus Frequency, both for given values of CT . Note that many values of RT and C T
will give the same oscillator frequency but only onne combination will yield a specific output deadtime at a given frequency. The
oscillator thresholds are temperature compensated, and the discharge current is trimmed and guaranteed to within ±10% at TJ
=25℃. These internal circuit refinements minimum variations of oscillator frequency and maximum output duty cycle. The
results are shown in Figure 3 and 4.
In many noise sensitive applications it may be desirable to frequency-lock the converter to an external system clock. This can be
accomplished by applying a clock signal to the circuit shown in Figure 20. For reliable locking. The free-running oscillator
frequency should be set about 10% less than the clock frequency . A method for multi unit synchronization is shown in Figure 21.
By tailoring the clock waveform, accurate Output duty cycle clamping can be achieved.
ERROR AMPLIFIER
A fully compensated Error Amplifier with access to the inverting input and output is provided. It features a typical DC voltage
gain of 90dB, and a unity gain bandwidth of 1.0MHz with 57 degrees of phase margin (Figure 7). The non-inverting input is
internally biased at 2.5V and is not pinned out. The converter output voltage is typically divided down and monitored by the
inverting input. The maximum input bias current is -2.0μA which can cause an output voltage error that is equal to the product of
the input bias current and the equivalent input divider source resistance.
The Error Amp Output (Pin 1) is provided for external loop compensation (Figure 31). The output voltage is offset by two diode
drops (≈1.4V) and divided by three before it connects to the inverting input of the Current Sense Comparator. This guarantees that
no drive pulses appear at the Output(Pin 6) when Pin 1 is at its lowest state (VOL). This occurs when the power supply is
operating and the load is removed, or at the beginning of a soft-start interval (Figure 23,24). The Error Amp minimum
feedback resistance is limited by the amplifier's source current (0.5mA) and the required output voltage (VOH) to reach the
comparator’s 1.0V clamp level:
Rf(MIN) = [3.0 (1.0V)+1.4V] / 0.5mA = 8800Ω
CURRENT SENSE COMPARATOR AND PWM LATCH
The PJ3842B operate as a current mode controller, whereby output switch conduction is initiated by the oscillator and terminated
when the peak inductor current reaches the threshold level established by the Error Amplifier Output/Compensation (Pin 1). Thus
the error signal controls the peak inductor current on a cycle-by-cycle basis. The Current Sense Comparator PWM Latch
configuration used ensures that only a single appears at the Output during any given oscillator cycle. The inductor current is
converted to a voltageby inserting the ground referenced sense resistor RS in series with the source of output switch Q1. This
voltage is monitored by the Current Sense Input (Pin 3) and compared to a level derived from the Error Amp Output. The peak
inductor current under normal operating conditions is controlled by the voltage at pin 1 where:
IPK = [V(Pin 1) - 1.4V] / 3RS
Abnormal operating conditions occur when the power supply output is overloaded or if output voltage sensing is lost, Under these
conditions, the Current Sense Comparator threshold will be internally clamped to 1.0V. Therefore the maximum peak switch
current is:
IPK (MAX) = 1.0V / RS
When designing a high power switching regulator it becomes desirable to reduce the internal clamp voltage in order to keep the
power dissipation of RS to a reasonable level. A simple method to adjust this voltage is shown in Figure 22. The two external
diodes are used to compensate the internal diodes yielding a constant clamp voltage over temperature. Erratic operation due to
noise pickup can result if there is an excessive reduction of the IPK (max) clamp voltage.
A narrow spike on the leading edge of the current waveform can usually be observed and may cause the power supply to exhibit
an instability when the output is lightly loaded. This spike is due to the power transformer interwinding capacitance and output
rectifier recovery time. The addition of an RC filter on the Current Sense Input with a time constant that approximates the spike
duration will usually eliminate the instability: refer to Figure 26.
13-14
2004/11.Rev B
PJ3842B / PJ3843B
High Performance Current Mode Controller
DIP-8 Mechanical drawing
1.Top View 2.Side View
A
DIP-8 DIMENSION
MILLIMETERS
INCHES
MAX
8
1
5
4
DIM
MIN
8.85
6.30
MAX
9.05
6.40
MIN
0.348
0.248
B
A
B
0.356
0.252
3.65
0.45
3.95
0.55
C
D
0.143
0.017
0.156
0.022
0.10BSC
2.54BSC
E
F
F
7.75
0.20
-
8.00
0.30
10°
0.305
0.007
0.315
0.012
G
H
C
-
10°
G
H
E
D
SOP-8 Mechanical drawing
1.Top View
2.Side View
SOP-8 DIMENSION
A
MILLIMETERS
INCHES
G
DIM
MIN
4.80
MAX
5.00
4.00
6.20
1.50
0.51
MIN
MAX
A
B
0.189
0.197
0.157
0.244
5
4
8
3.80
0.150
0.228
B
C
5.80
C
D
E
F
1.40
1
0.055
0.013
0.059
0.020
0.33
H
0.05BSC
1.27BSC
0.19
0.25
1.27
0.007
0.016
0.010
0.050
G
H
0.40
0°
8°
0°
8°
D
E
14-14
2004/11.Rev B
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