PLL2108X [ETC]
PLL2108X 50MHz ~ 300MHz FSPLL|Data Sheet ; PLL2108X的50MHz 〜 300MHz的FSPLL |数据表
| 型号： | PLL2108X |
| 厂家： | 
ETC |
| 描述： | PLL2108X 50MHz ~ 300MHz FSPLL|Data Sheet
|
| 文件： | 总10页 (文件大小：151K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
50MHz ~ 300MHz FSPLL
PLL2108X
Ver 1.3.0. (May. 2002)
GENERAL DESCRIPTION
FEATURES
0.13um CMOS device technology
•
The pll2108x is
a
Phase Locked Loop (PLL)
frequency synthesizer. The PLL provides frequency
multiplication capabilities. The output clock frequency
FOUT is related to the input clock frequency FIN by
the following equation:
• 1.2 Volt single power supply
• Output frequency range: 50M ~ 300MHz
• Jitter: ±150ps at 300MHz
FOUT=(m*FIN) / (p*2s)
• Duty ratio: 40% to 60% (All tuned range)
• Power down mode
Where FOUT is the output clock frequency. FIN is
the input clock frequency. m, p and s are the values
for programmable dividers. pll2108x consists of
a
• Off-chip loop filter
Phase Frequency Detector(PFD), a Charge Pump, an
Off-chip Loop Filter, a Voltage Controlled Oscillator
(VCO), a 6bit Pre-divider, an 8bit Main-divider and
2bit Post-scaler as shown in functional block diagram.
• Frequency is changed by programmable divider
NOTE
1. Don't set the P or M value as zero, that is, seting the P=000000, M=00000000 can cause malfunction of the PLL.
2. The proper range of P and M : 1<=P<=62, 1<=M<=248
3. The P and M must be selected considering stability of PLL and VCO output frequency range.
4. Please contact SEC application engineer for proper selection of the P, M, S values of the PLL.
No responsibility is assumed by SEC for its use nor for any infringements of patents or other rights of third parties that
may result from its use. The contents of the datasheet is subject to change without any notice.
FUNCTIONAL BLOCK DIAGRAM
FILTER
AVDD12D AVSS12D
Fin/P
UP
DN
R1
C2
Phase
Frequency
Detector
FIN
Charge
Pump
Pre-Divider
(P)
Fvco/M
6b
Voltage
Controlled
Oscillator
M[7:0]
P[5:0]
S[1:0]
Fvco
Vctrl
Main-Divider
(M)
8b
Post - Scaler
(S)
FOUT
PWRDN
(1,2,4,8)
AVDD12A AVSS12A
VABB
2b
SAMSUNG ELECTRONICS Co. LTD
50MHz~300MHz FSPLL
PLL2108X
CORE PIN DESCRIPTION
I/O
I/O TYPE ABBR.
NAME
PIN DESCRIPTION
TYPE
• AI : Analog Input
• DI : Digital Input
• AO: Analog Output
• DO: Digital Output
AVDD12D
AVSS12D
AVDD12A
AVSS12A
VABB
DP
Digital power supply
Digital ground
DG
AP
Analog power supply
Analog ground
AG
• AP : Analog Power
• AG: Analog Ground
• AB: Analog Sub Bias
• DP : Digital Power
• DG: Digital Ground
• DB: Digital Sub Bias
AB/DB Analog / Digital bulk bias
FIN
DI
PLL clock input
50MHz~300MHz
clock output
FOUT
DO
The external loop filter cap-
acitor should be connected
between the pin and analog
ground
FILTER
AO
DI
• BD: Bidirectional Port
Power down.
PWRDN
-If PWRDN is high, power
down mode is enabled.
6bit programmable
pre-divider.
P[5:0]
M[7:0]
S[1:0]
DI
DI
DI
8bit programmable
main-divider.
2bit programmable
post-scaler.
CORE CONFIGURATION
FIN
PWRDN
M[7:0]
M[7]
M[6]
M[5]
M[4]
M[3]
M[2]
M[1]
M[0]
FOUT
pll2108x
P[5:0]
S[1:0]
P[5]
P[4]
P[3]
P[2]
FILTER
P[1]
P[0]
S[1]
S[0]
SEC ASIC
ANALOG
2/10
50MHz~300MHz FSPLL
PLL2108X
ABSOLUTE MAXIMUM RATING
Characteristics
Symbol
Value
Unit
Applicable pin
AVDD12D
AVDD12A
Supply Voltage
2.5
V
AVDD12D, AVDD12A
vdd + 0.2
vss - 0.2
P[5:0] M[7:0] S[1:0]
FIN, PWRDN
Digital Input Voltage
Storage Temperature
Vin
V
Tstg
-45 ~ 150
°C
-
NOTES
1. ABSOLUTE MAXIMUM RATING specifies the values beyond which the device may be damaged permanently.
Exposure to ABSOLUTE MAXIMUM RATING conditions for extended periods may affect reliability. Each
condition value is applied with the other values kept within the following operating conditions and function
operation under any of these conditions is not implied.
2. All voltages are measured respect to VSS unless otherwise specified.
3. 100pF capacitor is discharged through a 1.5Kohm resistor (Human body model)
RECOMMENDED OPERATING CONDITIONS
Characteristics
Symbol
Min
Typ
Max
Unit
Remark
Supply Voltage Differential
AVDD12D-AVDD12A
-0.1
+0.1
V
Capacitance
tolerance
(+/-5%)
External Loop Filter
Capacitance
LF
1.8
nF
Operating Temperature
Topr
-40
85
°C
NOTES
1. It is strongly recommended that all the supply pins (AVDD12D, AVDD12A) be powered to the same supply
voltage to avoid power latch-up.
SEC ASIC
ANALOG
3/10
50MHz~300MHz FSPLL
PLL2108X
DC ELECTRICAL CHARACTERISTICS
Characteristics
Operating Voltage
Symbol
Min
1.14
Typ
Max
Unit
V
AVDD12D/AVDD12A
1.20
1.26
Digital Input Voltage High
Digital Input Voltage Low
Dynamic Current
VIH
VIL
Idd
0.7VDD
V
0.3VDD
TBD
V
3
mA
uA
Power Down Current
Ipd
TBD
* Operating voltage Min/Max are prelminary values and expected to be updated.
AC ELECTRICAL CHARACTERISTICS
Characteristics
Input Frequency
Symbol
FIN
Min
10
Typ
Max
Unit
40
300
300
60
MHz
MHz
MHz
%
VCO output frequency
Output Frequency
Fvco
100
50
FOUT
TID
Input Clock Duty Ratio
Output Clock Duty Ratio
Locking Time
40
50
TOD
TLT
40
50
60
%
300
us
50M~100MHz
TJCC
TJCC
TJCC
+/-600
+/-300
+/-150
TBD
TBD
TBD
ps
Cycle to Cycle Jitter 100M~200MHz
200M-300MHz
ps
ps
4/10
SEC ASIC
ANALOG
50MHz~300MHz FSPLL
PLL2108X
FUNCTIONAL DESCRIPTION
A PLL is the circuit synchronizing an output signal (generated by an VCO) with a reference or input signal in
frequency as well as in phase. The pll2108x can provide frequency multiplication capabilities, but can't
guarantee phase synchronization between FIN and FOUT.
pll2108X consists of the following basic blocks.
- The phase frequency detector (PFD) detects the phase difference between the reference clock and feedback
clock, then generates UP/DOWN error signals. If reference clock leads feedback clock, UP is high and
DOWN is low. If reference clock lags feedback clock, UP is low and DOWN is high.
- The charge pump charges or discharges the following loop filter according to UP/DOWN signal.
- The loop filter suppresses high frequency components in the charge pump voltage (Vctrl), allowing the dc
value to control the VCO frequency.
- The voltage-controlled oscillator generates the clock signal proportional to control voltage.
Required frequency is produced by appropriate selection of P, M and S dividers.
Fout = Fin*m/(p*s)
m=M+8 , p=P+2 , s=1,2,4,8
- Don't set the value P or M to all zero, that is 000000/ 00000000.
- The range of P and M : 1 <= P <= 62, 1 <= M <= 248
- The M and P must be selected considering stability and VCO range.
VCO output frequency range of pll2108x is from 100MHz to 200MHz.
Digital data format:
Main Divider
Pre Divider
Post Scaler
M7,M6,M5,M4,M3,M2,M1,M0
P5,P4,P3,P2,P1,P0
S1,S0
NOTES
. M[7] - M[0]: : main-divider
1<=M<=248
. P[5]
. S[1]
-
-
P[0] : pre-divider
S[0] : post-scaler
1<=P<=62
0<=S<=3
IMPORTANT NOTICE
- Please consult with SEC application engineer about the proper selection of M, P, S values.
5/10
SEC ASIC
ANALOG
50MHz~300MHz FSPLL
PLL2108X
CORE EVALUATION GUIDE
1.You can generate various output frequencies by changing M/P/S setting. There are two methods of controlling
divider values
- Method 1: 16 bit register can be used for easy control of divider values.
- Method 2: P, M and S pins are bypassed to the external port, and you can control each port directly.
It is undesirable to connect P[5:0], M[7:0] and S[1:0] to the internal power or ground directly
NOTES
: 10uF ELECTROLYTIC CAPACITOR
UNLESS OTHERWISE SPECIFIED
: 0.1uF CERAMIC CAPACITOR
UNLESS OTHERWISE SPECIFIED
1.2V
GND
FILTER
1.8 nF (Chip cap)
AVDD12D
AVSS12D
VABB
VABB
AVSS12A
AVDD12A
pll2108x
S0
M0 M1 M2 M3 M4 M5 M6 M7
S1
P5 P4 P3 P2 P1 P0
FOUT
M[7:0]
FIN
P[5:0]
PWRDN
S[1:0]
6/10
SEC ASIC
ANALOG
50MHz~300MHz FSPLL
PLL2108X
CORE LAYOUT GUIDE
1. The digital power(AVDD12D,AVSS12D) and the analog power(AVDD12A, AVSS12A) must be dedicated
to PLL only and separated. If the dedicated AVDD12D and AVSS12D are not allowed, please consult with
SEC application engineer.
2. The FOUT and FILTER pins must be placed far from the internal signals in order to avoid cross-talk
between the signal lines.
3. The blocks showing a large amount of digital switching current must be located away from the PLL core.
DESIGN CONSIDERATIONS
The following design considerations must be applied:.
1. Jitter is affected by the power noise, substrate noise, etc. It goes up when the noise level increases.
2. A CMOS-level input reference clock is recommend for signal compatibility with the PLL circuit. Other
levels such as TTL may degrade the tolerances.
3. The use of two, or more PLLs requires special design considerations. Please consult with SEC application
engineer for more information.
4. The PLL core should be placed as close as possible to the dedicated loop filter and analog power and
ground pins.
5. It is inadvisable to locate noise-generating signals near the PLL and its I/O cells. For example, data buses,
high frequency outputs and high current consuming cells, .
6. Other related I/O signals should be placed near the PLL I/O but do not have any pre-defined placement
restriction
7/10
SEC ASIC
ANALOG
50MHz~300MHz FSPLL
PLL2108X
PHANTOM CELL INFORMATION
- Pins of the core can be assigned externally(package pins) or internally(internal ports) depending on design
methods.
The term "external" implies that the pins should be assigned externally like power pins.
The term "internal/external" implies that these pins are user dependant
pll2108x
S0
M0 M1 M2 M3 M4 M5 M6 M7
S1
P5 P4 P3 P2 P1 P0
8/10
SEC ASIC
ANALOG
50MHz~300MHz FSPLL
PLL2108X
PIN LAYOUT GUIDE
Pin
Pin Name
Pin Layout Guide
Usage
AVDD12D
AVSS12D
AVDD12A
AVSS12A
VABB
External
External
External
External
External
-. Use dedicated power/ground pins for PLL
-. Power cuts are required to provide on-chip isolation
=> between dedicated PLL power/ground and all
other power/ground
-. Use good power and ground source on board
-. Do not place noisy, high frequency and high
power consuming circuitry pads near the FIN.
-. Use proper low jitter reference clock
FIN
External
-. Do not place noisy, high frequency and high
power consuming circuitry pads near the FOUT.
-. Internal routing path should be short.
This will minimize loading effect.
FOUT
External/Internal
-. FOUT signals should not be crossed by any
signals and should not run next to digital signals.
This will minimize capacitive coupling between
the two signals.
-. Do not place the noisy, high frequency and high
power consuming circuitry pads near the FILTER.
-. Ground shielding is needed for internal routing
path.
-. FILTER routing path should not be crossed by
any signals and should not run next to digital
signals.
FILTER
External
-. External loop filter pin should be placed between
analog power and ground to avoid stray coupling
outside the chip and magnetic coupling via bond
wires.
- Loop filter components should be placed as close
as possible.
PWRDN
M[7]~M[0]
P[5]~P[0]
Interanl/External
Internal/External
Internal/External
S[1]~S[0]
Internal/External
9/10
SEC ASIC
ANALOG
50MHz~300MHz FSPLL
PLL2108X
FEEDBACK REQUEST
Thanks for taking an interest in our products. If you have any question, Specify your needs in the
attached form. Thank you very much..
Parameter
Min
Typ
Max
Unit
Remarks
Supply Voltage
Output frequency range
Input frequency range
Cycle to Cycle Jitter
Lock up time
Dynamic current
Stand by current
Output clock duty ratio
• Do you need the I/O cells of SEC?
• How many FSPLLs are you using in your system?
• What is the PLL output loading condition?
• What is your p, m and s values ?
Specially requested function list :
10/10
SEC ASIC
ANALOG
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