PLX9656_技术文档

12/19/2002

PCI 9656 Blue Book Revision 0.90b Corrections

This document details several corrections to the PCI 9656 Blue Book, revision 0.90b. Please

review these corrections before proceeding with your design.

1. Toggling IDDQEN# At Power On Time

When using the PCI 9656AD, external logic is required on the IDDQEN# pin to

configure the PCI buffers for proper operation. This external logic is not required

when using the PCI 9656BA. The requirement for this logic is not included in the Blue

Book.

PCI 9656AD IDDQEN#

To put the PCI 9656AD into its IDDQ state, hold the IDDQEN# input signal (ball A10) in its

asserted state.

To configure the PCI 9656AD for normal operation, during initialization the IDDQEN# input signal

must transition from its asserted state to its de-asserted state prior to PCI RST# de-assertion.

This causes the silicon to configure its PCI I/O buffers for proper bus operation. After this

transition completes, hold IDDQEN# in its de-asserted state.

Note. For CompactPCI Hot Swap applications, IDDQEN# must be held in its de-

asserted state during pre-charge. As a result, CompactPCI Hot Swap

applications require that IDDQEN# transition from its de-asserted state to its

asserted state after pre-charge completes, and then transition back to its de-

asserted state prior to Local PCI RST# de-assertion.

PCI 9656BA IDDQEN#

To put the PCI 9656BA into its IDDQ state, hold the IDDQEN# input signal (ball A10) in its

asserted state.

To configure the PCI 9656BA for normal operation, hold IDDQEN# in its de-asserted state.

Note. For applications that use the PCI 9656BA’s PCI Power Management

D3cold PME Generation feature, de-assert IDDQEN# by tying it directly to the

2.5V power source for Vcore. The PCI 9656BA uses IDDQEN# to sense both

when Vcore is going away to prepare to enter the D3cold state and when Vcore

is coming back to prepare to leave the D3cold state. Do not tie IDDQEN# to the

2.5V power source for 2.5Vaux, and do not tie it to the 3.3V power source for

either Vring or Card_Vaux.

Even though the PCI 9656BA does not require any transitioning of its IDDQEN# input signal for

proper PCI bus operation, transitioning the PCI 9656BA’s IDDQEN# in accordance with the PCI

9656AD IDDQEN# requirements, above, will have no effect on PCI 9656BA operation. As a

result, the PCI 9656BA can be substituted for the PCI 9656AD in existing designs without

needing to remove the external IDDQEN# transitioning logic.

Sample Circuit Designs Supporting All Silicon Versions

The following circuit diagrams come directly from the schematics of two PLX hardware reference

design boards that have been validated empirically. The first is an example circuit for designs that

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do not need to support CompactPCI Hot Swap. The second is an example for designs that do

need to support CompactPCI Hot Swap.

Note. These circuit diagrams are provided as examples only. It is the designer’s

responsibility to create circuitry that meets the above stated IDDQEN# toggling

requirements for their particular design.

Figure 1. IDDQEN# Toggling Circuitry Example For Non-CompactPCI Hot Swap Designs

Figure 2. IDDQEN# Toggling Circuitry Example For CompactPCI Hot Swap Designs

2. USERi Pull-Up/Pull-Down At Power Up Time

When using the PCI 9656, an external pull-up or pull-down resistor is required on the

USERi pin to configure the chip for the desired PCI bus behavior during chip initialization.

A pull-up resistor configures the chip to issue PCI Retries during initialization [high =

retry], and a pull-down resistor configures the chip to do nothing on the PCI bus during

initialization. This is true for both the PCI 9656AD and the PCI 9656BA. The description

in the Blue Book regarding this is incorrect for these chip revisions.

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The following text replaces sections 2.4.1.2 and 4.4.1.2 of the Blue Book. Note that these

sections of the Blue Book look very similar to what is below. The key difference is that the polarity

of USERi is incorrectly reversed in the Blue Book descriptions. Follow the polarity in the

description below. Changes from the Blue Book are underlined.

2.4.1.2/4.4.1.2 Local Initialization

As stated in PCI r2.2, Section 3.5.1.1:

“If the target is accessed during initialization-time, it is allowed to do any of the

following:

1. Ignore the request (except if it is a boot device). This results in a Master Abort.

2. Claim the access and hold in wait sates until it can complete the request, not to

exceed the end of initialization-time.

3. Claim the access and terminate with [PCI] Retry.”

The PCI 9656 supports Option 1 (Initially Not Respond), and Option 3 (Initially Retry),

above. For CompactPCI Hot Swap live insertion systems, the preferred method for

the silicon is usually not to respond to PCI Configuration accesses during

initialization. For legacy systems, Retries are usually preferred for compatibility

reasons. However, it is ultimately the designer’s choice of which option to use.

The PCI 9656 determines the option to use as follows:

The USERi pin is sampled at the rising edge RST# to determine the selected PCI

Bus response mode during local initialization. If USERi is low (through an external 1K

ohm pull-down resistor), the PCI 9656 does not respond to PCI activity until the

device’s Local Bus initialization is complete. This results in a Master Abort (the

preferred method for CompactPCI Hot Swap systems). If USERi is high (through an

external 1K—4.7K ohm pull-up resistor), the PCI 9656 responds to PCI accesses

with PCI Retry cycles until the device’s Local Bus initialization is complete. Local Bus

initialization is complete when the Local Init Status bit is set (LMISC1[2]=1).

The LMISC1[2] bit can be programmed in one of three ways:

1. By a Local Bus master writing a 1 directly to LMISC1[2].

2. By the serial EEPROM specifying a value of 1 for LMISC1[2] during a serial

EEPROM load.

3. If a Local Bus Master is not present and either a serial EEPROM is not present or

a blank serial EEPROM is present, the PCI 9656 reverts to its power on/reset

default register values and sets this bit. (Refer to Table 2-18 on page 2-9.)

During run time, USERi can be used as a general purpose input as described in the

Tables 12-10, 12-11, and 12-12, for the M, C, and J mode Local Bus pins.

Refer to Section 9, “CompactPCI Hot Swap” for specifics on using this feature in

PICMG 2.1, R2.0 systems.

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3. EEDI/EEDO Pull-Up When Local Processor Present But EEPROM Not

Present

When using the PCI 9656, if initialization is to be performed by a Local Bus master and

no serial EEPROM is present, the EEDI/EEDO pin must not be pulled down. This is true

for both the PCI 9656AD and the PCI 9656BA. The description in the Blue Book

regarding this is vague.

Tables 2-18 and 4-18 of the Blue Book make no mention of a pull-up or pull-down resistor on the

EEDI/EEDO pin when a Local Processor is present but an EEPROM is not present. The correct

requirement is that the EEDI/EEDO pin must be either be left floating or pulled up with a 1K-ohm

or greater value resistor when an EEPROM is not present. In any case, the pin must not be pulled

down.

The following shows the corrected entry of Tables 2-18 and 4-18:

Table 1. Serial EEPROM Guidelines

Local

Processor

Serial

EEPROM

System Boot Condition

…

The Local Processor programs the PCI 9656 registers, then sets the

Local Init Status bit (LMISC1[2] = 1).

A 1K ohm or greater pull-up resistor on EEDI/EEDO is recommended,

but not required. The EEDI/EEDO pin already has an internal pull-up

(ref. Table 12-1).

Present

None

Note: Some systems may avoid configuring devices that do not

complete configuration accesses within 2²⁵PCI clocks after RST# has

been de-asserted. In addition, some systems may hang if Direct Slave

reads and writes are immediately retried. The value of the Direct Slave

Retry Delay Clocks (LBRD0[31:28]) may resolve the hang by delaying

assertion of the STOP# signal by the PCI 9656.

…

4. Updated Electrical Specifications

The following table updates Blue Book Table 13-5 for both the PCI 9656AD and the PCI

9656BA. Changes from the Blue Book are underlined.

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Table 2. Electrical Characteristics Over Operating Range

Parameter

Description

Output

High Voltage

Output

Low Voltage

Output

Test Conditions

Min

Max

Units

1

V_OH

I_OH= -12.0 mA

2.4

-

V

V_DD= Min

V_IN= V_IHor V_IL

1

V_OL

I_OL= 12.0 mA

-

0.4

-

2

V_OH

I_OH= -24.0 mA

2.4

-

V_DD= Min

High Voltage

V_IN= V_IHor V_IL

2

Output

Low Voltage

Input

V_OL

I_OL= 24.0 mA

0.4

5.5

0.8

V_IH

V_IL

-

2.0

-0.5

High Level

Input

Low Level

PCI 3.3V

V_OH3

Output

High Voltage

PCI 3.3V

Output

I_OH= -500 µA

I_OL= 1500 µA

0.9 V_DD

-

V

V_DD= Min

V_IN= V_IHor V_IL

V_OL3

-

0.1 V_DD

Low Voltage

PCI 3.3V Input

High Level

PCI 3.3V Input

Low Level

Input Leakage

Current

DC Current

Per Pin During

Pre-charge

Three-State

Output

V_IH3

V_IL3

I_Il

-

0.5 V_DDV_DD+0.5

V

-0.5

-10

0.3 V_DD

+10

V_SS= V_IN= V_DD, V_DD= Max

V_P= 0.8 to 1.2V

µA

3

I_LPC

-

1.0

mA

µA

I_OZ

V_DD= Max

-10

+10

Leakage

Current

4

Power Supply

Current

for I/O Ring

Power Supply

Current

I_DD

I/O Ring V_DD= 3.6V

PCLK = 66MHz, LCLK = 66MHz

-

95

185

50

mA

µA

(I/O Ring)

I_DD

(Core)

Core V_DD= 2.63V

PCLK = 66MHz, LCLK = 66MHz

for Core

I_CCL

I_CCH

I_CCZ

Quiescent

Power Supply

Current

V_CC= Max

V_IN= GND or V_CC

Notes:

1. For 12 mA I/O or output cells (Local Bus side).

2. For 24 mA I/O or output cells (Local Bus side).

3. I_LPCis the DC current flowing from VDD to Ground during pre-charge, as both PMOS and

NMOS devices remain on during pre-charge. It is not the leakage current flowing into or out

of the pin under pre-charge.

4. 40 Local Bus side I/Os switching simultaneously and 76 PCI side I/Os switching

simultaneously.

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5. PCI Arbiter Enable/Disable

When using the PCI 9656, the configuration register bit that is used to enable or disable

the PCI 9656’s PCI Arbiter can only be written by the EEPROM or a Local Bus master. A

PCI master cannot be write this bit. This is true for both the PCI 9656AD and the PCI

9656BA. The description in the Blue Book regarding this is incorrect.

Register 11-57 of the Blue Book incorrectly states that the PCI Arbiter Enable bit (PCIARB[0]) can

be written by a PCI master. In fact, a PCI master cannot write the PCI Arbiter Enable bit.

The following shows the corrected entry of Register 11-57:

Table 3. (PCIARB; PCI:100h, LOC:1A0h) PCI Arbiter Control

Value after

Reset

Bit

Description

Read

Write

PCI Arbiter Enable. Value of 0 indicates the PCI arbiter is disabled

and REQ0# and GNT0# are used by the PCI 9656 to acquire PCI

Bus use. Value of 1 indicates the PCI arbiter is enabled.

Local/

Serial

EEPROM

0

Yes

0

…

6. PCI BAR’s 4 & 5 Unused

For Direct Slave data transfers, the PCI 9656 supports mapping two PCI address spaces

to the Local Bus using PCI Base Address Registers (BAR’s) 2 and 3. This is true for both

the PCI 9656AD and the PCI 9656BA. The Blue Book PCI Configuration Register table

regarding this is potentially confusing.

Table 11-2 of the Blue Book could be interpreted to indicate that the PCI 9656 supports mapping

four PCI address spaces to the Local Bus for Direct Slave data transfers. The PCI 9656 in fact

only supports mapping two PCI address spaces.

The following shows the corrected entries of Table 11-2.

Table 4. PCI Configuration Registers

Local

Access

(Offset

from Chip

Select

To ensure software compatibility with other

versions of the PCI 9656 family and to ensure

compatibility with future enhancements, write 0 to

all unused bits.

PCI

PCI/

Local

Writeable

Serial

EEPROM

Writeable

Configuration

Register

Address

Address) 31

0

…

20h

24h

20h

24h

PCI Base Address 4; unused

PCI Base Address 5; unused

…

Y

N

7. Big Endian/Little Endian/Byte Lane Mode

The Blue Book descriptions of Big Endian and Little Endian conversion are potentially

confusing.

PCI 9656 Big Endian and Little Endian conversion are detailed in Blue Book Sections 2.3 and 4.3.

The following tables provide further clarification by detailing precisely PCI 9656 signal mappings

between the PCI bus and the Local Bus during Big Endian and Little Endian conversion.

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Table 5. C Mode Endian Mapping For Byte Lane Mode 0

C Mode Local Bus Pin

PCI Pins

Mapped 2^nd

(64-bit Transfers

Only)

Byte Lane Mode = 0 (BIGEND[4] = 0)

Little Endian Big Endian

16-bit

PCI Pins

Mapped 1^st

32-bit

8-bit

32-bit

1-LD24

1-LD25

16-bit

1-LD8

1-LD9

8-bit

AD32

AD33

AD34

AD35

AD36

AD37

AD38

AD39

AD40

AD41

AD42

AD43

AD44

AD45

AD46

AD47

AD48

AD50

AD51

AD52

AD53

AD54

AD55

AD56

AD57

AD58

AD59

AD60

AD61

AD62

AD63

AD0

AD1

1-LD0

1-LD1

1-LD2

1-LD3

1-LD4

1-LD5

1-LD6

1-LD7

1-LD8

1-LD9

1-LD0

1-LD1

1-LD2

1-LD3

1-LD4

1-LD5

1-LD6

1-LD7

1-LD8

1-LD9

1-LD0

1-LD1

1-LD2

1-LD3

1-LD4

1-LD5

1-LD6

1-LD7

2-LD0

2-LD1

2-LD2

2-LD3

2-LD4

2-LD5

2-LD6

2-LD7

3-LD0

3-LD1

3-LD2

3-LD3

3-LD4

3-LD5

3-LD6

3-LD7

4-LD0

4-LD1

4-LD2

4-LD3

4-LD4

4-LD5

4-LD6

4-LD7

1-LD0

1-LD1

1-LD2

1-LD3

1-LD4

1-LD5

1-LD6

1-LD7

2-LD0

2-LD1

2-LD2

2-LD3

2-LD4

2-LD5

2-LD6

2-LD7

3-LD0

3-LD1

3-LD2

3-LD3

3-LD4

3-LD5

3-LD6

3-LD7

4-LD0

4-LD1

4-LD2

4-LD3

4-LD4

4-LD5

4-LD6

4-LD7

AD2

AD3

AD4

AD5

AD6

AD7

1-LD26 1-LD10

1-LD27 1-LD11

1-LD28 1-LD12

1-LD29 1-LD13

1-LD30 1-LD14

1-LD31 1-LD15

AD8

AD9

1-LD16

1-LD17

1-LD18

1-LD19

1-LD20

1-LD21

1-LD22

1-LD23

1-LD8

1-LD0

1-LD1

1-LD2

1-LD3

1-LD4

1-LD5

1-LD6

1-LD7

2-LD8

2-LD9

AD10

AD11

AD12

AD13

AD14

AD15

AD16

AD17

AD18

AD19

AD20

AD21

AD22

AD23

AD24

AD25

AD26

AD27

AD28

AD29

AD30

AD31

1-LD10 1-LD10

1-LD11 1-LD11

1-LD12 1-LD12

1-LD13 1-LD13

1-LD14 1-LD14

1-LD15 1-LD15

1-LD16

1-LD17

1-LD18

1-LD19

1-LD20

1-LD21

1-LD22

1-LD23

1-LD24

1-LD25

2-LD0

2-LD1

2-LD2

2-LD3

2-LD4

2-LD5

2-LD6

2-LD7

2-LD8

2-LD9

1-LD9

1-LD10 2-LD10

1-LD11 2-LD11

1-LD12 2-LD12

1-LD13 2-LD13

1-LD14 2-LD14

1-LD15 2-LD15

1-LD0

1-LD1

1-LD2

1-LD3

1-LD4

1-LD5

1-LD6

1-LD7

2-LD0

2-LD1

2-LD2

2-LD3

2-LD4

2-LD5

2-LD6

2-LD7

1-LD26 2-LD10

1-LD27 2-LD11

1-LD28 2-LD12

1-LD29 2-LD13

1-LD30 2-LD14

1-LD31 2-LD15

Notes

1. During 64-bit PCI transfers, the lower 32 bits of the PCI bus (AD[31:0]) are always mapped first.

2. For each Local Bus Pin table entry, n-m means that row’s PCI pin maps to Local Bus pinm during Local Bus cycle n that either

results from the PCI cycle (PCI-to-Local Bus transfers) or results in the PCI cycle (Local Bus-to-PCI transfers). For example, a

Local Bus Pin of “2-LD5” for PCI Pin AD21 during 16–bit Little Endian Local Bus transfers (ref. the darkest shaded entry)

means that during a PCI-to-Local Bus transfer, the value of PCI Pin AD21 during each 32-bit PCI transfer will occur on Local

Bus pin LD5 of the second resulting 16-bit Local Bus transfer. During a Local Bus-to-PCI transfer, this means that the value of

PCI Pin AD21 will result from the value of Local Bus pin LD5 during the second 16-bit Local Bus transfer.

3. The mappings in the table only occur during data phases. Addresses always map to/from PCI AD[31:0] as indicated in the 32-bit

Little Endian column after the address translation specified in the configuration registers is performed.

4. Little and Big Endian Modes are selected by both register bits and pin signals, depending on the data phase type: Direct Master

Read/Write, Direct Slave Read/Write, DMA PCI -to-Local Bus / Local Bus-to-PCI, and Configuration Register Read/Write. See

the BIGEND register description in Table 11-41 and the BIGEND# pin description in Table 12-11 for details.

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Table 6. C Mode Endian Mapping For Byte Lane Mode 1

C Mode Local Bus Pin

PCI Pins

Mapped 2^nd

(64-bit Transfers

Only)

Byte Lane Mode = 1 (BIGEND[4] = 1)

Little Endian Big Endian

16-bit 16-bit

PCI Pins

Mapped 1^st

32-bit

8-bit

32-bit

8-bit

AD32

AD0

1-LD0

1-LD16 1-LD24 1-LD24 1-LD24 1-LD24

1-LD17 1-LD25 1-LD25 1-LD25 1-LD25

AD33

AD34

AD35

AD36

AD37

AD38

AD39

AD40

AD1

AD2

AD3

AD4

AD5

AD6

AD7

AD8

1-LD1

1-LD2

1-LD3

1-LD4

1-LD5

1-LD6

1-LD7

1-LD8

1-LD18 1-LD26 1-LD26

1-LD26 1-LD26

1-LD19 1-LD27 1-LD27 1-LD27 1-LD27

1-LD20 1-LD28 1-LD28 1-LD28 1-LD28

1-LD21 1-LD29 1-LD29 1-LD29 1-LD29

1-LD22 1-LD30 1-LD30 1-LD30 1-LD30

1-LD23 1-LD31 1-LD31

1-LD31 1-LD31

1-LD24 2-LD24 1-LD16 1-LD16 2-LD24

AD41

AD42

AD43

AD44

AD45

AD46

AD47

AD48

AD9

1-LD9

1-LD25 2-LD25 1-LD17 1-LD17 2-LD25

AD10

AD11

AD12

AD13

AD14

AD15

AD16

1-LD10 1-LD26 2-LD26 1-LD18 1-LD18 2-LD26

1-LD11 1-LD27 2-LD27 1-LD19 1-LD19 2-LD27

1-LD12 1-LD28 2-LD28 1-LD20 1-LD20 2-LD28

1-LD13 1-LD29 2-LD29 1-LD21 1-LD21 2-LD29

1-LD14 1-LD30 2-LD30 1-LD22 1-LD22 2-LD30

1-LD15 1-LD31 2-LD31 1-LD23 1-LD23 2-LD31

1-LD16 2-LD16 3-LD24

1-LD8

2-LD24 3-LD24

AD48

AD50

AD51

AD52

AD53

AD54

AD55

AD56

AD17

AD18

AD19

AD20

AD21

AD22

AD23

AD24

1-LD17 2-LD17 3-LD25

1-LD9

2-LD25 3-LD25

1-LD18 2-LD18 3-LD26 1-LD10 2-LD26 3-LD26

1-LD19 2-LD19 3-LD27 1-LD11 2-LD27 3-LD27

1-LD20 2-LD20 3-LD28 1-LD12 2-LD28 3-LD28

1-LD21 2-LD21 3-LD29 1-LD13 2-LD29 3-LD29

1-LD22

2-LD22 3-LD30 1-LD14 2-LD30 3-LD30

1-LD23 2-LD23 3-LD31 1-LD15 2-LD31 3-LD31

1-LD24 2-LD24 4-LD24

1-LD0

2-LD16 4-LD24

AD57

AD58

AD59

AD60

AD61

AD62

AD63

AD25

AD26

AD27

AD28

AD29

AD30

AD31

1-LD25 2-LD25 4-LD25

1-LD26 2-LD26 4-LD26

1-LD27 2-LD27 4-LD27

1-LD28 2-LD28 4-LD28

1-LD29 2-LD29 4-LD29

1-LD30 2-LD30 4-LD30

1-LD31 2-LD31 4-LD31

1-LD1

1-LD2

1-LD3

1-LD4

1-LD5

1-LD6

1-LD7

2-LD17 4-LD25

2-LD18 4-LD26

2-LD19 4-LD27

2-LD20 4-LD28

2-LD21 4-LD29

2-LD22 4-LD30

2-LD23 4-LD31

Notes

1. During 64-bit PCI transfers, the lower 32 bits of the PCI bus (AD[31:0]) are always mapped first.

2. For each Local Bus Pin table entry, n-m means that row’s PCI pin maps to Local Bus pinm during Local Bus cycle n that either

results from the PCI cycle (PCI-to-Local Bus transfers) or results in the PCI cycle (Local Bus-to-PCI transfers). For example, a

Local Bus Pin of “2-LD21” for PCI Pin AD21 during 16–bit Little Endian Local Bus transfers (ref. the darkest shaded entry)

means that during a PCI-to-Local Bus transfer, the value of PCI Pin AD21 during each 32-bit PCI transfer will occur on Local

Bus pin LD21 of the second resulting 16-bit Local Bus transfer. During a Local Bus-to-PCI transfer, this means that the value of

PCI Pin AD21 will result from the value of Local Bus pin LD21 during the second 16-bit Local Bus transfer.

3. The mappings in the table only occur during data phases. Addresses always map to/from PCI AD[31:0] as indicated in the 32-bit

Little Endian column after the address translation specified in the configuration registers is performed.

4. Little and Big Endian Modes are selected by both register bits and pin signals, depending on the data phase type: Direct Master

Read/Write, Direct Slave Read/Write, DMA PCI -to-Local Bus / Local Bus-to-PCI, and Configuration Register Read/Write. See

the BIGEND register description in Table 11-41 and the BIGEND# pin description in Table 12-11 for details.

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Table 7. J Mode Endian Mapping For Byte Lane Mode 0

J Mode Local Bus Pin

PCI Pins

Mapped 2^nd

(64-bit Transfers

Only)

Byte Lane Mode = 0 (BIGEND[4] = 0)

PCI Pins

Mapped 1^st

Little Endian Big Endian

32-bit

16-bit

8-bit

32-bit

16-bit

8-bit

1-LAD0

1-LAD24

1-LAD8

1-LAD0

AD32

AD0

1-LAD1

1-LAD2

1-LAD3

1-LAD4

1-LAD5

1-LAD6

1-LAD7

1-LAD8

1-LAD1

1-LAD2

1-LAD3

1-LAD4

1-LAD5

1-LAD6

1-LAD7

1-LAD8

1-LAD1

1-LAD2

1-LAD3

1-LAD4

1-LAD5

1-LAD6

1-LAD7

2-LAD0

1-LAD25

1-LAD9

1-LAD1

1-LAD2

1-LAD3

1-LAD4

1-LAD5

1-LAD6

1-LAD7

2-LAD0

AD33

AD34

AD35

AD36

AD37

AD38

AD39

AD40

AD1

AD2

AD3

AD4

AD5

AD6

AD7

AD8

1-LAD26 1-LAD10

1-LAD27 1-LAD11

1-LAD28 1-LAD12

1-LAD29 1-LAD13

1-LAD30 1-LAD14

1-LAD31 1-LAD15

1-LAD16

1-LAD0

1-LAD9

2-LAD1

2-LAD2

2-LAD3

2-LAD4

2-LAD5

2-LAD6

2-LAD7

3-LAD0

1-LAD17

1-LAD18

1-LAD19

1-LAD20

1-LAD21

1-LAD22

1-LAD23

1-LAD8

1-LAD1

1-LAD2

1-LAD3

1-LAD4

1-LAD5

1-LAD6

1-LAD7

2-LAD8

2-LAD1

2-LAD2

2-LAD3

2-LAD4

2-LAD5

2-LAD6

2-LAD7

3-LAD0

AD41

AD42

AD43

AD44

AD45

AD46

AD47

AD48

AD9

AD10

AD11

AD12

AD13

AD14

AD15

AD16

1-LAD10 1-LAD10

1-LAD11 1-LAD11

1-LAD12 1-LAD12

1-LAD13 1-LAD13

1-LAD14 1-LAD14

1-LAD15 1-LAD15

1-LAD16

2-LAD0

1-LAD17

1-LAD18

1-LAD19

1-LAD20

1-LAD21

1-LAD22

1-LAD23

1-LAD24

1-LAD25

1-LAD26 2-LAD10

1-LAD27 2-LAD11

1-LAD28 2-LAD12

1-LAD29 2-LAD13

1-LAD30 2-LAD14

1-LAD31 2-LAD15

2-LAD1

2-LAD2

2-LAD3

2-LAD4

2-LAD5

2-LAD6

2-LAD7

2-LAD8

2-LAD9

3-LAD1

3-LAD2

3-LAD3

3-LAD4

3-LAD5

3-LAD6

3-LAD7

4-LAD0

4-LAD1

4-LAD2

4-LAD3

4-LAD4

4-LAD5

4-LAD6

4-LAD7

1-LAD9

2-LAD9

3-LAD1

3-LAD2

3-LAD3

3-LAD4

3-LAD5

3-LAD6

3-LAD7

4-LAD0

4-LAD1

4-LAD2

4-LAD3

4-LAD4

4-LAD5

4-LAD6

4-LAD7

AD48

AD50

AD51

AD52

AD53

AD54

AD55

AD56

AD57

AD58

AD59

AD60

AD61

AD62

AD63

AD17

AD18

AD19

AD20

AD21

AD22

AD23

AD24

AD25

AD26

AD27

AD28

AD29

AD30

AD31

1-LAD10 2-LAD10

1-LAD11 2-LAD11

1-LAD12 2-LAD12

1-LAD13 2-LAD13

1-LAD14 2-LAD14

1-LAD15 2-LAD15

1-LAD0

1-LAD1

1-LAD2

1-LAD3

1-LAD4

1-LAD5

1-LAD6

1-LAD7

2-LAD0

2-LAD1

2-LAD2

2-LAD3

2-LAD4

2-LAD5

2-LAD6

2-LAD7

Notes

1. During 64-bit PCI transfers, the lower 32 bits of the PCI bus (AD[31:0]) are always mapped first.

2. For each Local Bus Pin table entry, n-m means that row’s PCI pin maps to Local Bus pinm during Local Bus cycle n that either

results from the PCI cycle (PCI-to-Local Bus transfers) or results in the PCI cycle (Local Bus-to-PCI transfers). For example, a

Local Bus Pin of “2-LAD5” for PCI Pin AD21 during 16–bit Little Endian Local Bus transfers (ref. the darkest shaded entry)

means that during a PCI-to-Local Bus transfer, the value of PCI Pin AD21 during each 32-bit PCI transfer will occur on Local

Bus pin LAD5 of the second resulting 16-bit Local Bus transfer. During a Local Bus-to-PCI transfer, this means that the value of

PCI Pin AD21 will result from the value of Local Bus pin LAD5 during the second 16-bit Local Bus transfer.

3. The mappings in the table only occur during data phases. Addresses always map to/from PCI AD[31:0] as indicated in the 32-bit

Little Endian column after the address translation specified in the configuration registers is performed.

4. Little and Big Endian Modes are selected by both register bits and pin signals, depending on the data phase type: Direct Master

Read/Write, Direct Slave Read/Write, DMA PCI -to-Local Bus / Local Bus-to-PCI, and Configuration Register Read/Write. See

the BIGEND register description in Table 11-41 and the BIGEND# pin description in Table 12-11 for details.

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Table 8. J Mode Endian Mapping For Byte Lane Mode 1

J Mode Local Bus Pin

PCI Pins

Mapped 2^nd

(64-bit Transfers

Only)

Byte Lane Mode = 1 (BIGEND[4] = 1)

Little Endian Big Endian

16-bit 16-bit

PCI Pins

Mapped 1^st

32-bit

8-bit

32-bit

8-bit

1-LAD0

1-LAD16 1-LAD24

1-LAD24 1-LAD24 1-LAD24

AD32

AD0

1-LAD1

1-LAD2

1-LAD3

1-LAD4

1-LAD5

1-LAD6

1-LAD7

1-LAD8

1-LAD17 1-LAD25

1-LAD18 1-LAD26

1-LAD19 1-LAD27

1-LAD20 1-LAD28

1-LAD21 1-LAD29

1-LAD22 1-LAD30

1-LAD23 1-LAD31

1-LAD24 2-LAD24

1-LAD25 1-LAD25 1-LAD25

1-LAD26 1-LAD26 1-LAD26

1-LAD27 1-LAD27 1-LAD27

1-LAD28 1-LAD28 1-LAD28

1-LAD29 1-LAD29 1-LAD29

1-LAD30 1-LAD30 1-LAD30

1-LAD31 1-LAD31 1-LAD31

1-LAD16 1-LAD16 2-LAD24

AD33

AD34

AD35

AD36

AD37

AD38

AD39

AD40

AD1

AD2

AD3

AD4

AD5

AD6

AD7

AD8

1-LAD9

1-LAD25 2-LAD25

1-LAD17 1-LAD17 2-LAD25

1-LAD18 1-LAD18 2-LAD26

1-LAD19 1-LAD19 2-LAD27

1-LAD20 1-LAD20 2-LAD28

1-LAD21 1-LAD21 2-LAD29

1-LAD22 1-LAD22 2-LAD30

1-LAD23 1-LAD23 2-LAD31

AD41

AD42

AD43

AD44

AD45

AD46

AD47

AD48

AD9

AD10

AD11

AD12

AD13

AD14

AD15

AD16

1-LAD10 1-LAD26 2-LAD26

1-LAD11 1-LAD27 2-LAD27

1-LAD12 1-LAD28 2-LAD28

1-LAD13 1-LAD29 2-LAD29

1-LAD14 1-LAD30 2-LAD30

1-LAD15 1-LAD31 2-LAD31

1-LAD16 2-LAD16 3-LAD24

1-LAD8

2-LAD24 3-LAD24

1-LAD17 2-LAD17 3-LAD25

1-LAD18 2-LAD18 3-LAD26

1-LAD19 2-LAD19 3-LAD27

1-LAD20 2-LAD20 3-LAD28

1-LAD21 2-LAD21 3-LAD29

1-LAD22 2-LAD22 3-LAD30

1-LAD23 2-LAD23 3-LAD31

1-LAD24 2-LAD24 4-LAD24

1-LAD25 2-LAD25 4-LAD25

1-LAD26 2-LAD26 4-LAD26

1-LAD27 2-LAD27 4-LAD27

1-LAD28 2-LAD28 4-LAD28

1-LAD29 2-LAD29 4-LAD29

1-LAD30 2-LAD30 4-LAD30

1-LAD31 2-LAD31 4-LAD31

1-LAD9

2-LAD25 3-LAD25

AD48

AD50

AD51

AD52

AD53

AD54

AD55

AD56

AD57

AD58

AD59

AD60

AD61

AD62

AD63

AD17

AD18

AD19

AD20

AD21

AD22

AD23

AD24

AD25

AD26

AD27

AD28

AD29

AD30

AD31

1-LAD10 2-LAD26 3-LAD26

1-LAD11 2-LAD27 3-LAD27

1-LAD12 2-LAD28 3-LAD28

1-LAD13 2-LAD29 3-LAD29

1-LAD14 2-LAD30 3-LAD30

1-LAD15 2-LAD31 3-LAD31

1-LAD0

1-LAD1

1-LAD2

1-LAD3

1-LAD4

1-LAD5

1-LAD6

1-LAD7

2-LAD16 4-LAD24

2-LAD17 4-LAD25

2-LAD18 4-LAD26

2-LAD19 4-LAD27

2-LAD20 4-LAD28

2-LAD21 4-LAD29

2-LAD22 4-LAD30

2-LAD23 4-LAD31

Notes

1. During 64-bit PCI transfers, the lower 32 bits of the PCI bus (AD[31:0]) are always mapped first.

2. For each Local Bus Pin table entry, n-m means that row’s PCI pin maps to Local Bus pinm during Local Bus cycle n that either

results from the PCI cycle (PCI-to-Local Bus transfers) or results in the PCI cycle (Local Bus-to-PCI transfers). For example, a

Local Bus Pin of “2-LAD21” for PCI Pin AD21 during 16–bit Little Endian Local Bus transfers (ref. the darkest shaded entry)

means that during a PCI-to-Local Bus transfer, the value of PCI Pin AD21 during each 32-bit PCI transfer will occur on Local

Bus pin LAD21 of the second resulting 16-bit Local Bus transfer. During a Local Bus-to-PCI transfer, this means that the value

of PCI Pin AD21 will result from the value of Local Bus pin LAD21 during the second 16-bit Local Bus transfer.

3. The mappings in the table only occur during data phases. Addresses always map to/from PCI AD[31:0] as indicated in the 32-bit

Little Endian column after the address translation specified in the configuration registers is performed.

4. Little and Big Endian Modes are selected by both register bits and pin signals, depending on the dat a phase type: Direct Master

Read/Write, Direct Slave Read/Write, DMA PCI -to-Local Bus / Local Bus-to-PCI, and Configuration Register Read/Write. See

the BIGEND register description in Table 11-41 and the BIGEND# pin description in Table 12-11 for details.

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Table 9. M Mode Endian Mapping For Byte Lane Mode 0

M Mode Local Bus Pin

PCI Pins

Mapped 2^nd

(64-bit Transfers

Only)

PCI Pins

Byte Lane Mode = 0 (BIGEND[4] = 0)

Little Endian Big Endian

16-bit 16-bit

Mapped 1^st

32-bit

8-bit

32-bit

1-LD7

1-LD6

1-LD5

1-LD4

1-LD3

1-LD2

1-LD1

1-LD0

8-bit

AD32

AD33

AD34

AD35

AD36

AD37

AD38

AD39

AD40

AD41

AD42

AD43

AD44

AD45

AD46

AD47

AD48

AD50

AD51

AD52

AD53

AD54

AD55

AD56

AD57

AD58

AD59

AD60

AD61

AD62

AD63

AD0

AD1

AD2

AD3

AD4

AD5

AD6

AD7

1-LD31 1-LD31 1-LD31

1-LD30 1-LD30 1-LD30

1-LD29 1-LD29 1-LD29

1-LD28 1-LD28 1-LD28

1-LD27 1-LD27 1-LD27

1-LD26 1-LD26 1-LD26

1-LD25 1-LD25 1-LD25

1-LD24 1-LD24 1-LD24

1-LD23

1-LD22

1-LD21

1-LD20

1-LD19

1-LD18

1-LD17

1-LD16

1-LD31

1-LD30

1-LD29

1-LD28

1-LD27

1-LD26

1-LD25

1-LD24

2-LD31

2-LD30

2-LD29

2-LD28

2-LD27

2-LD26

2-LD25

2-LD24

3-LD31

3-LD30

3-LD29

3-LD28

3-LD27

3-LD26

3-LD25

3-LD24

4-LD31

4-LD30

4-LD29

4-LD28

4-LD27

4-LD26

4-LD25

4-LD24

AD8

AD9

1-LD23 1-LD23 2-LD31 1-LD15 1-LD31

1-LD22 1-LD22 2-LD30 1-LD14 1-LD30

1-LD21 1-LD21 2-LD29 1-LD13 1-LD29

1-LD20 1-LD20 2-LD28 1-LD12 1-LD28

1-LD19 1-LD19 2-LD27 1-LD11 1-LD27

1-LD18 1-LD18 2-LD26 1-LD10 1-LD26

AD10

AD11

AD12

AD13

AD14

AD15

AD16

AD17

AD18

AD19

AD20

AD21

AD22

AD23

AD24

AD25

AD26

AD27

AD28

AD29

AD30

AD31

1-LD17 1-LD17 2-LD25

1-LD16 1-LD16 2-LD24

1-LD9

1-LD8

1-LD25

1-LD24

1-LD15 2-LD31 3-LD31 1-LD23 2-LD23

1-LD14 2-LD30 3-LD30 1-LD22 2-LD22

1-LD13 2-LD29 3-LD29 1-LD21 2-LD21

1-LD12 2-LD28

3-LD28 1-LD20 2-LD20

1-LD11 2-LD27 3-LD27 1-LD19 2-LD19

1-LD10 2-LD26 3-LD26 1-LD18 2-LD18

1-LD9

1-LD8

1-LD7

1-LD6

1-LD5

1-LD4

1-LD3

1-LD2

1-LD1

1-LD0

2-LD25 3-LD25 1-LD17 2-LD17

2-LD24 3-LD24 1-LD16 2-LD16

2-LD23 4-LD31 1-LD31 2-LD31

2-LD22 4-LD30 1-LD30 2-LD30

2-LD21 4-LD29 1-LD29 2-LD29

2-LD20 4-LD28 1-LD28 2-LD28

2-LD19 4-LD27 1-LD27 2-LD27

2-LD18 4-LD26 1-LD26 2-LD26

2-LD17 4-LD25 1-LD25 2-LD25

2-LD16 4-LD24 1-LD24 2-LD24

Notes

1. During 64-bit PCI transfers, the lower 32 bits of the PCI bus (AD[31:0]) are always mapped first.

2. For each Local Bus Pin table entry, n-m means that row’s PCI pin maps to Local Bus pinm during Local Bus cycle n that either

results from the PCI cycle (PCI-to-Local Bus transfers) or results in the PCI cycle (Local Bus-to-PCI transfers). For example, a

Local Bus Pin of “2-LD26” for PCI Pin AD21 during 16–bit Little Endian Local Bus transfers (ref. the darkest shaded entry)

means that during a PCI-to-Local Bus transfer, the value of PCI Pin AD21 during each 32-bit PCI transfer will occur on Local

Bus pin LD26 ofthe second resulting 16-bit Local Bus transfer. During a Local Bus-to-PCI transfer, this means that the value of

PCI Pin AD21 will result from the value of Local Bus pin LD26 during the second 16-bit Local Bus transfer.

3. The mappings in the table only occur during data phases. Addresses always map to/from PCI AD[31:0] as indicated in the 32-bit

Little Endian column after the address translation specified in the configuration registers is performed.

4. Little and Big Endian Modes are selected by both register bits and pin signals, depending on the data phase type: Direct Master

Read/Write, Direct Slave Read/Write, DMA PCI -to-Local Bus / Local Bus-to-PCI, and Configuration Register Read/Write. See

the BIGEND register description in Table 11-41 and the BIGEND# pin description in Table 12-11 for details.

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Table 10. M Mode Endian Mapping For Byte Lane Mode 1

M Mode Local Bus Pin

PCI Pins

Mapped 2^nd

(64-bit Transfers

Only)

PCI Pins

Byte Lane Mode = 1 (BIGEND[4] = 1)

Little Endian Big Endian

16-bit 16-bit

Mapped 1^st

32-bit

8-bit

32-bit

1-LD7

1-LD6

1-LD5

1-LD4

1-LD3

1-LD2

1-LD1

1-LD0

8-bit

AD32

AD33

AD34

AD35

AD36

AD37

AD38

AD39

AD40

AD41

AD42

AD43

AD44

AD45

AD46

AD47

AD48

AD50

AD51

AD52

AD53

AD54

AD55

AD56

AD57

AD58

AD59

AD60

AD61

AD62

AD63

AD0

AD1

AD2

AD3

AD4

AD5

AD6

AD7

1-LD31 1-LD15

1-LD30 1-LD14

1-LD29 1-LD13

1-LD28 1-LD12

1-LD27 1-LD11

1-LD26 1-LD10

1-LD7

1-LD6

1-LD5

1-LD4

1-LD3

1-LD2

1-LD1

1-LD0

2-LD7

2-LD6

2-LD5

2-LD4

2-LD3

2-LD2

2-LD1

2-LD0

3-LD7

3-LD6

3-LD5

3-LD4

3-LD3

3-LD2

3-LD1

3-LD0

4-LD7

4-LD6

4-LD5

4-LD4

4-LD3

4-LD2

4-LD1

4-LD0

1-LD7

1-LD6

1-LD5

1-LD4

1-LD3

1-LD2

1-LD1

1-LD0

1-LD7

1-LD6

1-LD5

1-LD4

1-LD3

1-LD2

1-LD1

1-LD0

2-LD7

2-LD6

2-LD5

2-LD4

2-LD3

2-LD2

2-LD1

2-LD0

3-LD7

3-LD6

3-LD5

3-LD4

3-LD3

3-LD2

3-LD1

3-LD0

4-LD7

4-LD6

4-LD5

4-LD4

4-LD3

4-LD2

4-LD1

4-LD0

1-LD25

1-LD24

1-LD23

1-LD22

1-LD21

1-LD20

1-LD19

1-LD18

1-LD17

1-LD16

1-LD9

1-LD8

1-LD7

1-LD6

1-LD5

1-LD4

1-LD3

1-LD2

1-LD1

1-LD0

AD8

AD9

1-LD15 1-LD15

1-LD14 1-LD14

1-LD13 1-LD13

1-LD12 1-LD12

1-LD11 1-LD11

1-LD10 1-LD10

AD10

AD11

AD12

AD13

AD14

AD15

AD16

AD17

AD18

AD19

AD20

AD21

AD22

AD23

AD24

AD25

AD26

AD27

AD28

AD29

AD30

AD31

1-LD9

1-LD8

1-LD9

1-LD8

2-LD7

2-LD6

2-LD5

2-LD4

2-LD3

2-LD2

2-LD1

2-LD0

1-LD15 2-LD15

1-LD14 2-LD14

1-LD13 2-LD13

1-LD12 2-LD12

1-LD11 2-LD11

1-LD10 2-LD10

1-LD23

1-LD22

1-LD21

1-LD20

1-LD19

1-LD18

1-LD17

1-LD16

1-LD9

1-LD8

1-LD7

1-LD6

1-LD5

1-LD4

1-LD3

1-LD2

1-LD1

1-LD0

2-LD9

2-LD8

2-LD7

2-LD6

2-LD5

2-LD4

2-LD3

2-LD2

2-LD1

2-LD0

1-LD31 2-LD15

1-LD30 2-LD14

1-LD29 2-LD13

1-LD28 2-LD12

1-LD27 2-LD11

1-LD26 2-LD10

1-LD25

1-LD24

2-LD9

2-LD8

Notes

1. During 64-bit PCI transfers, the lower 32 bits of the PCI bus (AD[31:0]) are always mapped first.

2. For each Local Bus Pin table entry, n-m means that row’s PCI pin maps to Local Bus pinm during Local Bus cycle n that either

results from the PCI cycle (PCI-to-Local Bus transfers) or results in the PCI cycle (Local Bus-to-PCI transfers). For example, a

Local Bus Pin of “2-LD10” for PCI Pin AD21 during 16–bit Little Endian Local Bus transfers (ref. the darkest shaded entry)

means that during a PCI-to-Local Bus transfer, the value of PCI Pin AD21 during each 32-bit PCI transfer will occur on Local

Bus pin LD10 of the second resulting 16-bit Local Bus transfer. During a Local Bus-to-PCI transfer, this means that the value of

PCI Pin AD21 will result from the value of Local Bus pin LD10 during the second 16-bit Local Bus transfer.

3. The mappings in the table only occur during data phases. Addresses always map to/from PCI AD[31:0] as indicated in the 32-bit

Little Endian column after the address translation specified in the configuration registers is performed.

4. Little and Big Endian Modes are selected by both register bits and pin signals, depending on the data phase type: DirectMaster

Read/Write, Direct Slave Read/Write, DMA PCI -to-Local Bus / Local Bus-to-PCI, and Configuration Register Read/Write. See

the BIGEND register description in Table 11-41 and the BIGEND# pin description in Table 12-11 for details.

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8. Local Bus Pause Timer Count Must Be Even (MARBR[8] = 0)

The Blue Book includes a description of the Local Bus Pause Timer in the MARBR

register (Register Description 11-40). For the PCI 9656AD, the Local Bus Pause Timer

count must be even (MARBR[8] = 0). This restriction is not included in the Blue Book

description. For the PCI 9056BA, this count may be odd or even (MARBR[8] = 0 or 1).

The PCI 9656 includes a Local Bus Pause Timer (MARBR[15:8]) for specifying how long to stay

off of the Local Bus between transfers to/from the Local Bus during DMA.

For the PCI 9656AD, this count must be even (MARBR[8] = 0). Note that this counter is 0 after

reset, so the only time this correction is of concern is if the Local Bus Pause Timer count is ever

changed from its reset value.

For the PCI 9056BA, this count may be odd or even (MARBR[8] = 0 or 1).

9. ALE Output Delay Timing For Any Local Bus Clock Rate

The Blue Book includes Figure 13-3 that shows the ALE output delay timing to the

Processor/Local Bus clock for a clock rate of 33MHz. It does not show the output delay

timing for other clock rates.

The following figure shows the PCI 9656AD ALE output delay timing for any Processor/Local Bus

clock rate. It replaces Figure 13-3 in the Blue Book for the PCI 9656AD silicon. LC_HIGHis the time

in ns that the Processor/Local Bus clock is high. (Note. When two times are given like x/y ns, x ns

is the minimum value and y ns is the maximum value.)

LC_HIGH

1.5V

Local Clock

3.1/6.9 ns

LC_HIGH+15.1/15.4 ns (33 MHz)

LC_HIGH+7.6/7.9 ns (66 MHz)

2.9/6.5 ns

ALE

2.9/7.8 ns

Address Bus

Figure 3. PCI 9656AD ALE Output Delay to the Local Clock

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The following figure shows the PCI 9656BA ALE output delay timing for any Processor/Local Bus

clock rate. It replaces Figure 13-3 in the Blue Book for the PCI 9656BA silicon. LC_HIGHis the time

in ns that the Processor/Local Bus clock is high. (Note. When two times are given like x/y ns, x ns

is the minimum value and y ns is the maximum value.)

LC_HIGH

1.5V

Local Clock

3.4/6.9 ns

LC_HIGH+14.8/14.9 ns (33 MHz)

LC_HIGH+6.8/6.9 ns (66 MHz)

3.6/7.0 ns

ALE

3.0/6.4 ns

Address Bus

Figure 4. PCI 9656BA ALE Output Delay to the Local Clock

10. M Mode LA30 & LA 31 Pin Outs

Description:

The Blue Book Table 14-3 pin outs for pins P19 and P20 are indicated incorrectly. The M

Mode LA31 and LA30 signals are swapped. This is true for both the PCI 9656AD and the

PCI 9656BA.

Blue Book Table 14-3 indicates that pin P19 is “LA31 (M), LBE1# (C, J)” and pin P20 is “LA30

(M), LBE0# (C, J)”. This is incorrect.

For the PCI 9656AD and PCI 9656BA, pin P19 is “LA30 (M), LBE1# (C, J)” and pin P20 is “LA31

(M), LBE0# (C, J)”.

Note that in Table 12-10 the pin numbers for LA30 and LA31 are indicated correctly.

11. AC Timing

Description:

PLX had conducted exhaustive static timing analysis (STA) of the PCI 9656AD and PCI

9656BA silicon. The following six tables contain the results of that analysis and replace

tables 13-6, 13-7, 13-8, and 13-9 in the Blue Book.

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Table 11. C Mode Local Bus Input AC Timing Specifications

Signals

(Synchronous Inputs)

T_SETUP

(V_CC= 3.0V, T_a= 85°C)

T_HOLD

(V_CC= 3.0V, T_a= 85°C)

Blue Book AD STA BA STA

Blue Book

AD STA

4.8 ns

4.0 ns

1.7 ns

4.8 ns

1.7 ns

4.7 ns

2.0 ns

4.4 ns

4.0 ns

4.6 ns

4.9 ns

4.2 ns

5.0 ns

4.7 ns

2.4 ns

4.7 ns

BA STA

ADS#

4.5 ns

2.1 ns

4.0 ns

3.4 ns

0.3 ns

4.0 ns

2.9 ns

4.2 ns

2.9 ns

3.3 ns

3.4 ns

3.6 ns

3.1 ns

2.5 ns

3.5 ns

4.0 ns

2.9 ns

4.0 ns

1 ns

BIGEND#

BLAST#

BREQi

BTERM#

CCS#

DMPAF/EOT#

DP[3:0]

DREQ[1:0]#

LA[31:2]

LBE[3:0]#

LD[31:0]

LHOLDA

LW/R#

READY#

USERi/LLOCKi#

WAIT#

Input Clocks

Min

Max

0 MHz

Local Clock Input Frequency

PCI Clock Input Frequency

66 MHz

Table 12. C Mode Local Bus Output AC Timing Specifications

Signals

(Synchronous Outputs)

Output T_VALID

(C_L= 50pF, V _CC= 3.0V, T_a= 85°C)

Blue Book

AD¹STA

7.6 ns

9.5 ns

8.3 ns

7.6 ns

8.5 ns

7.9 ns

8.0 ns

7.6 ns

7.8 ns

7.5 ns

10.2 ns

7.6 ns

9.0 ns

7.6 ns

BA²STA

6.3 ns

6.8 ns

6.3 ns

6.6 ns

6.8 ns

6.3 ns

6.4 ns

6.8 ns

7.5 ns

6.3 ns

7.2 ns

6.3 ns

6.4 ns

ADS#

BLAST#

BREQo

9ns

BTERM#

DACK[1:0]#

DMPAF/EOT#

DP[3:0]

LA[31:2]

LBE[3:0]#

LD[31:0]

LHOLD

LSERR#

LW/R#

READY#

USERo/LLOCKo#

WAIT#

1.

On high-to-low transitions, output T_VALIDvalues increase/decrease by 23 ps for each increase/decrease of 1pF.

On low-to-high transitions, output T_VALIDvalues increase/decrease by 20 ps for each increase/decrease of 1pF.

2.

On high-to-low transitions, output T_VALIDv alues increase/decrease by 16 ps for each increase/decrease of 1pF.

On low-to-high transitions, output T_VALIDvalues increase/decrease by 20 ps for each increase/decrease of 1pF.

On high-to-low transitions, the slew rate at 50 pF loading is 1.93 V/ns typical; .94 V/ns worst case.

On low-to-high transitions, the slew rate at 50 pF loading is 1.15 V/ns typical; .70 V/ns worst case.

- 15 -

9656-SIL-DC1-P0-.96

12/19/2002

Table 13. J Mode Local Bus Input AC Timing Specifications

Signals

(Synchronous Inputs)

T_SETUP

(V_CC= 3.0V, T_a= 85°C)

T_HOLD

(V_CC= 3.0V, T_a= 85°C)

Blue Book

AD STA

4.9 ns

4.5 ns

4.8 ns

4.0 ns

1.7 ns

4.8 ns

1.7 ns

4.7 ns

2.0 ns

4.4 ns

4.0 ns

4.9 ns

4.6 ns

4.2 ns

5.0 ns

4.7 ns

2.4 ns

4.7 ns

BA STA

Blue Book AD STA BA STA

ADS#

ALE

BIGEND#

BLAST#

BREQi

BTERM#

CCS#

4.5 ns

2.1 ns

1.7 ns

4.0 ns

3.4 ns

0.3 ns

4.2 ns

2.9 ns

4.2 ns

2.9 ns

3.3 ns

3.4 ns

3.1 ns

3.6 ns

2.5 ns

3.5 ns

4.2 ns

2.9 ns

4.0 ns

1 ns

Max

1 ns

DMPAF/EOT#

DP[3:0]

DREQ[1:0]#

LA [28:2]

LAD[31:0]

LBE[3:0]#

LHOLDA

LW/R#

READY#

USERi/LLOCKi#

WAIT#

Input Clocks

Min

0 MHz

66 MHz

Local Clock Input Frequency

PCI Clock Input Frequency

Table 14. J Mode Local Bus Output AC Timing Specifications

Signals

(Synchronous Outputs)

Output T_VALID

(C_L= 50pF, V _CC= 3.0V, T_a= 85°C)

Blue Book

AD¹STA

BA²STA

ADS#

ALE

9 ns

7.6 ns

8.0 ns

7.6 ns

9.5 ns

8.3 ns

7.6 ns

7.9 ns

8.5 ns

7.9 ns

8.0 ns

7.8 ns

7.6 ns

7.5 ns

10.2 ns

7.6 ns

9.0 ns

7.6 ns

6.3 ns

See item 9, above.

6.3 ns

BLAST#

BREQo

BTERM#

DACK[1:0]#

DEN#

DMPAF/EOT#

DP[3:0]

6.8 ns

6.3 ns

6.4 ns

6.6 ns

6.8 ns

6.3 ns

6.4 ns

6.3 ns

6.8 ns

7.5 ns

6.3 ns

7.2 ns

6.3 ns

6.4 ns

DT/R#

LA[28:2]

LAD[31:0]

LBE[3:0]#

LHOLD

LSERR#

LW/R#

READY#

USERo/LLOCKo#

WAIT#

1

2

On high-to-low transitions, output T_VALIDvalues increase/decrease by 23 ps for each increase/decrease of 1pF.

On low-to-high transitions, output T_VALIDvalues increase/decrease by 20 ps for each increase/decrease of 1pF.

On high-to-low transitions, output T_VALIDvalues increase/decrease by 16 ps for each increase/decrease of 1pF.

On low-to-high transitions, output T_VALIDvalues increase/decrease by 20 ps for each increase/decrease of 1pF.

On high-to-low transitions, the slew rate at 50 pF loading is 1.93 V/ns typical; .94 V/ns worst case.

On low-to-high transitions, the slew rate at 50 pF loading is 1.15 V/ns typical; .70 V/ns worst case.

- 16 -

9656-SIL-DC1-P0-.96

12/19/2002

Table 15. M Mode Local Bus Input AC Timing Specifications

Signals

(Synchronous Inputs)

T_SETUP

(V_CC= 3.0V, T_a= 85°C)

T_HOLD

Blue Book

AD STA

4.9 ns

4.5 ns

4.4 ns

5.3 ns

4.8 ns

1.7 ns

2.0 ns

4.4 ns

5.2 ns

4.9 ns

4.7 ns

5.3 ns

5.2 ns

4.8 ns

5.0 ns

1.9 ns

Min

BA STA

Blue Book AD STA

BA STA

1 ns

BB#

4.5 ns

2.7 ns

3.8 ns

2.9 ns

4.0 ns

3.8 ns

4.1 ns

2.9 ns

3.3 ns

3.6 ns

3.1 ns

4.2 ns

3.5 ns

4.1 ns

4.4 ns

2.1 ns

3.6 ns

3.2 ns

1 ns

Max

66 MHz

BDIP#

BG#

BI#

BIGEND#/WAIT#

BURST#

CCS#

DP[0:3]

DREQ[1:0]#

LA[0:31]

LD[0:31]

MDREQ#/DMPAF/ EOT#

RD/WR#

TA#

TEA#

TS#

TSIZ[0:1]#

USERi/LLOCK#

Input Clocks

Local Clock Input Frequency

PCI Clock Input Frequency

0 MHz

Table 16. M Mode Local Bus Output AC Timing Specifications

Signals

Output T_VALID

(Synchronous Outputs)

(C_L= 50pF, V _CC= 3.0V, T_a= 85°C)

Blue Book

AD¹STA

9.4 ns

7.7 ns

7.6 ns

7.5 ns

7.6 ns

7.9 ns

8.0 ns

7.8 ns

8.5 ns

7.6 ns

9.5 ns

9.0 ns

9.6 ns

7.6 ns

BA²STA

BB#

BDIP#

9 ns

6.8 ns

6.4 ns

6.3 ns

6.8 ns

6.3 ns

6.8 ns

6.3 ns

6.6 ns

6.3 ns

6.8 ns

7.2 ns

7.5 ns

6.3 ns

BIGEND#/WAIT#

BR#

BURST#

DACK[1:0]#

DP[0:3]

LA[0:31]

LD[0:31]

MDREQ#/DMPAF/ EOT#

RD/WR#

RETRY#

TA#

TEA#

TS#

TSIZ[0:1]#

USERo/LLOCKo#

1

On high-to-low transitions, output T_VALIDvalues increase/decrease by 23 ps for each increase/decrease of 1pF.

On low-to-high transitions, output T_VALIDvalues increase/decrease by 20 ps for each increase/decrease of 1pF.

2

On high-to-low transitions, output T_VALIDvalues increase/decrease by 16 ps for each increase/decrease of 1pF.

On low-to-high transitions, output T_VALIDvalues increase/decrease by 20 ps for each increase/decrease of 1pF.

On high-to-low transitions, the slew rate at 50 pF loading is 1.93 V/ns typical; .94 V/ns worst case.

On low-to-high transitions, the slew rate at 50 pF loading is 1.15 V/ns typical; .70 V/ns worst case.

- 17 -

9656-SIL-DC1-P0-.96

12/19/2002

12. Pin Types

Description:

The following tables detail the pin types of the PCI 9656AD and PCI 9656BA silicon. The

information in these tables is intended to replace the Pin Type columns of Blue Book

Tables 12-4 through 12-12.

Each table includes 5 columns for each pin:

1. Each entry in the leftmost column contains the name of the signal (or signals, in the case of

multiplexed pins) connected to that pin.

2. Each entry in the next column contains the pin number (or pin numbers in the case of

address buses, data buses, etc. that share the same pin type).

3. Each entry in the next column contains the pin type in the Blue Book.

4. Each entry in the next column contains the actual pin type for the AD silicon revision. Shaded

entries in this column indicate where the actual pin type of the AD silicon differs from the pin

type given in the Blue Book. While these changes should not effect designs that follow the

Blue Book pin types, for designs that use the AD version of silicon, the designers should look

carefully at the shaded entries in this column.

5. Each entry in the rightmost column contains the actual pin type for the BA silicon revision.

Shaded entries in this column indicate where the actual pin type of the BA silicon differs from

the actual pin type of the AD silicon. While these changes should not effect designs intended

to use both AD and BA silicon revisions, for AD designs that are intended to use the BA as a

drop-in replacement for the AD, the designers should look carefully at the shaded entries in

this column.

- 18 -

9656-SIL-DC1-P0-.96

12/19/2002

Table 17. PCI 9656AD/PCI 9656BA PCI Pin Types

Symbol

ACK64#

Pin Number Blue Book r.90b Pin Type

True AD Pin Type

True BA Pin Type

I/O

STS

PCI

I/O

STS

PCI

N1

STS

PCI

T4, U3, W1,

V3, Y2, W4,

V4, U5, Y3,

Y4, V5, W5,

Y5, V6, U7,

W6, Y6, V7,

W7, Y7, V8,

W8, Y8, V9,

W9, Y9, W10,

V10, Y10, Y11,

W11, V11, A5,

D7, C6, B5,

A4, C5, B4,

A3, B3, B2,

A2, C3, B1,

C2, D2, D3,

H3, H2, H1,

J4, J3, J2,

I/O

TS

PCI

I/O

TS

PCI

I/O

TS

PCI

AD[63:0]

J1, K2, K1,

L2, L3, L4,

M1, M2, M3,

M4

T2, U1, T3,

C/BE[7:0]# U2, D5, E4,

I/O

TS

I/O

TS

I/O

TS

G1, K3

PCI

I/O

STS

PCI

I/O

STS

PCI

I/O

STS

PCI

I/O

STS

PCI

I/O

STS

PCI

I/O

STS

PCI

E1

DEVSEL#

FRAME#

C1

O

GNT0#

O

TP

PCI

TP

PCI

GNT0#

REQ#

C7

REQ#

O

STS

PCI

Note:

If ((RST# asserted)

or

Note:

If ((RST# asserted)

or

(BD_SEL# not asserted)) (BD_SEL# not asserted))

Pin goes Hi-Z.

O

TP

PCI

Note:

If ((RST# asserted)

or

Note:

If ((RST# asserted)

or

W12, U11, P4,

R2, R1, N3

O

TP

GNT[6:1]#

(BD_SEL# not asserted) (BD_SEL# not asserted)

or

PCARB[0]=0))

Pins go Hi-Z.

I

PCARB[0]=0))

Pins go Hi-Z.

I

C4

B7

I

IDSEL

INTA#

I/O

OC

PCI

I/O

OC

PCI

I/O

OC

PCI

I/O

STS

PCI

I/O

STS

PCI

I/O

TS

I/O

STS

PCI

I/O

STS

PCI

I/O

TS

I/O

STS

PCI

I/O

STS

PCI

I/O

TS

D1

G4

G2

IRDY#

LOCK#

PAR

PCI

I/O

TS

PCI

I

I/O

STS

PCI

I/O

TS

PCI

I

I/O

STS

PCI

I/O

TS

PCI

I

I/O

STS

PCI

V1

L1

F2

PAR64

PCLK

PERR#

- 19 -

9656-SIL-DC1-P0-.96

12/19/2002

Table 17. PCI 9656AD/PCI 9656BA PCI Pin Types

Symbol

PME#

Pin Number Blue Book r.90b Pin Type

True AD Pin Type

True BA Pin Type

O

OC

PCI

B9

OC

PCI

OC

PCI

REQ0#

I

REQ0#

GNT#

B6

I

GNT#

I

V12, Y12, R3,

T1, P2, P1

I

REQ[6:1]#

REQ64#

I/O

STS

PCI

I/O

STS

PCI

I/O

STS

PCI

N2

If (HOSTEN# asserted) If (HOSTEN# asserted)

O

TP

PCI

TP

PCI

A6

I/O

RST#

else

I

I/O

OC

PCI

I/O

STS

PCI

I/O

STS

PCI

I/O

G3

F3

E3

SERR#

STOP#

TRDY#

OC

PCI

I/O

STS

PCI

I/O

OC

PCI

I/O

STS

PCI

I/O

STS

PCI

STS

PCI

- 20 -

9656-SIL-DC1-P0-.96

12/19/2002

Table 18. PCI 9656AD/PCI 9656BA C Mode Pin Types

Symbol

ADS#

Pin Number

Blue Book r.90b Pin Type

True AD Pin Type

True BA Pin Type

I/O

TS

I/O

TS

I/O

TS

C17

24 mA

I

I/O

TS

24 mA

I

I/O

TS

24 mA

I

I/O

TS

C12

A18

BIGEND#

BLAST#

24 mA

C16

A17

I

O

OC

I

O

DTS

24 mA

I

O

DTS

24 mA

BREQi

BREQo

24 mA

I/O

DTS

24 mA

I

I/O

DTS

24 mA

I

O

I/O

DTS

24 mA

I

O

C20

D12

BTERM#

CCS#

TP

24 mA

Note:

O

TP

If ((HOSTEN# not asserted & RST#

C13, A13

DACK[1:0]#

asserted)

24 mA

or

(HOSTEN# asserted & LRESET#

asserted)

or

(HOSTEN# asserted & LRESET#

asserted)

or

(BD_SEL# not asserted))

Pins go Hi-Z.

If ((DMAMODE0[14]=1)

or

(DMAMODE1[14]=1))

I

If ((DMAMODE0[14]=1)

or

else

(DMAMODE1[14]=1))

DMPAF

O

TP

24 mA

I

TS

24 mA

DMPAF

EOT#

D14

else

EOT#

I

Note for 2nd case:

If ((HOSTEN# not asserted & RST#

O

TP

asserted

24 mA

or

(HOSTEN# asserted & LRESET#

asserted)

or

(BD_SEL# not asserted))

Pin goes Hi-Z.

I/O

TS

24 mA

I/O

TS

24 mA

I/O

TS

24 mA

D18, B20, C18,

B19

DP[3:0]

A14, B13

I

DREQ[1:0]#

W14, Y15, V14,

W15, Y16, U14,

V15, W16, Y17,

V16, W17, Y18,

U16, V17, W18,

Y19, V18, W19,

Y20, W20, V19,

U18, T17, V20,

U20, T18, T19,

T20, R18, P17

I/O

TS

24 mA

I/O

TS

24 mA

I/O

TS

24 mA

LA[31:2]

I/O

TS

24 mA

I/O

TS

24 mA

I/O

TS

24 mA

R20, P18, P19,

P20

LBE[3:0]#

LCLK

D20

I

- 21 -

9656-SIL-DC1-P0-.96

12/19/2002

Table 18. PCI 9656AD/PCI 9656BA C Mode Pin Types

Symbol

LD[31:0]

Pin Number

N18, N19, N20,

M17, M18, M19,

M20, L19, L18,

L20, K20, K19,

K18, K17, J20,

J19, J18, J17,

H20, H19, H18,

G20, G19, F20,

G18, F19, E20,

G17, F18, E19,

E18, D19

Blue Book r.90b Pin Type

True AD Pin Type

True BA Pin Type

I/O

TS

24 mA

I/O

TS

24 mA

I/O

TS

24 mA

O

TP

24 mA

Note:

O

TP

O

TP

If ((HOSTEN# not asserted & RST#

B18

asserted)

LHOLD

24 mA

or

(HOSTEN# asserted & LRESET#

asserted)

or

(BD_SEL# not asserted))

Pin goes Hi-Z.

B17

B15

I

O

I

O

I

O

LHOLDA

LINTi#

A15

A16

D16

LINTo#

OC

24 mA

OC

24 mA

If (HOSTEN# asserted)

OC

24 mA

If (HOSTEN# asserted)

I

I/O

TP

24 mA

LRESET#

LSERR#

else

O

TP

24 mA

O

OC

O

TP

24 mA

O

OC

O

OC

24 mA

I/O

TS

24 mA

I/O

TS

24 mA

I/O

TS

24 mA

R19

B10

E17

LW/R#

I

PMEREQ#

READY#

I/O

DTS

24 mA

I/O

DTS

24 mA

I/O

DTS

24 mA

USERi

I

USERi

B14

I

LLOCKi#

I

O

TP

O

TP

24 mA

USERo

O

TS

Note:

If ((HOSTEN# not asserted & RST#

USERo

C14

B16

24 mA

asserted)

LLOCKo#

or

(HOSTEN# asserted & LRESET#

asserted)

or

(HOSTEN# asserted & LRESET#

asserted)

LLOCKo#

O

or

(BD_SEL# not asserted))

Pin goes Hi-Z.

(BD_SEL# not asserted))

Pin goes Hi-Z.

I/O

TS

I/O

TS

I/O

TS

WAIT#

24 mA

- 22 -

9656-SIL-DC1-P0-.96

12/19/2002

Table 19. PCI 9656AD/PCI 9656BA J Mode Pin Types

Blue Book r.90b Pin

True AD Pin Type

Type

Symbol

ADS#

Pin Number

True BA Pin Type

I/O

TS

I/O

TS

I/O

TS

C17

24 mA

I/O

TS

24 mA

I

24 mA

I/O

TS

24 mA

I

24 mA

I/O

TS

24 mA

I

V14

C12

A18

ALE

BIGEND#

BLAST#

I/O

TS

I/O

TS

I/O

TS

24 mA

C16

A17

I

O

OC

24 mA

I/O

I

O

DTS

24 mA

I/O

I

O

DTS

24 mA

I/O

BREQi

BREQo

C20

D12

BTERM#

CCS#

DTS

24 mA

I

DTS

24 mA

I

DTS

24 mA

I

O

TP

24 mA

O

TP

24 mA

Note:

O

TP

If ((HOSTEN# not asserted & RST#

C13, A13

asserted)

DACK[1:0]#

24 mA

or

(HOSTEN# asserted & LRESET#

asserted)

or

(BD_SEL# not asserted))

Pins go Hi-Z.

O

TS

24 mA

O

TS

24 mA

O

TS

24 mA

Y15

DEN#

If ((DMAMODE0[14]=1)

or

(DMAMODE1[14]=1))

I

If ((DMAMODE0[14]=1)

or

else

(DMAMODE1[14]=1))

DMPAF

O

TP

24 mA

I

DMPAF

EOT#

TS

24 mA

D14

else

EOT#

I

Note for 2nd case:

If ((HOSTEN# not asserted & RST#

O

TP

asserted

24 mA

or

(HOSTEN# asserted & LRESET#

asserted)

or

(BD_SEL# not asserted))

Pin goes Hi-Z.

I/O

TS

24 mA

I/O

TS

24 mA

I/O

TS

24 mA

D18, B20, C18,

B19

DP[3:0]

A14, B13

W14

I

O

TS

I

O

TS

I

O

TS

DREQ[1:0]#

DT/R#

24 mA

W15, Y16, U14,

V15, W16, Y17,

V16, W17, Y18,

U16, V17, W18,

Y19, V18, W19,

Y20, W20, V19,

U18, T17, V20,

U20, T18, T19,

T20, R18, P17

I/O

TS

24 mA

I/O

TS

24 mA

I/O

TS

24 mA

LA[28:2]

- 23 -

9656-SIL-DC1-P0-.96

12/19/2002

Table 19. PCI 9656AD/PCI 9656BA J Mode Pin Types

Blue Book r.90b Pin

True AD Pin Type

Type

Symbol

Pin Number

True BA Pin Type

N18, N19, N20,

M17, M18, M19,

M20, L19, L18,

L20, K20, K19,

K18, K17, J20,

J19, J18, J17,

H20, H19, H18,

G20, G19, F20,

G18, F19, E20,

G17, F18, E19,

E18, D19

I/O

TS

24 mA

I/O

TS

24 mA

I/O

TS

24 mA

LAD[31:0]

I/O

TS

24 mA

I

I/O

TS

24 mA

I

I/O

TS

24 mA

I

R20, P18, P19,

P20

LBE[3:0]#

LCLK

D20

O

TP

24 mA

Note:

O

TP

O

TP

If ((HOSTEN# not asserted & RST#

B18

asserted)

LHOLD

24 mA

or

(HOSTEN# asserted & LRESET#

asserted)

or

(BD_SEL# not asserted))

Pin goes Hi-Z.

I

B17

B15

I

O

I

O

LHOLDA

LINTi#

I

O

A15

A16

D16

LINTo#

OC

24 mA

OC

24 mA

If (HOSTEN# asserted)

OC

24 mA

If (HOSTEN# asserted)

I

I/O

TP

24 mA

else

LRESET#

LSERR#

O

TP

24 mA

O

OC

O

TP

24 mA

O

OC

O

OC

24 mA

I/O

TS

24 mA

I

I/O

TS

24 mA

I

I/O

TS

24 mA

I

R19

B10

E17

LW/R#

PMEREQ#

READY#

I/O

DTS

I/O

DTS

I/O

DTS

24 mA

USERi

I

USERi

B14

I

LLOCKi#

I

O

TP

24 mA

O

TP

24 mA

USERo

O

TS

Note:

USERo

If ((HOSTEN# not asserted & RST#

C14

B16

24 mA

asserted)

LLOCKo#

or

(HOSTEN# asserted & LRESET#

LLOCKo#

O

asserted)

or

(BD_SEL# not asserted))

Pin goes Hi-Z.

I/O

TS

I/O

TS

I/O

TS

WAIT#

24 mA

- 24 -

9656-SIL-DC1-P0-.96

12/19/2002

Table 20. PCI 9656AD/PCI 9656BA M Mode Pin Types

Symbol

BB#

Pin Number

Blue Book r.90b Pin Type

True AD Pin Type

True BA Pin Type

I/O

DTS

C16

OC

DTS

24 mA

I/O

TS

24 mA

I/O

TS

24 mA

I/O

TS

24 mA

B16

BDIP#

B17

C20

I

BG#

BI#

If(MARBR(31)=0)

BIGEND#

I

BIGEND#

WAIT#

C12

WAIT#

I/O

TS

else

I/O

TS

I/O

TS

24 mA

O

TP

24 mA

Note:

O

TP

O

TP

If ((HOSTEN# not asserted & RST#

B18

asserted)

BR#

24 mA

or

(HOSTEN# asserted & LRESET#

asserted)

or

(BD_SEL# not asserted))

Pin goes Hi-Z.

I/O

TS

24 mA

I

I/O

TS

24 mA

I

I/O

TS

24 mA

I

A18

D12

BURST#

CCS#

O

TP

O

TP

24 mA

Note:

O

TP

If ((HOSTEN# not asserted & RST#

C13, A13

asserted)

DACK[1:0]#

24 mA

or

(HOSTEN# asserted & LRESET#

asserted)

or

(BD_SEL# not asserted))

Pins go Hi-Z.

I/O

TS

24 mA

I

I/O

TS

24 mA

I

I/O

TS

24 mA

I

D18, B20, C18,

B19

DP[0:3]

A14, B13

DREQ[1:0]#

W14, Y15, V14,

W15, Y16, U14,

V15, W16, Y17,

V16, W17, Y18,

U16, V17, W18,

Y19, V18, W19,

Y20, W20, V19,

U18, T17, V20,

U20, T18, T19,

T20, R18, P17,

P19, P20

I/O

TS

24 mA

I/O

TS

24 mA

I/O

TS

24 mA

LA[0:31]

D20

I

LCLK

N18, N19, N20,

M17, M18, M19,

M20, L19, L18,

L20, K20, K19,

K18, K17, J20,

J19, J18, J17,

H20, H19, H18,

G20, G19, F20,

G18, F19, E20,

G17, F18, E19,

E18, D19

I/O

TS

24 mA

I/O

TS

24 mA

I/O

TS

24 mA

LD[0:31]

B15

I

LINTi#

- 25 -

9656-SIL-DC1-P0-.96

12/19/2002

Table 20. PCI 9656AD/PCI 9656BA M Mode Pin Types

Symbol

LINTo#

Pin Number

Blue Book r.90b Pin Type

True AD Pin Type

True BA Pin Type

O

OC

24 mA

A15

OC

24 mA

OC

24 mA

If (HOSTEN# asserted)

I

I/O

TP

A16

LRESET#

else

24 mA

O

TP

24 mA

O

TP

24 mA

If ((DMAMODE0[14]=1)

or

(DMAMODE1[14]=1))

I

MDREQ#

O

TS

24 mA

If ((DMAMODE0[14]=1)

or

(DMAMODE1[14]=1))

else

MDREQ#

DMPAF

EOT#

O

TP

24 mA

I

DMPAF

O

TS

D14

else

Note for 2nd case:

If ((HOSTEN# not asserted & RST#

24 mA

O

TP

24 mA

asserted

EOT#

I

or

(HOSTEN# asserted & LRESET#

asserted)

or

(BD_SEL# not asserted))

Pin goes Hi-Z.

I

B10

R19

I

PMEREQ#

RD/WR#

I/O

TS

I/O

TS

I/O

TS

24 mA

O

OC

24 mA

I/O

O

DTS

24 mA

I/O

O

DTS

24 mA

I/O

A17

E17

RETRY#

TA#

DTS

24 mA

I/O

OC

24 mA

I/O

OC

24 mA

I/O

OC

24 mA

D16

TEA#

I/O

TS

24 mA

I/O

TS

24 mA

I/O

TS

24 mA

C17

TS#

I/O

TS

24 mA

I/O

TS

24 mA

I/O

TS

24 mA

R20, P18

TSIZ[0:1]

USERi

I

USERi

B14

I

LLOCKi#

I

O

TP

O

TP

24 mA

USERo

O

Note:

TS

If ((HOSTEN# not asserted & RST#

USERo

C14

24 mA

asserted)

LLOCKo#

or

(HOSTEN# asserted & LRESET#

asserted)

or

(HOSTEN# asserted & LRESET#

asserted)

LLOCKo#

O

or

(BD_SEL# not asserted))

Pin goes Hi-Z.

(BD_SEL# not asserted))

Pin goes Hi-Z.

- 26 -

9656-SIL-DC1-P0-.96

12/19/2002

Table 21. PCI 9656AD/PCI 9656BA JTAG Pin Types

Symbol Pin Number Blue Book r.90b Pin TypeTrue AD Pin TypeTrue BA Pin Type

A8

I

TCK

A7

I

O

I

O

I

O

TDI

C8

TDO

TS

PCI

I

TS

PCI

I

TS

PCI

I

B8

TMS

D9

I

TRST#

Table 22. PCI 9656AD/PCI 9656BA Hot Swap Pin Types

Symbol Pin Number Blue Book r.90b Pin TypeTrue AD Pin TypeTrue BA Pin Type

U12

C9

Y14

I

64EN#

BD_SEL#

CPCISW

O

OC

PCI

O

TP

O

OC

PCI

O

OC

PCI

O

Y13

V13

ENUM#

OC

LEDon#

24 mA

Table 23. PCI 9656AD/PCI 9656BA System Pin Types

Symbol

Pin Number Blue Book r.90b Pin TypeTrue AD Pin TypeTrue BA Pin Type

A10

A19, A20

C15

I

IDDQEN#

MODE[1:0]

HOSTEN#

Table 24. PCI 9656AD/PCI 9656BA EEPROM Pin Types

Symbol

EECS

Pin Number Blue Book r.90b Pin Type

True AD Pin Type

True BA Pin Type

O

TP

O

TP

O

12 mA

TP

12 mA

B12

B11

A12

Note:

If (BD_SEL# not asserted)If (BD_SEL# not asserted)

Pin goes Hi-Z.

I/O

TS

I/O

TS

I/O

TP

12 mA

EEDI/EEDO

Note:

If (CNTRL[31]=1)

Pin goes Hi-Z.

Note:

If (CNTRL[31]=1)

Pin goes Hi-Z.

O

TP

O

TP

O

TP

12 mA

EESK

12 mA

Note:

If (BD_SEL# not asserted)If (BD_SEL# not asserted)

Pin goes Hi-Z. Pin goes Hi-Z.

- 27 -

9656-SIL-DC1-P0-.96

12/19/2002

Table 25. PCI 9656AD/PCI 9656BA Power & Ground Pin Types

Symbol

2.5V_AUX

Pin Number Blue Book r.90b Pin TypeTrue AD Pin Type True BA Pin Type

D10

I

C10

A11

I

Card_V_AUX

PRESENT_DET

W3

I

V_BB

Note:

Changes from V_BB

to V_SS

.

C11, C19, E2,

P3, U9, U19

I

V_CORE

V_DDA

V_IO

I

W2

Note:

Changes from V_DDA

to V_RING

.

A9, F1, V2,

W13

I

A1, D4, D6,

D8, D11, D13,

D15, D17, F4,

F17, H4, H17,

K4, L17, N4,

N17, R4, R17,

U4, U6, U8,

U10, U13, U15,

U17

I

V_RING

J9-J12,

K9-K12,

L9-L12,

M9-M12

I

V_SS

I

Y1

V_SSA

Note:

Changes from V_SSA

to V_SS

.

- 28 -

9656-SIL-DC1-P0-.96


型号：	PLX9656
厂家：	ETC
描述：	I/O Accelerator\|PCI9656 Data Book Corrections I / O加速器\| PCI9656数据手册更正\n PC
文件：	总28页 (文件大小：164K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

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