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Released
PM4328
TM
TECT3
TECT3
High Density T1/E1 Framer with
Integrated M13 Multiplexer
Production Release Errata
Proprietary and Confidential
Released
Issue 2: July, 2002
Proprietary and Confidential to PMC-Sierra, Inc., and for its Customers’ Internal Use
Document ID: PMC-PMC-2011799, Issue 2
1
PM4328 TECT3 Production Release Errata
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Legal Information
Copyright
© 2002 PMC-Sierra, Inc.
The information is proprietary and confidential to PMC-Sierra, Inc., and for its customers’
internal use. In any event, you cannot reproduce any part of this document, in any form, without
the express written consent of PMC-Sierra, Inc.
PMC-2011799 (R2)
Disclaimer
None of the information contained in this document constitutes an express or implied warranty by
PMC-Sierra, Inc. as to the sufficiency, fitness or suitability for a particular purpose of any such
information or the fitness, or suitability for a particular purpose, merchantability, performance,
compatibility with other parts or systems, of any of the products of PMC-Sierra, Inc., or any
portion thereof, referred to in this document. PMC-Sierra, Inc. expressly disclaims all
representations and warranties of any kind regarding the contents or use of the information,
including, but not limited to, express and implied warranties of accuracy, completeness,
merchantability, fitness for a particular use, or non-infringement.
In no event will PMC-Sierra, Inc. be liable for any direct, indirect, special, incidental or
consequential damages, including, but not limited to, lost profits, lost business or lost data
resulting from any use of or reliance upon the information, whether or not PMC-Sierra, Inc. has
been advised of the possibility of such damage.
Trademarks
SBI, TECT3, TECT3, and PMC-Sierra are trademarks of PMC-Sierra, Inc. Other product and
company names mentioned herein may be the trademarks of their respective owners.
Patents
The technology discussed may be protected by one or more Patents. Relevant patent applications
and other patents may also exist.
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Contacting PMC-Sierra
PMC-Sierra
8555 Baxter Place Burnaby, BC
Canada V5A 4V7
Tel: (604) 415-6000
Fax: (604) 415-6200
Document Information: document@pmc-sierra.com
Corporate Information: info@pmc-sierra.com
Technical Support: apps@pmc-sierra.com
Web Site: http://www.pmc-sierra.com
Revision History
Issue No. Issue Date
Details of Change
2
July 2002
Added errata items 2.2, 3.2 to 3.14. Change bars relative to
Issue 1 of TECT3 errata document.
1
August 2001
Document created.
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Table of Contents
Legal Information ................................................................................................................ 2
Contacting PMC-Sierra ....................................................................................................... 3
Table of Contents ................................................................................................................ 4
1
Introduction.................................................................................................................. 6
1.1 Device Identification............................................................................................ 6
1.2 References ......................................................................................................... 6
Device Functional Deficiency List ............................................................................... 7
2.1 Use of HDLC Controller in E1 Mode................................................................... 7
2
2.2 DS3 PRGD block limits useable repeating patterns in unchannelized M23 mode
............................................................................................................................ 7
2.2.1 Description............................................................................................. 7
2.2.2 Workaround............................................................................................ 8
2.2.3 Performance with Workaround .............................................................. 9
2.2.4 Performance without Workaround ......................................................... 9
2.3 Automatic SBI tributary reset not available when mixing sync and async tributaries per
SPE..................................................................................................................... 9
2.3.1 Description............................................................................................. 9
2.3.2 Workaround.......................................................................................... 10
2.3.3 Performance with Workaround ............................................................ 10
2.3.4 Performance without Workaround ....................................................... 10
Documentation Deficiency List.................................................................................. 11
3.1 SBI Initialization Sequencing............................................................................ 11
3.1.1 Initialization of the SBI Extract Threshold............................................ 11
3.1.2 SBI Initialization Sequence .................................................................. 12
3.2 A11 is incorrectly included as “No Connect” pin............................................... 12
3.3 AIS Insertion in DS3 Diagnostic Loopback....................................................... 13
3.4 E1 Multiframe pulse configurations .................................................................. 13
3.5 CENT bit description of TJAT and RJAT Configuration registers are incorrect 13
3.6 M13 TJAT and RJAT settings incorrect in Programmer’s Guide ...................... 14
3.7 IILPU max spec limit has been revised ............................................................ 14
3.8 Egress mode settings incorrect for Clock Slave: Clear Channel...................... 14
3.9 Behavior of FIFO status handling needs clarification....................................... 15
3.10 INSBI automatic depth check logic behavior clarification................................. 15
3.11 Technical Overview clarifications...................................................................... 16
3
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3.12 RJAT SYNC bit description in EXSBI CLK_MODE field clarified ..................... 16
3.13 VT/TU mapping modes not supported in TECT3 ............................................. 16
3.14 Duplication of Ground Pin Descriptions............................................................ 17
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1
Introduction
In this document:
Sꢀ Section 2 lists the known functional errata for the Production Released PM4328 TECT3.
Sꢀ Section 3 lists documentation errors found in the following TECT3 documents:
Sꢀ Issue 1 of the Data Sheet (PMC-2011596)
Sꢀ Issue 1 of the PM4328 TECT3 Register Description (PMC-2011623)
Sꢀ Issue 4 of the TEMUX/TEMAP/TECT3 Programmer’s Guide (PMC-1991268)
Sꢀ Issue 1 of the PM4328 TECT3 Technical Overview (PMC-2011775)
1.1
Device Identification
The information contained in Section 2 relates to the Production Released version of the PM2331
TECT3 device only. The device revision code is marked at the end of the Wafer Batch Code on
the face of the device.
Ball A1
PMC Logo
Index Marks
TEMUX Logo
TM
T
ECT3
Part Number
PM4328-PI
Wafer Batch Code
C
A
Country of
Assembler
Myyww
Philippines
Assembly Date Code
1.2
References
Sꢀ Issue 1 of the PM4328 TECT3 Data Sheet (PMC-2011596).
Sꢀ Issue 1 of the PM4328 TECT3 Register Description (PMC-2011623)
Sꢀ Issue 4 of the TEMUX/TEMAP/TECT3 Programmer’s Guide (PMC-1991268)
Sꢀ Issue 1 of the PM4328 TECT3 Technical Overview (PMC-2011775)
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2
Device Functional Deficiency List
This section lists the known functional deficiencies for the Production Released version of the
TECT3 as of the publication date of this document.
Please report any functional deficiencies not covered in this errata to PMC-Sierra.
2.1
Use of HDLC Controller in E1 Mode
When using the internal HDLC controllers in E1 mode there are some restrictions to be aware of:
Sꢀ If data is inserted into a timeslot from the internal HDLC controller and the previous timeslot
has an idle code byte inserted from the TPSC, the last two bits of the idle code can be
corrupted. This means that if timeslot 4 has data inserted from the HDLC controller, and an
idle code has been inserted in timeslot 3 from the TPSC, the least significant two bits of
timeslot 3 can be corrupted. It is recommended that HDLC traffic be inserted from the
backplane rather than the internal controller if idle codes are being transmitted in the
preceding timeslot.
Sꢀ If data is inserted into timeslot 1 from the internal HDLC controller, the least significant bit in
timeslot 0 for NFAS frames only (i.e., Sa8) can be corrupted if configured to come from the
backplane. The National Use Bits codeword, however, operates correctly on Sa8 if enabled.
It is recommended that timeslot 1 not be used for HDLC traffic inserted from the internal
controller.
Sꢀ In normal operation, if a timeslot is configured for both HDLC transmission and idle code
insertion, HDLC is supposed to be transmitted and the idle code ignored. It is possible in
TECT3 for the last two bits of the HDLC data to be corrupted. To get around this, simply
disable idle code insertion for that timeslot when HDLC data is being transmitted.
Sꢀ Inserting HDLC data into the National bits Sa8, Sa7, Sa6, or Sa5 can cause the neighboring
more significant bit to be corrupted. For example, if HDLC is inserted into Sa7, then Sa6 can
be corrupted, but only if Sa6 is inserted from the backplane. The National bits are always
inserted error-free when they are generated via the National Bits Codeword register of the E1-
TRAN block.
Sꢀ Inserting HDLC data into the Si bit in TS0 (i.e., the international bit) can cause the least
significant two bits of an IDLE code in TS31 to be corrupted.
2.2
DS3 PRGD block limits useable repeating patterns in
unchannelized M23 mode
2.2.1
Description
As described in the TECT3 Data Sheet, Section 12.1: DS3 Framing Format, the TECT3 device
provides support for both the C-bit parity and M23 DS3 framing formats. The DS3 frame format
is shown in Figure 27 of the Data Sheet (copied below):
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84 bits
84 bits
84 bits
84 bits
84 bits
84 bits
84 bits
84 bits
X
X
P
P
M
M
M
F
F
F
F
F
F
F
C
C
C
C
C
C
C
F
F
F
F
F
F
F
C
C
C
C
C
C
C
F
F
F
F
F
F
F
C
C
C
C
C
C
C
F
F
F
F
F
F
F
M-subframe 1
M-subframe 2
M-subframe 3
M-subframe 4
M-subframe 5
M-subframe 6
M-subframe 7
1
2
1
2
1
2
3
1
1
1
1
1
1
1
1
1
1
1
1
1
1
2
2
2
2
2
2
2
2
2
2
2
2
2
2
3
3
3
3
3
3
3
3
3
3
3
3
3
3
4
4
4
4
4
4
4
The C-bit Parity ID bit is the first C-bit (C1) of the M-subframe 1. In the receive direction, the
CBITV register bit in the DS3 FRMR Status register is used to report the state of this C-bit Parity
ID. If the ID bit is 1, the DS3 frame received is assumed to be C-bit parity. If the C-bit Parity ID
is 0 or toggling, the DS3 signal stream received is assumed to be M23.
Unchannelized repeating patterns are regenerated each time the PRGD Pattern Insertion Register
#4 is written to (Register 103BH). In M23 mode, the DS3 PRGD always sets all C-bits to the
same value, a value based on the last transmitted bit. For an all-1’s pattern, all C-bits will be 1.
Similarly for an all-0’s pattern, all C-bits will be 0. For an alternating 10101010 pattern for
instance, there is a 50/50 chance of all C-bits being 1.
An issue arises when attempting to generate an unchannelized all-1’s M23 pattern. Recall that an
M23 signal stream would require the C-bit Parity ID to be 0 or toggling. However, the DS3
PRGD will set all C-bits (and hence the C-Bit Parity ID) to 1 when generating an all-1’s pattern.
The receiver will therefore interpret the DS3 frame to be C-bit parity rather than the correct M23
format. As a result, a frame mismatch would be declared if an all-1’s is generated in M23 mode.
Similarly, an alternating 10101010 M23 pattern has a 50/50 chance of being misinterpreted as a
C-bit parity DS3 stream while in unchannelized DS3. For patterns containing one or more 0’s,
the occurrence of this problem is related to the 1’s density of the pattern. An example is a 31-
ones, 1-zero pattern in M23 mode. On average, this pattern will work without frame mismatch
one every 32 tries, as there is a 1/32 chance of C-bit parity ID being 0.
In C-bit parity mode, there are no problems passing all-1’s because the ID bit is always
overwritten with a 1.
2.2.2
Workaround
There is no way to generate an all-1s pattern while in unchannelized M23 mode without seeing
frame mismatch errors. Because the DS3 PRGD block limitation applies to unchannelized DS3
only, utilizing C-bit parity mode (instead of M23) allows the generation of an all-1’s pattern.
In the event that unchannelized M23 mode must be used, several other patterns can be used
without declaring DS3 frame mismatch. For patterns containing one or more 0’s, the occurrence
of this mistaken M23 signal for C-bit parity is related to the 1’s density of the pattern.
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The following algorithm can be used to to generate patterns other than all-1’s in M23 mode:
Sꢀ Write to PRGD Pattern Insertion Register #4 (Register 103BH) to generate unchannelized
repeating patterns.
Sꢀ At the receiver, check the framer for a DS3 frame mismatch. If using a loopback or
another TECT3, the DS3 framing circuitry of the TECT3 reports the frame mismatch
using DS3 FRMR status bit CBITV.
Sꢀ If frame mismatch has occurred, repeat. Else, transmitted pattern is correct.
An all-0’s pattern can always be transmitted correctly while the TECT3 is in unchannelized M23
mode.
2.2.3
2.2.4
Performance with Workaround
There is no workaround to implement the generation of an all-1s pattern while in unchannelized
M23 mode. Using C-bit parity DS3 framing format is recommended to generate all-1’s.
The TECT3 device will operate normally in DS3 testing scenarios with the suggested workaround
in place for M23 mode.
Performance without Workaround
DS3 Frame Mismatch will be declared when attempting to generate all-1’s pattern in
unchannelized M23 mode.
2.3
Automatic SBI tributary reset not available when mixing sync
and async tributaries per SPE
2.3.1
Description
In the INSBI Control Register 1720H, the DC_RSTEN bit controls the INSBI automatic depth
check logic, whereby the link will automatically reset upon detection of a depth check error, i.e.
INSBI underrun or overflow. When the DC_RSTEN bit is set to 1, the automatic reset is enabled.
If DC_RSTEN is set to 0, the link must be manually reset upon depth interrupt.
However, there is a limitation to this automatic depth check logic. In Register 1726H: INSBI
Tributary Control Indirect Access Data, the SYNCH_TRIB bit controls whether tributaries
operate in synchronous mode on the SBI DROP bus. However, when there is a mix of
synchronous and non-synchronous tributaries, i.e. SYNCH_TRIB = 1 for some and
SYNCH_TRIB=0 for others, the INSBI automatic depth check logic does not operate properly.
Hence, underflows or overflows in the SBI FIFOs are not serviced with a link reset. Data
corruption may occur as result.
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As stated in Errata item 3.10, DC_RSTEN should not be set to 1 when INSBI SYNCH_TRIB bit
(Register 1726H: INSBI Tributary Control Indirect Access Data) settings are mixed between 0
and 1, indicating only some tributaries are synchronous to the SBI bus”.
2.3.2
Workaround
When underruns or overruns are detected via the interrupt indications of Registers 1721H or
1722H respectively, the tributary must be manually reset to clear the error condition.
To reset a given tributary, an indirect write access must be performed to Register 1726: Tributary
Control RAM Indirect Data Register for the errored tributary, with the last value written to the
register. This will write a logic 1 to the ENBL bit that will trigger a reset of that tributary.
2.3.3
2.3.4
Performance with Workaround
Device operates normally after a manual reset of the errored tributary
Performance without Workaround
Without manually resetting the tributary, it may never exit the errored state and data corruption
will result.
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3
Documentation Deficiency List
This section is a notification of additional information to Issue 1 of the TECT3 Datasheet, PMC-
2011596, dated August 2001. The following information was full and complete as of the
publication date of this document.
Please report any documentation deficiencies not covered in this errata to PMC-Sierra.
3.1
SBI Initialization Sequencing
When using TECT3 with SBI over layer 2 devices like the FREEDM-84, you should take care in
the initialization of both devices to make sure they initialize in the proper states. When using the
FREEDM-84 device, please use the recommended initialization sequence below.
3.1.1
Initialization of the SBI Extract Threshold
The SBI Extract Depth must be programmed correctly. In the FREEDM-84, Register 0x5EC and
0x5E8 sets the fill levels of the SBI FIFO before data is read out for E1 and T1 modes
respectively. Depending on the mode, E1 or T1, the corresponding register (0x5EC or 0x5E8)
should be programmed to 00000078H.
Register 0x5EC : SBI EXTRACT MIN_THR and MAX_THR for E1
Bit
Type
Function
Default
Bit 31 to 8 R/W
Reserved
000000H
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
MIN_THR_E1[3]
MIN_THR_E1[2]
MIN_THR_E1[1]
MIN_THR_E1[0]
MAX_THR_E1[3]
MAX_THR_E1[2]
MAX_THR_E1[1]
MAX_THR_E1[0]
0
0
1
0
1
1
0
1
MIN_THR_E1[3:0]:
The Minimum Threshold for E1 bits (MIN_THR_E1[3:0]) specify the FIFO depth below
which a slow down request is made from the EXSBI to the PISO block.
MAX_THR_E1[3:0]:
The Maximum Threshold for E1 bits (MAX_THR_E1[3:0]) specify the FIFO depth which
when exceeded will cause a speed up request from the EXSBI to the PISO block to be made.
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Register 0x5E8 : SBI EXTRACT MIN_THR and MAX_THR for T1
Bit
Type
Function
Default
Bit 31 to 8 R/W
Reserved
000000H
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
MIN_THR_T1[3]
MIN_THR_T1[2]
MIN_THR_T1[1]
MIN_THR_T1[0]
MAX_THR_T1[3]
MAX_THR_T1[2]
MAX_THR_T1[1]
MAX_THR_T1[0]
0
0
1
0
1
1
0
1
MIN_THR_T1[3:0]:
The Minimum Threshold for T1 bits (MIN_THR_T1[3:0]) specify the FIFO depth below
which a slow down request is made from the EXSBI to the PISO block.
MAX_THR_T1[3:0]:
The Maximum Threshold for T1 bits (MAX_THR_T1[3:0]) specify the FIFO depth which
when exceeded will cause a speed up request from the EXSBI to the PISO block to be made.
3.1.2
SBI Initialization Sequence
When initially configuring the Egress path of the TECT3 and layer 2 device (like the FREEDM-
84) combination, the INSBI of the layer 2 device should be the last portion of the tributary path to
be enabled. If the layer 2 device INSBI tributary is enabled before the TECT3 EXSBI tributary,
there is chance that the layer 2 device INSBI could generate inadvertent errors (i.e. packet errors).
Enabling the layer 2 device INSBI after the TECT3 EXSBI ensures correct operation.
3.2
A11 is incorrectly included as “No Connect” pin
In the TECT3 pin description, Miscellaneous section, pin A11 is incorrectly listed as a “No
Connect” pin. A11 is properly listed elsewhere in the pin description tables, one of several pins
shared between Ingress Data ID[20] and System Drop Bus SDDATA[3].
The pin “AA11” should instead be listed as “No Connect”.
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3.3
3.4
AIS Insertion in DS3 Diagnostic Loopback
In the TECT3 datasheet, Figure 38: DS3 Diagnostic Loopback Diagram states that AIS can
optionally be inserted into the transmit datapath when a DS3 is in diagnostic loopback. This is
incorrect. AIS cannot be inserted in the transmit path when in DS3 diagnostic loopback mode.
E1 Multiframe pulse configurations
The IMFPCFG[1:0] bits in Register 005H+80H*N (T1/E1 Ingress Serial Interface Mode Select)
select whether IFP[x] (ingress frame pulse) indicates E1 CRC, signaling or both CRC and
signaling multiframe boundaries. These IFP[x] modes are listed in Table 3 in the TECT3 Register
Description as follows:
Table 3:
Ingress Frame Alignment Configuration
IMFPCFG[1] IMFPCFG[0] Operation
0
0
1
1
0
1
0
1
Both E1 CRC and Signaling multiframe
E1 CRC multiframe
E1 Signaling multiframe
Both E1 CRC and Signaling multiframe
However, these bits should be set to signaling MF pulses in E1 mode of the TECT3 as follows:
1. Basic framing without CAS: must use signaling multiframe pulse, IMFPCFG[1:0]=10
2. CRC-4 multiframe without CAS:
a. Signaling multiframe pulse IMFPCFG[1:0]=10, or
b. CRC multiframe pulse IMFPCFG[1:0]=01
3. CAS modes: Basic Framing with CAS or CRC-4 multiframe with CAS:
a. Signaling multiframe pulse IMFPCFG[1:0]=10
3.5
CENT bit description of TJAT and RJAT Configuration registers
are incorrect
The following text should be ignored from the CENT bit description of the T1/E1 TJAT and
RJAT Configuration Registers, Register 0017H + 80H*N and Register 0013H + 80H*N
respectively:
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“It is recommended to set this bit to 1”.
For the recommended setting of the TJAT and RJAT Configuration Register bits, refer to Errata
item 3.5 below for the DS3 M13 operational modes.
3.6
M13 TJAT and RJAT settings incorrect in Programmer’s Guide
The TJAT and RJAT Configuration Register recommendations are incorrect in the TECT3
Programmer’s Guide for channelized DS3 applications.
Sections 6.2.1 (T1) and 7.1.1 (E1) state the TJAT and RJAT manual centering procedures setting
Register 0017H + 80H*N TJAT Configuration and Register 0013H + 80H*N RJAT Configuration
to values of 0x20.
Neither centering procedure should be followed for channelized DS3 T1 or E1 applications.
Rather, these two registers should be programmed with values of 0x31 upon initialization for all
modes. The only exception is where PM73122 AAL1gator-32 is connected to the TECT3’s
system side SBI bus and operating in SRTS mode. In this particular application, the RJAT
Configuration Register 0013H + 80H*N must be set to 0x23.
3.7
3.8
IILPU max spec limit has been revised
In Table 29 of the TECT3 datasheet: D.C. Characteristics, the input low current parameter, IILPU
maximum has been changed from +100ꢁA to +150ꢁA.
Egress mode settings incorrect for Clock Slave: Clear Channel
In Register 006H+80H*N: T1/E1 Egress Serial Interface Mode Select, the egress clock mode,
EMODE, bit determines which serial interface mode is being used for this tributary.
In Table 4 of TECT3 Register Description: Egress Serial Interface Mode Selection, the Clock
Slave: Clear Channel operation should be configured by EMODE[2:0] = 010, not 01X.
The correct table should read as follows:
EMODE[2] EMODE[1] EMODE[0] Operation
1
1
0
0
1
0
X
X
1
Clock Master: NxChannel
Clock Master: Clear Channel
Clock Slave: EFP Enabled
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EMODE[2] EMODE[1] EMODE[0] Operation
0
0
0
1
0
0
Clock Slave: External Signaling
Clock Slave: Clear Channel
3.9
Behavior of FIFO status handling needs clarification
In the extract and insert SBI (EXSBI, INSBI) FIFOs, the TECT3 has a priority mechanism for
reporting underruns and overruns on certain tributaries. In general, lower-numbered tributaries
can seemingly block the reporting of FIFO events on higher-numbered tributaries.
Consider an example where all tributaries underrun continuously. After reading status register
errors for the first few tributaries, it may be the case that new underrun events are registered. In
this case, errors will appear again for lower number tributaries before errors for higher number
tributaries can be read.
In general, errors for a particular tributary cannot be read from the status register if an error on
any lower numbered tributary has not been read.
This behaviour will only become evident in the rare event that several tributaries are
simultaneously exhibiting FIFO errors. Note that this priority mechanism does not inhibit normal
behavior of the TECT3 device.
3.10 INSBI automatic depth check logic behavior clarification
The following clarification needs to be made regarding the behavior of the INSBI automatic
depth check logic:
Append the following statement to the DC_RSTEN bit description found in Register 1720H:
INSBI Control and SYNCH_TRIB bit description in Register 1726H: INSBI Tributary Control
Indirect Access Data:
“The INSBI automatic depth check logic does not support a mix of synchronous and non-
synchronous tributaries, i.e. DC_RSTEN should not be set to 1 when INSBI
SYNCH_TRIB bit (Register 1726H: INSBI Tributary Control Indirect Access Data)
settings are mixed between 0 and 1, indicating only some tributaries are synchronous to
the SBI bus”.
Proprietary and Confidential to PMC-Sierra, Inc., and for its Customers’ Internal Use
Document ID: PMC-PMC-2011799, Issue 2
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PM4328 TECT3 Production Release Errata
Released
3.11 Technical Overview clarifications
In Sections 4.3 and 4.4 of the TECT3 Technical Overview, the “DS3 Add Drop Multiplexer”
examples should be re-labelled as “DS3 Terminal Multiplexer” applications.
3.12 RJAT SYNC bit description in EXSBI CLK_MODE field clarified
In Register 1716H: EXSBI Tributary Control Indirect Access Data, the CLK_MODE[1:0] bit
bndescription includes the following statement:
"When using the phase field of the Link Rate octet, the SYNC bit in the RJAT
configuration register needs to be set."
For clarification, the TECT3 RJAT is not usually connected to the TECT3 EXSBI. Hence, this
comment about the “phase field” is more relevant to the device that uses this information,
PM73122 AAL1gator-32’s EXSBI, rather than TECT3.
3.13 VT/TU mapping modes not supported in TECT3
In the TECT3 datasheet, Section 12.12: Serial Clock and Data Format, the following paragraph
should be removed:
"In normal E1 mode, the first 21 sets of clock and data pins are used in each direction.
The clock and data pins numbered between 22 and 28 are not defined, as the 22 nd
through 28 th framer blocks are not used in this mode."
In Section 8: Pin Description, T1 and E1 System Side Serial Clock and Data Interface, the
following statement should also be removed:
"In E1 mode only ICLK[1:21] and ISIG[1:21] are used."
The pin description for ICLK and ISIG should also be updated with the following:
"In ITU-T G.747 multiplexed E1 mode, every fourth set of clock and data pins are not
used in each direction. (i.e. Pins 1-3, 5-7, 9-11, 13-15, 17-19, 21-23, 25-27 are defined
while pins 4, 8, 12, 16, 20, 24, and 28 are not defined.)"
The above sections infer that E1s can be VT/TU mapped into SONET/SDH, however not
supported by the TECT3 device. Other than G.747 (E1 in DS3), there is no other way to pass an
E1 through the TECT3.
Proprietary and Confidential to PMC-Sierra, Inc., and for its Customers’ Internal Use
Document ID: PMC-PMC-2011799, Issue 2
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PM4328 TECT3 Production Release Errata
Released
3.14 Duplication of Ground Pin Descriptions
The description of ground pins N3, Y12, L20 and B12 has been duplicated in two rows of the pin
description section, pins VSSQ[1:4] and VSS3.3[19:22]. These pins should only be described in
the VSS3.3 row. The VSSQ row should be eliminated. In any event these pins should be
connected to GND as described.
Proprietary and Confidential to PMC-Sierra, Inc., and for its Customers’ Internal Use
Document ID: PMC-PMC-2011799, Issue 2
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PM4328 TECT3 Production Release Errata
Released
Notes
Proprietary and Confidential to PMC-Sierra, Inc., and for its Customers’ Internal Use
Document ID: PMC-PMC-2011799, Issue 2
18
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