PQ2FADSZURM [ETC]
MPC82xx Family Application Development System Users Manual ; MPC82XX应用开发系统用户手册\n
| 型号： | PQ2FADSZURM |
| 厂家： | 
ETC |
| 描述： | MPC82xx Family Application Development System Users Manual
|
| 文件： | 总224页 (文件大小：3178K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Freescale Semiconductor, Inc.
User’s Manual
PQ2FADS-ZU-UM
Revision 0.0
April 8, 2003
PQ2FADS-ZU User’s
Manual
PQ2FADS-ZU
User’s Manual
© Motorola, Inc., 2003
For More Information On This Product,
Go to: www.freescale.com
Freescale Semiconductor, Inc.
Important Notice to Users
While every effort has been made to ensure the accuracy of all information in
this document, Motorola assumes no liability to any party for any loss or
damage caused by errors or omissions or by statements of any kind in this
document, its updates, supplements, or special editions, whether such errors are
omissions or statements resulting from negligence, accident, or any other cause.
Motorola further assumes no liability arising out of the application or use of any
information, product, or system described herein: nor any liability for incidental
or consequential damages arising from the use of this document. Motorola
disclaims all warranties regarding the information contained herein, whether
expressed, implied, or statutory, including implied warranties of
merchantability or fitness for a particular purpose. Motorola makes no
representation that the interconnection of products in the manner described
herein will not infringe on existing or future patent rights, nor do the
descriptions contained herein imply the granting or license to make, use or sell
equipment constructed in accordance with this description.
Trademarks
This document includes these trademarks:
Motorola and the Motorola logo are registered trademarks
of Motorola, Inc.
Motorola, Inc., is an Equal Opportunity / Affirmative Action Employer.
For an electronic copy of this book, visit Motorola’s web site at http://e-www.motorola.com/
© Motorola, Inc., 2003; All Rights Reserved
PQ2FADS-ZU - Revision 0.0
2
User’s Manual
MOTOROLA
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Table of Contents
Table of Contents
Section 1
General Information
1.1
1.2
1.3
1.4
1.5
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Definitions, Acronyms, and Abbreviations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2
Related Documentation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2
Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
PQ2FADS-ZU Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
Section 2
Hardware Preparation and Installation
2.1
2.2
2.3
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Unpacking Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Hardware Preparation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
2.3.1 Setting VDDL Level Range - P24 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
2.3.2 Setting VDDL Supply Voltage Level . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
2.3.3 Setting MODCK(1:3) for PLLs Multiplication Factor - SW6 (#6 - #8) . . . . . . . 10
2.3.4 Setting Hard - Reset Configuration Source - JP7 . . . . . . . . . . . . . . . . . . . . . . . . 11
2.3.5 Setting Boot Source . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
2.3.6 Setting MODCKH(0:3) - for PLLs Multiplication Factors . . . . . . . . . . . . . . . . . 13
2.3.7 Setting PCI_MODCK - for PCI Bus Clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
2.3.8 Setting PCI_ARBITER - for PCI Mode Enabled . . . . . . . . . . . . . . . . . . . . . . . . 13
2.3.9 Setting PCI_DLL - for PCI Mode Enabled . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
2.3.10 Setting Local Bus functionality - SDRAM or PCI . . . . . . . . . . . . . . . . . . . . . . . 13
2.3.11 60x Bus Parity Support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
2.3.12 Clock-In Source selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
2.3.13 FCC2 Ethernet Port mode - MII/RMII . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
2.3.14 FCC3 Ethernet Port mode - MII/RMII . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
2.3.15 USB Speed selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
2.3.16 USB Mode selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
2.3.17 COP/JTAG Connection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
2.3.18 Power On/Off Switch . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Installation Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
2.4.1 Host Controlled Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
2.4.2 Stand Alone Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
2.4.3 COP/JTAG Connector - P15 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
2.4.4 Terminal to PQ2FADS-ZU RS-232 Connection . . . . . . . . . . . . . . . . . . . . . . . . . 18
2.4.5 10/100-Base-T Ethernet Ports Connection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
2.4
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Table of Contents
2.4.6 Memory Installation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
2.4.6.1 Flash Memory SIMM Installation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Section 3
Operating Instructions
3.1
3.2
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Controls and Indicators . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
3.2.1 Power-On RESET Switch - SW1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
3.2.2 ABORT Switch - SW2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
3.2.3 SOFT RESET Switch - SW3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
3.2.4 HARD RESET - Switches - SW2 & SW3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
3.2.5 SW5 - Reset Configuration Switch . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
3.2.6 SW4 - Software Options Switch . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
3.2.7 P24 - VDDL Voltage Level Range Selection . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
3.2.8 JP13 - IDDL Measurement . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
3.2.9 JP5 - Thermal Sense Connector . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
3.2.10 JP12 - IDDH Measurement . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
3.2.11 JP14 - VPP Source Selector . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
3.2.12 GND Bridges . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
3.2.13 Power O.K. Indicator - LD1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
3.2.14 12V Indicator - LD2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
3.2.15 UTOPIA 16 Bit Indicator - LD3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
3.2.16 UTOPIA Multi PHY Indicator - LD4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
3.2.17 5V Indicator - LD5 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
3.2.18 3.3V Indicator - LD6 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
3.2.19 USB Power Indicator - LD7 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
3.2.20 -12V Indicator - LD8 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
3.2.21 RUN Indicator - LD9 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
3.2.22 ATM ON - LD10 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
3.2.23 Fast Ethernet Port 2 Enabled - LD11 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
3.2.24 Fast Ethernet Port 1 Enabled - LD12 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
3.2.25 RS232 Port 1 ON - LD13 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
3.2.26 Fast Ethernet Port 1 Full Duplex Indicator - LD14 . . . . . . . . . . . . . . . . . . . . . . . 25
3.2.27 RS232 Port 2 ON - LD15 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
3.2.28 Fast Ethernet Port 1 100Base-Tx Indicator - LD16 . . . . . . . . . . . . . . . . . . . . . . . 25
3.2.29 Ethernet Port 1 Tx/Rx Indicator - LD17 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
3.2.30 General Purpose Led 2 Indicator - LD18 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
3.2.31 Ethernet Port 1 LINK Indicator - LD19 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
3.2.32 Fast Ethernet Port 2 Full Duplex Indicator - LD20 . . . . . . . . . . . . . . . . . . . . . . . 25
3.2.33 General Purpose Led 1 Indicator - LD21 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
3.2.34 Fast Ethernet Port 2 100Base-Tx Indicator - LD22 . . . . . . . . . . . . . . . . . . . . . . . 26
3.2.35 USB Enabled Indicator - LD23 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
3.2.36 Ethernet Port 2 LINK Indicator - LD24 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
3.2.37 Ethernet Port 2 Tx/Rx Indicator - LD25 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
II
PQ2FADS-ZU User Manual
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Table of Contents
3.2.38 VDDL Indication - LD26 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
3.2.39 Parallel Port connection - LD27 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
3.2.40 External Debugger Connection Indicator - LD28 . . . . . . . . . . . . . . . . . . . . . . . . 26
Section 4
Functional Description
4.1
Reset & Reset - Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
4.1.1 Power - On ResetPQ2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
4.1.1.1 Power - On Reset Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
4.1.2 Hard Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
4.1.2.1 COP/JTAG Port Hard - Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
4.1.2.2 Manual Hard Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
4.1.2.3 Internal Sources Hard - Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
4.1.2.4 Hard Reset Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
4.1.3 Soft Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
4.1.3.1 COP/JTAG Port Soft - Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
4.1.3.2 Manual Soft Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
4.1.3.3 Internal Sources Soft - Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
4.1.4 PCI Bus Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
Local Interrupter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
4.2.1 ABORT Interrupt . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
4.2.2 ATM UNI Interrupt . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
4.2.3 Fast Ethernet PHY Interrupt . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
4.2.4 PCI Interrupt . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
Clock Generator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
4.3.1 PQ2 Clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
4.3.2 PCI Clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
Bus Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
4.4.1 Single PQ2 Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
4.4.2 60X Bus Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
Buffering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
Chip - Select Generator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
Synchronous Dram (60X Bus) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
4.7.1 SDRAM Programming . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
4.7.2 SDRAM Refresh . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
4.7.3 L2-Cache Support Influence On SDRAM Design . . . . . . . . . . . . . . . . . . . . . . . 44
4.7.4 SDRAM Error Correction Support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
Synchronous Dram (Local Bus) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
4.8.1 Local Bus SDRAM Programming . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
4.8.2 SDRAM Refresh . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
4.8.3 Local Bus SDRAM Functionality . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
4.8.4 Local SDRAM Error Correction Support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
Flash Memory SIMM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
4.9.1 Flash Programming Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49
4.2
4.3
4.4
4.5
4.6
4.7
4.8
4.9
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4.9.2 Flash and L2Cache . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49
4.10 E2PROM Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
4.11 PCI Bus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51
4.12 L2-CACHE Support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52
4.12.1 L2 Cache Configuration & Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53
4.13 Communication Ports . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54
4.13.1 ATM Port . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54
4.13.2 100/10 Base - T Ports . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55
4.13.2.1 DM9161 Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55
4.13.3 RS232 Ports . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56
4.13.3.1 RS-232 Ports’ Signal Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56
4.13.4 USB Port . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57
4.13.5 PC Parallel Port . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57
4.14 Board Control & Status Register - BCSR . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57
4.14.1 BCSR0 - Board Control - Status Register 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58
4.14.2 BCSR1 - Board Control - Status Register 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59
4.14.3 BCSR2 - Board Control - Status Register - 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . 60
4.14.4 BCSR3 - Board Control - Status Register 3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64
4.14.5 BCSR4 - Board Control - Status Register 4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64
4.14.6 BCSR5 and BCSR7- Board Control - Status Register 3 & 5 . . . . . . . . . . . . . . . 65
4.15 COP/JTAG Port . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66
Section 5
Memory Map and Initialization
5.1
5.2
Memory Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69
PQ2 Register Programming . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73
5.2.1 System Initializations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74
5.2.2 Memory Controller Registers Programming . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75
Section 6
Physical Properties
6.1
Power Supply . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79
6.1.1 5V Rail . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81
6.1.2 3.3V Rail . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81
6.1.3 5V Stand By Rail . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81
6.1.4 VDDH Rail . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81
6.1.5 VDDL Bus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81
6.1.6 12V Rail . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81
6.1.7 -12V Rail . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81
Connectors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82
6.2.1 ATX Power Connector . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82
6.2.2 Fast Ethernet Port Connectors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82
6.2
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6.2.3 ATM 155 Port Connection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82
6.2.4 RS232 PortS Connector . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82
6.2.5 CPM Expansion Connector . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82
6.2.6 COP/JTAG Port Connector . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82
6.2.7 Logic Analyzer Connectors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83
6.2.8 Mach’s In System Programming (ISP) Connector . . . . . . . . . . . . . . . . . . . . . . . 83
6.2.9 PCI Connectors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83
6.2.10 System Expansion Connector . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83
6.2.11 USB Connector . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83
6.2.12 Parallel Port Connector . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83
PCB Layout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83
6.3
Section 7
Support Information
7.1
Interconnect signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84
7.1.1 P1 - RS232 ports 1 and 2 Connectors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84
7.1.2 P3 and P4 - 100/10 - Base-T Ethernet port Connector . . . . . . . . . . . . . . . . . . . . 85
7.1.3 P15 - COP / JTAG Connector . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85
7.1.4 P7 - CPM Expansion Connector . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86
7.1.5 P11, P12, P13, P14, P16, P17, P18, P23, P28,P29, P30- Logic Analyzer MICTOR
Connectors 93
7.1.6 P10, P8, P9 - PCI Connectors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94
7.1.7 P27 - ATX Power Supply Connector . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96
7.1.8 P19,P20 - Mach/Lattice ISP Connector . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96
7.1.9 P27 - System Expansion Connector . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97
7.1.10 P2 - USB Connector . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103
Programmable Logic Equations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103
7.2.1 U35 - BCSR Code . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103
7.2.2 U41 - Power switch debounce . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 168
Schematics and Bill Of Materials . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 174
7.3.1 Schematics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 174
7.3.2 Bill of Materials . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 203
7.2
7.3
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Table of Contents
VI
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List of Tables
List of Tables
1-1
2-1
4-1
4-2
4-3
4-4
4-5
4-6
PQ2FADS-ZU specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
. MODCK(1:3) Encoding . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
BCSR/FLASH Hard Reset Configuration Word . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
E2PROM Hard Reset Configuration Word . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
PCI Interrupt Register Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
PCI Interrupt Mask Register Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
PQ2FADS-ZU Chip Select Assignments . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
100 MHz SDRAM Mode Register Programming . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
100 MHz SDRAM Mode Register Programming . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
L2 Cache CFG(0:2) Settings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53
BCSR0 Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59
BCSR1 Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60
BCSR2 Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61
FLASH Presence Detect (7:5) Encoding . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62
FLASH Presence Detect (4:1) Encoding . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62
EXTOOLI(0:3) Assignment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62
PQ2 Board Version Encoding . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63
PQ2 Board Revision Encoding . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63
External Tool Revision Encoding . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63
L2 Cache Size Encoding . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63
BCSR3 Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64
PCI Board Present Signal Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65
BCSR4 Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65
BCSR5 to BCSR7 Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66
COP/JTAG Port Signals Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67
PQ2FADS-ZU Memory Map - FLASH (or BCSR) as Boot Device . . . . . . . . . . . . . 69
PQ2FADS-ZU Memory Map - E2PROM as Boot Device . . . . . . . . . . . . . . . . . . . . 71
BCSR/FLASH Power On Reset Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74
E2PROM Power On Reset Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74
SIU REGISTERS’ PROGRAMMING . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75
Memory Controller Initializations For 100Mhz - FLASH as Boot Device . . . . . . . . 76
Memory Controller Initializations For 100Mhz - E2PROM as Boot Device . . . . . . 77
Memory Controller Initializations For 100Mhz . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78
Expansion Connectors Maximum Current Consumption . . . . . . . . . . . . . . . . . . . . . 80
Maximum Power Consumption Per Add-In Card . . . . . . . . . . . . . . . . . . . . . . . . . . . 80
P1 Connector . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84
P3,P4 - 100/10 Base-T Ethernet Connector . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85
P15 - COP/JTAG Connector . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85
P4 - CPM Expansion Connector . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87
P7, P8, P9 - PCI Connectors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94
4-7
4-8
4-9
4-10
4-11
4-12
4-13
4-14
4-15
4-16
4-17
4-18
4-19
4-21
4-20
4-22
4-23
5-1
5-2
5-3
5-4
5-5
5-6
5-7
5-8
6-1
6-2
7-1
7-2
7-3
7-4
7-5
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List of Tables
7-6
7-7
7-8
7-9
P27 - ATX Power Supply Connector . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96
P15 - Lattice ISP Connector . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97
P17 - System Expansion Connector . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98
P2 - USB Connector . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103
II
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List of Figures
List of Figures
1-1
2-1
2-2
2-3
2-4
2-5
2-6
2-7
PQ2FADS-ZU Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
PQ2FADS-ZU Top Side Part Location Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
VDDL Range Selection - P24 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
VDDL Trimmer - RP2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
SW6 Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Hard Reset Configuration Source Selection - JP7 . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
SW5 Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
JP9 - Local Bus Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
JP10 - 60x Parity Support Selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Clock Source Selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
FCC2 Ethernet Mode Selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
FCC3 Ethernet Mode Selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Host Controlled Operation Scheme - Command Converter . . . . . . . . . . . . . . . . . . . 17
Host Controlled Operation Scheme - Parallel Port . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Stand Alone Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
P15 - COP/JTAG Port Connector . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
P1A/P1B - RS232 Serial Port Connector . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Flash Memory SIMM Insertion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
SW4 - Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
JP5 - Therm Connector . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
JP14 - VPP Source Selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
PCI Host Configuration Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
PCI Interrupt Routing Scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
Main Clock Generator Scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
PCI Clock Generator Scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
60x SDRAM Connection Scheme - No L2 Cache . . . . . . . . . . . . . . . . . . . . . . . . . . 43
SDRAM - 60x Bus Connection Scheme with L2 Cache . . . . . . . . . . . . . . . . . . . . . . 43
60x SDRAM Data Parity Support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
Local Bus SDRAM Connection Scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
Local Bus SDRAM Data Parity Support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
FLASH SIMM Connection Scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49
E2PROM Connection scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51
PCI Bus Scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52
RS232 Serial Ports Connector . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56
Debug Station Connection Schemes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66
COP/JTAG Port Connector . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67
PQ2FADS-ZU Power Scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80
PQ2FADS-ZU Bill of Materials . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 203
2-8
2-9
2-10
2-11
2-12
2-13
2-14
2-15
2-16
2-17
3-1
3-2
3-3
4-1
4-2
4-3
4-4
4-5
4-6
4-7
4-8
4-9
4-10
4-11
4-12
4-13
4-14
4-15
6-1
7-1
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1
General Information
1.1
Introduction
This document is an operation guide for the PQ2FADS-ZU board. It contains operational,
functional and general information about the PQ2FADS-ZU. This board is meant to serve as a
platform for s/w and h/w development for the POWER QUICC II family of processors. Using its
on-board resources and a debugger, a developer is able to download code, run it, set breakpoints,
display memory and registers and connect proprietary h/w via the expansion connectors, to be
incorporated into a desired system with the POWER QUICC II processors.
1
This board could also be used as a demonstration tool (i.e., application s/w may be programmed
into its Flash memory and ran in exhibitions etc.).
1. Either on or off-board.
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General Information
1.2
Definitions, Acronyms, and Abbreviations
PQ2FADS-ZU
MPC8260
PQ2
PowerQUICC II Family ADS Board
PowerQuicc 2 Hip3
PowerQuicc 2 Hip4
MPC8280
PQ2
PowerQuicc 2 Hip7
PowerQUICC 2 Processors family
MPC8260 - PowerQUICC 2
PowerPC
VOYAGER
PPC
PCI
Peripheral Components Interconnect
Universal Serial Bus
USB
CPM
Communication Processor Module
Synchronous Dynamic Random Access Memory
Voyager Application Development System
1024 bytes
SDRAM
VADS
Kbyte
LSB
Least Significant Byte
lsb
least significant bit
Mbyte
DIMM
SIMM
TBD
1048576 bytes
Dual In-line Memory Module
Single In-line Memory Module
To Be Defined
UPM
User Programmable Machine
Evaluation Board
EVB
GPCM
GPL
General Purpose Chip-select Machine
General Purpose Line
BCSR
FLASH
ZIF
Board Control and Status Register
Non volatile reprogrammable memory.
Zero Input Force
BGA
Ball Grid Array
ADI
Application Development Interface.
Common On-chip Processor
Segmentation And Reassembly
Universal Test & OPerations Interface for ATM
COP
SAR
UTOPIA
1.3
Related Documentation
•
•
•
•
MPC8260, PQ2, MPC8280 - User’s Manual.
VADS Users’ Manual.
MPC2605 Data Sheet.
PMC-SIERRA 5384 Long Form Data Sheet
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General Information
•
DM9161 (by DAVICOM) Data Sheet
1.4
Specifications
The PQ2FADS-ZU specifications are given in Table 1-1.
Table 1-1. PQ2FADS-ZU specifications
CHARACTERISTICS
SPECIFICATIONS
Power requirements (no other boards attached)
+5Vdc @ TBD A (Typ.), TBD A (Max.)
+3.3Vdc @ TBD A (Typ.), TBD A (Max.)
+12Vdc - @TBD A Max.
-12Vdc - @TBD A Max.
Microprocessor
MPC8260 running @ 66 MHz Bus Clock Frequency.
MPC8264/5/6 running @ up to 83 MHz Bus Clock Frequency.
MPC8280/5 running @ up to 100 MHz Bus Clock Frequency.
Addressing
Total address range on PPC Bus:
Total address range on Local Bus:
4 Giga Bytes (32 address lines)
256 KBytes External (18 address lines)
4 Giga Bytes Internal (32 address lines internal decoding)
Flash Memory SIMM (PPC Bus)
Synchronous Dynamic RAM DIMM (PPC Bus)
8 MByte, 32 bits wide expandable to 32 MBytes
32 MByte, 64 bits wide with optional parity.
Synchronous DRAM On Local Bus
Operating temperature
Storage temperature
8 MBytes, 32 bit wide with optional parity.
0OC - 70OC (room temperature)
-25OC to 85OC
Relative humidity
5% to 90% (non-condensing)
Dimensions:
Length
12" (305 mm)
9" (229 mm)
Width
Thickness
0.063" (1.6 mm)
1.5
PQ2FADS-ZU Features
•
•
Supports MPC8260 (Hip3), PQ2 (Hip4) and MPC8280 (Hip7) processors.
64 bit PowerQUICC II Communication Processor, running @ up to 100MHz external bus
frequency.
•
32 MByte Synchronous Dram (soldered on-board), residing on 60X bus (PBI mode) with
optional parity support, controlled by SDRAM machine 1. Optional address Latch -
Multiplexer is available if L2 cache module is assembled.
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•
•
Optional 1/2 MByte L2-Cache on-board using 2 MPC2605 Look-Aside cache modules.
8 MByte, 80 pin Flash SIMM, buffered from 60X bus. Support for upto 32 MByte,
controlled by GPCM, 5V/12V Programmable, with Automatic Flash SIMM identification,
via BCSR. Support for both On and OFF SIMM Flash reset.
•
5V/12V VPP (in-circuit programming voltage) for Flash SIMM - jumper selectable.
2
•
•
•
•
8 KBytes E PROM, buffered from the 60x bus, controlled by the GPCM.
Board Control & Status Register - BCSR, Controlling Boards’ Operation.
On-board COP/JTAG connector.
On-board logic to support direct connection to standard Parallel Port (EPP/SPP modes) in
Desk Top PC for debug purposes using CodeWarrior tools.
•
•
•
Power-On Reset Option via JTAG.
Selectable Local bus function - Local Bus SDRAM connection or PCI bus in host mode.
8MByte Synchronous Dram (soldered on-board), residing on local bus with optional parity
support, controlled by SDRAM machine 2.
2
•
Programmable Power-On Reset and Hard-Reset Configuration via E PROM or via Flash
memory for the PQ2 core.
•
•
PCI Local Bus is PCI Standard 2.2 compliant.
3 PCI slots are available to host up to 3 masters/targets cards @ 3.3V only - arbitration is
supported by the on-chip Arbiter.
•
•
•
•
PCI bus supports 25 - 66 MHz @ 3.3V devices (determined by the user).
Simple generic Interrupt Controller to handle the PCI interrupts (4 in each PCI slot).
Module Enable Indications for all on-board modules.
High density (MICTOR) Logic Analyzer connectors, carrying all 60x, local bus and CPM
signals, for fast logic analyzer connection.
•
•
•
155 Mbps ATM UNI on FCC1 with Optical I/F, connected to the PQ2 via UTOPIA Level
2 I/F supporting 8/16 bit in single/multi PHY, using the PMC-SIERA 5384.
Two 100/10-Base-T Ports on FCC2 and FCC3 with T.P. I/F, MII/RMII controlled, using
Davicom DM9161.
USB Port, USB 1.1 Standard Compliant, using Philips PDIUSBP11 USB transceiver. USB
Port is with shutdown option and speed selectable - BCSR controlled.
•
•
Dual RS232 port residing on SCC1 & SCC2.
Module disable (i.e., low-power mode) option for all communication transceivers -BCSR
controlled, enabling use of communication ports, off-board via the expansion connectors.
•
Dedicated PQ2 communication ports expansion connectors for convenient tools’
connection, carrying also necessary bus signals, for transceivers’ M/P I/F connection. Use
is done with 2 X 128 pin DIN 41612 receptacle connectors.
•
•
External Tools’ identification & status read capability, via BCSR.
1
Separate Power-On Reset Push - Button, Soft / Hard Reset Push - Button and ABORT
Push - Button.
•
ATX Power Supply.
1. Hard reset is applied by depressing BOTH Soft Reset & ABORT buttons.
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•
•
Multi-Range PQ2 internal logic operation voltage - selectable by jumper between three
ranges - 1.3V to 1.7V for MPC8280 (Hip7), 1.7V to 1.9V for PQ2 (Hip4) or 2.3V to 2.7V
for MPC8260 (Hip3).
Software Option Switch provides 8 S/W options via BCSR.
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PCI Slot 33/66Mhz 3.3V
PCI Slot 33/66Mhz 3.3V
60x Bus
Logic Analyzer
Mictors
OPTIONAL
PCI Slot 33/66Mhz 3.3V
3.3V
SDRAM
32 MBytes
64 - Bit
3.3V
60X Bus Add.
0 Ω Res.
60X Bus Data.
SDRAM
8 MBytes
32 - Bit
3.3V
L2-CACHE
512K
60X Bus
64 - Bit
OPTIONAL
BUS
SWITCH
5V
FLASH SIMM.
60X Bus (buffered)
8 - 32MByte
32 - Bit
3.3V
3.3V<->5V
PQ2
DATA Transceivers &
Address Latches
2
E PROM
8KByte
8 - bit
SCC1
Reset,
Main
Interrupts
Clock
SCC2
3.3V
3.3V
FCC2
Magnetics
Magnetics
DM9161
3.3V
FCC3
DM9161
3.3V
FCC1
PM5384
SCC4
PDIUSBP11
Logic Analyzer
Mictors
Buffered System Bus
CPM
Figure 1-1. PQ2FADS-ZU Block Diagram
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2
Hardware Preparation and Installation
2.1
Introduction
This chapter provides unpacking instructions, hardware preparation, and installation instructions
for the PQ2FADS-ZU.
2.2
Unpacking Instructions
NOTE: If the shipping carton is damaged upon receipt, request carrier’s agent to be present
during unpacking and inspection of equipment.
Unpack equipment from shipping carton. Refer to packing list and verify that all items are
present. Save packing material for storing and reshipping of equipment.
CAUTION
AVOID
INTEGRATED
DISCHARGE CAN DAMAGE CIRCUITS.
TOUCHING
AREAS
OF
CIRCUITRY;
STATIC
2.3
Hardware Preparation
To select the desired configuration and ensure proper operation of the PQ2FADS-ZU board,
changes of the Dip-Switch settings may be required before installation. The location of the
switches, indicators, Dip-Switches, and connectors is illustrated in Figure 2-1.. The board has been
factory tested and is shipped with Dip-Switch settings as described in the following paragraphs.
Parameters can be changed for the following conditions:
•
•
•
PQ2’s Internal Logic Supply Level Range Via connector P24.
PQ2’s Internal Logic Supply Level within range (VDDL) Via potentiometer RP2.
PQ2’s MODCK(1:3). Determining Core’s and CPM’s PLLs multiplication factor via dip-
switches SW6(#6 - #8).
•
PQ2’s Hard Reset Configuration word Source - BCSR or Memory (FLASH/EEPROM) - via
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jumper JP7.
•
•
•
•
•
•
•
•
•
•
•
PQ2’s Boot code Source - EEPROM/FLASH - via dip-switch SW5(1).
PQ2’s MODCKH(0:3) via SW6(1-4).
PQ2’s PCI_MODCK via SW6(5).
PQ2’s PCI_ARBITER via SW5(2).
PQ2’s PCI_DLL via SW5(3).
Local Bus functionality - SDRAM/PCI - via jumper JP9.
PQ2’s 60x Bus parity support On/Off - via jumper JP10.
Clock-In source - External or On-Board clock oscillator - JP11.
FCC2 and FCC3 MII/RMII modes - via jumpers JP2 and JP3 respectively.
USB speed (12Mbits/s or 1.5Mbits/s) and mode (Host or Slave) - software controlled in BCSR.
PQ2’s COP/JTAG connection - COP/JTAG connector (P15) or direct connection to PC parallel
port (P31) - selected automatically by connecting parallel cable.
•
ATX Power Supply On/Off Switch - via SW7.
JP2
JP3
P15
JP7
SW5
SW6
JP9
JP10
JP11
P24
RP2
P31
SW7
Figure 2-1. PQ2FADS-ZU Top Side Part Location Diagram
2.3.1 Setting VDDL Level Range - P24
To support all revisions of the PQ2, provisions are taken to provide necessary voltage levels on
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VDDL, to match the process by which the PQ2 is manufactured. Via P24, four voltage level
ranges are provided (P24 setting options are shown in Figure 2-2.):
1. When a jumper is placed between positions 1 - 2 of P24, a level range of 2.3V to 2.7V on
VDDL is selected. This level matches the specification for the MPC8260 (Hip3).
2. When a jumper is placed between positions 3 - 4 of P24, a level range of 1.7V to 1.9V on
VDDL is selected. This level matches the specification for the PQ2 (Hip4).
3. When a jumper is placed between positions 5 - 6 of P24, a level range of 1.3V to 1.7V is
selected for VDDL. This level matches the specification for the MPC8280 (Hip7).
4. When a jumper is misplaced for P24, a level range of 1.8V to 2.0V is selected for VDDL.
This level matches the specification for the faster (83MHz bus speed) PQ2 (Hip4).
.
P24
P24
P24
P24
6
4
2
5
3
1
6
4
2
5
3
1
6
4
2
6
4
2
5
3
1
5
3
1
1.7V - 1.9V
2.3V - 2.7V
1.8V - 2.0V
1.3V - 1.7V
Figure 2-2. VDDL Range Selection - P24
WARNING
P24 is Factory Set according to the revision of
PQ2 with which it is assembled. Prior to chang-
ing a PQ2 device, Extra Care should be taken
with P24 setup. If a selected Voltage Range is
above the specification for the newly inserted
PQ2, PERMANENT DAMAGE might be inflicted
to the device.
P24 selects only a range of Voltage levels on VDDL. The actual level is selected by RP2. See next
paragraph.
2.3.2 Setting VDDL Supply Voltage Level
After VDDL’s Voltage Level Range is selected via P24, the actual level of VDDL is tuned via
RP2. VDDL may be measured upon JP13, using a DVM or any other high input impedance
voltage measuring device.
VDDL level is factory set at the mid-range for the appropriate level range, but may be changed
via RP2. Rotating RP2 CCW will increase VDDL voltage up to range-high, while rotating it CW,
will decrease VDDL down to range-low. LD26 provides visual indication for VDDL level, it
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illuminates brighter with rise of VDDL. VDDL change Vs. RP2’s rotation direction is shown in
Figure 2-3.:
RP2
LOW
HIGH
Figure 2-3. VDDL Trimmer - RP2
WARNING
While in higher ranges of VDDL and higher rang-
es of internal operation frequencies, the PQ2
might require some sort of COOLING measures
to be taken. Failure in doing so, might result in
PERMANENT DAMAGE inflicted to the PQ2.
2.3.3 Setting MODCK(1:3) for PLLs Multiplication Factor -
SW6 (#6 - #8)
After (1K cycles) the negation of the Power On Reset signal, the PQ2 samples the 7 MODCK
lines - the lower 3 on MODCK(1-3) and the upper four - MODCKH(0:3) field (read from the
1
Hard-Reset Configuration Word when the PCI is disabled ), to establish the multiplication factors
of the CPM’s and Core’s PLLs. The levels on MODCK(1:3) lines are set using SW6, switches #6
- #8. When an individual switch is at the OFF position its associated MODCK line is pulled-high
(‘1’), while when at the ON position, the associated MODCK is pulled-down (‘0’). SW6 is shown
in Figure 2-4., while the various combinations for SW6 (#6 - #8) and their associated
MODCK(1:3) values are shown in Table 2-1..
1.May be either boot FLASH or EEPROM or BCSR on the ADS.
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.
1
1
2
3
4
5
6
7
8
0
MODCKH0
MODCKH1
MODCKH2
MODCKH3
MODCKH0
MODCKH1
MODCKH2
MODCKH3
PCI_MODCK
MODCK1
MODCK2
MODCK3
PCI_MODCK
MODCK1
MODCK2
MODCK3
SW6
Factory Set
Figure 2-4. SW6 Description
Table 2-1. . MODCK(1:3) Encoding
MODCK(1:3)
Switch 6
Switch 7
Switch 8
0
1
2
3
4
5
6
7
ON
ON
ON
ON
ON
OFF
ON
ON
OFF
OFF
ON
ON
OFF
ON
OFF
OFF
OFF
OFF
ON
OFF
ON
OFF
OFF
OFF
2.3.4 Setting Hard - Reset Configuration Source - JP7
The Boot sequence which starts when HRESET is asserted, may be from two sources:
1. BCSR (default Hard-Reset Configuration Word - CS0 is assumed to be assigned to the
FLASH)
2. Memories (FLASH/EEPROM - user controlled Hard-Reset Configuration Word)
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When a jumper is placed between positions 1 - 2 of JP7, the Hard Reset Configuration source is a
memory (FLASH/EEPROM) as configured by switch SW5-1. When a jumper is set between
positions 2 - 3 of JP7, the Hard Reset Configuration source is the BCSR. See Figure 2-5..
JP7
JP7
2
1
3
1
2
3
FLASH/EEPROM is Hard Reset
Configuration Source
BCSR is Hard Reset
Configuration Source
Factory Setup
Figure 2-5. Hard Reset Configuration Source Selection - JP7
2.3.5 Setting Boot Source
1
The Hard - Reset configuration word , read by the PQ2 while HRESET is asserted, may be taken
from three sources:
1. Flash Memory SIMM
2. EEPROM
3. BCSR
For additional information as for the contents of the Hard-Reset configuration word see 4.1.2.4
"Hard Reset Configuration" on page 29.
SW5#1 actually assigns CS0 to the FLASH (default when booting from the BCSR) or to the
EEPROM. When SW5 #1 is OFF, the Hard Reset configuration word is taken from EEPROM,
when it is ON, the Hard Reset configuration word is taken from the Flash SIMM. See Figure 2-6..
1
1
2
3
4
0
EEPROM BOOT
PCI_ARBITER (OFF)
PCI_DLL (ON)
FLASH BOOT
PCI_ARBITER (ON)
PCI_DLL (OFF)
PCI CONFIG 3
PCI CONFIG 3
SW5
Factory Set
Figure 2-6. SW5 Description
1.In fact 8 Hard-Reset configuration words are read by a configuration master, however only the first is rel-
evant for a single PQ2.
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2.3.6 Setting MODCKH(0:3) - for PLLs Multiplication Factors
When the Hard Reset configuration word is taken from Flash SIMM/EEPROM, the functionality
of the MODCKH(0-3) bits in the Hard Reset Configuration Word depends on the mode of the
PCI. When the PCI mode in the PQ2 (Hip4 and Hip7) is enabled (by jumper JP9), the
MODCKH(0:3) lines are taken from SW6(#1 - #4) and the MODCKH(0:3) bits in the Hard Reset
Configuration Word are ignored. When the PCI mode in the PQ2 is disabled (Local Bus SDRAM
is enabled), MODCKH(0:3) are taken from the Hard Reset Configuration Word. SW6(#1 - #4) set
the upper 4 bits of the MODCK field during Hard Reset Configuration acquisition. When an
individual switch of SW4 #1 - #4 is at the OFF position, its corresponding MODCKH line is
pulled-high (‘1’) during Hard Reset, while when at the ON position, pulled-down (‘0’) (see Figure
2-4.).
2.3.7 Setting PCI_MODCK - for PCI Bus Clock
The settings of this line, determines the frequency of the PCI bus (when the PQ2 is in PCI mode).
When PCI_MODCK is set low, the PCI bus frequency is set by the MODCK lines. When set high,
the PCI bus frequency is half of what is set by the MODCK lines. When switch SW6 #5 is at the
OFF position, its corresponding PCI_MODCK line is pulled-high (‘1’ - enabled), while when at
the ON position, pulled-down (‘0 - disabled’) (see Figure 2-4.).
2.3.8 Setting PCI_ARBITER - for PCI Mode Enabled
The settings of this line, determines the operation of the PCI Arbiter (when the PQ2 is in PCI
mode). When PCI_ARBITER is set low, the PCI Arbiter in the PQ2 is enabled. When set high,
the PCI Arbiter is disabled and an external arbiter can be used. When switch SW5 #2 is at the
OFF position, its corresponding PCI_ARBITER line is pulled-high (‘1’ - disabled), while when
at the ON position, pulled-down (‘0’ - enabled) (see Figure 2-6.).
2.3.9 Setting PCI_DLL - for PCI Mode Enabled
The settings of this line, determines the operation of the DLL for PCI Mode enabled. When PCI
Mode is enabled, the DLL must be enabled. When PCI_DLL is set low, the DLL is disabled.
When set high, the DLL is enabled. When switch SW5 #3 is at the OFF position, its
corresponding PCI_DLL line is pulled-high (‘1’ - enabled), while when at the ON position,
pulled-down (‘0’ - disabled) (see Figure 2-6.).
2.3.10 Setting Local Bus functionality - SDRAM or PCI
There are two modes to set the Local bus - Local Bus (SDRAM) or PCI. The mode is determined
by setting JP9. When a jumper is placed between positions 1 - 2 of JP9, the PCI mode is enabled.
When a jumper is placed between positions 2–3 of JP9, the PCI mode is disabled and the Local
bus is connected to SDRAM (see Figure 2-7.).
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JP9
JP9
2
1
3
1
2
3
PCI Enabled
Local Bus SDRAM Enabled
Factory Setup
Figure 2-7. JP9 - Local Bus Mode
2.3.11 60x Bus Parity Support
Error correction (parity) on the 60x bus transactions is optional by setting JP10. Since the 8 data
parity pins are muxed with other functions, Bus Mux is used to connect the data parity pins to the
SDRAM device. When a jumper is placed between positions 1 - 2 of JP10, the 60x parity support
is disabled. When a jumper is placed between positions 2–3 of JP10, the 60x parity support is
enabled. See Figure 2-8.
JP10
JP10
1
2
3
1
2
3
60x Parity Disabled
60x Parity Enabled
Factory Setup
Figure 2-8. JP10 - 60x Parity Support Selection
2.3.12 Clock-In Source selection
The main clock source can be selected between an external (off-board) source by connecting to
P21 or an on-board clock oscilator. The selection is done by setting JP11. When a jumper is
placed between positions 1 - 2 of JP11, the external clock source is enabled. When a jumper is
placed between positions 2–3 of JP11, the on-board clock oscilator is enabled. See Figure 2-9.
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.
JP11
2
JP11
2
1
3
1
3
External Clock
On-board Clock Oscilator
Factory Setup
Figure 2-9. Clock Source Selection
2.3.13 FCC2 Ethernet Port mode - MII/RMII
The Ethernet PHY on FCC2 is set by default to 100Base-Tx Full Duplex and can be configured to
operate in MII or RMII interface. The selection is done by setting JP2. When a jumper is placed
between positions 1 - 2 of JP2, the MII interface is enabled. When a jumper is placed between
positions 2–3 of JP2, the RMII interface is enabled. See Figure 2-10.
JP2
JP2
1
2
3
1
2
3
RMII Mode
MII Mode
Factory Setup
Figure 2-10. FCC2 Ethernet Mode Selection
NOTE: For the mode change to take place, the setting of JP2 should be done while the
board is powered-off.
2.3.14 FCC3 Ethernet Port mode - MII/RMII
The Ethernet PHY on FCC3 is set by default to 100Base-Tx Full Duplex and can be configured to
operate in MII or RMII interface. The selection is done by setting JP3. When a jumper is placed
between positions 1 - 2 of JP3, the MII interface is enabled. When a jumper is placed between
positions 2–3 of JP3, the RMII interface is enabled. See Figure 2-11.
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JP3
JP3
2
1
3
1
2
3
RMII Mode
MII Mode
Factory Setup
Figure 2-11. FCC3 Ethernet Mode Selection
NOTE: For the mode change to take place, the setting of JP3 should be done while the
board is powered-off.
2.3.15 USB Speed selection
The USB port supports two speeds - 12Mbits/s and 1.5Mbits/s. The selection is software
controlled in the BCSR. At power-up, the default selection is 12Mbits/s.
2.3.16 USB Mode selection
The USB port supports two modes - Host and Slave. The selection is software controlled in the
BCSR. At power-up, the default selection is Host.
2.3.17 COP/JTAG Connection
There are two options to connect to the COP port of the PQ2 - COP/JTAG connector or a Parallel
port (of a PC). The COP/JTAG connector requires a command converter while the second option
connects directly to the parallel port of a PC and eliminates the need for one. The selection is done
automaticaly - if a cable is connected to the parallel port in a PC then this connection has the
priority over the COP/JTAG connector.
2.3.18 Power On/Off Switch
The Power-On or Off is done by switching SW7.
2.4
Installation Instructions
When the PQ2FADS-ZU has been configured as desired by the user, it can be installed according
to the required working environment as follows:
•
•
Host Controlled Operation
Stand-Alone
2.4.1 Host Controlled Operation
In this configuration the PQ2FADS-ZU is controlled by a host computer via the COP port, which
is a subset of the JTAG port. This configuration allows for extensive debugging using on-host
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debugger. There are two options to connect to the COP port:
1. The host is connected to the board by a COP controller (command converter) provided by
a third party.
Host
Computer
16 Wire
Flat Cable
Media I/F
Media2COP
MEDIA
P15
ATX Power Supply
P27
Figure 2-12. Host Controlled Operation Scheme - Command Converter
2. The host is connected to the board directly from the host’s parallel port.
Host
Computer
Standard
Parallel Cable
Media I/F
MEDIA
ATX Power Supply
P27
P31
Figure 2-13. Host Controlled Operation Scheme - Parallel Port
2.4.2 Stand Alone Operation
In this mode, the board is not controlled by the host via the COP port. It may connect to host via
one of its other ports, e.g., RS232 port, Fast Ethernet port, ATM155 port etc. Operating in this
mode requires an application program to be programmed into the board’s Flash memory.
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Host
Computer
RS232
Ethernet
ATM 155 (optics)
P1A/P1B
U1
ATX Power Supply
Figure 2-14. Stand Alone Configuration
2.4.3 COP/JTAG Connector - P15
The PQ2FADS-ZU COP interface connector, P15, is a 16 pin, male, Header connector. The
connection between the PQ2FADS-ZU and the COP controller is by a 16 line flat cable, supplied
with the COP controller board obtained from a third party developer. Figure 2-15. shows the pin
configuration of the connector.
.
1
2
4
6
8
TDO
TDI
GND
TRST
V3.3
3
5
QREQ
7
9
TCK
TMS
N.C.
10
12
14
GND
11
13
SRESET
HRESET
GND
N.C.
15
16
GND
CKSTP_OUT
Figure 2-15. P15 - COP/JTAG Port Connector
2.4.4 Terminal to PQ2FADS-ZU RS-232 Connection
A serial (RS232) terminal or any other RS232 equipment, may be connected to the RS-232
connectors P1A and P1B. The RS-232 connectors are a 9 pin, female, D-type connectors,
arranged in a stacked configuration. P1B connected to SCC2 of the PQ2 is the lower and P1A,
connected to SCC1 of the PQ2, is the upper in the stack.
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Hardware Preparation and Installation
The connectors are arranged in a manner that allows for 1:1 connection with the serial port of an
1
IBM-AT or compatibles, i.e. via a flat cable. The pinout which is identical for both P1A and P1B
is shown in Figure 2-16..
CD
TX
1
2
6
7
8
9
DSR
N.C.
CTS
N.C.
RX
3
4
5
DTR
GND
Figure 2-16. P1A/P1B - RS232 Serial Port Connector
2.4.5 10/100-Base-T Ethernet Ports Connection
o
The 10/100-Base-T port connectors - P3 and P4, are an 8-pin, 90 , receptacle RJ45 connector. The
connection between the 10/100-Base-T ports to the network is done by a standard cable, having
two RJ45/8 jacks on its ends. The pinout of P3 and P4 is described in Table 7-2. "P3,P4 - 100/10
Base-T Ethernet Connector" on page 85.
2.4.6 Memory Installation
The PQ2FADS-ZU is supplied with one type of memory module:
•
Flash Memory SIMM.
2.4.6.1 Flash Memory SIMM Installation
To install a memory SIMM, it should be taken out of its package, put diagonally in its socket -
U54 - and then raised to a vertical position until the metal lock clips are locked. See Figure 2-17..
1.IBM-AT is a trademark of International Business Machines Inc.
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Hardware Preparation and Installation
CAUTION
The memory SIMMs have alignment nibble near
their # 1 pin. It is important to align the memory
correctly before it is twisted, otherwise damage
might be inflicted to both the memory SIMM and
its socket.
(1)
(2)
Flash
SIMM
Metal Lock Clip
SIMM Socket
Figure 2-17. Flash Memory SIMM Insertion
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Operating Instructions
3
Operating Instructions
3.1
Introduction
This chapter provides necessary information to use the PQ2FADS-ZU in host-controlled and
stand-alone configurations. This includes controls and indicators, memory map details, and
software initialization of the board.
3.2
Controls and Indicators
The PQ2FADS-ZU has the following switches and indicators.
3.2.1 Power-On RESET Switch - SW1
The Power-On RESET switch SW1 performs Power-On reset to the PQ2, as if the power was re-
applied to the ADS. When the PQ2 is reset that way, all configuration and all data residing in
volatile memories are lost. After PORST signal is negated, the PQ2 re-acquires the power-on reset
and hard-reset configuration data from the hard-reset configuration source. (Flash | EEPROM |
BCSR).
3.2.2 ABORT Switch - SW2
The ABORT switch is normally used to abort program execution, this by issuing a level 0
interrupt to the PQ2. If the ADS is in stand alone mode, it is the responsibility of the user to
provide means of handling the interrupt, since there is no resident debugger with the PQ2FADS-
ZU. The ABORT switch signal is debounced, and may be disabled by software.
3.2.3 SOFT RESET Switch - SW3
The SOFT RESET switch SW3 performs Soft reset to the PQ2 internal modules, maintaining
PQ2’s configuration (clocks & chip-selects) and SDRAMs’ contents. The switch signal is
debounced, and it is not possible to disable it by software.
3.2.4 HARD RESET - Switches - SW2 & SW3
When BOTH switches - SW2 and SW3 are depressed simultaneously, HARD reset is generated to
1
the PQ2. When the PQ2 is HARD reset, all its configuration is lost , including data stored in the
SDRAMs and the PQ2 has to be re-initialized.
1.Except for Hard-Reset configuration word, which is acquired only once, after PON-Reset.
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3.2.5 SW5 - Reset Configuration Switch
SW5 is a 4-switch Dip-Switch. For its function see Section 2.3.5.
3.2.6 SW4 - Software Options Switch
SW4 is a 4-switch Dip-Switch. This switch is connected over SWOPT(0:2) lines which are
available at BCSR2, S/W options may be manually selected, according to SW4 state. SW4 is
factory set to all ON. See Figure 3-1.
1
2
3
4
SWOPT0 Driven to ’0’
SWOPT0 Pulled to ’1’
SWOPT1 Pulled to ’1’
SWOPT1 Driven to ’0’
SWOPT2 Driven to ’0’
SWOPT2 Pulled to ’1’
RESERVED
SW1
Figure 3-1. SW4 - Description
3.2.7 P24 - VDDL Voltage Level Range Selection
P24 selects between 4 different voltage level ranges available for VDDL. For further information
over its function see Section 2.3.1.
3.2.8 JP13 - IDDL Measurement
JP13 resides in IDDL’s main current flow. To measure IDDL, JP13 should be removed using a
solder tool and a current meter should be connected instead with wires as short and thick as
possible.
Warning
The job of removing JP13 and soldering the cur-
rent meter connections instead is very delicate
and should be done by a skilled technician.
If this process is done by unskilled hands or re-
peated more than 3 times, permanent damage
may occur to the PQ2FADS-ZU.
3.2.9 JP5 - Thermal Sense Connector
There are 2 dedicated pins THERM(0:1) which provide a way to take internal temperature
measurements of the PQ2. These pins should be connected to GND for normal operation. JP5 is
factory set with a jumper on its 2 - 3 positions, so that THERM1 is connected to GND.
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Operating Instructions
.
JP2
3
2
1
GND
THERM1
THERM0
Figure 3-2. JP5 - Therm Connector
3.2.10 JP12 - IDDH Measurement
JP12 resides in IDDH’s main current flow. To measure IDDH, JP12 should be removed using a
solder tool, and a current meter should be connected, with as wires as short and thick as possible.
Warning
The job of removing JP12 and soldering current
meter connections instead is very delicate and
should be done by a skilled technician.
If this process is done by unskilled hand or re-
peated more than 3 times, permanent damage
might be inflicted to the PQ2FADS-ZU.
3.2.11 JP14 - VPP Source Selector
JP14 selects the source for VPP - programming voltage for the Flash SIMM. When a jumper is
located between pins 2 - 3 of JP14 , the VPP is connected to the VCC plane of the board,
providing 5V VPP. When a jumper is located between positions 1 - 2 of JP14, VPP is drawn from
the 12V plane, that provides 12V VPP. JP14 options are shown in Figure 3-3.
.
JP14
JP14
1
1
12V VPP
5V VPP
Factory Set
Figure 3-3. JP14 - VPP Source Selection
3.2.12 GND Bridges
There are 7 GND bridges on the PQ2FADS-ZU. These bridges are meant to assist general
measurements and logic-analyzer connection.
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Operating Instructions
Warning
When connecting to a GND bridge, use only IN-
SULATED GND clips. Otherwise, un-insulated
clips may cause short- circuits, touching "HOT"
points around them. Failure in doing so, might
result in permanent damage to the PQ2FADS-
ZU.
3.2.13 Power O.K. Indicator - LD1
The green Power O.K. LED indicator lights if the ATXpower supply is generating all the voltages.
3.2.14 12V Indicator - LD2
The green 12V led - LD2, indicates the presence of the +12V supply on the board.
3.2.15 UTOPIA 16 Bit Indicator - LD3
The green UTOPIA16 led - LD3, indicates that the UTOPIA is in 16 bit mode. When off - the
UTOPIA is in 8 bit mode.
3.2.16 UTOPIA Multi PHY Indicator - LD4
The green Multi PHY led - LD4, indicates that the UTOPIA is in Multi PHY mode. When off -
the UTOPIA is in single PHY mode.
3.2.17 5V Indicator - LD5
The green 5V led - LD5, indicates the presence of the +5V supply on the board.
3.2.18 3.3V Indicator - LD6
The green 3.3V led - LD6, indicates the presence of the +3.3V supply on the board.
3.2.19 USB Power Indicator - LD7
The green USB Power led - LD7, indicates the presence of 5V in the USB cable.
3.2.20 -12V Indicator - LD8
The green -12V led - LD8, indicates the presence of the -12V supply on the board.
3.2.21 RUN Indicator - LD9
When the green RUN led - LD9 is lit, it indicates that the PQ2 is performing cycles on the PPC
Bus. When dark, the PQ2 is either running internally or stuck.
3.2.22 ATM ON - LD10
When the yellow ATM ON led is lit, it indicates that the ATM-UNI transceiver - the PM5384, is
enabled for communication. When it is dark, the ATM-UNI transceiver is disconnected from the
PQ2, enabling the use of its associated FCC1 pins off-board via the expansion connectors.
ATM ON led is controlled by BCSR1.
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3.2.23 Fast Ethernet Port 2 Enabled - LD11
When the yellow ETH2 ON led is lit, it indicates that the fast ethernet port 2 transceiver - the
DM9161, is connected to FCC3. When it is dark, it indicates that the DM9161 is in power down
mode and disconnected from FCC3, enabling the use of its associated FCC3 pins off-board via the
expansion connectors. The state of LD11 is controlled by BCSR1.
3.2.24 Fast Ethernet Port 1 Enabled - LD12
When the yellow ETH1 ON led is lit, it indicates that the fast ethernet port 1 transceiver - the
DM9161, is connected to FCC2. When it is dark, it indicates that the DM9161 is in power down
mode and disconnected from FCC2, enabling the use of its associated FCC2 pins off-board via the
expansion connectors. The state of LD12 is controlled by BCSR1.
3.2.25 RS232 Port 1 ON - LD13
When the yellow RS232 Port 1 ON led is lit, it designates, that the RS232 transceiver connected
to P1A (upper DB9 connector), is active and communication via that medium is allowed. When
darkened, it designates that the transceiver is in shutdown mode and its associated SCC1 pins may
be used off-board via the expansion connectors.
3.2.26 Fast Ethernet Port 1 Full Duplex Indicator - LD14
When the Dm9161 on FCC2 is enabled and is in Full Duplex operation mode, the red led - LD14
lights.
3.2.27 RS232 Port 2 ON - LD15
When the yellow RS232 Port 2 ON led is lit, it designates, that the RS232 transceiver connected
to P1B (lower DB9 connector), is active and communication via that medium is allowed. When
darkened, it designates that the transceiver is in shutdown mode and its associated SCC2 pins may
be used off-board via the expansion connectors.
3.2.28 Fast Ethernet Port 1 100Base-Tx Indicator - LD16
When the DM9161 on FCC2 is enabled and is in 100 Mbps operation mode, the green led - LD16
lights.
3.2.29 Ethernet Port 1 Tx/Rx Indicator - LD17
The green Ethernet Transmit/Receive LED indicator blinks whenever the Dm9161 on FCC2 is
transmitting or receiving data via the 10/100-Base-T port.
3.2.30 General Purpose Led 2 Indicator - LD18
This is a general purpose red LED which is user controlled by BCSR0.
3.2.31 Ethernet Port 1 LINK Indicator - LD19
The yellow Ethernet Twisted Pair Link Integrity LED indicator - LINK, lights to indicate good
link integrity on the 10/100-Base-T port. LD19 is off when the link integrity fails.
3.2.32 Fast Ethernet Port 2 Full Duplex Indicator - LD20
When the Dm9161 on FCC3 is enabled and is in Full Duplex operation mode, the red led - LD20
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Operating Instructions
lights.
3.2.33 General Purpose Led 1 Indicator - LD21
This is a general purpose green LED which is user controlled by BCSR0.
3.2.34 Fast Ethernet Port 2 100Base-Tx Indicator - LD22
When the DM9161 on FCC3 is enabled and is in 100 Mbps operation mode, the green led - LD22
lights.
3.2.35 USB Enabled Indicator - LD23
The yellow USB enable LED indicates that the USB transceiver is connected to the PQ2.
3.2.36 Ethernet Port 2 LINK Indicator - LD24
The yellow Ethernet Twisted Pair Link Integrity LED indicator - LINK, lights to indicate good
link integrity on the 10/100-Base-T port. LD24 is off when the link integrity fails.
3.2.37 Ethernet Port 2 Tx/Rx Indicator - LD25
The green Ethernet Transmit/Receive LED indicator blinks whenever the Dm9161 on FCC3 is
transmitting or receiving data via the 10/100-Base-T port.
3.2.38 VDDL Indication - LD26
The green VDDL indicator led - LD26 is lit to indicate a VDDL power activity. Since VDDL
level may vary, LD26’s illumination level also varies accordingly.
3.2.39 Parallel Port connection - LD27
The green Parallel Port connection LED indicates that the board is connected directly to the Pc’s
parallel port and the COP/JTAG connector (P15) is irrelevant.
3.2.40 External Debugger Connection Indicator - LD28
The green external debugger connection LED indicates that a command converter can be
connected to the COP/JTAG connector (P15).
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Functional Description
4
Functional Description
In this chapter the various modules combining the PQ2FADS-ZU are described to their design
details.
4.1
Reset & Reset - Configuration
There are several reset sources on the PQ2FADS-ZU:
1. Power On Reset
2. Manual Hard-Reset
3. Manual Soft-Reset
4. PCI bus reset
5. PQ2 Internal Sources. (See also the PQ2 U/M)
4.1.1 Power - On ResetPQ2
The power on reset to the PQ2 initializes the processor state after power up. A dedicated logic,
using Seiko S-80728AN-DR-T1, which is a voltage detector of 2.8V +/- 2.4%, asserts PORESET
input to the PQ2 for a period of ~2.5sec. This time period is long enough to cover also the VDDL
stabilization, powered by a different voltage regulator. It is assumed that the stabilization time for
both linear regulators (see also Section 6.1 Power Supply) are about the same. Power-On-Reset
may be generated manually as well by an on-board dedicated push-button (SW1). Power-On
Reset can also be generated by the JTAG logic, which is integrated with BCSR.
4.1.1.1 Power - On Reset Configuration
At the end of Power - On reset sequence, MODCK(1:3) are sampled by the PQ2 to configure the
various clock modes of the PQ2 (core, cpm, bus, PCI...). Selection between the MODCK(1:3)
combination options is done by means of dip-switches (Section 2.3.3) on the mother board while
PCI_MODCKH(0:3) are obtained from the relevant dedicated pins (by means of dip-switches -
Section 2.3.6) when the PQ2 is in active PCI mode (determined by the state of PCI_MODE pin). If
the PCI is set to be inactive, the MODCKH(0:3) bits are obtained from the Hard Reset
2
Configuration Word in the Flash or in the E PROM (depends on who is the boot device) or from
PCI_MODCKH(0:3) dip-switches if the Hard Reset Config Word is sourced from the BCSR.
The configuration master is determined upon the rising edge of PORST, according to the state of
RSTCONF (Section 2.3.5) signal, driven low on this board, to set the PQ2 as a configuration
master.
After power-on reset negates, the hard-reset sequence starts, during which, many other different
options are configured (see Section 4.1.2.4 "Hard Reset Configuration" on page 29), among
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Functional Description
these options, are additional clock configuration bits - PCI_MODCKH(0:3) - the most significant
bits of the MODCK field, which determine additional options for the clock generator. Although
these bits are sampled whenever the hard-reset sequence is entered, they are influential only once
- after power-on reset. If a hard reset sequence is entered later, MODCKH(0:3), although
sampled, are don’t care.
The PCI_MODCK signal, which is sampled concurrently with the PCI_MODCK(0:3) pins,
determines the PCI bus clock frequency (see Section 2.3.7). When set high, it divides the PCI bus
frequency by two. When reset low, the PCI bus frequency is as determined by the MODCK(1:3)
and PCI_MODCKH(0:3) signals.
4.1.2 Hard Reset
Hard-Reset may be generated on the ADS by the following sources:
1. COP/JTAG Port
2. Manual Hard reset.
3. PQ2’s internal sources.
Hard-Reset, when generated, causes the PQ2 to reset all its internal hardware except for PLL
logic, re-acquires the Hard-reset configuration from its current source, and jumps to the Reset
vector in the exception table. Since hard-reset resets also the refresh logic for dynamic RAMs,
their content is lost as well.
HRESET when asserted, is extended internally by the PQ2 for additional 512 bus clock cycles at
the end of which, the PQ2 waits for 16 bus clock cycles and then, re-checks the state of the
HRESET line.
HRESET is an open-drain signal and must be driven with an open-drain gate by which ever
external source is driving it. Otherwise, contention will occur over that line, which might cause
permanent damage to either board logic and/or to the PQ2 itself.
4.1.2.1 COP/JTAG Port Hard - Reset
To provide convenient hard-reset capability for a COP/JTAG controller, HRESET line appears at
the COP/JTAG port connector. The COP/JTAG controller may directly generate hard-reset by
asserting (low) this line.
4.1.2.2 Manual Hard Reset
To allow run-time Hard-reset, when the COP controller is disconnected from the PQ2FADS-ZU
and to support resident debuggers, manual Hard is facilitated. Depressing both Soft-Reset (SW3)
and ABORT (SW2) buttons asserts the HRESET pin of the PQ2, generating a HARD RESET
sequence.
Since the HRESET line may be driven internally by the PQ2, it must be driven to the PQ2 with an
open-drain gate. If off-board H/W connected to the PQ2FADS-ZU is to drive HRESET line, then
it should do so with an open-drain gate, this, to avoid contention over this line.
When Hard Reset is generated, the PQ2 is reset in a destructive manner, i.e., the hard reset
configuration is re-sampled and all registers (except for the PLL’s) are reset, including memory
controller registers - reset of which results in a loss of dynamic memory contents.
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To save on board’s real-estate, this button is not a dedicated one, but is shared with the Soft-Reset
button and the ABORT button - when both are depressed, Hard Reset is generated.
4.1.2.3 Internal Sources Hard - Reset
The PQ2 has internal sources which generate Hard Reset. Among these sources are:
1. Loss of Lock Reset. When one of the PLLs (Core, CPM), is out of lock, hard-reset is gen-
erated.
2. Check-Stop Reset. When the core enters a Check-Stop state from some reason, hard-reset
may be generated, depended on CSRE bit in the RMR.
3. Bus Monitor Reset. When the bus monitor is enabled and a bus cycle is not terminated,
hard-reset is generated.
4. S/W Watch Dog Reset. When the S/W watch-dog is enabled, and application s/w fails to
perform its reset routine, it will generate hard - reset.
5. COP/JTAG Reset (Internal). Hard reset may be forced by driving the HRESET line via the
external pin’s scan chain. Not useful for run time.
In general, the PQ2 asserts a reset line HARD or SOFT for a period 512 clock cycles after a reset
source has been identified. A hard reset sequence is followed by a soft reset sequence.
4.1.2.4 Hard Reset Configuration
When Hard-Reset is applied to the PQ2 (externally as well as internally), it samples the Hard-
Reset configuration word. This configuration may be taken from an internal default, in case
1
2
RSTCONF is negated during HRESET asserted or taken from the Flash /E PROM/BCSR (MS 8
bits of the data bus) in case RSTCONF signal is asserted along with HRESET. The default
2
configuration word can be taken from the E PROM/BCSR in case the Flash has been tampered
2
with. The selection between the BCSR, FLASH and the E PROM as the source of the default
configuration word is determined by a dedicated dip-switch (see Section 2.3.5) and a jumper (see
Section 2.3.4).
2
2
During hard reset sequence, the configuration master reads the Flash (or E PROM or BCSR)
memory at addresses 0, 8, 0x18, 0x20,... a byte each time, to assemble the 32 bit configuration
word. A total of 64 bytes of data is read from D(0:7) to acquire 8 full configuration words for
system that may have upto 8 PQ2 chips.
3
2
The configuration word for a single PQ2 is stored in the Flash memory SIMM, in the E PROM
or as default in the BCSR, while the other seven words are not initialized, as there are no
additional PQ2 on the PQ2FADS-ZU. The default configuration word is shown in Table 4-1. for
2
the FLASH and in Table 4-2. for the E PROM. PCI module configuration is 256 Bytes long and
should start at address 0x100.
There are four possible configuration words:
1. In general, from any device residing on CS0.
2. In general, The PQ2 for which RSTCONF is asserted along with PORST asserted or in particular, the
PQ2 residing on the PQ2FADS-ZU.
3. Although the PQ2 as configuration master reads 8 configuration words, only the 1’st configuration word
is influential.
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Functional Description
•
PQ2FADS-ZU without L2 Cache - FLASH/BCSR is the boot device. CS0 is assigned to
the FLASH and CS4 is assigned to the E PROM.
2
2
•
•
PQ2FADS-ZU without L2 Cache - E PROM is the boot device. CS0 is assigned to the
2
E PROM and CS4 is assigned to the FLASH.
PQ2FADS-ZU with L2 Cache - FLASH is the boot device. CS0 is assigned to the FLASH
and CS4 is assigned to the E PROM.
2
2
•
PQ2FADS-ZU with L2 Cache - E PROM is the boot device. CS0 is assigned to the
2
E PROM and CS4 is assigned to the FLASH.
.
Table 4-1. BCSR/FLASH Hard Reset Configuration Word
Data
Bus
Bits
Prog
Value
[Bin]
Offset In
Flash
[Hex]
Value
[Hex]
Field
Implication
ERB
0
1
’0’
’0’
Internal Arbitration Selected.
0
0C / 1Ca
EXMC
Internal Memory Controller. CS0 active at
system boot.
CDIS
EBM
2
3
’0’
Core Enabled.
’0’ /’1’
‘0’ - Single PQ2 Mode for boards without
L2Cache
‘1’ - 60X Bus Modea for boards with L2Cache
BPS
CIP
4:5
6
11
’0’
32 Bit Boot Port Size
Sets Core Initial Prefix MSR[IP]=1, so that
system exception table is placed at address
0xFFF00100 regardless of FLASH memory
size
ISPS
7
‘0’
64 bit internal space for external master
accesses. In fact don’t care on this board since
external master is not supported.
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Functional Description
Table 4-1. BCSR/FLASH Hard Reset Configuration Word
Data
Bus
Bits
Prog
Value
[Bin]
Offset In
Flash
[Hex]
Value
[Hex]
Field
Implication
L2CPC
8:9
‘10’
CI/BADDR(29)/IRQ2 selected as BADDR(29)
WT/BADDR(30)/IRQ3 selected as BADDR(30)
L2_HIT/IRQ4 selected as unassigned
8
B2
CPU_BG/BADDR(31)/IRQ5 as BADDR(31)
DPPC
10:11
‘11’
Data Parity Pin configuration as:
DP0 as EXT_BR2
DP1 as EXT_BG2
DP2 as EXT_DBG2
DP3 as EXT_BR3
DP4 as EXT_BG3
DP5 as EXT_DBG3
DP6 as IRQ6
DP7 as IRQ7
Reserved
ISB
12
’0’
Reserved.
13:15
’010’
IMMR initial value 0x0F000000, i.e., the
internal space resides initially at this address.
BMS
BBD
16
17
’0’
’0’
Boot memory (Flash) at 0xFE000000.
10
36 / 02b
ABB/IRQ2 pin is ABB
DBB/IRQ3 pin is DBB
MMR
LBPC
APPC
18:19
20:21
22:23
’11’/’00’ ‘11’ - Mask Masters Requests. Boot Master is
PCI when PCI is enabled in the FLASH.
‘00’ - No masking, Local Bus SDRAM mode in
the BCSR.
’01’/’00’ ‘11’ - Local Bus pins function as PCI bus
(FLASH).
‘00’ - Local Bus pins function as Local Bus
(BCSR).
’10’
MODCK1/AP(1)/TC(0) functions as BKSEL0
MODCK2/AP(2)/TC(1) functions as BKSEL1
MODCK3/AP(3)/TC(2) functions as BKSEL2
IRQ7~/APE~ functions as IRQ7~
CS11~/AP(0) functions as CS11~
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Table 4-1. BCSR/FLASH Hard Reset Configuration Word
Data
Bus
Bits
Prog
Value
[Bin]
Offset In
Flash
[Hex]
Value
[Hex]
Field
Implication
CS10PC
24:25
26
’01’
’0’
CS10~/BCTL1/DBG_DIS~ functions as BCTL1
18
45
ALD_EN
PCI Auto Load Enable. When high, PCI Bridge
Configuration is done automatically from the
FLASH/E2PROM (CPM is configuration master
- PPC core should be disabled) right after the
Hard Configuration Word. When low, the PPC
Core should configure the PCI Bridge.
Reserved
27
’0’
Reserved.
MODCK_HIc
28:31
‘0101’
Determines the Core’s frequency out of power-
up reset. Actually, not relevant when the PCI is
active since the PCI_MODCK(0:3) take
presidency.
a. For L2 Cache Boards.
b. BCSR is set for no PCI configuration
c. Applies only ONCE after power-up reset.
2
Table 4-2. E PROM Hard Reset Configuration Word
Data
Bus
Bits
Prog
Value
[Bin]
Offset In
Flash
[Hex]
Value
[Hex]
Field
Implication
ERB
0
1
’0’
’0’
Internal Arbitration Selected.
0
04 / 14a
EXMC
Internal Memory Controller. CS0 active at
system boot.
CDIS
EBM
2
3
’0’
Core Enabled.
’0’ /’1’
‘0’ - Single PQ2 Mode for boards without
L2Cache
‘1’ - 60X Bus Modea for boards with L2Cache
BPS
CIP
4:5
6
‘01’
’0’
8 Bit Boot Port Size
Sets Core Initial Prefix MSR[IP]=1, so that
system exception table is placed at address
0xFFF00100 regardless of FLASH memory
size
ISPS
7
‘0’
64 bit internal space for external master
accesses. In fact don’t care on this board since
external master is not supported.
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2
Table 4-2. E PROM Hard Reset Configuration Word
Data
Bus
Bits
Prog
Value
[Bin]
Offset In
Flash
[Hex]
Value
[Hex]
Field
Implication
L2CPC
8:9
‘10’
CI/BADDR(29)/IRQ2 selected as BADDR(29)
WT/BADDR(30)/IRQ3 selected as BADDR(30)
L2_HIT/IRQ4 selected as unassigned
8
B2
CPU_BG/BADDR(31)/IRQ5 as BADDR(31)
DPPC
10:11
‘11’
Data Parity Pin configuration as:
DP0 as EXT_BR2
DP1 as EXT_BG2
DP2 as EXT_DBG2
DP3 as EXT_BR3
DP4 as EXT_BG3
DP5 as EXT_DBG3
DP6 as IRQ6
DP7 as IRQ7
Reserved
ISB
12
’0’
Reserved.
13:15
’010’
IMMR initial value 0x0F000000, i.e., the
internal space resides initially at this address.
BMS
BBD
16
17
’0’
’0’
Boot memory (E2PROM) at 0xFE000000.
10
36
ABB/IRQ2 pin is ABB
DBB/IRQ3 pin is DBB
MMR
LBPC
APPC
18:19
20:21
22:23
’11’
’01’
’10’
Mask Masters Requests. Boot Master is PCI.
Local Bus pins function as PCI bus.
MODCK1/AP(1)/TC(0) functions as BKSEL0
MODCK2/AP(2)/TC(1) functions as BKSEL1
MODCK3/AP(3)/TC(2) functions as BKSEL2
IRQ7~/APE~ functions as IRQ7~
CS11~/AP(0) functions as CS11~
CS10PC
ALD_EN
24:25
26
’01’
’0’
CS10~/BCTL1/DBG_DIS~ functions as BCTL1
18
45
PCI Auto Load Enable. When high, PCI Bridge
Configuration is done automatically from the
FLASH/E2PROM (CPM is configuration source
- PPC core should be disabled) right after the
Hard Configuration Word. When low, the PPC
Core should configure the PCI Bridge.
Reserved
27
’0’
Reserved.
MODCK_HIb
28:31
‘0101’
Determines the Core’s frequency out of power-
up reset. Actually, not relevant when the PCI is
active since the PCI_MODCK(0:3) take
presidency.
a. For L2 Cache Boards.
b. Applies only ONCE after power-up reset.
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The PCI configuration registers which are set at Hard-Reset sequence are shown in Figure 4-1.
Address
Offset (Hex)
Reserved
Device ID (0x18C0)
PCI Status
Vendor ID (0x1057)
PCI Command
00
04
08
0C
10
14
18
Class Code
BIST Control
Subclass Code
Header Type
Standard Programming
Latency Timer
Revision ID
Cache Line Size
PIMMR Base Address Register
Subsystem ID
Subsystem Vendor ID
2C
34
38
3C
40
44
Capability Pointer
/ / / / / / / /
MAX LAT
MIN GNT
Interrupt Pin
Interrupt Line
/ / / / / / / /
PCI Arbiter Control
PCI Function
Figure 4-1. PCI Host Configuration Registers
4.1.3 Soft Reset
Soft - Reset may be generated on the board from the below sources:
1. COP/JTAG Port
2. Manual Soft Reset
3. Internal PQ2 source.
Soft-Reset, when generated, causes the PQ2 to reset its internal logic, while keeping its hard-reset
configuration and memory controller setup and then jumping to the Reset vector in the exception
table. Since soft-reset does not reset the refresh logic for dynamic RAMs, their contents is
preserved.
SRESET when asserted, is extended internally by the PQ2 for an additional 512 bus clock cycles
at the end of which, the PQ2 waits for 16 bus clock cycles and then, re-checks the state of the
SRESET line.
SRESET is an open-drain signal and must be driven with an open-drain gate by every external
source driving it. Otherwise, contention will occur over that line, which might cause permanent
damage to either the boards’ logic and / or to the PQ2 itself.
4.1.3.1 COP/JTAG Port Soft - Reset
To provide convenient soft-reset capability for a COP/JTAG controller, SRESET line appears at
the COP/JTAG port connector - P3. The COP/JTAG controller may directly generate Soft-reset by
asserting (low) this line.
4.1.3.2 Manual Soft Reset
To allow run-time Soft-reset, when the COP controller is disconnected from the PQ2FADS-ZU
and to support resident debuggers, a Soft Reset push-button is provided. When the Soft Reset
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Functional Description
push-button is depressed, the SRESET line is asserted to the PQ2, generating a Soft Reset
sequence.
Since the SRESET line may be driven internally by the PQ2, it must be driven by an open-drain
gate, to avoid contention over that line. If off-board H/W connected to the PQ2FADS-ZU is to
drive SRESET line, then, it should do so with an open-drain gate, this, to avoid contention over
this line.
4.1.3.3 Internal Sources Soft - Reset
The only internal Soft-reset source is the COP/JTAG soft-reset, which may be generated using
Public JTAG instructions to shift active-value (‘0’) to the SRESET pin via the boundary scan
chain. This is not useful for run time.
4.1.4 PCI Bus Reset
The PCI Module in the PQ2 can generate a reset signal dedicated for PCI devices which reside on
the PCI bus. This is a reset to the PCI bus which is initiated by the PCI bus Host - the PQ2 on this
board. This reset can also be initiated by a Soft PCI Reset by setting a dedicated bit in a PCI
control register (consult the PQ2 User Manual for details).
4.2
Local Interrupter
There are external interrupts which are applied to the PQ2 via its interrupt controller:
1. ABORT (NMI)
2. ATM UNI interrupt
3. Fast Ethernet PHY Interrupt
4. PCI interrupt
4.2.1 ABORT Interrupt
The ABORT (NMI), is generated by a push-button. When this button is depressed, the IRQ0
input to the PQ2 is asserted. The purpose of this type of interrupt, is to support the use of resident
debugger if any is made available to the board. This interrupt is enabled by setting the MSR[EE]
bit.
To support external (off-board) generation of an NMI, the IRQ0 line, is driven by an open-drain
gate. This allows for an external h/w, to also drive this line. If an external h/w indeed does so, it is
compulsory that IRQ0 is driven by an open-drain (or open-collector) gate.
4.2.2 ATM UNI Interrupt
To support ATM UNI (User Network I/F) event report by means of interrupt, the interrupt output
of the UNI (INTB) is connected to IRQ7 line of the PQ2. This IRQ7 input is shared with the Fast
Ethernet PHY Interrupt. Since INTB of the UNI is an open-drain output, it is possible to connect
additional (on and off-board) interrupt requesters on the same IRQ7, provided that they drive
IRQ7 with open-drain gate as well. When an interrupt request appears in IRQ7, it is necessary to
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check the source of the interrupt whether it’s the ATM UNI or the Fast Ethernet PHY.
4.2.3 Fast Ethernet PHY Interrupt
To support the two fast Ethernet Transceivers event reports by means of interrupt, the interrupt
outputs of the DM9161 are connected to IRQ7 line of the PQ2. This IRQ7 input is shared with the
ATM UNI Interrupt.
4.2.4 PCI Interrupt
Each PCI slot can generate up to four interrupts to a total of twelve (3 slot x 4 interupts each).
Each PCI expansion board can generate an interrupt at any given time. Since there is only one
interrupt input available in the PQ2, an Interrupt Controller is used. The Interrupt Controller
receives all the possible interrupts from the PCI slots and generate one interrupt (IRQ6) to the
PQ2.
A simple generic Interrupt Controller is implemented using a CPLD device. The Interrupt
Controller is implemented as an Interrupt Register and an Interrupt Mask Register. The Interrupt
Controller has its’ own dedicated chip-select line (CS8). A simple priority scheme is devised to
prioritize the interrupts from different slots. The PCI IRQ routing are according to Figure 4-2..
SLOT
0
SLOT
1
SLOT
2
PQ2
DATA
A
B
C
D
A
B
C
D
A
B
C
D
INTA
INTB
INTC
INTD
ADDRESS
CONTROL
PCI
Interrupt
Controller
IRQ
IRQ6
Figure 4-2. PCI Interrupt Routing Scheme
An interrupt request in any of the INTx lines, will set three interrupt bits in the PCI Interrupt
Register (if not masked in the Interrupt Mask Register) since there are three possible interrupt
sources for every INTx line. It is up to the user to implement a polling process to verify the real
interrupt source (by polling the Interrupt Pending bit in the PCI device) and clear the other two.
The PCI Interrupt Register can be read at any time and accessed at offset 0x0 from CS8 base
address. The description of the PCI Interrupt Register is in Table 4-3..
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Table 4-3. PCI Interrupt Register Description
PON
DEF
BIT
MNEMONIC
Function
ATT.
0
PCI0_INTA
PCI Slot 0 INTA. PCI Slot 0 Interrupt A:
‘0’ - no interrupt was requested
‘1’ - an interrupt was requested and waiting to be handled
0
R
R
1
PCI0_INTB
PCI0_INTC
PCI0_INTD
PCI1_INTA
PCI1_INTB
PCI1_INTC
PCI1_INTD
PCI2_INTA
PCI2_INTB
PCI2_INTC
PCI2_INTD
Reserved
PCI Slot 0 INTB. PCI Slot 0 Interrupt B:
‘0’ - no interrupt was requested
‘1’ - an interrupt was requested and waiting to be handled
0
0
0
0
0
0
0
0
0
0
0
2
PCI Slot 0 INTC. PCI Slot 0 Interrupt C:
‘0’ - no interrupt was requested
‘1’ - an interrupt was requested and waiting to be handled
R
3
PCI Slot 0 INTD. PCI Slot 0 Interrupt D:
‘0’ - no interrupt was requested
‘1’ - an interrupt was requested and waiting to be handled
R
4
5
PCI Slot 1 INTA. PCI Slot 1 Interrupt A:
‘0’ - no interrupt was requested
‘1’ - an interrupt was requested and waiting to be handled
R
PCI Slot 1 INTB. PCI Slot 1 Interrupt B:
‘0’ - no interrupt was requested
‘1’ - an interrupt was requested and waiting to be handled
R
6
PCI Slot 1 INTC. PCI Slot 1 Interrupt C:
‘0’ - no interrupt was requested
‘1’ - an interrupt was requested and waiting to be handled
R
7
PCI Slot 1 INTD. PCI Slot 1 Interrupt D:
‘0’ - no interrupt was requested
‘1’ - an interrupt was requested and waiting to be handled
R
8
PCI Slot 2 INTA. PCI Slot 2 Interrupt A:
‘0’ - no interrupt was requested
‘1’ - an interrupt was requested and waiting to be handled
R
9
PCI Slot 2 INTB. PCI Slot 2 Interrupt B:
‘0’ - no interrupt was requested
‘1’ - an interrupt was requested and waiting to be handled
R
10
11
12-31
PCI Slot 2 INTC. PCI Slot 2 Interrupt C:
‘0’ - no interrupt was requested
‘1’ - an interrupt was requested and waiting to be handled
R
PCI Slot 2 INTD. PCI Slot 2 Interrupt D:
‘0’ - no interrupt was requested
‘1’ - an interrupt was requested and waiting to be handled
R
Un-implemented
R/W
Also available is an Interrupt Mask Register which provides the user with the option to mask any
of the possible PCI interrupt sources. It can be read or written at any time and accessed at offset
0x4 from CS8 base address.The description of the PCI Interrupt Mask Register is in Table 4-4..
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Functional Description
Table 4-4. PCI Interrupt Mask Register Description
PON
DEF
BIT
MNEMONIC
Function
ATT.
0
MPCI0_INTA
Mask PCI Slot 0 INTA. Mask PCI Slot 0 Interrupt A:
‘0’ - interrupt is available
‘1’ - interrupt is masked
0
0
0
0
0
0
0
0
0
0
0
0
R/W
1
MPCI0_INTB
MPCI0_INTC
MPCI0_INTD
MPCI1_INTA
MPCI1_INTB
MPCI1_INTC
MPCI1_INTD
MPCI2_INTA
MPCI2_INTB
MPCI2_INTC
MPCI2_INTD
Reserved
Mask PCI Slot 0 INTB. Mask PCI Slot 0 Interrupt B:
‘0’ - interrupt is available
‘1’ - interrupt is masked
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
2
Mask PCI Slot 0 INTC. Mask PCI Slot 0 Interrupt C:
‘0’ - interrupt is available
‘1’ - interrupt is masked
3
Mask PCI Slot 0 INTD. Mask PCI Slot 0 Interrupt D:
‘0’ - interrupt is available
‘1’ - interrupt is masked
4
5
Mask PCI Slot 1 INTA. Mask PCI Slot 1 Interrupt A:
‘0’ - interrupt is available
‘1’ - interrupt is masked
Mask PCI Slot 1 INTB. Mask PCI Slot 1 Interrupt B:
‘0’ - interrupt is available
‘1’ - interrupt is masked
6
Mask PCI Slot 1 INTC. Mask PCI Slot 1 Interrupt C:
‘0’ - interrupt is available
‘1’ - interrupt is masked
7
Mask PCI Slot 1 INTD. Mask PCI Slot 1 Interrupt D:
‘0’ - interrupt is available
‘1’ - interrupt is masked
8
Mask PCI Slot 2 INTA. Mask PCI Slot 2 Interrupt A:
‘0’ - interrupt is available
‘1’ - interrupt is masked
9
Mask PCI Slot 2 INTB. Mask PCI Slot 2 Interrupt B:
‘0’ - interrupt is available
‘1’ - interrupt is masked
10
11
12-31
Mask PCI Slot 2 INTC. Mask PCI Slot 2 Interrupt C:
‘0’ - interrupt is available
‘1’ - interrupt is masked
Mask PCI Slot 2 INTD. Mask PCI Slot 2 Interrupt D:
‘0’ - interrupt is available
‘1’ - interrupt is masked
Un-implemented
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4.3
Clock Generator
There are two main clock circuits on board:
1. PQ2 System Clock
2. PCI Clock
4.3.1 PQ2 Clock
The PQ2 requires a single clock source as the main clock source. All PQ2 60x bus timings are
referenced to the main clock input - CLKIN1. The main clock input is in 1:1 ratio to the bus clock,
with internal skew elimination (PLL). Use is done with 66MHz (for Hip3 and Hip4 devices) 3.3V
clock oscilator (100MHz for Hip7 device), which is connected to a low inter-skew buffer (U39)to
split the load between all various clock consumers on both boards.
Special care is taken to isolate and terminate the clock route between the on-board PLL and the
PQ2, this to provide a "clean" clock input for proper operation. The main clock scheme is shown
in Figure 4-3.
PQ2
CLOCK GEN.
66 MHZ
60x SDRAM
BCSR
Low
Skew
Buffers
L2CACHE
EXPANSION
MICTOR
LB SDRAM
Figure 4-3. Main Clock Generator Scheme
4.3.2 PCI Clock
The PCI bus clock is derived internally from the main clock input CLKIN1. The generated PCI
clock is output from a PCI-dedicated PLL (named DLL). That clock output is feeding an on-board
low-skew and fast (low propagation delay PLL) clock distributor which distributes the PCI clock
to all on-board PCI devices. One of the outputs is fed back to the PCI clock to the PQ2 through
CLKIN2 input. This clock input is driven to the DLL which synchronizes the DLL output clock to
the CLKIN2 input clock and thus, maintains low skew between the DLL output and CLKIN2
input. All PCI bus timings are referenced to the CLKIN2 input clock. Special care was taken
when the board layout was done to keep all copper traces away from the Clock Distributor outputs
at the same lengths, including the output that is fed back to CLKIN2. This is in compliance with
the PCI standard to achieve bus synchronization and low skew. The PCI clock scheme is shown in
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Figure 4-4.
Low Skew PLL
PQ2
PCI Device
OUT1
#1
DLLOUT
CLKIN1
CLKIN2
IN
CLOCK GEN.
66 MHZ
PCI Device
#2
OUT2
OUT3
OUT4
PCI Device
#3
Figure 4-4. PCI Clock Generator Scheme
4.4
Bus Configuration
The PQ2 may be configured in 2 possible bus modes depending on the presence of L2 cache on
board.
1. Single PQ2 Mode
2. 60X Bus Mode.
4.4.1 Single PQ2 Mode
When a L2 Cache is not present on the board, the PQ2 is configured in Single PQ2 Mode. I.e.,
assuming only one PQ2 on the 60x bus, with no support for external master access. This allows
for internal address multiplexing to occur which makes the external address multiplexers
redundant and therefore not assembled. This improves SDRAM performance.
4.4.2 60X Bus Mode
When L2 Cache is installed on the PQ2FADS-ZU, the PQ2 may no longer operate in single PQ2
mode since the address must be seen as is by the cache. That requires the use of the external
address multiplexers for the SDRAM. In this mode, SDRAM performance is decreased due to
added wait-state, caused by the delay associated with the external multiplexers, on the 1’st access
in a page,.
NOTE
In this mode, only devices which are 60x com-
patible (or devices which have 64 bit data bus
and are buffered from the 60x bus) can operate
on the 60x bus. This due to the 60x bus address
tenure feature. This means that when the L2
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Cache is used, the Flash, EEPROM, BCSR and
PCI Interrupt Controller are not accesible. For
further details, consult the PQ2 User Manual.
4.5
Buffering
In order to achieve best performance, it is necessary to reduce the capacitive load over the 60X
bus as much as possible. Therefore, the slower devices on the bus, i.e., the Flash SIMM,
2
E PROM, ATM UNI M/P interface, PCI Interrupt Controller and the BCSR are buffered, while
the SDRAM and the cache are not buffered from the 60X bus.
Latches are provided over address and strobe (when necessary) lines while transceivers are
provided for data. Use is done with 74ALVT buffers (by Philips) which are 3.3V operated and 5V
1
tolerant and provide bus hold to reduce pull-up/pull-down resistors count (as required by the
PQ2). This type of buffers reduces noise on board due to reduced transitions’ amplitude.
To further reduce noise and reflections, serial damping resistors are placed over SDRAM address
and all PQ2 strobe lines.
2
The data transceivers are open only if there is an access to a valid buffered board address or
3
during Hard - Reset configuration . That way data conflicts are avoided in case an unbuffered
memory read or off-board memory is read - provided that it is not mapped to an address valid on
board. It is the users’ responsibility to avoid such errors.
On the Local bus, Bus Muxing devices are used to direct the local bus signal to either PCI slots or
SDRAM (according to the local bus functionality) and therfore no use of buffers is done.The PCI
bus is not buffered at all because the PCI Standard is very strict and defines exactly the electrical
characteristics of the bus which is buffer free.
4.6
Chip - Select Generator
The memory controller of the PQ2 is used as a chip-select generator to access on-board (and off-
board) memories, saving boards’ area, reducing cost, power consumption and increasing
flexibility. To enhance off-board application development, memory modules (including the
4
BCSRx) may be disabled via BCSR in favor of an external memory connected via the expansion
connectors. That way, a CS line may be used off-board via the expansion connectors, while its
associated local memory is disabled.
5
When a CS region, assigned to a buffered memory, is disabled via BCSR, the local data
1. Required for Flash, E2PROM, Interrupt Controller and BCSR
2. An address which is covered in a Chip-Select region, that controls a buffered device.
3. To allow a configuration word stored in the Flash/E2PROM memory to become active.
4. After the BCSR is removed from the local memory map, there is no way to access it but to re-apply
power to the PQ2FADS-ZU.
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Functional Description
1
transceivers are disabled during access to that region, avoiding possible contention over data
lines.
The PQ2 chip-select assignments to the various memories / registers on the PQ2FADS-ZU are
shown in Table 4-5.
Table 4-5. PQ2FADS-ZU Chip Select Assignments
Chip
Select:
Timing
Machine
Assignment
Bus
Flash SIMM / E2PROMa
BCSR
CS0
60X (Buffered)
GPCM
CS1
CS2
CS3
CS4
60X (Buffered)
60X (Main)
GPCM
SDRAM
SDRAM Machine 1
SDRAM Machine 2
GPCM
SDRAM
Local Bus
E2PROM / Flash SIMMa
60X (Buffered)
CS5
CS6
ATM UNI Microprocessor I/F
60X (Main)
GPCM
Communication Tool M/P
Interface CS1.
60X (Buffered)
GPCM/UPMx
CS7
Communication Tool M/P
Interface CS2.
60X (Buffered)
GPCM/UPMx
CS8
PCI Interrupt Controller
Unused, user available
60X (Buffered)
-
GPCM
-
CS(9-11)
a. Selection is done by a dip-switch.
4.7
Synchronous Dram (60X Bus)
To enhance performance, especially in higher operation frequencies - 32MBytes of SDRAM are
provided on board. The SDRAM is unbuffered from the PQ2 60X bus. Use is done with two
MTLC4M32B2 by Micron or compatibles, which each is 1M X 32bit X 4banks.
The SDRAM’s timing is controlled by SDRAM Machine #1 associated with 60X bus, via its
assigned Chip Select lines (See Table 4-5.). The SDRAM Machine supports PBI (Page Bank
Interleave) which increases the SDRAM throughput. The SDRAM connection scheme when no
5. When an unbuffered CS region is being accessed, buffers do not open anyway.
1. During read cycles.
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L2 cache is used is shown in Figure 4-5.
CS2
CS0
RAS
SDRAS
SDCAS
SDWE
CAS
WE
BANKSEL(1:2)
BA(1:0)
A11
A17
SDA10
A10
A9
A19
A(20:28)
A(8:0)
SDDQM(0:7)
D(0:63)
DQMB(0:7)
DQ(0:63)
CKE
CLK
SYSCLK
MT48LC4M32B2-6
Figure 4-5. 60x SDRAM Connection Scheme - No L2 Cache
The SDRAM connection scheme when L2 cache is installed is shown in Figure 4-6.
MT48LC4M32B2-6
CS2
CS0
SDRAS
SDCAS
RAS
CAS
SDWE
WE
LATCH
BANKSEL(1:2)
BA(1:0)
A(28..21)
SDRMA11
A11
A10
PSDA10
A(6:28)
ALE
SDRMA9
SDRMA(8:0)
A9
LE
A(8:0)
A(18..6)
SDDQM(0:7)
D(0:63)
DQMB(0:7)
DQ(0:63)
PSDAMUX
CKE
CLK
CLK
Figure 4-6. SDRAM - 60x Bus Connection Scheme with L2 Cache
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Functional Description
4.7.1 SDRAM Programming
After power-up, the SDRAM needs to be initialized by means of programming to establish its
mode of operation. The SDRAM is programmed according to the following procedure:
1. Issue Precharge-All command
2. Issue 8 CBR refresh commands
3. Issue MODE-SET command.
An SDRAM is programmed by issuing a Mode Register Set command. During that command,
data is passed to the Mode Register through the SDRAMs’ address lines. This command is fully
supported by the SDARM machine of the PQ2. Before that can take place, the SDRAM machine
of the PQ2 has to be initialized.
Mode Register programming values are shown in Table 4-6.:
Table 4-6. 100 MHz SDRAM Mode Register Programming
SDRAM
SDRAMMode
Address
Value
Meaning:
Reg Field
a
Line
A11 (MSB)
A10
Reserved
Reserved
Opcode
’0’
’0’
A9
’0’ / ’1’
0 - Burst Read & Burst Write (Copy-Back data cache)
1 - Burst Read & Single Write (Write-Through Data cache)
A8
A7
Reserved
Reserved
’0’
’0’
A6 - A4
A3
CAS Latency
Burst Type
Burst Length
’011’
’0’
Data Valid 3 Clocks cycles after CAS Asserted
Sequential Burst
A2 - A0
’010’
4 Operand Burst Length
a. Actually SDRAMs’ A0 is connected to PQ2s’ A28 and so on...
4.7.2 SDRAM Refresh
The SDRAM is refreshed using its auto-refresh mode. I.e., using SDRAM machine one’s periodic
timer, an auto-refresh command is issued to the SDRAM every 8.2 µsec, so that all 4096 SDRAM
rows are refreshed within specified 34 msec, while leaving an interval of ~30 msec of refresh
redundancy within that window, as a safety measure, to cover for possible delays in bus
availability for the refresh controller.
4.7.3 L2-Cache Support Influence On SDRAM Design
To support an optional L2-Cache on the PQ2FADS-ZU, the following measures need to be taken:
1. Optional Latches - Multiplexers are added over selected address lines. See Figure 4-6.
These Latches - Multiplexers are normally by-passed by 0 Ω resistors that are not assem-
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bled in L2cache boards.
2. The PQ2 supports additional wait-state on SDMUX line, so that the row-address may be
allowed to propagate via the Latch - Multiplexers in time for the Activate command.
3. To support SDRAM PBI (Page Based Interleaving), the relative location of the Row-
Address field, is shifted up the address lines, depended on the number of internal banks
within an SDRAM. This since the Bank Select line(s) are inserted between the Column
(LSB) and Row (MSB) address lines.
4. The L2 Cache used is the MPC2605. This device can operate at maximum speed of
66MHz. Therefore, the USE OF L2 CACHE WILL LIMIT THE 60X BUS
FREQUENCY TO 66MHZ ONLY (compared to 100MHz without L2 Cache - for the
MPC8280).
The performance of the SDRAM is decreased by the addition of the external multiplexers of the
SDRAMs’ address lines.
4.7.4
SDRAM Error Correction Support
The PQ2FADS-ZU has an optional support for Parity Error Correction for SDRAM accesses. To
support that option, the DP(0:7) lines are connected to the SDRAM DP(0:7) lines. Since the PQ2
muxes DP(0:7) signals with other signals, bus switch is used to select between DP(0:7) signals
and other functions.
PQ2
60x SDRAM
DP0/EXT_BR2
DP1/EXT_BG2
DP2/EXT_DBG2
DP3/EXT_BR3
DP4/EXT_BG3
DP5/EXT_DBG3
DP6/IRQ6
DP(0:7)
DP(0:7)
EXT_BR2
EXT_BG2
EXT_DBG2
EXT_BR3
EXT_BG3
EXT_DBG3
IRQ6
EXT/IRQ
DP7/IRQ7
IRQ7
Figure 4-7. 60x SDRAM Data Parity Support
NOTE: When using the Data Parity option, IRQ6 and IRQ7 pins change functionality to
Data Parity pins. Therfore, the two interrupt lines are switched to IRQ2 and IRQ3
so the user should be aware and switch to work with the relevant IRQs. To be able
to work with IRQ2 and IRQ3, this function must be enabled in SIUMCR register.
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4.8
Synchronous Dram (Local Bus)
To enhance performance, especially in higher operation frequencies - 8MBytes of SDRAM are
provided on board. The SDRAM is unbuffered from the PQ2 local bus. Use is done with one
MTLC2M32B2 by Micron or compatibles, which each is 512K X 32bit X 4banks.
The SDRAM’s timing is controlled by SDRAM Machine #2 associated with local bus, via its
assigned Chip Select lines (See Table 4-5.). The SDRAM Machine supports PBI (Page Bank
Interleave) which increases the SDRAM throughput. The SDRAM connection scheme is shown
in Figure 4-8.
CS3
CS0
LSDRAS
RAS
LSDCAS
CAS
LSDWE
WE
LA(17:18)
BA(1:0)
LSDA10
A10
LA20
A9
A(21:29)
A(8:0)
LSDDQM(0:3)
DQMB(0:3)
D(0:63)
DQ(0:63)
CKE
SYSCLK
CLK
MT48LC2M32B2-6
Figure 4-8. Local Bus SDRAM Connection Scheme
4.8.1 Local Bus SDRAM Programming
After power-up, the SDRAM needs to be initialized by means of programming to establish its
mode of operation. The SDRAM is programmed according to the following procedure:
1. Issue Precharge-All command
2. Issue 8 CBR refresh commands
3. Issue MODE-SET command.
An SDRAM is programmed by issuing a Mode Register Set command. During that command,
data is passed to the Mode Register through the SDRAMs’ address lines. This command is fully
supported by the SDARM machine of the PQ2. Before that can take place, the SDRAM machine
of the PQ2 has to be initialized.
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Mode Register programming values are shown in Table 4-6.:
Table 4-7. 100 MHz SDRAM Mode Register Programming
SDRAM
Address
SDRAMMode
Value
Meaning:
Reg Field
a
Line
A11 (MSB)
A10
Reserved
Reserved
Opcode
’0’
’0’
A9
’0’ / ’1’
0 - Burst Read & Burst Write (Copy-Back data cache)
1 - Burst Read & Single Write (Write-Through Data cache)
A8
A7
Reserved
Reserved
’0’
’0’
A6 - A4
A3
CAS Latency
Burst Type
Burst Length
’011’
’0’
Data Valid 3 Clocks cycles after CAS Asserted
Sequential Burst
A2 - A0
’011’
8 Operand Burst Length
a. Actually SDRAMs’ A0 is connected to PQ2s’ LA29 and so on...
4.8.2 SDRAM Refresh
The SDRAM is refreshed using its auto-refresh mode. I.e., using SDRAM machine one’s periodic
timer, an auto-refresh command is issued to the SDRAM every 8.2 µsec, so that all 2096 SDRAM
rows are refreshed within specified 17 msec, while leaving an interval of ~47 msec of refresh
redundancy within that window, as a safety measure, to cover for possible delays in bus
availability for the refresh controller.
4.8.3 Local Bus SDRAM Functionality
The local bus can function in two mode:
1. Local Bus (SDRAM)
2. PCI
Both options are implemented on-board and the selection is done with the PCI_MODE pin
(jumper JP9). Bus Muxing devices are used to direct the local bus signals to the PCI or to the
SDRAM.
4.8.4 Local SDRAM Error Correction Support
The PQ2FADS-ZU has an optional support for Parity Error Correction for Local Bus SDRAM
accesses. To support that option, the LCL_DP(0:3) lines are connected to a Local Bus SDRAM
device which functions as ECC memory. Since the PQ2 muxes LCL_DP(0:3) signals with other
PCI signals, bus mux is used to select between LCL_DP(0:3) signals and PCI function.
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PQ2
Local SDRAM
LCL_DP(0:3)
LCL_DP(0:3)
LCL_DP0/PCI_C/BE0
LCL_DP1/PCI_C/BE1
LCL_DP2/PCI_C/BE2
LCL_DP3/PCI_C/BE3
PCI Bus
PCI_C/BE(0:3)
PCI_C/BE(0:3)
Figure 4-9. Local Bus SDRAM Data Parity Support
4.9
Flash Memory SIMM
The PQ2FADS-ZU is provided with 8Mbyte of 95 nsec flash memory SIMM, the
SM73228XG1JHBGO by Smart Modular Technology which is composed of four
LH28F016SCT-L95 chips by Sharp, arranged as 2M X 32 in a single bank. Support is given also
to 16MBytes and 32 MBytes simms. The Flash SIMM resides on an 80 pin SIMM socket and is
buffered from the 60X bus to reduce capacitive load over it.
2
To minimize use of PQ2s’ chip-select lines, only one chip-select line (CS0 or CS4 if the E PROM
is using CS0) is used to select the Flash as a whole, while distributing chip-select lines among the
module’s internal banks is done by on-board programmable logic, according to the Presence-
Detect lines of the Flash SIMM inserted to the PQ2FADS-ZU.
The access time of the Flash memory provided with the PQ2FADS-ZU is 95 nsec, however,
devices with different delay are supported as well. By reading the delay section of the Flash
SIMM Presence-Detect lines (see Table 4-12.), the debugger can establish (via register OR0 in
case CS0 is used or OR4 if CS4 is used) the correct number of wait-states needed to access the
Flash SIMM (considering 100MHz system clock frequency).
The control over the Flash is done with the GPCM and a dedicated CS0 (or CS4) region which
1
controls the whole bank. During hard - reset initialization , the debugger or any application S/W
for that matter, reads the Flash Presence-Detect lines via BCSR and determines how to program
registers BR0 & OR0 (or BR4 & OR4), within which the size and the delay of the region are
determined.The Flash module may be disabled / enabled at any time by writing ’1’ /’0’
1. i.e., initialization that follow the hard reset sequence at system boot.
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respectively to the FlashEn bit in BCSR1. The Flash connection scheme is shown in Figure 4-10..
FLASH SIMM
DATA(0:31)
D(31:0)
ADDRESS(7:29)
A(22:0)
WE0
WE0
WE1
WE1
WE2
WE2
WE3
WE3
POE
POE
BCSR
CS1
CS2
CS1
CS2
FLASH
CS
CS0
CS4
CS3
CS4
CS3
CS4
PD1
PD2
PD3
PD4
PD1
PD2
PD3
PD4
PD5
PD6
PD7
PD5
PD6
PD7
Figure 4-10. FLASH SIMM Connection Scheme
As can be seen in Figure 4-10., the FLASH CS is distributed to four CS signals. The distribution
depends on the size of the FLASH module installed - it is read by the BCSR using the PD(1-7)
pins.
The Hard-Reset configuration word stored in the FLASH differs from the one stored in the
2
2
E PROM in the BPS field which is the Boot Port Size - the E PROM is 8 bits while the FLASH is
32 bits.
4.9.1 Flash Programming Voltage
Support is given to 5V as well as 12V programmable modules. The selection between VPP’s
voltage levels is done via a dedicated jumper. To avoid inadvertent programming or erasure of the
Flash it is recommended to leave the jumper open so that no VPP is applied to the Flash SIMM.
4.9.2 Flash and L2Cache
If the L2 cache is installed, the PQ2 needs to be programmed to 60x bus mode. This requires the
latches for the buffered address bus to the Flash (As well as all other slow static devices) to be
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enabled. The 3 lowest order address lines for the Flash, are provided by the BADDR(27-29) lines
of the PQ2. However, BADRR29 function of the PQ2 is multiplexed with CI (Cache Inhibit)
function over the same pin. Therefore, prior to enabling the L2Cache, any code residing in the
1
Flash, should be moved into the PowerPC bus SDRAM , prior to changing BADDR29 function
to CI via SIUMCR.
4.10 E2PROM Memory
2
The PQ2FADS-ZU is provided with 8 KBytes of E PROM memory in a PLCC package. The
2
E PROM resides on a socket in case it is desired to replace or re-program a different
2
configuration for the board. The E PROM is used only for the purpose of supplying the Reset
Configuration Word during power-on reset and for storing the PCI configuration data. It is used as
a back-up for the Flash memory in case the Flash is not installed or the data it holds is incorrect.
As a back-up, it holds the default Hard-Reset configuration word and the default PCI
2
configuration. The Hard-Reset configuration word stored in the E PROM differs from the one
2
stored in the FLASH in the BPS field which is the Boot Port Size - the E PROM is 8 bits while
the FLASH is 32 bits. It uses a single chip-select, CS0 or CS4, which depends on the chip-select
2
used by the Flash. The selection of the chip-select is done by a dip-switch. The E PROM
connection scheme is shown in Figure 4-11.
2
The device used is ATMEL AT28HC64B, a 5V Byte alterable E PROM, 150ns access time with
byte-wide JEDEC pinout. Although the device is placed in a socket, it can be programmed on-
board. In order to program the device on-board, it has to be unlocked - it can be locked to prevent
unauthorized alterations of its contents. The lock can be done by hardware or software. The
hardware lock is done by write inhibit - the PQ2 does not assert WE during write cycles (set in the
BRx register). The software lock is achieved by writing a unique sequence to the device. To
1. It is required to do so anyway, since the L2Cache must operate within a full 64-bit data bus environment.
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unlock, a different unique sequence has to be written.
2
E PROM Socket
DATA(0:7)
I/O(7:0)
A(14:0)
ADDRESS(17:31)
BCSR
POE
WE0
CS
OE
WE
CE
2
E PROM
CS0
CS4
CS
2
Figure 4-11. E PROM Connection scheme
Additional address lines are connected to the socket according to the JEDEC format as an option
2
to use E PROM up to 32 KByte. To allow proper operation with the L2 Cache, the PQ2 needs to
2
1
be set to 60X bus mode in which the address bus for the E PROM is latched.
4.11 PCI Bus
The PQ2 has a PCI module which enables it to act as an Host (Master) or a Target. On this board,
the PQ2 serves only as a PCI host - a bridge between the PCI Bus and the PowerPC core.
The PQ2 PCI Bridge is designed to connect the PowerPC processor and memory system to the
PCI system bus, to which I/O components are connected. The PCI Bridge enables the PQ2 to
gluelessly bridge PCI masters and agents to a PowerPC system host. It uses a 32-bit multiplexed,
address/data bus that can run from 25MHz up to 66MHz. The interface provides address and data
parity with error checking and reporting. It also provides three physical address spaces: 32-bit
address memory; 32-bit address I/O; and the PCI configuration space.
The PQ2 also includes an on-chip Arbiter which enables arbitration of up to three PCI masters.
Only three PCI slots are supported on the PQ2FADS-ZU because of the Arbiter capacity. Each
slot can host either a PCI master or PCI target. The PQ2 as a Bridge can support more PCI devices
but that will require extra slots that can host PCI targets only. Therefore, to avoid dedicated slots
for PCI targets, only three slots are implemented.
1. As well as all other slow static devices.
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The PCI Bridge is implemented on the PQ2 Local Bus. Due to PCI Standard restrictions, no other
application can reside on the local bus. The PCI bus can operate at frequencies of 25MHz up to
66MHz @ 3.3V only. The 3.3V restriction is due to the PQ2 which is not 5V compliant. The PCI
bus layout is shown in Figure 4-12. Special care was taken when the layout of the PQ2FADS-ZU
was done so that the PCI standard recommendations are followed strictly.
Main Clock
66MHz
PCI Clock
PCI Clock
PCI Clock
JTAG
PCI
Clock
PQ2
Distribution
PCI Clock
PCI Clock
CLKIN2
CLKIN1
DLLOUT
PCI Bus
PCI
IRQ
Arbiter
Interrupt
Controller
Figure 4-12. PCI Bus Scheme
The clock source for the PQ2 is Main Clock 66MHz (or 100MHz) clock oscillator. The PCI Clock
is derived internally from the Main Clock and output at DLLOUT. That clock is then distributed
to each PCI device on the bus in a way that they are all synchronized (by keeping all clock traces
the same length). The PCI Clock is also fed back to the PQ2 for synchronization and skew
elimination purposes.
An interrupt from any PCI slot is handled by a simple generic Interrupt Controller. Each slot can
generate up to four interrupts for a total of twelve interrupts that the controller will support. It will
be made of two register mapped in a dedicated CS region. One is an Interrupt Register (see Table
4-3.) and the second is Interrupt Mask Register (see Table 4-4.). A simple priority scheme is
devised to allow the controller to support more than one interrupt concurrently.
4.12 L2-CACHE Support
To enhance benchmarking, optional support is provided for L2-Cache. Use is done with two
1
MPC2605 devices, each containing 256KBytes of look-aside cache along with its control,
providing a total of 512KByte L2-cache.
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The cache is connected directly over the 60X bus and is supported gluelessly by the PQ2.
The presence of the L2-Cache, calls for the introduction of latch - multiplexers over SDRAMs’
address lines because the MPC2605 snooping logic needs to monitor the address as is (linear
rather than multiplexed) and the bus works by the 60X bus protocol, allowing address pipelining .
These latch - multiplexers are soldered in place only in case a cache is installed on-board.
Otherwise they are omitted and bypassed by 0 Ω resistors. See also Section 4.7.3 L2-Cache
Support Influence On SDRAM Design.
1
4.12.1 L2 Cache Configuration & Control
The cache is configured via 5 configuration lines, CFG(0:4), for the following functions:
1. Cache size is set by CFG(0:2). The various settings of these lines per each cache module
are encoded in Table 4-8.
Table 4-8. L2 Cache CFG(0:2) Settings
L2CacheSize
CFG(0:2)
[Byte]
256K
512K
’000’ (Reserved)
’010’ -1’st Module (A26 == 0)
’011’ - 2’nd Module (A26 == 1)
2. Snoop is Enabled - CFG3 driven low for both modules.
3. AACK assertion enabled - CFG4 driven high for both modules.
The caches’ HRESET lines are connected directly to the SRESET line of the PQ2 so that
whenever Soft-reset is asserted to or by the PQ2, the cache is reset along with it, loosing all data
previously stored in it. The cache has 5 control lines that control its operation and state:
•
•
PWRDWN - constantly set to high (no power down support on the PQ2FADS-ZU)
2
L2FLUSH - assertion of which flushes out the cache array. This signal is controlled by
BCSR0.
•
L2MISS_INH - in fact Cache-Lock. When Asserted the cache does not change its contents.
Controlled by BCSR0.
•
•
L2TAG_CLR - Clears all tag memory. Controlled by BCSR0.
L2UPDATE_INH - In fact cache freeze (without information loss). Controlled by BCSR0.
All the above signals are connected directly to both cache modules.
1. i.e., residing on the same bus as the processor.
1. Only single level is allowed with the PQ2.
2. For minimum 8 Bus clock cycles.
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4.13 Communication Ports
The PQ2FADS-ZU has several communication ports, to allow convenient evaluation of the CPM
features. Obviously, it is not possible to provide all types of communication interfaces supported
by the CPM, but it is made convenient to connect any communication interface devices to the
PQ2 via the CPM Expansion connectors, residing on the edge of the board.
All CPM pins are visible on MICTOR connectors. In order to avoid long routes and stubs, bus
muxing devices are used to direct the CPM signals to a communication element on-board or to the
expansion connector. A signal that is used on-board, will not be visible in the expansion connector
and vise-versa. The control is done by enabling/disabling the communication elements on-board.
The communication ports’ interfaces provided on the PQ2FADS-ZU are listed below:
1. 155 Mbps ATM UNI on FCC1 with Optical interface, using the UTOPIA Level 2 interface
- support for 8 or 16 bit in multi or single PHY.
2. Two 100/10-Base-T Ports on FCC2 and FCC3 with T.P. interface, MII or RMII (on Hip7
devices only) controlled.
3. Dual RS232 ports residing on SMC1 & SMC2.
4. USB port, 1.1 USB standard compliant, with speed control (12 or 1.5 Mbps) and mode
control (Host or slave).
4.13.1 ATM Port
To support the PQ2s’ ATM controller, a 155.52Mbps User Network Interface (UNI) is provided
on board, connected to FCC1 of the PQ2 via UTOPIA I/F. Use is done with PM5384 S/UNI-155-
ULTRA by PMC-SIERA. Although these transceivers are capable of supporting 51.84Mbps rate,
support is given to 155.52Mbps only. The PHY supports UTOPIA level 2 which means support
for 8 or 16 bit UTOPIA bus in single or multi PHY mode. The control over the mode of UTOPIA
bus connection is done through BCSR3.
The control over the transceiver is done using the microprocessor interface of the transceiver,
controlled by the PQ2 memory controllers’ GPCM. Since the UNI is 5V powered and the PQ2 is
3.3V powered (5V intolerant), the UNI is buffered (LCX buffers) from the PQ2 on both the
receive part of UTOPIA interface and the microprocessor control ports.
The ATM transceiver may be enabled / disabled at any time by writing ’0’ /’1’ respectively to the
ATMEN bit in BCSRx. When ATMEN is negated, (’1’) the microprocessor control port is also
detached from the PQ2 and its associated FCC may be used off-board via the expansion
connectors.
The ATM transceiver reset input is driven by HRESET signal of the PQ2, so that the UNI is reset
whenever a hard-reset sequence occurs. The UNI may also be reset by either asserting ATM_RST
bit in BCSR1 (see Table 4-10.) or by asserting (’1’) the RESET bit in the Master Reset and Identify
/ Load Meters register via the UNI microprocessor interface.
The UNI transmit and receive clocks are fed with a 19.44 MHz +/- 20 ppm, clock generator, 5 V
powered, while the receive and transmit fifos’ clocks of the UTOPIA interface are provided by
the PQ2. The PQ2 can provide the same clock for both UTOPIA transmit and receive or separate
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1
clocks for each, hard-configured .
The ATM SAR is connected to the physical medium by an optical interface. Use is done with
HP’s HFBR 5805 optical interface, which operates at 1300 nm with upto 2 Km transmission
range.
The ATM PHY is connected to IRQ7 and generates an interrupt when an appropriate event
occurs.
NOTE: When the 60x Data Parity option is on, IRQ7 pin switches functionality to parity
and the interrupt output is routed to IRQ3. It is the responsibilty of the user to set
the appropriate functionality of the IRQ3 pin (SIUMCR register).
NOTE: When 16 bit UTOPIA bus is used, the extra pins are in conflict with other
functions. In that case, the16 bit UTOPIA bus will disable the USB, RS232 port 2
and the Fast Ethernet MDC functions.
NOTE: When Multi PHY UTOPIA bus is used, the extra pins are in conflict with other
functions. In that case, the multi PHY UTOPIA bus will disable the two RS232
port functions.
4.13.2 100/10 Base - T Ports
Two fast Ethernet ports with T.P. (100-Base-TX) I/F is provided on the PQ2FADS-ZU. These
ports also support 10 Mbps ethernet (10-Base-T) via the same transceiver - the DM9161 by
Davicom.
The DM9161 are connected to FCC2 and FCC3 of the PQ2 via MII or RMII interface, which is
used for both - devices’ control and data path. The initial configuration of the DM9161 on the
PQ2FADS-ZU is set by external resistors - 100Base-Tx Full Duplex in MII mode. The selection
between MII/RMII for FCC2 and FCC3 is done by jumpers JP2 and JP3 respectively. The
DM9161 must be set to MII or RMII while in power-down.
The DM9161 reset input is driven by either asserting the FETH_RST bit in BCSR1 (see Table 4-
10.) or by asserting a specific bit in an internal register via MII I/F.
To allow external use of FCC2 and FCC3, their pins appear at the CPM expansion connectors and
the ethernet transceiver may be Disabled / Enabled at any time via the MIIs’ MDIO port.
The DM9161 is able to interrupt the PQ2 via IRQ7 line. This line is shared also with the CPM
expansion connectors. Therefore, any tool that is connected to IRQ7, should drive these lines with
an Open Drain buffer.
NOTE: When the 60x Data Parity option is on, IRQ7 pin switches functionality to parity
and the interrupt output is routed to IRQ3. It is the responsibilty of the user to set
the appropriate functionality of the IRQ3 pin (SIUMCR register).
4.13.2.1 DM9161 Control
2
The DM9161 is controlled via the MII management port which is a 2 wire interface: a clock
1. Using resistors.
2. Also known as MII MDIO port.
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(MDC) and a bidirectional data line (MDIO). This is in fact a bus, i.e., up to 32 devices may
reside over it, while the protocol defines a 5-bit slave address field, which is compared against the
slave address set to each device by hardware during device reset, according to the levels on some
pins. On the board, the slave address is hard-set to b00000 for FCC2 and b00011 for FCC3. The
PQ2 interfaces this port using two PI/O pins: PC9 for MDIO and PC10 for MDC. There is no
special support within the PQ2 for the MDIO port and the protocol is implemented in S/W.
1
The MDIO port may interrupt a host in 2 ways: (a ) driving low the MDIO line during IDLE time
or (b) using a dedicated interrupt line MDINT. This line is connected to the PQ2’s DP7/CSE1/
IRQ7 line, appearing also at the CPM expansion connectors.
Since IRQ7 may also be driven by any tool, connected to the expansion connectors, it should be
driven with an Open Drain buffer. IRQ7 is pulled-up on the board.
NOTE: If ATM 16 bit UTOPIA bus or USB port are enabled, either one will conflict with
the MDC and MDIO signals. Therfore, the MDC and MDIO functionality will
switch to PC3 and PC2 respectively.
4.13.3 RS232 Ports
To assist user’s applications and to provide convenient communication channels with both a
terminal and a host computer, two identical RS232 ports are provided on the PQ2FADS-ZU,
connected to SCC1 and SCC2 ports of the PQ2. Use is done with MAX3241 transceiver which
generates RS232 levels internally using a single 3.3V supply and has a standby mode. When the
RS232EN1 or RS232EN2 bits in BCSR1 are asserted (low), the corresponding transceiver is
enabled. When negated, the corresponding transceiver is in standby mode, within which the
receiver outputs are tri-stated, enabling the use of the corresponding ports’ pins off-board via the
expansion connectors.
Nine pins, female D-Type stacked connector is used, configured to be directly (via a flat cable)
connected to a standard IBM-PC like RS232 connector.
DCD
1
6
7
8
9
DSR
RTS
CTS
N.C.
TX
2
3
4
5
TX
DTR
GND
Figure 4-13. RS232 Serial Ports Connector
4.13.3.1 RS-232 Ports’ Signal Description
In the list below, the directions ’I’,’O’, and ’I/O’ are relative to the PQ2FADS-ZU board. (i.e.’I’
means input to the PQ2FADS-ZU)
•
•
•
CD (O) - Data Carrier Detect. This line is always asserted by the PQ2FADS-ZU.
TX (O) - Transmit Data.
RX (I) - Receive Data.
1. Not supported on the board.
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•
DTR (I) - Data Terminal Ready. This signal is used by the software on the PQ2FADS-ZU to
detect if a terminal is connected to the board.
•
•
•
DSR (O) - Data Set Ready. This line is always asserted by the PQ2FADS-ZU.
RTS (I) - Request To Send. This line is not connected in the PQ2FADS-ZU.
CTS (O) - Clear To Send. This line is always asserted by the PQ2FADS-ZU.
NOTE: RS232 port 2 (SCC2) functionality is in conflict with ATM 16 bit UTOPIA bus
and Multi PHY UTOPIA bus. RS232 port 1 is in conflict with Multi PHY
UTOPIA bus. It is up to the user to determine the desired function on the shared
pins.
4.13.4 USB Port
The USB port resides on the PQ2FADS-ZU and is driven by the USB port of the MPC8280 (Hip7
only) through SCC4. A dedicated USB transceiver - the PDIUSBP11 by PHILIPS is provided,
along with a tri-state buffer, separating this port from the MPC8280’s USB port, this to allow Port
disable option and off-board use of MPC8280 USB pins.
To correctly support the 2 speed modes of the USB, detachable pull-up resistors (3.3V) are
provided over D+ and D- lines of the USB, controlled by the USB_SPD bit of BCSR4. When
USB_SPD is in low-speed level (low) D- is pulled-up while D+ remains floating. When
USB_SPD bit is in high-speed level, D+ is being pulled-up and D- floats.
Also, 5V power will optionally be provided for the USB connector, controlled by USB_VCC0 in
BCSR4. When USB_VCC0 is driven low, a 5V supply will be connected to pin 1 of the USB
connectors.
NOTE: The USB function is in conflict with ATM 16 bit UTOPIA bus and Fast Ethernet
MDC functions. It is up to the user to select the desired function on the shared
pins.
4.13.5 PC Parallel Port
A new feature to this board is the direct connection to a PC parallel port for the purpose of
debugger connection (CodeWarrior). An on-board logic is used to interface to the parallel port
and translate the signals to COP/JTAG format. The parallel port support both EPP and SPP modes
of the parallel port in a PC. The direct connection eliminates the need for an external command
converter. When connected to a PC’s parallel port, the parallel port connection has automatic
priority over the COP/JTAG connector interface.
4.14 Board Control & Status Register - BCSR
Most of the hardware options on the PQ2FADS-ZU are controlled or monitored by the BCSR,
which is a 32 bit wide read / write register file. The BCSR is accessed via the PQ2s’ memory
controller (see Table 4-5.) and in fact includes 8 registers: BCSR0 to BCSR7. Since the minimum
block size for a CS region is 32KBytes and only A(27:29) lines are decoded by the BCSR for
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register selection, BCSR0 - BCSR7 are duplicated inside that region.
The following functions are controlled / monitored by the BCSR:
1. PBI
2. L2 Cache Inhibit
3. L2 Cache Flush
4. L2 Cache Lock
5. L2 Cache tag Clear.
6. ATM Port Control which includes:
•
•
•
•
Transceiver Enable / Disable
Transceiver Reset.
UTOPIA 8/16 bit
UTOPIA single/multi PHY
7. Fast Ethernet Ports Control which includes:
•
•
Transceiver Initial Enable
Transceiver Reset
8. RS232 port 1 Enable / Disable.
9. RS232 port 2 Enable / Disable.
10. USB Port Control which includes:
•
•
•
Transceiver Initial Enable
USB Speed
USB Power
11. Flash Size / Delay Identification.
2
12. CS0 assignment after hard-Reset to FLASH SIMM / E PROM.
13. External (off-board) tools Support which include:
•
•
•
Tool Identification
Tool Revision
Tool Status Information
14. S/W Option Identification.
15. Board revision code.
16. Power-on Reset via JTAG (optional).
17. PCI cards Present Detect and card type.
18. Local Bus Mode
Since part of the PQ2FADS-ZUs’ modules are controlled by the BCSR and since they may be
disabled in favor of external hardware, the enable signals for these modules are presented at the
CPM expansion connectors, so that off- board hardware may be mutually exclusive enabled with
on-board modules.
4.14.1 BCSR0 - Board Control - Status Register 0
The BCSR0 is a control register on the PQ2FADS-ZU. It is accessed at offset 0 from BCSR base
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1
address. It may be read or written at any time . BCSR0 gets its defaults upon Power-On reset.
BCSR0 fields are described in Table 4-9..
Table 4-9. BCSR0 Description
PON
DEF
BIT
MNEMONIC
Function
ATT.
0
PBI
Page Base Interleaving. In 60X mode (i.e., with L2-Cache), this bit should
reflect (system programmer responsibility) the state of PBI bit in
PSDMR. In Single PQ2 Mode (i.e., without L2-Cache), this bit has no
effect.
0
R/W
1
Reserved
L2C_INH
S
0
R/W
2
L2 Cache Inhibit. When this bit is active (low), the L2 cache is inhibited
and unable to respond to cacheable cycles. However, bus activity is still
monitored by the cache so that it may respond immediately after this signal
is negated. This signal is connected to the MPC2605’s L2 UPDATE INH.
This signal has no function in a PQ2FADS-ZU that does not have an L2
Cache installed.
0
R,W
3
L2C_FLUSH
L2 Cache Flush. When this bit is active (low) for min. 8 bus cycles, the
MPC2605 initiates a process within which, valid lines are marked invalid,
while dirty lines are written back to memory and marked invalid. This signal
is connected to the L2 FLUSH signal of the MPC2605.
1
R,W
This signal has no function in a PQ2FADS-ZU that does not have an L2
Cache installed.
4
5
L2C_LOCK
L2 Cache Lock. When this bit is active (low), the MPC2605 will stop
entering new data into the cache, while yet maintaining existing data and
responding to cacheable cycles.
This signal has no function in a PQ2FADS-ZU that does not have an L2
Cache installed.
1
1
R,W
R,W
L2C_CLEAR
L2 Cache Clear. When this bit is active (Low) for min. 8 bus clock cycles,
the L2 cache invalidates all its entries, without flushing, the same process
as with HRESET asserted. However, it still monitors the bus, so it can
immediately respond when this process ends.
This signal is connected to the L2 TAG CLR of the MPC2605, but has no
function when a cache is not installed on the PQ2FADS-ZU.
6 - 31
Reserved
Un-implemented
0
R
4.14.2 BCSR1 - Board Control - Status Register 1
The BCSR1 is a control register on the PQ2FADS-ZU. It is accessed at offset 4 from BCSR base
2
address. It may be read or written at any time . BCSR1 gets its defaults upon Power-On reset. The
1. Provided that BCSR is not disabled.
2. Provided that BCSR is not disabled.
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Functional Description
fields are described in Table 4-10.
Table 4-10. BCSR1 Description
PON
DEF
BIT
MNEMONIC
Function
ATT.
0
Conf_Word
Config_Source. When asserted (low) Hard Reset Configuration Word is
sourced from the BCSR. When negated, Hard Reset Configuration Word is
sourced from the FLASH/EEPROM. The assignments selection is done via
a dedicated jumper JP7.
0
0
1
R
1
2
FLASH_CS0
ATM_EN
FLASH CS0. When asserted (low) CS0 is assigned to the FLASH SIMM
and CS4 is assigned to E2PROM. When negated, CS0 is assigned to the
E2PROM and CS4 is assigned to the FLASH SIMM. The assignments
selection is done via a dedicated jumper.
R
ATM Port Enable. When asserted (low) the ATM UNI chip (PM5350)
connected to FCC1 is enabled for transmission and reception. When
negated, the ATM transceiver is in standby mode and its associated
buffersa are in tri-state mode, freeing all its i/f signals for off-board use via
the expansion connectors.
R,W
3
4
ATM_RST
FETHIEN1
ATM Port Reset. When asserted (low), the ATM port transceiver is in reset
state. This line is driven also by HRESET signal of the PQ2.
1
1
R,W
R,W
Fast Ethernet Port 1 Initial Enable. When asserted (low) the DM9161’s
MII port, residing on FCC2, is enabled after Power-Up or after FETH_RST
is negated. When negated (high), the DM9161’s MII port is isolated after
Power-Up or after FETH_RST is negated and all i/f signals are tri-stated.
After initial value has been set, this signal has no influence over the
DM9161 and MII isolation may be controlled via MDIO 0.10 bit.
5
FETH1_RST
Fast Ethernet port 1 Reset. When active (low) the DM9161 is reset. This
line is also driven by HRESET signal of the PQ2. Since MDDIS pin of the
DM9161 is driven low with this application, the negation of this signal
causes all the H/W configuration bits to be sampled for initial values and
device control is moved to the MDIO channel, which is the control path of
the MII port.
1
R,W
6
7
RS232EN_1
RS232EN_2
Reserved
RS232 port 1 Enable. When asserted (low) the RS232 transceiver for port
1, is enabled. When negated, the RS232 transceiver for port 1, is in standby
mode and SCC1 pins are available for off-board use via the expansion
connectors.
1
1
0
R,W
R,W
R
RS232 port 2 Enable. When asserted (low) the RS232 transceiver for port
2, is enabled. When negated, the RS232 transceiver for port 2, is in standby
mode and SCC2 pins are available for off-board use via the expansion
connectors.
8 - 31
Un-implemented
a. Required for voltage levels adaptation.
4.14.3 BCSR2 - Board Control - Status Register - 2
BCSR2 is a status register which is accessed at offset 8 from the BCSR base address. Its a read-
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1
only register which may be read at any time . BCSR2s’ various fields are described in Table 4-11.
Table 4-11. BCSR2 Description
PON
DEF
BIT
MNEMONIC
Function
ATT.
0 - 7
TSTAT(0:7)
Tool Status (0:7). This field is reserved for external tool status report. The
exact meaning of each bit within this field is tool unique and therefore will be
documented separately per each tool. These signals are available at the
System expansion connector.
-
R
8 - 11
TOOLREV(0:3)
EXTTOLI(0:3)
TOOL Revision (0:3). This field may contain the revision code of an
external tool connected to the PQ2. The various combinations of this field
will be described per each tool users’ manual. These signals are available
at the System expansion connector. The revision option for the external
tools are shown in Table 4-17.
R
R
12 - 15
External Tools Identification. These lines, which are available at the CPM
expansion connectors, are intended to serve as tools’ identifier. On-board S/
W may check these lines to detect The presence of various tools (h/w
expansions) at the CPM expansion connectors. For the external tools’
codes and their associated combinations see Table 4-14.
-
16 - 17
18 - 19
SWOPT(0:1)a
L2CSIZE(0:1)
Software Option (0:1). This field shows the state of a dedicated dip-
switches providing an option to manually change a program flow.
0
-
R
R
L2 Cache Size (0:1). This filed encodes the size of the L2 Cache, present
on the PQ2FADS-ZU. For the encoding of the various cache sizes see
Table 4-18.
20 - 21
22 - 23
BVERN(0:1)
BREVN(0:1)
Board Version Number (0:1). This field represents the version code, hard-
assigned to the PQ2FADS-ZU. See Table 4-15., for version encoding.
11
-
R
R
Board Revision Number (0:1). This field represents the revision code,
hard-assigned to the PQ2FADS-ZU. See Table 4-16., for revisions’
encoding.
24
SWOPT2
Software Option 2. This is the LSB of the field. Shows the state of a
dedicated dip-switch providing an option to manually change a program
flow.
0
-
R
R
25 - 27
FLASH_PD(7:5)
Flash Presence Detect(7:5). These lines are connected to the Flash SIMM
presence detect lines, which encode the Delay of Flash SIMM mounted on
the Flash SIMM socket. For the encoding of FLASH_PD(7:5) see Table 4-
12.
28 - 31
FLASH_PD(4:1)
Flash Presence Detect(4:1). These lines are connected to the Flash SIMM
presence detect lines which encode the type of Flash SIMM mounted on the
Flash SIMM socket. For the encoding of FLASH_PD(4:1) see Table 4-13.
-
R
a. There is additional bit to this field. See next on the same table.
1. Provided that BCSR is not disabled.
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Table 4-12. FLASH Presence Detect (7:5) Encoding
FLASH_PD(7:5)
FLASH DELAY [nsec]
000
001
Not Supported
150
010
100/120
80/90
011
100
70
101 - 111
Not Supported
Table 4-13. FLASH Presence Detect (4:1) Encoding
FLASH_PD(4:1)
Flash TYPE / SIZE
0000
SM73288XG4JHBG0 - 32 MByte (4 banks of 4 X 2M X 8) by Smart Modular
Technology.
0001
SM73248XG2JHBG0 - 16 MByte (2 banks of 4 X 2M X 8) by Smart Modular
Technology.
0010
SM73228XG1JHBG0 - 8 MByte (1 bank of 4 X 2M X 8) by Smart Modular
Technology.
0011 - 1111
Not Supported
Table 4-14. EXTOOLI(0:3) Assignment
EXTTOOLI(0:3)
External Tool
0
1
T/ECOM - PQ2 Communication tool
Reserved
2
T1 Circuit Emulation Tool
Reserved
3 - E
F
Tool Non Existent
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Table 4-15. PQ2 Board Version Encoding
Version Number (0:1) [Hex]
PQ2 Board Version
0
PQ2 - Voyager ADS
1
2
3
Reserved
PQ2 - Add In Card
PQ2 - Motherboard
Table 4-16. PQ2 Board Revision Encoding
Revision Number (0:1) [Hex] PQ2 Board Revision
0
ENG (Engineering)
1
2
3
PILOT
A
Reserved
Table 4-17. External Tool Revision Encoding
TOOLREV(0:3) [hex]
External Tool Revision
0
1
ENGINEERING
PILOT
2
A
3 - F
Reserved
Table 4-18. L2 Cache Size Encoding
L2CSIZE(0:1)
L2 Cache Size
’00’
’01’
’10’
’11’
Reserved
512 KBytes
Reserved
No L2 Cache
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4.14.4 BCSR3 - Board Control - Status Register 3
BCSR3 is a control register which is accessed at offset 0xC from the BCSR base address. Its a
1
read- write register which may be read or written at any time . BCSR3s’ various fields are
described in Table 4-20.
Table 4-19. BCSR3 Description
PON
BIT
MNEMONIC
Function
ATT.
DEF
0
USB_EN
USB Port Enable. When asserted (low) the USB chip connected to SCC4
is enabled for transmission and reception. When negated, the USB
transceiver is in standby mode and its associated buffersa are in tri-state
mode, freeing all its i/f signals for off-board use via the expansion
connectors.
1
R/W
1
USB_HI_SPEED
USB Hi Speed. When asserted (low) the USB chip connected to SCC4 is
set for hi speed (12 Mbps) transmission and reception. When negated, the
USB transceiver is set to low speed (1.5 Mbps) transmission and reception
0
R/W
2
3
USBVCC0
FETHIEN2
USB Port VCC EN. When asserted (high), 5V power is applied to the USB
Bus. When negated, power to the USB port is disconnected.
0
1
R/W
R/W
Fast Ethernet Port 2 Initial Enable. When asserted (low) the DM9161’s
MII port, residing on FCC3, is enabled after Power-Up or after FETH_RST
is negated. When negated (high), the DM9161’s MII port is isolated after
Power-Up or after FETH_RST is negated and all i/f signals are tri-stated.
After initial value has been set, this signal has no influence over the
DM9161 and MII isolation may be controlled via MDIO 0.10 bit.
4
FETH2_RST
Fast Ethernet port 2 Reset. When active (low) the DM9161 is reset. This
line is also driven by HRESET signal of the PQ2. Since MDDIS pin of the
DM9161 is driven low with this application, the negation of this signal
causes all the H/W configuration bits to be sampled for initial values and
device control is moved to the MDIO channel, which is the control path of
the MII port.
1
R/W
5
6
7
ATM16
ATM 16 bit UTOPIA. When asserted (low) the UTOPIA is set for 16 bit.
When negated (high), the UTOPIA is set for 8 bit..
1
1
R/W
R/W
R
ATM_SINGLE_PH ATM SINGLE PHY. When asserted (low) the UTOPIA is set to Multi PHY.
Y
When negated (high), the UTOPIA is set for Single PHY.
PCI_MODE
PCI_MODE. When asserted (low) the Local Bus function is set to PCI.
When negated (high), the Local Bus is set for Local Bus SDRAM.
8-31
Reserved
un-implemented
a. Required for voltage levels adaptation.
4.14.5 BCSR4 - Board Control - Status Register 4
BCSR4 is a status register which is accessed at offset 0x10 from the BCSR base address. Its a
1. Provided that BCSR is not disabled.
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read- only register which may be read at any time . BCSR4s’ various fields are described in Table
4-20.
Table 4-20. BCSR4 Description
PON
DEF
BIT
MNEMONIC
Function
ATT.
0 - 1
PCI0_PRSNT(0:1) PCI Slot 0 Present (0:1). This field holds a code that tells whether a PCI
expansion board is pluged in PCI slot 0 and the total power requirements of
the board according to the PCI spec. The different expansion board types
are listed in Table 4-21.
11
R
2 - 3
4 - 5
6
PCI1_PRSNT(0:1) PCI Slot 1 Present (0:1). This field holds a code that tells whether a PCI
expansion board is pluged in PCI slot 1 and the total power requirements of
the board according to the PCI spec. The different expansion board types
are listed in Table 4-21.
11
11
1
R
R
R
R
PCI2_PRSNT(0:1) PCI Slot 2 Present (0:1). This field holds a code that tells whether a PCI
expansion board is pluged in PCI slot 2 and the total power requirements of
the board according to the PCI spec. The different expansion board types
are listed in Table 4-21.
M66EN
66MHz Enable. This field shows if one of the expansion boards used is not
capable of operating in 66MHz mode:
‘1’ - All expansion boards are 66MHz capable
‘0’ - One of the expansion boards is not 66MHz capable
7
PCI_MODCK
Reserved
PCI_MODCK. This field shows the PCI bus clock settings.
-
8-31
un-implemented
Table 4-21. PCI Board Present Signal Definitions
PCIx_PRSNT (0:1) [Hex]
Expansion Configuration
0
1
2
3
Expansion board present, 7.5W maximum
Expansion board present, 25W maximum
Expansion board present, 15W maximum
No expansion board present
4.14.6 BCSR5 and BCSR7- Board Control - Status Register 3 &
5
BCSR5 to BCSR7 are additional control / status registers which may be accessed as a word at
offset 0x14 to 0x1C from BCSR base address. These registers are not implemented. They may be
read or written but with no valid data nor any effect on the board. The description of BCSR3 and
1. Provided that BCSR is not disabled.
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BCSR5 is shown in Table 4-22.
Table 4-22. BCSR5 to BCSR7 Description
PON
DEF
BIT
MNEMONIC
Reserved
Function
ATT.
0 - 31
Un Implemented
-
-
4.15 COP/JTAG Port
The COP - Control Observation Port, is part of the PQ2’s JTAG machine, implemented as a set of
additional instructions and logic within the JTAG permissions. This port may be connected to a
1
dedicated debug station , for extensive system debug.
There are several third party debug solutions on the market. These debug-stations may be
connected to the host computer via either Ethernet, Parallel-Port, RS232 or any other media.
The debug station connection scheme is shown in Figure 4-14..
Host
Ethernet/
Parallel/
RS232/
USB...
ADS
16 Wire
Media
Adaptor
Media
Media To COP
COP
Flat Cable
Figure 4-14. Debug Station Connection Schemes
To support debug station connection to the COP/JTAG port, a 16 pin generic header connector is
provided on the PQ2FADS-ZU, carrying the COP/JTAG signals as well as additional signals
aiding in system debug. The pinout of this connector, which is a general Motorola
recommendation for including a COP/JTAG port in a design, is shown in Figure 4-15. and detailed
1. Not provided with the PQ2FADS-ZU.
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in Table 4-23..
1
2
4
6
8
TDO
TDI
N.C.
3
TRST
V3.3
5
QREQ
7
9
TCK
TMS
N.C.
N.C.
10
12
14
11
13
SRESET
HRESET
GND
"KEY"
15
16
GND
CKSTP_OUT
Figure 4-15. COP/JTAG Port Connector
Table 4-23. COP/JTAG Port Signals Description
Pin No.
Signal Name
Attribute
Description
1
TDO
O
Transmit Data Out. This the JTAG’s serial data output driven by
Falling edge of TCK.
2
3
N.C.
TDI
-
I
Not Connected.
Transmit Data In. This is the JTAG serial data input, sampled by
the PQ2 on the rising edge of TCK. This line is pulled up internally
by the PQ2.
4
5
TRST
I
Test port Reset (L). When this signal is active (Low), it resets the
JTAG logic. This line is pull-down on the PQ2FADS-ZU with a
1KΩ resistor, to provide constant reset of the JTAG logic.
QREQ
O
Quiescent Request (L). When asserted (low), this line indicates
that the PQ2 desires to enter low-power mode. This signal may
be required by a debug station.
6
7
V3.3
TCK
O
I
3.3V power supply bus.
Test port Clock. This clock shifts in / out data to / from the PQ2
JTAG port. Data is driven on the falling edge of TCK and is
sampled both internally and externally on it’s rising edge.
TCK is pulled up internally by the PQ2.
8
9
N.C.
TMS
-
I
Not Connected.
Test Mode Select. This signal qualified with TCK in a same
manner as TDI, changes the state of the JTAG machine. This line
is pulled up internally by the PQ2.
10
N.C.
-
Not Connected.
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Functional Description
Table 4-23. COP/JTAG Port Signals Description
Pin No.
Signal Name
Attribute
Description
11
SRESET
I/O, O.D.
Soft Reset (L). This is the PQ2’s soft reset which is in fact a non-
maskable interrupt, making the PowerPC take the reset exception
from the reset vector. This line may be driven by the PQ2 as well
during soft-reset sequence, for 512 system clocks. This line is
pulled up on the PQ2FADS-ZU with a 1KΩ resistor. When driven
externally, it MUST be driven with an Open Drain gate. Failure
in doing so might result in permanent damage to the PQ2
and / or to board logic.
12
13
GND
O
Digital GND. Main GND plane.
HRESET
I/O, O.D.
PQ2’s Hard Reset (L). When asserted by an external H/W,
generates Hard-Reset sequence for the PQ2. During that
sequence, asserted by the MPC for 512 system clocks. Pulled Up
on the PQ2FADS-ZU using a 1KΩ resistor.
When driven by an external tool, MUST be driven with an Open
Drain gate. Failure in doing so might result in permanent
damage to the PQ2 and / or to board logic.
14
15
N.C.
-
Not Connected.
XBR3
(CKSTOP_OUT)
I/O
Normally configured as XBR3 which has no function with this
connector. May be configured as CKSTOP_OUT - Check Stop
Out (L). When asserted (Low) indicates that the PQ2 core has
entered a Check-Stop state.
16
GND
O
Digital GND. Main GND plane.
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Memory Map and Initialization
5
Memory Map and Initialization
5.1
Memory Map
All accesses to PQ2FADS-ZU’s memory slaves are controlled by the PQ2’s memory controller.
Therefore, the memory map is reprogrammable to the desire of the user. After Hard Reset is
performed by the debug station, the debugger checks for existence, size, delay and type of the
FLASH memory SIMM mounted on board and decides on the assignments of CS0 and CS4
2
(E PROM and FLASH) and programs the memory controller accordingly. The SDRAM,
2
E PROM and the FLASH memory, respond to all types of memory access i.e., problem /
supervisory, program / data and DMA.
This memory map is a recommended memory map and since it is a "soft" map, devices’ address
may be moved about the map, to the convenience of any user. There are actually two memory
maps which depend on the device assigned to CS0 (regardless of the Hard Reset Configuration
Word source). The memory address for the device assigned to CS0 is always the same as
2
determined in the Hard-Reset configuration word. Since the FLASH and E PROM require
different memory spaces, different memory maps are devised for each case. For details see Table
5-1. and Table 5-2.
Table 5-1. PQ2FADS-ZU Memory Map - FLASH (or BCSR) as Boot Device
Address
Range
Memory
Type
Port
Size
Memory
Size
Device Name
00000000
01FFFFFF
-
60x SDRAM
32MByte
64MByte
64
64 MByte
01000000
03FFFFFF
-
-
04000000
044FFFFF
Empty Space
Optional 4MByte local bus SDRAM for legacy
support
-
5 MByte
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Memory Map and Initialization
Table 5-1. PQ2FADS-ZU Memory Map - FLASH (or BCSR) as Boot Device
Address
Range
Memory
Type
Port
Size
Memory
Size
Device Name
BCSR(0:7)a
04500000
04507FFF
-
32
32 KByte
04500000
04507FE3
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
BCSR0
4 Byte
04500004
04507FE7
BCSR1
BCSR2
4 Byte
04500008
04507FEB
4 Byte
0450000C
04507FEF
BCSR3
4 Byte
04500010
04507FF3
BCSR4
4 Byte
04500014
04507FF7
BCSR5
4 Byte
04500018
04507FFB
BCSR6
4 Byte
0450001C
04507FFF
BCSR7
4 Byte
04508000
045FFFFF
Empty Space
-
8
~1 MByte
32 KByte
~1 MByte
128 KByte
64 KByte
32 KByte
~800 KByte
~ 8 MByte
~ 2 GByte
1 Gbyte
04600000
ATM UNI Proc. PMC5384 M/P I/F
Control
04607FFFb
04608000
046FFFFF
Empty Space
-
04700000c
0471FFFF
PQ2
Internal
32
-
MAPd
04720000
0472FFFF
Empty Space
04730000
04737FFF
PCI
Controller
Interrupt
32
-
04738000
047FFFFF
Empty Space
PCI Memory
Empty Space
PCI Memory
04800000
04FFFFFF
Agents PIMMR (via PCI Direct)
05000000
7FFFFFFF
Tool Board is located at 60000000 and 70000000
PCI Agents GPL WIndows
80000000
32
BFFFFFFF
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Memory Map and Initialization
Table 5-1. PQ2FADS-ZU Memory Map - FLASH (or BCSR) as Boot Device
Address
Range
Memory
Type
Port
Size
Memory
Size
Device Name
C0000000 - Empty Space
C1FFFFFF
-
32 MByte
C2000000e - E2PROM
C2007FFF
ATMEL AT28HC64B
8
32 KByte
C2008000 - Empty Space
CFFFFFFF
~200
MByte
D0000000 - Local
Bus 8MByte
32
32
8 MByte
~1 GByte
32 MByte
D07FFFFF
SDRAM
D0800000 - Empty Space
FDFFFFFF
FE000000f - Flash SIMM
FEFFFFFF
32M SIMM -
SM73288
FF000000
FF7FFFFF
-
16M SIMM -
SM73248
FF800000
FFFFFFFF
-
8M SIMM
SM73228
-
a. The device appears repeatedly in multiples of its port-size (in bytes) X depth. E.g., BCSR0
appear at memory locations 4700000, 4700020, 4700040..., while BCSR1 appears at
4700004, 4700024, 4700044... and so on.
b. The internal space of the ATM UNI control port is 256 bytes, however, the minimal block size
tha may be controlled by the GPCM is 32 KBytes.
c. Initially at h0F000000 - h0F00FFFF, set by hard reset configuration.
d. Refer to the PQ2 User’s Manual for complete description of the internal memory map.
e. An 8 Kbyte device is used (16 Kbyte and 32 Kbyte devices can also be used) so it appears
repeatedly in 8Kbyte multiples starting from C2000000.
f. Set by hard-reset configuration.
2
Table 5-2. PQ2FADS-ZU Memory Map - E PROM as Boot Device
Address
Range
Memory
Type
Port
Size
Memory
Size
Device Name
00000000
00FFFFFF
-
SDRAM DIMM
32 MByte
64 MByte
64
64 MByte
01000000
03FFFFFF
-
-
04000000
044FFFFF
Empty Space
-
5 MByte
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Memory Map and Initialization
2
Table 5-2. PQ2FADS-ZU Memory Map - E PROM as Boot Device
Address
Range
Memory
Type
Port
Size
Memory
Size
Device Name
BCSR(0:7)a
04500000
04507FFF
-
32
32 KByte
04500000
04507FE3
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
BCSR0
4 Byte
04500004
04507FE7
BCSR1
BCSR2
4 Byte
04500008
04507FEB
4 Byte
0450000C
04507FEF
BCSR3
4 Byte
04500010
04507FF3
BCSR4
4 Byte
04500014
04507FF7
BCSR5
4 Byte
04500018
04507FFB
BCSR6
4 Byte
0450001C
04507FFF
BCSR7
4 Byte
04508000
045FFFFF
Empty Space
-
8
~1 MByte
32 KByte
~1 MByte
128 KByte
64 KByte
32 KByte
~800 KByte
~ 8 MByte
~ 2 GByte
1 Gbyte
04600000
ATM UNI Proc. PMC5384 M/P I/F
Control
04607FFFb
04608000
046FFFFF
Empty Space
-
04700000c
0471FFFF
PQ2
Internal
32
-
MAPd
04720000
0472FFFF
Empty Space
04730000
04737FFF
PCI
Controller
Interrupt
32
-
04738000
047FFFFF
Empty Space
PCI Memory
Empty Space
PCI Memory
04800000
04FFFFFF
Agents PIMMR (via PCI Direct)
05000000
7FFFFFFF
Tool Board is located at 60000000 and 70000000
PCI Agents GPL WIndows
80000000
32
BFFFFFFF
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Memory Map and Initialization
2
Table 5-2. PQ2FADS-ZU Memory Map - E PROM as Boot Device
Address
Range
Memory
Type
Port
Size
Memory
Size
Device Name
C0000000 - Empty Space
C1FFFFFF
-
32 MByte
C2000000 - Flash SIMM
C2FFFFFF
32M SIMM -
SM73288
32
32 MByte
C3000000 -
C37FFFFF
16M SIMM -
SM73248
C3800000 -
C3FFFFFF
8M SIMM
SM73228
-
C4000000 - Empty Space
CFFFFFFF
~200
MByte
D0000000 - Local
Bus 8MByte
32
8
8 MByte
~1 GByte
32 KByte
D07FFFFF
SDRAM
D0800000 - Empty Space
FFFFDFFF
FFF00000e -
E2PROM
ATMEL AT28HC64B
FFFFFFFF
a. The device appears repeatedly in multiples of its port-size (in bytes) X depth. E.g., BCSR0
appears at memory locations 4700000, 4700020, 4700040..., while BCSR1 appears at
4700004, 4700024, 4700044... and so on.
b. The internal space of the ATM UNI control port is 256 bytes, however, the minimal block size
that may be controlled by the GPCM is 32 KBytes.
c. Initially at h0F000000 - h0F00FFFF, set by hard reset configuration.
d. Refer to the PQ2 User’s Manual for complete description of the PQ2’s internal memory map.
e. An 8 Kbyte device is used (16 Kbyte and 32 Kbyte devices can also be used) so it appears
repeatedly in 8Kbyte multiples starting from FFF00000.
5.2
PQ2 Register Programming
The PQ2 provides the following functions on the PQ2FADS-ZU:
1. System functions which include:
•
•
•
PPC Bus SDRAM Controller
Local Bus Host to PCI Bridge or SDRAM Controller
Chip Select generator
2. Communication functions which include:
•
•
•
•
ATM SAR
Dual Fast Ethernet controller
UART for terminal or host computer connection
USB Controller
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Memory Map and Initialization
The internal registers of the PQ2 must be programmed after Hard reset as described in the
following paragraphs. The addresses and programming values are in Hexadecimal base.
For more information on the following initializations, see the PQ2 User’s Manual.
5.2.1 System Initializations
The Power-On Reset Configuration word is set in the BCSR or FLASH or in the E PROM. There
2
are two configuration words - one for the BCSR and FLASH (when it is assigned to CS0) and the
2
other to the E PROM (when it is assigned to CS0). The two configurations are detailed in Table 5-
3. and Table 5-4. respectively.
a
Table 5-3. BCSR/FLASH Power On Reset Configuration
Flash
Init
Address
[hex]
Description
Value[hex]
0C / (1Cb)
0
Internal arbitration, Internal memory controller, Core enabled, Single PQ2 (60X Bus
modeb), 32 Bit boot port size, Exceptions vectored to 0xFFFxxxxx, Internal space
64 bit slave for external master.
8
B2
L2cache signals configured as BADDRx lines, DP(1:7) configured as L2 cache I/F
and IRQ(6:7),Initial internal space @ 0x0F000000
10
32c / (36d)
Boot memory space @ 0xFE000000 - 0xFFFFFFFF, ABB/IRQ2 pin is ABB, DBB/
IRQ3 pin is DBB, No masking on bus request lines, Local bus pins function as
Local bus (in BCSR) or PCI (in FLASH), PCI is boot master, AP(1;3) configured as
BNKSEL(0:2), APE configured as IRQ7 and CS11 as CS11.
18
45
CS10 configured as BCTL1
a. Programmed into the Flash (E2PROM) memory in addresses 0x0, 0x8, 0x10 & 0x18
b. With L2 Cache
c. Programmed in BCSR - Local Bus pins function is Local Bus
d. Programmed in FLASH - Local Bus pins function is PCI
2
a
Table 5-4. E PROM Power On Reset Configuration
EEPROM
Address
[hex]
Init
Value[hex]
Description
04 / (14b)
0
Internal arbitration, Internal memory controller, Core enabled, Single PQ2 (60X Bus
modeb), 8 Bit Boot size, Exceptions vectored to 0xFFFxxxxx, Internal space 64 bit
slave for external master.
8
B2
L2cache signals configured as BADDRx lines, DP(1:7) configured as L2 cache I/F
and IRQ(6:7),Initial internal space @ 0x0F000000
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2
a
Table 5-4. E PROM Power On Reset Configuration
EEPROM
Address
[hex]
Init
Value[hex]
Description
10
36
Boot memory space @ 0xFE000000 - 0xFFFFFFFF, ABB/IRQ2 pin is ABB, DBB/
IRQ3 pin is DBB, No masking on bus request lines, Local bus pins function as PCI,
PCI is boot master, AP(1;3) configured as BNKSEL(0:2), APE configured as IRQ7
and CS11 as CS11.
18
45
CS10 configured as BCTL1
a. Programmed into the E2PROM in addresses 0x0, 0x8, 0x10 & 0x18
b. With L2 Cache
Table 5-5. SIU REGISTERS’ PROGRAMMING
Init
Value[hex]
Register
Description
RMR
0001
Check-Stop Reset enabled.
IMMR
SYPCR
04700000
Internal space @ 0x047000000
FFFFFFC3
Software watchdog timer count - FFFF, Bus-monitor timing FF, PPC Bus-monitor -
Enabled, Local Bus-monitor - Enabled, S/W watch-dog - disabled, S/W watch-dog
(if enabled) causes reset, S/W watch-dog (if enabled) - prescaled.
BCR
100C0000
Single PQ2 (60X Bus modea), 1 wait-states on address tenure, No L2Cache
(L2Cache assumeda), 1 clock hit delay (when L2cache available), 1-level Pipeline
depth, Extended transfer mode enabled for PCC, Extended transfer mode disabled
for Local Buses, Odd parity for PPC & Local Buses, External Master delay enabled,
Internal space responds as 64 bit slave for external master (not relevant for this
application).
(88444000a)
a. With L2 Cache
5.2.2 Memory Controller Registers Programming
The memory controller on the PQ2FADS-ZU is initialized to 100MHz operation, i.e., registers’
programming is based on 100MHz timing calculation (it will also work for slower bus speeds but
the timing will have to be optimized). There are two possible initializations for the memory
controller:
2
•
•
Flash SIMM is assigned to CS0 and E PROM is assigned to CS4.
2
Flash SIMM is assigned to CS4 and E PROM is assigned to CS0.
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Memory Map and Initialization
Both options are shown in Table 5-6.and Table 5-7.
Table 5-6. Memory Controller Initializations For 100Mhz - FLASH as Boot Device
Init Value
[hex]
Reg.
Device Type
Bus
Description
BR0
SM73228XG1JHBG0 by
Smart Modular Tech.
PPC
FF801801
Base at FF800000, 32 bit port size, no parity,
GPCM
SM73248XG2JHBG0 by
Smart Modular Tech.
FF001801
FE001801
FF800876
FF000876
FE000876
04501801
Base at FF000000, 32 bit port size, no parity,
GPCM
SM73288XG4JHBG0 by
Smart Modular Tech.
Base at FE000000, 32 bit port size, no parity,
GPCM
OR0
SM73228XG1JHBG0 by
Smart Modular Tech.
8MByte block size, CS early negate, 11 w.s.,
Timing relax
SM73248XG2JHBG0 by
Smart Modular Tech.
16MByte block size, CS early negate, 11 w.s.,
Timing relax
SM73288XG4JHBG0 by
Smart Modular Tech.
32MByte block size, CS early negate, 11 w.s.,
Timing relax
BR1
BCSR
PPC
PPC
Base at 04500000, 32 bit port size, no parity,
GPCM
OR1
BR2
FFFF8010
00000041
32 KByte block size, all types access, 1 w.s.
SDRAM
Base at 0, 64 bit port size, no parity, Sdram
machine 1
MT48LC4M32B2
MICRON
by
by
OR2
FE002EC0
32MByte block size, 4 banks per device, row starts
at A7, 12 row lines, internal bank interleaving
allowed, normal AACK operation
BR3
OR3
SDRAM
MT48LC2M32B2
MICRON
Local
Bus
D0001861
FF803280
Base at D0000000, 32 bit port size, no parity,
Sdram machine 2.
8MByte block size, 4 banks per device, row starts
at A9, 11 row lines, internal bank interleaving
allowed, normal AACK operation
BR4
OR4
BR5
OR5
E2PROM
PPC
PPC
C2000801
FFFF8866
04600801
FFFF8E56
Base at C2000000, 8 bit port size, write protect
disabled, no parity, GPCM
AT28HC64B-70JC
Atmel
by
32 KByte block size, CS output half a clock after
address, all types access, 6 w.s., Timing relax
PM5384 - ATM UNI
Base at 04600000, 8 bit port size, no parity, GPCM
on PPC bus.
32K Byte block size, delayed CS assertion, early
CS and WE negation for write cycle, relaxed
timing, 7 w.s. for read, 8 for write, extended hold
time after read.
BR8
OR8
PCI Interrupt Controller
PPC
04731801
FFFF8010
Base at 04730000, 32 bit port size, no parity,
GPCM on PPC bus.
32 KByte block size, all types access, 1 w.s.
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Memory Map and Initialization
2
Table 5-7. Memory Controller Initializations For 100Mhz - E PROM as Boot Device
Init Value
[hex]
Reg.
Device Type
E2PROM
Bus
Description
BR0
PPC
FFF00801
Base at FFFFE000, 8 bit port size, write protect
disabled, no parity, GPCM
OR0
BR1
AT28HC64B-70JC
Atmel
by
FFFF8866
04501801
32 KByte block size, CS output half a clock after
address, all types access, 6 w.s., Timing relax
BCSR
PPC
PPC
Base at 04500000, 32 bit port size, no parity,
GPCM
OR1
BR2
FFFF8010
00000041
32 KByte block size, all types access, 1 w.s.
SDRAM
MT48LC4M32B2
MICRON
Base at 0, 64 bit port size, no parity, Sdram
machine 1
by
by
OR2
FE002EC0
32MByte block size, 4 banks per device, row starts
at A7, 12 row lines, internal bank interleaving
allowed, normal AACK operation
BR3
OR3
SDRAM
MT48LC2M32B2
MICRON
Local
Bus
D0001861
FF803280
Base at D0000000, 32 bit port size, no parity,
Sdram machine 2.
8MByte block size, 4 banks per device, row starts
at A9, 11 row lines, internal bank interleaving
allowed, normal AACK operation
BR4
SM73228XG1JHBG0 by
Smart Modular Tech.
PPC
C3801801
C3001801
C2001801
FF800876
FF000876
FE000876
04600801
FFFF8E56
Base at C3800000, 32 bit port size, no parity,
GPCM
SM73248XG2JHBG0 by
Smart Modular Tech.
Base at C3000000, 32 bit port size, no parity,
GPCM
ASM73288XG4JHBG0
by Smart Modular Tech.
Base at C2000000, 32 bit port size, no parity,
GPCM
OR4
SM73228XG1JHBG0 by
Smart Modular Tech.
8MByte block size, CS early negate, 11 w.s.,
Timing relax
SM73248XG2JHBG0 by
Smart Modular Tech.
16MByte block size, CS early negate, 11 w.s.,
Timing relax
SM73288XG4JHBG0 by
Smart Modular Tech.
32MByte block size, CS early negate, 11 w.s.,
Timing relax
BR5
OR5
PM5384 - ATM UNI
PPC
PPC
Base at 04600000, 8 bit port size, no parity, GPCM
on PPC bus.
32K Byte block size, delayed CS assertion, early
CS and WE negation for write cycle, relaxed
timing, 7 w.s. for read, 8 for write, extended hold
time after read.
BR8
OR8
PCI Interrupt Controller
04731801
FFFF8010
Base at 04730000, 32 bit port size, no parity,
GPCM on PPC bus.
32 KByte block size, all types access, 1 w.s.
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Memory Map and Initialization
Table 5-8. Memory Controller Initializations For 100Mhz
Init Value
[hex]
Reg.
Device Type
Bus
PPC
Description
PSDMR
MT48LC4M32B2
(32 MByte)
C24B36A3
Page Based Interleaving, Refresh enabled, normal
operation mode, address muxing mode 2, A14-A16 on
BNKSEL, A8 on PSDA10, 8 clocks refresh recovery, 3
clocks precharge to activate delay, 3 clocks activate to
read/write delay, 4 beat burst length, 2 clock last data
out to precharge, 2 clock write recovery time, no extra
cycle on address phase, normal timing for control lines,
3 clocks CAS latency.
Single
PQ2
Bus
Mode
LSDMR
MT48LC2M32B2
(8 MByte)
Local
Bus
C28737A3
Page Based Interleaving, Refresh enabled, normal
operation mode, address muxing mode 2, A16-A18 on
BNKSEL, A9 on LSDA10, 8 clocks refresh recovery, 3
clocks precharge to activate delay, 3 clocks activate to
read/write delay, 8 beat burst length, 2 clock last data
out to precharge, 2 clock write recovery time, no extra
cycle on address phase, normal timing for control lines,
3 clocks CAS latency.
PSRT
PPC Bus Sdram Supported
PPC
13
13
Divide MPTPR output by 20 (PSRT +1) Generates
refresh every 8.2 µsec, while 15.6µsec required. This
will work also for 66MHz bus (12.4µsec).
LSRT
MPTPR
Local
Bus
Divide MPTPR output by 20 (PSRT +1) Generates
refresh every 8.2 µsec, while 15.6µsec required. This
will work also for 66MHz bus (12.4µsec).
All SDRAMs on board
2800
Divide Bus clock by 41 (MPTPR+1) (decimal)
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Physical Properties
6
Physical Properties
6.1
Power Supply
The board gets the power from the ATX Power Supply (it seats in an ATX Chassis). All the power
rails on the board are derived from the ATX Power Supply. There are 4 power rails with the PQ2:
1. VDDH (I/O)
2. VDDL (Internal Logic)
3. VCCSYN (CPM PLL)
4. VCCSYN1 (Core PLL)
and there are 5 power rails on the PQ2FADS-ZU:
1. VCC (5V) rail
2. Stand By (5V) rail
3. V3.3 (3.3V) rail
4. VDDL (1.7V-2.5V) rail
5. +12V rail
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Physical Properties
6. -12V rail
PCI Connectors
PQ2FADS-ZU Logic & Peripherals
5V
5V
3.3V
12V
3.3V
5V
-12V
3.3V
3.3V
VDDL
2-2.5V
VCCSYN
VDDL
VCCSYN1
VDDH
ATX
Power Supply
PQ2
Figure 6-1. PQ2FADS-ZU Power Scheme
To support off-board application development, the power buses are connected to the expansion
connectors so that external logic may be powered directly from the board. The maximum current
allowed to be drawn from the board on each bus also depends on the current drawn by the PCI
bus. The figures are shown in Table 6-1.
Table 6-1. Expansion Connectors Maximum Current Consumption
Power Bus
Max. Current
VCC
V3.3
TBD
TBD
The PCI Standard specifies that each Add-In card should consume maximum 25Watt from all
power sources combined. The maximum current consumption allowed per power source for a
total of 25Watt according to the PCI Standard is shown in Table 6-2.
Table 6-2. Maximum Power Consumption Per Add-In Card
Power Rail
Add-In Card
5V
5A Max. (system depended)
7.6A Max. (system depended)
500mA
3.3V
12V
-12V
100mA
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Physical Properties
6.1.1 5V Rail
Some of the PQ2FADS-ZU peripherals (not including the PCI Add-In cards which should be
3.3V ONLY on the PCI interface but can use 5V for other components on-board) reside on the 5V
bus. Since the PQ2 is not 5V tolerant, buffering is provided between 5V peripherals and the PQ2,
protecting the PQ2 from the higher voltage level.
6.1.2 3.3V Rail
The PQ2, SDRAM, PCI Add-In cards, address and data buffers are powered by the 3.3 bus, which
is produced from the ATX power supply.
6.1.3 5V Stand By Rail
The 5V stand by power rail comes from the ATX Power Supply. Its’ only use is to power the logic
required to support the power button in the front panel on the ATX chasis.
6.1.4 VDDH Rail
The PQ2’s VDDH power bus (3.3V) is produced from the 5V bus using a low-voltage drop linear
voltage regulator made by Micrel, the MIC29501-3.3BU.
A production option is made so that the level on this bus may be varied by means of trimming
potentiometer - TR2. However this will requires replacing some components. This option allows
the VDDH to be in the range of 3.0V - 3.6V.
6.1.5 VDDL Bus
The PQ2’s internal logic and the PLL are powered with a lower-voltage power source, voltage of
which may be in 3 ranges of levels:
•
•
•
2.3V - 2.7V
1.7V - 1.9V
1.8V - 2.0V
Selection between the above range levels is done via a jumper, which selects between different
resistor values within the VDDL’s variable regulator feedback network, while the fine tuning
within a range is done by means of a trimming potentiometer.
Changing the voltage to the Core logic of the PQ2, obviously has an influence over the maximal
speed of the core. There is the power-speed trade-off, i.e., lower operation speeds may be obtained
with lower voltage supply.
6.1.6 12V Rail
The 12V bus from the ATX Power Supply supports the PCI slots and the VPP 12V option from
programming the FLASH.
6.1.7 -12V Rail
The -12V bus from the ATX Power Supply supports the PCI slots.
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Physical Properties
6.2
Connectors
The PQ2FADS-ZU has connectors attached, to serve the following functions:
1. ATX Power Supply
2. 100 / 10 - Base-T Ethernet ports
3. ATM 155Mbps port
4. RS232 port 1
5. RS232 port 2
6. CPM Expansion
7. COP / JTAG
8. Logic Analyzer Connectors
9. Programmable logic In System Programming (ISP)
10. PCI Connectors
11. System Expansion
12. USB Connector
13. Parallel Port Connector
6.2.1 ATX Power Connector
The ATX power connector is a 20-lead, standard ATX power connector. The female part is
soldered to the PCB, while the plug is connected to the power supply. That way fast connection /
disconnection of power is facilitated.
6.2.2 Fast Ethernet Port Connectors
The Ethernet connector on the PQ2FADS-ZU is a Twisted-Pair (100/10-Base-T) connector. Use is
0
done with 90 RJ45-8 connector.
6.2.3 ATM 155 Port Connection
The ATM 155 I/F to the media, is optical rather than electrical. Use is done with HP’s HFBR 5805
optical I/F which is placed on the edge of the board for convenient connection.
6.2.4 RS232 PortS Connector
0
The RS232 port connector is a stacked 9 pin, 90 , female D-Type connector, which saves on board
space (made of two connectors for two ports).
6.2.5 CPM Expansion Connector
The CPM expansion connectors carries all CPM pins, i.e., Port A to Port D signals. Use done with
DIN 41612, 128 pin T.H. PCB connector, residing on the board, allowing convenient vertical
connection to off-board tools. Power supply pins are also provided through this connector.
6.2.6 COP/JTAG Port Connector
The debug port connector is a Motorola standard COP/JTAG connector for the 60X processors
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Physical Properties
O
family.It is a generic 16 pin (2 X 8), Male, SMD, 90 protected header connector.
6.2.7 Logic Analyzer Connectors
To support fast connection to HPs’ 16500 Logic Analyzers series for debugging purposes, a set of
dedicated connectors is provided. Use is done with 38 pin, SMT, high density, matched
impedance MICTOR connectors made by AMP.
These connectors carry the unbuffered 60X signals and should be placed as near to the PQ2 as
possible to provide short PCB routes, yielding better reflections and crosstalk immunity. They do
not carry the PCI bus signals due to the restrictions enforced by the PCI Standard. There are also
connectors for the CPM signals.
6.2.8 Mach’s In System Programming (ISP) Connector
This is a 10 pin generic 0.100" pitch header connector, providing In System Programming capability for
Vantis made programmable logic on board.
6.2.9 PCI Connectors
A set of three standard PCI 3.3V keyed, 124 pin, 32-bit connectors is provided for connecting up
to three PCI Add-In cards.
6.2.10 System Expansion Connector
The System Expansion Connector is a 128 pin, DIN 41612 connector, which provides a minimal system I/
F required to interface to other tool-boards which may use the CPM Expansion Connector. This connector
contains 16 bit (lower PPC bus) address lines, 16 bit (higher PPC bus) Data lines plus useful GPCM and
UPM control lines.
6.2.11 USB Connector
The USB connector is standard type A type A USB connector.
6.2.12 Parallel Port Connector
The parallel connector is a standard 25 pin D-Type male connector.
6.3
PCB Layout
The PQ2FADS-ZU layout was done in a manner suitable for high-frequency operation and it
follows closely the PCI Standard layout recommendations. Following is a list of measures which
are taken to meet this design goal:
•
•
•
•
Traces are as short as possible.
Clock signals and sensitive strobe signals are shielded and routed as a chain.
Multilayer PCB, with ground and supply layers.
PCI signals lengths and impedance according to PCI Standard Rev. 2.2.
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Support Information
7
Support Information
In this chapter all information needed for support, maintenance and connectivity to the PQ2-ADS-
PCI is provided.
7.1
Interconnect signals
The PQ2FADS-ZU interconnects with external devices via the following set of connectors:
1. P1 - RS232 ports 1 and 2
2. P2 - USB Connector
3. P3 and P4 - 100 / 10 - Base-T Ethernet ports
4. P15 - COP / JTAG
5. P7 - CPM Expansion
6. P11, P12, P13, P14, P16, P17, P18, P23, P28,P29,P30 - Logic Analyzer MICTOR
Connectors
7. P10, P8, P9 - PCI Slots Connectors
8. P27 - ATX Power Supply Connector
9. P26,P20 - Mach/Lattice and ALTERA In System Programming (ISP)
10. P25 - System Expansion
11. P31 - Parallel Port connector
7.1.1 P1 - RS232 ports 1 and 2 Connectors
P1 is a dual 9 Pin D-Type connectors as described in Table 7-1.
Table 7-1. P1 Connector
Pin No.
Signal Name
Description
Carrier Detect output from the PQ2FADS-ZU.
1
2
3
4
5
6
CD
TX
Transmit Data output from the PQ2FADS-ZU.
Receive Data input to the PQ2FADS-ZU.
Data Terminal Ready input to the PQ2FADS-ZU.
Ground signal of the PQ2FADS-ZU.
RX
DTR
GND
DSR
Data Set Ready output from the PQ2FADS-ZU.
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Table 7-1. P1 Connector
Pin No.
Signal Name
Description
7
8
9
N.C.
CTS
N.C.
No connect
Clear To Send output from the PQ2FADS-ZU.
No connect
7.1.2 P3 and P4 - 100/10 - Base-T Ethernet port Connector
P3 or P4 is a RJ-45 Type Connector for Twisted Pair Ethernet as described in Table 7-2.
Table 7-2. P3,P4 - 100/10 Base-T Ethernet Connector
Pin No.
Signal Name
TPTX
Description
1
2
3
4
5
6
7
8
Twisted-Pair Transmit Data positive output from the PQ2FADS-ZU.
Twisted-Pair Transmit Data negative output from the PQ2FADS-ZU.
Twisted-Pair Receive Data positive input to the PQ2FADS-ZU.
Not connected, Bob Smith terminated on the PQ2FADS-ZU.
TPTX~
TPRX
N.C.
TPRX~
N.C.
Twisted-Pair Receive Data negative input to the PQ2FADS-ZU.
Not connected, Bob Smith terminated on the PQ2FADS-ZU.
7.1.3 P15 - COP / JTAG Connector
P15 is a Motorola standard COP / JTAG connector for the 60X processors family. It is a 16 pin
protected header connector as described in Table 7-3.
Table 7-3. P15 - COP/JTAG Connector
Pin No.
1
Signal Name
Attribute
O
Description
TDO
Transmit Data Output. This the PQ2’s JTAG serial data output driven by
Falling edge of TCK.
2
3
GND
TDI
O
I
Digital GND. Main GND plane.
Transmit Data In. This is the JTAG serial data input of the ADS,
sampled on the rising edge of TCK.
4
TRST#
I
Test port Reset~ (L). When this signal is active (Low), it resets the JTAG
logic of the PQ2. This line is pull-down on the ADS with a 1KΩ resistor,
to provide constant reset of the JTAG logic.
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Table 7-3. P15 - COP/JTAG Connector
Pin No.
5
Signal Name
Attribute
O
Description
QREQ#
Quiescent Request (L). When asserted (low), this line indicates that the
PQ2 desires to enter low-power mode. This signal may be required by a
debug station.
6
7
3v3
O
I
3.3V power supply bus.
TCK
Test port Clock. This clock shifts in / out data to / from the JTAG logic.
Data is driven on the falling edge of TCK and is sampled both internally
and externally on it’s rising edge.
TCK is pulled up internally by the PQ2.
8
9
N.C.
TMS
-
I
Not Connected.
Test Mode Select. This signal qualified with TCK in a same manner as
TDI, changes the state of the JTAG machine. This line is pulled up
internally by the PQ2.
10
11
GND
O
Digital GND. Main GND plane.
SRESET#
I/O, O.D. Soft Reset (L). This is the PQ2’s soft reset which is in fact a non-
maskable interrupt, making the PPC take the reset exception from the
reset vector. This line may be driven by the PQ2 as well during soft-reset
sequence, for 512 system clocks. This line is pulled up on the ADS with
a 1KΩ resistor. When driven externally, it MUST be driven with an
Open Drain gate. Failure to do so may result in permanent damage
to the PQ2 and / or to ADS logic.
12
13
GND
O
Digital GND. Main GND plane.
HRESET#
I/O, O.D. PQ2’s Hard Reset (L). When asserted by an external H/W, generates
Hard-Reset sequence for the PQ2. During that sequence, asserted by the
PQ2 for 512 system clocks. Pulled Up on the ADS using a 1KΩ resistor.
When driven by an external tool, MUST be driven with an Open
Drain gate. Failure to do so may result in permanent damage to the
PQ2 and / or to ADS logic.
14
15
N.C.
-
Not Connected.
XBR3#
(CKSTOP_OUT#)
I/O
Normally configured as XBR3# which has no function with this
connector. May be configured as CKSTP_OUT# - Check Stop Out (L).
When asserted (Low) indicates that the PQ2 core has entered a Check-
Stop state.
16
GND
O
Digital GND. Main GND plane.
7.1.4 P7 - CPM Expansion Connector
0
P7 is a 128 pin, 90 , DIN 41612 connector, which allows for convenient expansion of the PQ2’s
serial ports. This connector contains all CPM pins plus power supply pins, to provide for easy tool
connection as described in Table 7-4.
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Support Information
Table 7-4. P4 - CPM Expansion Connector
Pin No.
A1
Signal Name
Attribute
I/O, T.S.
Description
RS_RXD1 (PD31a)
When RS232 port #1 is enabled, this signal is the receive data line for
that port. When this port is disabled, this signal is tristated and may be
used to any available alternate function for PD31.
A2
RS_TXD1 (PD30)
I/O, T.S.
When RS232 port #1 is enabled, this signal is the transmit data line for
that port. When this port is disabled, this signal may be used to any
available alternate function for PD30.
A3
A4
PD29
I/O, T.S
I/O, T.S.
PQ2’s Port D 29 line. Parallel I/O or CPM dedicated line.May be used
for any of it’s available functions.
RS_RXD2 (PD28)
When RS232 port #2 is enabled, this signal is the receive data line for
that port. When this port is disabled, this signal is tristated and may be
used to any available alternate function for PD28.
A5
RS_TXD2 (PD27)
I/O, T.S.
I/O, T.S.
When RS232 port #2 is enabled, this signal is the transmit data line for
that port. When this port is disabled, this signal may be used to any
available alternate function for PD27.
A6
A7
PD26
PQ2’s PD(26:18) Port D lines. Parallel I/O or CPM dedicated lines. May
be used for any of their available functions.
PD25
A8
PD24
A9
PD23
A10
A11
A12
A13
A14
A15
PD22
PD21
PD20
PD19
PD18
ATMRXPTY (PD17)
I/O, T.S.
I/O, T.S.
ATM Receive Parity Line. When the ATM port is enabled, this line is
connected to the receive parity of the PM5350 ATM UNI. When this
port is disabled, this signal is tristated and may be used for any available
function of PD17.
A16
ATMTXPTY (PD16)
ATM Transmit Parity Line. When the ATM port is enabled, this line is
connected to the transmit parity of the PM5350 ATM UNI. When this
port is disabled, this signal may be used for any available function of
PD16.
A17
A18
I2CSDA (PD15)
I2CSCL (PD14)
I/O, T.S.
I/O, T.S.
This signal is connected to the serial I2C data line. This line may be used
off-board as an I2C data line for external I2C device.
This signal is connected to the serial I2C clock line. This line may be
used off-board as an I2C clock line for external I2C device.
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Table 7-4. P4 - CPM Expansion Connector
Pin No.
Signal Name
Attribute
I/O, T.S.
Description
A19
A20
A21
A22
A23
A24
A25
A26
A27
A28
A29
PD13
PD12
PD11
PD10
PD9
PQ2’s PD(13:4) Port D lines. Parallel I/O or CPM dedicated lines. May
be used for any of their available functions.
PD8
PD7
PD6
PD5
PD4
ATMRCLKDIS
I
ATM Receive Clock Out Disable. When active (H), the ATMRCLK
output, on pin C29 of this connector, is Tri-stated. When either not
connected or driven low, ATMRCLK on pin C29, is enabled. This
provides compatibility with ENG revision of T/ECOM communication
tools.
A30
A31
A32
B1
EXPVCC
O
5V Supply. Connected to ADS’s 5V VCC plane. Provided as power
supply for external tool.
ATMTXEN# (PA31)
I/O, T.S.
ATM Transmit Enabled (L). When this signal is asserted (Low), while
the ATM port is enabled and ATMTFCLK is rising, an octet of data,
ATMTXD(7:0), is written into the transmit FIFO of the PM5350. When
the ATM port is disabled, this line may be used for any available
function of PA31.
B2
B3
ATMTCA (PA30)
ATMTSOC (PA29)
I/O, T.S.
ATM Transmit Cell Available (H). When this signal is asserted (High),
while the ATM port is enabled, it indicates that the transmit FIFO of the
PM5350 is empty and ready to except a new cell. When negated, it may
show either that the transmit FIFO is Full or close to Full, depending on
PM5350 internal programming.
When the ATM port is disabled, this line may be used for any available
function of PA30.
I/O, T.S.
ATM Transmit Start Of Cell (H). When this signal is asserted (High) by
the PQ2, while the ATM port is enabled, it indicates to the PM5350 the
start of a new ATM cell over ATMTXD(7:0), i.e., the 1’st octet is present
there.
When the ATM port is disabled, this line may be used for any available
function of PA29.
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Table 7-4. P4 - CPM Expansion Connector
Pin No.
B4
Signal Name
Attribute
I/O, T.S.
Description
ATMRXEN# (PA28)
ATM Receive Enable (L). When this signal is asserted (Low), while the
ATM port is enabled and ATMRFCLKb goes high, on octet of data is
available at the PM5350’s ATMRXD(7:0) lines.
When negated while ATMRFCLK goes high data on ATMRXD(7:0) is
invalid, however driven.
When the ATM port is disabled, this line may be used for any available
function for PA28.
B5
B6
ATMRSOC (PA27)
ATMRCA (PA26)
I/O, T.S.
I/O, T.S.
I/O, T.S.
ATM Receive Start Of Cell (H). When this signal is asserted (High),
while the ATM port is enabled, it indicates, that the 1’st octet of data for
the received cell is available at the PM5350’s ATMRXD(7:0) lines. This
line is updated over the rising edge of ATMRFCLK.
When the ATM port is disabled, this line is tristated and may be used for
any available function for PA27.
ATM Receive Cell Available (H). When this signal is asserted (High),
while the ATM port is enabled and ATMRFCLK goes high, it indicates
that the PM5350’s receive FIFO is either full or that there are 4 empty
bytes left in it - PM5350 internal programming dependent.
When the ATM port is disabled, this line is tristated and may be used for
any available function of PA26.
B7
ATMTXD0 (PA25)
ATMTXD1 (PA24)
ATMTXD2 (PA23)
ATMTXD3 (PA22)
ATMTXD4 (PA21)
ATMTXD5 (PA20)
ATMTXD6 (PA19)
ATMTXD7 (PA18)
ATMRXD7 (PA17)
ATMRXD6 (PA16)
ATMRXD5 (PA15)
ATMRXD4 (PA14)
ATMRXD3 (PA13)
ATMRXD2 (PA12)
ATMRXD1 (PA11)
ATMRXD0 (PA10)
ATM Transmit Data (7c:0). When the ATM port is enabled, this bus
carries the ATM cell octets, written to the PM5350’s transmit FIFO. This
bus is considered valid only when ATMTXEN# is asserted and are
sampled on the rising edge of ATMTFCLK.
When the ATM port is disabled, these lines may be used for any
available respective function.
B8
B9
B10
B11
B12
B13
B14
B15
B16
B17
B18
B19
B20
B21
B22
I/O, T.S.
ATM Receive Data (7c:0). When the ATM port is enabled, this bus
carries the cell octets, read from the PM5350 receive FIFO. This lines
are updated on the rising edge of ATMRFCLKb.
When the ATM port is disabled, these lines are tristated and may be used
for any available respective function.
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Table 7-4. P4 - CPM Expansion Connector
Pin No.
Signal Name
Attribute
I/O, T.S.
Description
B23
B24
B25
B26
B27
B28
B29
B30
B31
B32
C1
PA9
PQ2’s Port A (9:0). Parallel I/O or dedicated CPM lines. May be used
for any of their available functions.
PA8
PA7
PA6
PA5
PA4
PA3
PA2
PA1
PA0
FETHTXER (PB31)
I/O, T.S.
Fast-Ethernetd Transmit Error (H). When the Ethernet port is enabled,
this signal will be asserted (High) by the PQ2 when an error is
discovered in the transmit data stream. When the port is operation at 100
Mbps, the LXT970 responds by sending invalid code symbols on the
line.
When the Ethernet port is disabled, this line may be used for any
available function of PB31.
C2
FETHRXDV (PB30)
I/O, T.S.
Fast-Ethernet Receive Data Valid (H). When this signal is asserted
(High) while the Fast Ethernet port is enabled and FETHRXCK goes
high, it indicates that data is valid on the MII Receive Data lines -
FETHRXD(3:0).
When the Fast Ethernet port is disabled, this line is tristated and may be
used for any available function go PB30.
C3
C4
FETHTXEN (PB29)
FETHRXER (PB28)
I/O, T.S.
I/O, T.S.
Fast-Ethernet Transmit Enable (H). The PQ2 will assert (High) this line,
to indicate data valid on the FETHTXD(3:0) lines.
When the Fast-Ethernet port is disabled, this line may be used for any
available function of PB29.
Fast-Ethernet Receive Error (H). When this signal is asserted (High) by
the LXT970, while the Ethernet port is enabled and FETHRXCK goes
high, it indicates that the port is receiving invalid data symbols from the
network.
When the Ethernet port is disabled, this line is tristated and may be used
for any available function of PB28.
C5
FETHCOL (PB27)
I/O, T.S.
Fast-Ethernet Port Collision Detected (H). When this signal is asserted
(High) by the LXT970, while the ethernet port is enabled, it indicates a
Collision state over the line. When the LXT970 is in Full-Duplex mode,
this line is inactive.
When the Ethernet port is disabled, this line is tristated and may be used
for any available function of the PB27.
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Table 7-4. P4 - CPM Expansion Connector
Pin No.
C6
Signal Name
Attribute
I/O, T.S.
Description
FETHCRS (PB26)
Fast-Ethernet Carrier Sense (H). When this signal is asserted (High),
while the Ethernet port is enabled and the LXT970 is in half-duplex
mode, it indicates that either the transmit or receive media are non-idle.
When the LXT970 is in either full-duplex or repeater operation, it
indicates that the receive medium is non-idle.
When the Ethernet port is disabled, this line may be used for any
available function of PB26.
C7
FETHTXD3 (PB25)
I/O, T.S.
I/O, T.S.
I/O, T.S.
Fast Ethernet Transmit Data (3:0). This is the MII transmit data bus. The
PQ2 drives these lines according to rising edge of FETHTXCK.
When the ethernet port is disabled, these lines may be used for any
available respective function.
C8
FETHTXD2 (PB24)
C9
FETHTXD1 (PB23)
C10
C11
C12
C13
C14
C15
C16
C17
C18
C19
C20
C21
C22
C23
C24
C25
C26
C27
C28
C29
FETHTXD0 (PB22)
FETHRXD0 (PB21)
Fast Ethernet Receive Data (3:0). This is the MII receive data bus. The
LXT970 drives these lines according to rising edge of FETHRXCK.
When the ethernet port is disabled, these lines are tristated and may be
used for any available respective parenthesized function.
FETHRXD1 (PB20)
FETHRXD2 (PB19)
FETHRXD3 (PB18)
PB17
PQ2’s Port B (17:4) Parallel I/O lines. May be used to any of their
available functions.
PB16
PB15
PB14
PB13
PB12
PB11
PB10
PB9
PB8
PB7
PB6
PB5
PB4
ATMRCLK
O, T.S.
ATM Receive Clock. A divide by 8 of the ATM line clock recovered by
the ATM receive logic. Provided to assist Circuit Emulation Tool.
Enabled only when pin A29 of this connector is either not connected or
driven low. Otherwise, Tri-stated.
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Table 7-4. P4 - CPM Expansion Connector
Pin No.
Signal Name
Attribute
O
Description
C30
C31
C32
D1
GND
Digital Ground. Connected to main GND plane of the ADS.
PC31
I/O, T.S.
PQ2’s Port C (31:22) Parallel I/O lines. May be used to any of their
available functions.
D2
PC30
D3
PC29
D4
PC28
D5
PC27
D6
PC26
D7
PC25
D8
PC24
D9
PC23
D10
D11
PC22
ATMTFCLK (PC21)
I/O, T.S.
ATM Transmit FIFO Clock. Upon the rising edge of this clock (driven
by the PQ2), while the ATM port is enabled, the cell octets are written to
the PM5350’s transmit FIFO. This clock samples ATMTXD(7:0),
ATMTXPTY, ATMTXEN# and ATMTSOC.
When the ATM port is disabled, this line may be used for any available
function of PC21.
D12
D13
PC20
I/O, T.S.
I/O, T.S.
PQ2’s Parallel I/O Port-C 20. Parallel I/O line. May be used for any of
its available functions
FETHRXCK (PC19)
Fast-Ethernet Receive Clock. When the Ethernet port is enabled, this
clock (25 MHz for 100 Mbps, 2.5 MHz for 10 Mbps) is extracted from
the received data and driven to the PQ2 to qualify incoming receive
data.
When the Ethernet port is disabled, this line is tristated and may be used
for any available function of PC19
D14
FETHTXCK (PC18)
I/O, T.S.
Fast-Ethernet Transmit Clock. When the Ethernet port is enabled, this
clock (25 MHz for 100 Mbps, 2.5 MHz for 10 Mbps) is normally
extracted from the received data and driven to the PQ2 to qualify out
coming transmit data. In Slave mode (not used with this application) this
clock should be input to the LXT970.
When the Ethernet port is disabled, this line is tristated and may be used
for any available function of PC18
D15
D16
D17
PC17
PC16
PC15
I/O, T.S.
PQ2’s Port C (17:15) Parallel I/O lines. May be used to any of their
available functions.
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Table 7-4. P4 - CPM Expansion Connector
Pin No.
D18
Signal Name
Attribute
I/O, T.S.
Description
RS_CD1# (PC14)
RS232 Port 1 Carrier Detect (L). Connected via RS232 transceiver to
RS232 DTR1# input, allowing detection of a connected terminal to this
port. This line is simply a PI/O input line to the PQ2.
When RS232 Port 1 is disabled, this line is tristated and may be used for
any available function of PC14.
D19
D20
PC13
I/O, T.S.
I/O, T.S.
PQ2’s Port C 13 Parallel I/O line. May be used to any of its available
functions.
RS_CD2# (PC12)
RS232 Port 2 Carrier Detect (L). Connected via RS232 transceiver to
RS232 DTR2# input, allowing detection of a connected terminal to this
port. This line is simply a PI/O input line to the PQ2.
When RS232 Port 2 is disabled, this line is tristated and may be used for
any available function of PC12.
D21
D22
PC11
I/O, T.S.
I/O, T.S.
PQ2’s Port C 11 Parallel I/O line. May be used to any of its available
functions.
FETHMDC (PC10)
Fast-Ethernet Port Management Data Clock. This slow clock (S/W
generated) qualifies the management data I/O to read / write the
LXT970’s internal registers.
When the Ethernet port is disabled, this line may be used for any
available function of PC10.
D23
FETHMDIO (PC9)
I/O, T.S.
I/O, T.S.
Fast-Ethernet Port Management Data I/O. This signal serves as
bidirectional serial data line, qualified by FETHMDC, to allow read /
write the LXT970’s internal registers.
When the Ethernet port is disabled, this line may be used for any
available function of PC9.
D24
D25
D26
D27
D28
D29
D30
D31
D32
PC8
PC7
PC6
PC5
PC4
PC3
PC2
PC1
PC0
PQ2’s Port C (8:0) Parallel I/O lines. May be used to any of their
available functions.
a. The functions in parenthesis, are PQ2’s parallel I/Os.
b. Normally connected to ATMTFCLK on the ADS.
c. MS bit.
d. For that matter, both 100-Base-T and 10-Base-T.
7.1.5 P11, P12, P13, P14, P16, P17, P18, P23, P28,P29, P30-
Logic Analyzer MICTOR Connectors
These are 38 pin, SMT, high density, matched impedance connector made by AMP. They contain
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the PQ2 60X bus, 60X system and memory controller signals, unbuffered. The pinout of these
connectors is shown in the schematics. For signal description of these connectors, see the PQ2
User’s Manual.
7.1.6 P10, P8, P9 - PCI Connectors
These are 2 X 62 , 3.3V keyed, 32 bit PCI connectors. The pinout of each connector is available in
Table 7-5.
For signal descriptions for these connectors, see the PCI v2.2 Standard.
Table 7-5. P7, P8, P9 - PCI Connectors
Pin
Number
Side B
Comments
Side A
Comments
1
2
-12V
TCK
Not Connected
TRST#
+12V
3
Ground
TDO
TMS
4
TDI
5
+5V
+5V
6
+5V
INTA#
INTC#
+5V
7
INTB#
INTD#
PRSNT1#
Reserved
PRSNT2#
Not Connected
Not Connected
Connected to GND
Not Connected
Connected to GND
3.3 volt key
Not Connected
Not Connected
8
9
Reserved
+3.3V(I/O)
Reserved
10
11
12
Not Connected
3.3 volt key
CONNECTOR
KEY
CONNECTOR
KEY
13
CONNECTOR
KEY
3.3 volt key
CONNECTOR
KEY
3.3 volt key
14
15
16
17
18
19
20
21
Reserved
Ground
CLK
Not Connected
3.3Vaux
RST#
Not Connected
+3.3V (I/O)
GNT#
Ground
REQ#
Ground
PME#
+3.3V (I/O)
AD[31]
AD[29]
Not Connected
AD[30]
+3.3V
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Table 7-5. P7, P8, P9 - PCI Connectors
Pin
Number
Side B
Comments
Side A
Comments
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
Ground
AD[27]
AD[25]
+3.3V
AD[28]
AD[26]
Ground
AD[24]
IDSEL
+3.3V
C/BE[3]#
AD[23]
Ground
AD[21]
AD[19]
+3.3V
AD[22]
AD[20]
Ground
AD[18]
AD[16]
+3.3V
AD[17]
C/BE[2]#
Ground
IRDY#
+3.3V
FRAME#
Ground
TRDY#
Ground
STOP#
+3.3V
DEVSEL#
Ground
LOCK#
PERR#
+3.3V
Not Connected
SDONE
SBO#
Not Connected
Not Connected
SERR#
+3.3V
Ground
PAR
C/BE[1]#
AD[14]
Ground
AD[12]
AD[10]
M66EN
AD[15]
+3.3V
AD[13]
AD[11]
Ground
AD[09]
Coupled to GND,
using a 0.01uF
capacitor
50
51
Ground
Ground
Ground
Ground
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Table 7-5. P7, P8, P9 - PCI Connectors
Pin
Number
Side B
Comments
Side A
Comments
52
53
54
55
56
57
58
59
60
61
62
AD[08]
AD[07]
+3.3V
C/BE[0]#
+3.3V
AD[06]
AD[04]
Ground
AD[02]
AD[00]
+3.3V (I/O)
REQ64#
+5V
AD[05]
AD[03]
Ground
AD[01]
+3.3V (I/O)
ACK64#
+5V
Not Connected
Not Connected
+5V
+5V
7.1.7 P27 - ATX Power Supply Connector
This is a standard ATX Form Factor Power Connector as described in Table 7-6.
Table 7-6. P27 - ATX Power Supply Connector
Pin
Signal
Pin
Signal
1
2
+3.3VDC
+3.3VDC
Groung
11
12
13
14
15
16
17
18
19
20
+3.3VDC-Sense
-12VDC
Groung
3
4
+5VDC
Power_On
Groung
5
Groung
6
+5VDC
Groung
7
Groung
Groung
8
Power_OK
+5VStand_By
+12VDC
-5VDC
9
+5VDC
10
+5VDC
7.1.8 P19,P20 - Mach/Lattice ISP Connector
This is a 10 pin generic 0.100" pitch header connector, providing In System Programming (ISP)
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capability for Latice made programmable logic on board. The pinout of P15 is shown in Table 7-7.
Table 7-7. P15 - Lattice ISP Connector
Pin No.
1
Signal Name
ISPTCK
Attribute
I
Description
ISP Test port Clock. This clock shifts in / out data to / from the
programmable logic JTAG chain.
2
3
N.C.
-
I
Not Connected.
ISPTMS
ISP Test Mode Select. This signal qualified with ISPTCK, changes the
state of the prog. logic JTAG machine.
4
5
GND
O
I
Digital GND. Main GND plane.
ISPTDI
ISP Transmit Data In. This is the prog. logic’s JTAG serial data input,
sampled on the rising edge of TCK.
6
7
VCC
O
O
5V power supply bus.
ISPTDO
ISP Transmit Data Output. This the prog. logic’s JTAG serial data output
driven by Falling edge of TCK.
8
9
GND
N.C.
N.C.
O
-
Digital GND. Main GND plane.
Not Connected.
10
-
Not Connected.
7.1.9 P27 - System Expansion Connector
0
P27 is a 128 pin, 90 , DIN 41612 connector, which provides a minimal system I/F required to
interface various types of communication transceivers. This connector contains 16 bit (lower PPC
bus) address lines, 16 bit (higher PPC bus) Data lines plus useful GPCM and UPM control lines.
The pinout of P17 is shown in Table 7-8.
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Table 7-8. P17 - System Expansion Connector
Pin No.
Signal Name
Attribute
O
Description
A1
A2
EXPA16
EXPA17
EXPA18
EXPA19
EXPA20
EXPA21
EXPA22
EXPA23
EXPA24
EXPA25
EXPA26
EXPA27
EXPA28
EXPA29
EXPA30
EXPA31
EXP12V
Expansion Address (16a:31). This is a Latched-Buffered version of the
PQ2’s PPC Address lines (16:31), provided for external tool connection.
To avoid reflection these lines are series terminated with 43 Ω resistors.
A3
A4
A5
A6
A7
A8
A9
A10
A11
A12
A13
A14
A15
A16
A17
A18
A19
A20
A21
A22
A23
A24
A25
O
These can be connected to the positive 12V source from the PCI edge
connector thru J3. This line is fused by a 0.5A ressetable poly-switch.
N.C.
-
Not Connected.
EXP3.3V
O
3.3V Power Out. These lines are connected to the main 3.3V plane of
the PQ2PCIAI-ADS, this, to provide 3.3V power where necessary for
external tool connected.
N.C.
-
Not Connected.
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Table 7-8. P17 - System Expansion Connector
Pin No.
Signal Name
EXPVCC
Attribute
O
Description
A26
A27
A28
A29
A30
A31
A32
B1
5V Supply. Connected to ADS’s 5V VCC plane. Provided as power
supply for external tool.
GND
O
I
Digital Ground. Connected to main GND plane of the ADS.
B2
B3
B4
TSTAT0
Tool Status (0a:7). These lines may be driven by an external tool to be
read via BCSR2 of the ADS. These lines are pulled-up on the ADS, by
10 KΩ resistors. See also Table 4-11. "BCSR2 Description" on page 61.
B5
TSTAT1
B6
TSTAT2
B7
TSTAT3
B8
TSTAT4
B9
TSTAT5
B10
B11
B12
B13
B14
B15
B16
B17
B18
B19
B20
B21
B22
B23
B24
TSTAT6
TSTAT7
TOOLREV0
TOOLREV1
TOOLREV2
TOOLREV3
EXTOLI0
EXTOLI1
EXTOLI2
EXTOLI3
N.C.
I
I
Tool Revision (0a:3). These lines should be driven by an external tool
with the Tool Revision Code, to be read via BCSR2 of the ADS. These
lines are pulled-up on the ADS, by 10 KΩ resistors. See also Table 4-11.
"BCSR2 Description" on page 61.
External Tool Identification (0a:3). These lines should be driven by an
external tool with the Tool Identification Code, to be read via BCSR2 of
the ADS. These lines are pulled-up on the ADS, by 10 KΩ resistors. See
also Table 4-11. "BCSR2 Description" on page 61
-
Not Connected
EXP3.3V
O
3.3V Power Out. These lines are connected to the main 3.3V plane of
the PQ2PCIAI-ADS, this, to provide 3.3V power where necessary for
external tool connected.
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Table 7-8. P17 - System Expansion Connector
Pin No.
Signal Name
Attribute
Description
B25
B26
B27
B28
B29
B30
B31
B32
C1
N.C.
-
Not Connected
EXPVCC
O
5V Supply. Connected to ADS’s 5V VCC plane. Provided as power
supply for external tool.
GND
O
O
O
O
Digital Ground. Connected to main GND plane of the ADS.
Buffered System Clock..
C2
CLK8
C3
GND
Digital Ground. Connected to main GND plane of the ADS.
C4
BTOOLCS1#
Buffered Tool Chip Select 1 (L). This is a buffered PQ2’s CS6# line,
reserved for an external tool.
C5
BTOOLCS2#
O
Buffered Tool Chip Select 2 (L). This is a buffered PQ2’s CS7# line,
reserved for an external tool.
C6
C7
GND
O
O
Digital Ground. Connected to main GND plane of the ADS.
ATMEN#
ATM Port Enable (L). This line enables the ATM port UNI’s output lines
towards the PQ2. An external tool, using the same pins as does the ATM
port should consult this signal before driving the same lines. Failure to
do so might result in permanent damage to the PM5350 ATM UNI.
C8
C9
ATMRST#
FETHRST#
HRESET#
O
O
ATM Port Reset (L). This signal resets the ATM UNI (PM5350). An
external tool may use this signal to its benefit.
Ethernet Port Reset (L). This signal resets the LXT970 Ethernet
transceiver. An external tool may use this signal to its benefit.
C10
I/O, O.D. PQ2’s Hard Reset (L). When asserted by an external H/W, generates
Hard-Reset sequence for the PQ2. During that sequence, asserted by the
PQ2 for 512 system clocks. Pulled Up on the ADS using a 1KΩ resistor.
When driven by an external tool, MUST be driven with an Open
Drain gate. Failure to do so might result in permanent damage to
the PQ2 and / or to ADS logic.
C11
IRQ6#
I
Interrupt Request 6 (L). Connected to PQ2‘s DP6/CSE0/IRQ6# signal.
Pulled up on the ADS with a 10 KΩ resistor. This line is shared with the
ATM UNI’s interrupt line and therefore, when driven by an external
tool, MUST be driven with an Open Drain gate. Failure to do so may
result in permanent damage to the PQ2 or to ADS logic.
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Table 7-8. P17 - System Expansion Connector
Pin No.
C12
Signal Name
IRQ7#
Attribute
I
Description
Interrupt Request 7 (L). Connected to PQ2‘s DP7/CSE1/IRQ7# signal.
Pulled up on the ADS with a 10 KΩ resistor. This line is shared with the
Fast Ethernet transceiver’s interrupt line and therefore, when driven by
an external tool, MUST be driven with an Open Drain gate. Failure
to do so might result in permanent damage to the PQ2 and / or to
ADS logic.
C13
C14
C15
C16
C17
C18
C19
C20
C21
C22
C23
C24
C25
C26
C27
C28
C29
C30
C31
C32
D1
GND
O
Digital Ground. Connected to main GND plane of the ADS.
EXPD0
EXPD1
EXPD2
EXPD3
EXPD4
EXPD5
EXPD6
EXPD7
EXPD8
EXPD9
EXPD10
EXPD11
EXPD12
EXPD13
EXPD14
EXPD15
N.C.
I/O, T.S.
Expansion Data (0a:15). This is a double buffered version of the PPC
bus D(0:15) lines, controlled by on-board logic. These lines will be
driven only if BTOOLCS1# or BTOOLCS2# are asserted. Otherwise
they are tristated.
The direction of these lines is determined by buffered BCTL0, in
function of W/R#.
-
Not Connected
GND
O
O
Digital Ground. Connected to main GND plane of the ADS.
D2
D3
D4
EXPWE0#
EXPWE1#
Expansion Write Enable (0:1) (L). These are buffered GPCM Write
Enable lines (0:1). They are meant to qualify writes to GPCM controlled
8/16 data bus width memory devices. This to provide eased access to
various communication transceivers.
D5
EXPWE0# controls EXPD(0:7) while EXPWE1# controls EXPD(8:15).
These lines may also function as UPM controlled Byte Select Lines,
which allow control over almost any type of memory device.
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Table 7-8. P17 - System Expansion Connector
Pin No.
Signal Name
Attribute
Description
D6
D7
GND
O
O
Digital Ground. Connected to main GND plane of the ADS.
EXPGL0#
EXPGL1#
EXPGL2#
EXPGL3#
EXPGL4#
EXPGL5#
GND
Expansion General Purpose Lines (0:5) (L). These are buffered
GPL(0:5)# lines which assist UPM control over memory device if
necessary. These are output only signals and therefore, do not support H/
W controlled UPM waits.
D8
D9
D10
D11
D12
D13
D14
O
O
Digital Ground. Connected to main GND plane of the ADS.
EXPALE
Expansion Address Latch Enable (H). This is the buffered PQ2‘s ALE,
provided for expansion board’s use.
D15
EXPCTL0
GND
O
O
Expansion Control Line 0. This line is a buffered version of PQ2’s
BCTL0 (Bus Control Line 0) which serves as W/R#, provided for
expansion board’s use.
D16
D17
D18
D19
D20
D21
D22
D23
D24
D25
D26
D27
D28
D29
D30
D31
D32
Digital Ground. Connected to main GND plane of the ADS.
a.MS Bit.
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7.1.10 P2 - USB Connector
This is a four pin standard USB connector type-A. The pinout is shown in .
Table 7-9. P2 - USB Connector
Pin No.
Signal Name
5V Power
Description
1
2
3
4
Power line of the USB cable
Twisted-Pair Transmit Data negative
Twisted-Pair Receive Data positive
Ground connection
D-
D+
GND
7.2
Programmable Logic Equations
There are 4 programmable logic devices on board.
1. U35 - BCSR and PCI Interrupt Controller
2. U41 - Power switch debounce
7.2.1 U35 - BCSR Code
MODULE PQ2HipXBCSR
TITLE 'MPC82xx ads control status register'
"******************************************************************************
"* In this file (Prototype) the following changes were made (12/03/02):
"* - Added support for LBPC in Hard Reset Config Word (determined by external
"* signal nPCI_Mode)
"******************************************************************************
"******************************************************************************
"* In this file (Prototype) the following changes were made (11/01/02):
"* - Added support for USB, Second Fast Ethernet, PARITY option on 60x,
"* CPM MUX control.
"******************************************************************************
"******************************************************************************
"* In this file (Prototype) the following changes were made (07/15/02):
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"* - Added support for a second Fast Ethernet PHY.
"* - Removed support for fast down-load through JTAG.
"******************************************************************************
"******************************************************************************
"* Device declaration.
*
"******************************************************************************
"******************************************************************************
"* #######
*
"* #
#
# ##### ###### ##### #
#
##
#
####
*
"* #
# #
##
#
#
#
# ## # # # #
#
*
"* #####
"* #
#
##### # # # # # # # #
##### # # # ###### #
####
*
##
#
#
#
#
#
#
*
*
"* #
# #
# # # ## # # #
#
#
"* ####### #
#
###### # # # # # # ###### ####
*
"******************************************************************************
"******************************************************************************
"* Pins declaration.
*
"******************************************************************************
"* System i/f pins
"******************************************************************************
SYSCLK
PIN 124;
IntContCs_B
BrdContRegCs_B
DVal_B
PIN 48; " PCI INterrupt Controller CS
PIN 47; " BCSR CS
PIN 53;
R_B_W
PIN 46; " BCTL0 signal
PIN ; " Alternate Buffers Enable source
BCTL1
A7
PIN 69; " for flash support
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A8
PIN 68; " for flash support
PIN 15;
A27
A28
A29
PIN 12;
PIN 11;
D0
D1
D2
D3
D4
D5
D6
D7
D8
D9
D10
D11
PIN 75istype 'com' ;
PIN 22istype 'com' ;
PIN 132istype 'com' ;
PIN 77istype 'com' ;
PIN 16istype 'com' ;
PIN 142istype 'com' ;
PIN 60istype 'com' ;
PIN 87istype 'com' ;
PIN 66istype 'com' ;
PIN 72istype 'com' ;
PIN 70istype 'com' ;
PIN 39istype 'com' ;
"******************************************************************************
"* Board Control Pins. Read/Write.
"******************************************************************************
L2Inh_B
PIN 130istype 'reg,buffer' ; " flash enable.
L2Flush_B
L2Lock_B
L2Clear_B
PIN 42istype 'reg,buffer' ; " 60x bus sdram enable
PIN 112istype 'reg,buffer' ; " bursting sram enable
PIN 128istype 'reg,buffer' ; " local bus sdram enable
SignaLamp0_B
SignaLamp1_B
PIN 44istype 'reg,buffer' ; " status lamp 0 for misc s/w visual
PIN 38istype 'reg,buffer' ; " status lamp 1 for misc s/w visual
AtmEn_B
AtmDis_B
PIN 134istype 'reg,buffer' ; " atm uni enable
PIN 114istype 'com' ; " atm uni disable
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Atm16_B
PIN 28istype 'reg,buffer' ; " UTOPIA 16 bit enable
PIN 116istype 'com' ; " UTOPIA 8 bit enable
Atm8_B
AtmSinglePHY_B
AtmMultiPHY_B
PIN 4istype 'reg,buffer' ; " UTOPIA Single PHY enable
PIN 58istype 'com' ; " UTOPIA Multi PHY enable
AtmRst_B NODE istype 'reg,buffer' ; " atm uni reset bit
AtmRstOut_B PIN 76istype 'com' ; " atm uni reset driven by register
" or by HRESET_B
USBEn_B PIN 5istype 'reg,buffer' ; " USB enable
USBDis_B PIN 86istype 'com' ; " USB disable
USBHiSpd_B PIN 26istype 'reg,buffer' ; " USB Hi Speed Select
USBLowSpd_B PIN 133istype 'com' ; " USB Low Speed Select
USBVccO
PIN 7istype 'reg,buffer' ; " USB Line Voltage Select
FEthEn1_B
FEthDis1_B
FEthEn2_B
FEthDis2_B
FEthRst1_B
FEthRstOut1_B
PIN 9istype 'reg,buffer' ; " fast ethernet trans. 1 enable
PIN 23istype 'com' ; " fast ethernet trans. 1 Disable
PIN 40istype 'reg,buffer' ; " fast ethernet trans. 2 enable
PIN 79istype 'com' ; " fast ethernet trans. 2 Disable
NODE istype 'reg,buffer' ; " fast ethernet trans. 1 reset bit
PIN 139istype 'com' ; " fast eth trans 1 reset driven by
" register or by HRESET_B
FEthRst2_B
NODE istype 'reg,buffer' ; " fast ethernet trans. 2 reset bit
PIN 110istype 'com' ; " fast eth trans 2 reset driven by
" register or by HRESET_B
FEthRstOut2_B
FEthMDSel1
FEthMDSel2
PIN 10istype 'com' ; " F. Eth. MDIO MDC Mux1
PIN 6istype 'com' ; " F. Eth. MDIO MDC Mux2
RS232En1_B
RS232Dis1_B
RS232En2_B
RS232Dis2_B
PIN 32istype 'reg,buffer' ; " RS232 port 1 enable
PIN 56istype 'com' ; " RS232 port 1 Disable
PIN 3istype 'reg,buffer' ; " RS232 port 2 enable
PIN 8istype 'com' ; " RS232 port 2 Disable
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PCI_Mode_B
PIN 19 ; " Local Bus PCI Select
Local_Bus_B PIN 98istype 'com' ; " Local Bus SDRAM Select
ModckH0 PIN 67 ; " MODCKH0
ModckH1 PIN 65 ; " MODCKH1
ModckH2 PIN 61 ; " MODCKH2
ModckH3 PIN 59 ; " MODCKH3
PCI_IRQ_B
PIN 100istype 'com,buffer' ; " PCI Interrupt to PQ2 (o.d.)
PCI_INTA_B
PCI_INTB_B
PCI_INTC_B
PCI_INTD_B
PIN 97 ; " PCI Interrupt from PCI card
PIN 126 ; " PCI Interrupt from PCI card
PIN 125 ; " PCI Interrupt from PCI card
PIN 120 ; " PCI Interrupt from PCI card
"******************************************************************************
"* Board Status Registers Chip-Selects
"******************************************************************************
Bcsr2Cs_B
Bcsr4Cs_B
PIN 89istype 'com' ;
PIN 81istype 'com' ;
"******************************************************************************
"* Flash/EEPROM Associated Pins.
"******************************************************************************
F_PD1
F_PD2
F_PD3
F_PD4
PIN 57 ;
PIN 55 ;
PIN 45 ;
PIN 43 ;
Cs0_B
PIN 54 ; " flash/eeprom chip-select input
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Cs4_B
PIN 94 ; " eeprom/flash chip-select input
PIN 137istype 'com' ; " EEPROM chip-select
EEpromCs_B
FlashCs1_B
FlashCs2_B
FlashCs3_B
FlashCs4_B
PIN 144istype 'com' ; " Flash bank1 chip-select
PIN 138istype 'com' ; " Flash bank2 chip-select
PIN 143istype 'com' ; " Flash bank3 chip-select
PIN 140istype 'com' ; " Flash bank4 chip-select
"******************************************************************************
"* PM5384 ATM UNI Associated Pins.
"******************************************************************************
AtmUniCsIn_B
PIN 119 ;
AtmUniCsOut_B
PIN 62istype 'com' ; " remove if short of pins
"******************************************************************************
"* Reset & Interrupt Logic Pins.
"******************************************************************************
PORIn_B
PIN 41 ;
"RstConf_B
PIN istype 'com'; Hard Reset master select.
Rst0
Rst1
PIN 33 ; " connected to N.C. of Reset P.B.
PIN 31 ; " connected to N.O. of Reset P.B.
HardReset_B
SoftReset_B
PIN 18istype 'com' ; " Actual hard reset output (O.D.)
PIN 17istype 'com' ; " Actual soft reset output (O.D.)
Abr0
PIN 30 ; " connected to N.C. of Abort P.B.
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Abr1
PIN 29 ; " connected to N.O. of Abort P.B.
NMIEn
NMI_B
NODE istype 'com' ; " enables T.S. NMI pin
PIN 20istype 'com' ; " Actual NMI pin (O,O.D.)
"******************************************************************************
"* Data Buffers Enables and Reset configuration support
"******************************************************************************
TEA_B
PIN 102 ; " Transfer Error Acknowledge.
DataBufEn_B
PIN 85istype 'com,invert' ; " data buffer enable
ToolCs1_B
ToolCs2_B
PIN 27 ; " comm tool cs line 1.
PIN 21 ; " comm tool cs line 2.
ToolDataBufEn_B
PIN 91istype 'com,invert' ; " tool data buffer enable
"******************************************************************************
"* Hard Reset Configuration Logic
"******************************************************************************
boot_device_B PIN 118 ; " selects EEPROM/FLASH_B as boot device
bcsrConfEn PIN 93 ; " selects Hard Reset Configuration Source
" as BCSR or EEPROM/FLASH.
"******************************************************************************
"* Auxiliary Pins.
"******************************************************************************
"******************************************************************************
"* ###
"* #
*
#
# ##### ###### ##### #
#
##
#
####
*
*
"* # ## #
"* # # # #
#
#
#
#
# ## # # # #
#
##### # # # # # # # #
####
*
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"* # # # #
"* # # ##
#
#
#
#
##### # # # ###### #
# # # ## # # #
#
*
*
#
#
"* ###
#
#
#
###### # # # # # # ###### ####
*
"******************************************************************************
"* System Hard Reset Configuration.
"******************************************************************************
DataOeNODE istype 'com' ; " data bus output enable on read.
DataPCIOeNODE istype 'com' ; " data bus output enable on PCI read.
"******************************************************************************
"* Control Register Enable Protection.
"******************************************************************************
"******************************************************************************
"* Reset & Interrupt Logic Pins.
"******************************************************************************
RstDeb1NODE istype 'keep,com' ; " reset push button debouncer
AbrDeb1NODE istype 'keep,com' ; " abort push button debouncer
HardResetEnNODE istype 'com' ; " enables T.S. hard reset pin
SoftResetEnNODE istype 'com' ; " enables T.S. soft reset pin
"******************************************************************************
"* data buffers enable.
"******************************************************************************
SyncHardReset_B NODE istype 'reg,buffer' ; " synchronized hard reset
DSyncHardReset_B NODE istype 'reg,buffer' ; " double synchronized hard reset
HoldOffCnt2,
HoldOffCnt1,
HoldOffCnt0 NODE istype 'reg,buffer' ; " data buf en hold-off counter
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HoldOffTc
NODE istype 'com' ; " terminal count for that counter
"******************************************************************************
"* Power On Reset
"******************************************************************************
S_PORIn_B
NODE istype 'reg,buffer' ; " synced pon reset.
"******************************************************************************
"* PCI Interrupt Register.
"******************************************************************************
Slot0IntANODE istype 'reg,invert' ; " PCI Slot 0 Interrupt A
Slot0IntBNODE istype 'reg,invert' ; " PCI Slot 0 Interrupt B
Slot0IntCNODE istype 'reg,invert' ; " PCI Slot 0 Interrupt C
Slot0IntDNODE istype 'reg,invert' ; " PCI Slot 0 Interrupt D
Slot1IntANODE istype 'reg,invert' ; " PCI Slot 1 Interrupt A
Slot1IntBNODE istype 'reg,invert' ; " PCI Slot 1 Interrupt B
Slot1IntCNODE istype 'reg,invert' ; " PCI Slot 1 Interrupt C
Slot1IntDNODE istype 'reg,invert' ; " PCI Slot 1 Interrupt D
Slot2IntANODE istype 'reg,invert' ; " PCI Slot 2 Interrupt A
Slot2IntBNODE istype 'reg,invert' ; " PCI Slot 2 Interrupt B
Slot2IntCNODE istype 'reg,invert' ; " PCI Slot 2 Interrupt C
Slot2IntDNODE istype 'reg,invert' ; " PCI Slot 2 Interrupt D
"******************************************************************************
"* PCI Interrupt Mask Register.
"******************************************************************************
Slot0IntAMaskNODE istype 'reg,buffer' ; " PCI Slot 0 Interrupt A Mask
Slot0IntBMaskNODE istype 'reg,buffer' ; " PCI Slot 0 Interrupt B Mask
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Slot0IntCMaskNODE istype 'reg,buffer' ; " PCI Slot 0 Interrupt C Mask
Slot0IntDMaskNODE istype 'reg,buffer' ; " PCI Slot 0 Interrupt D Mask
Slot1IntAMaskNODE istype 'reg,buffer' ; " PCI Slot 1 Interrupt A Mask
Slot1IntBMaskNODE istype 'reg,buffer' ; " PCI Slot 1 Interrupt B Mask
Slot1IntCMaskNODE istype 'reg,buffer' ; " PCI Slot 1 Interrupt C Mask
Slot1IntDMaskNODE istype 'reg,buffer' ; " PCI Slot 1 Interrupt D Mask
Slot2IntAMaskNODE istype 'reg,buffer' ; " PCI Slot 2 Interrupt A Mask
Slot2IntBMaskNODE istype 'reg,buffer' ; " PCI Slot 2 Interrupt B Mask
Slot2IntCMaskNODE istype 'reg,buffer' ; " PCI Slot 2 Interrupt C Mask
Slot2IntDMaskNODE istype 'reg,buffer' ; " PCI Slot 2 Interrupt D Mask
"******************************************************************************
"* PCI Interrupt Request to PQ2.
"******************************************************************************
PCI_InterruptNODE istype 'com' ; " generated Interrupt to PQ2
"******************************************************************************
"* Misceleneous.
"******************************************************************************
KeepPinsConnected NODE istype 'com' ;
"******************************************************************************
"* #####
*
"* # # #### # # #### ##### ##
#
# #####
*
"* #
"* #
"* #
#
#
#
# ## # #
#
# # ## #
# # # #
###### # # #
#
*
# # # # ####
#
#
#
*
# # # #
#
#
#
*
"* # # # # # ## #
#
#
#
#
# # ##
# #
#
*
"* ##### #### # # ####
#
#
#
*
112
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"*
*
"* ######
*
"* # # ###### #### #
## #####
*
"* # # #
#
# #
# # #
#
*
*
"* # # ##### #
#
#
# # # #####
*
"* # # #
"* # # #
#
#
#
###### #####
# # #
*
# #
#
"* ###### ###### #### ###### # # #
"*
#
*
*
"* ## #####
#
#### #
# ## #
# # # #
#
*
"* # #
#
#
#
#
#
#
*
"* #
#
*
"* ######
#
#
#
# # # #
# # ##
*
"* #
"* #
#
#
#
#
#
#
#
*
#### #
#
*
"******************************************************************************
H, L, X, Z = 1, 0, .X., .Z. ;
C, D, U = .C., .D., .U. ;
"******************************************************************************
"* SIMULATION = 1 ;
"******************************************************************************
"* Signal groups
"******************************************************************************
Add = [A27..A29] ;
Data = [D0..D7] ;
DataPCI = [D0..D11] ;
ContReg = [L2Inh_B,
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L2Flush_B,
L2Lock_B,
L2Clear_B,
SignaLamp0_B,
SignaLamp1_B,
AtmEn_B,
AtmRst_B,
Atm16_B,
AtmSinglePHY_B,
FEthEn1_B,
FEthRst1_B,
FEthEn2_B,
FEthRst2_B,
RS232En1_B,
RS232En2_B,
USBEn_B,
USBHiSpd_B,
USBVccO] ;
ReadBcsr0 = [0,
0,
L2Inh_B,
L2Flush_B,
L2Lock_B,
L2Clear_B,
SignaLamp0_B,
SignaLamp1_B] ;
ReadBcsr1 = [bcsrConfEn,
boot_device_B,
AtmEn_B,
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AtmRst_B.fb,
FEthEn1_B,
FEthRst1_B.fb,
RS232En1_B,
RS232En2_B] ;
ReadBcsr3 = [USBEn_B,
USBHiSpd_B,
USBVccO,
FEthEn2_B,
FEthRst2_B.fb,
Atm16_B,
AtmSinglePHY_B,
PCI_Mode_B];
DrivenContReg = [L2Inh_B,
L2Flush_B,
L2Lock_B,
L2Clear_B,
SignaLamp0_B,
SignaLamp1_B,
AtmEn_B,
Atm16_B,
AtmSinglePHY_B,
FEthEn1_B,
FEthEn2_B,
RS232En1_B,
RS232En2_B,
USBEn_B,
USBHiSpd_B,
USBVccO] ;
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ClockedContReg = [L2Inh_B,
L2Flush_B,
L2Lock_B,
L2Clear_B,
SignaLamp0_B,
SignaLamp1_B,
AtmEn_B,
AtmRst_B,
Atm16_B,
AtmSinglePHY_B,
FEthEn1_B,
FEthEn2_B,
FEthRst1_B,
FEthRst2_B,
RS232En1_B,
RS232En2_B,
USBEn_B,
USBHiSpd_B,
USBVccO] ;
IntReg = [Slot0IntA,
Slot0IntB,
Slot0IntC,
Slot0IntD,
Slot1IntA,
Slot1IntB,
Slot1IntC,
Slot1IntD,
Slot2IntA,
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Slot2IntB,
Slot2IntC,
Slot2IntD] ;
IntMaskReg = [Slot0IntAMask,
Slot0IntBMask,
Slot0IntCMask,
Slot0IntDMask,
Slot1IntAMask,
Slot1IntBMask,
Slot1IntCMask,
Slot1IntDMask,
Slot2IntAMask,
Slot2IntBMask,
Slot2IntCMask,
Slot2IntDMask] ;
ToolCs =
[ToolCs1_B,ToolCs2_B] ;
FlashCsOut = [FlashCs4_B,FlashCs3_B,FlashCs2_B,FlashCs1_B] ;
Reset = [HardReset_B,SoftReset_B] ;
ResetEn = [HardResetEn,SoftResetEn] ;
TransRst = [AtmRstOut_B,FEthRstOut1_B,FEthRstOut2_B] ;
Rst =
Abr =
[Rst1,Rst0] ;
[Abr1,Abr0] ;
Debounce = [RstDeb1,AbrDeb1] ;
SyncReset =
[SyncHardReset_B,DSyncHardReset_B] ;
RstCause = [PORIn_B,Rst1,Rst0,Abr1,Abr0] ;
HoldOffCnt = [HoldOffCnt2,HoldOffCnt1,HoldOffCnt0] ;
F_PD =
Cs =
[F_PD4, F_PD3, F_PD2, F_PD1] ;
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[Cs0_B,Cs4_B,BrdContRegCs_B,IntContCs_B,AtmUniCsIn_B,ToolCs1_B,ToolCs2_B] ;
BufEn =
[DataBufEn_B,ToolDataBufEn_B] ;
[A27,A28];
ConfAdd =
@ifndef L2CACHE {
CfgByte0 = [0,0,0,0,1,1,0,0];
CfgByte1 = [1,0,1,1,0,0,1,0];
CfgByte2 = [0,0,0,0,0,Local_Bus_B.pin,1,0];
CfgByte3 = [0,0,0,0,ModckH0,ModckH1,ModckH2,ModckH3];
}
@ifdef L2CACHE {
CfgByte0 = [0,0,0,1,1,1,0,0];
CfgByte1 = [1,0,1,1,0,0,1,0];
CfgByte2 = [0,0,0,0,0,Local_Bus_B.pin,1,0];
CfgByte3 = [0,0,0,0,ModckH0,ModckH1,ModckH2,ModckH3];
}
"******************************************************************************
"* Power On Reset definitions
"******************************************************************************
PON_RESET_ACTIVE = 0 ;
PON_RESET = (S_PORIn_B.fb == PON_RESET_ACTIVE) ;
"******************************************************************************
"* Register Access definitions
"******************************************************************************
BCSR0_ADD = 0 ;
BCSR1_ADD = 1 ;
BCSR2_ADD = 2 ;
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BCSR3_ADD = 3 ;
BCSR4_ADD = 4 ;
VGR_WRITE_BCSR_0 = (!BrdContRegCs_B & !DVal_B & R_B_W & !A27 & !A28 &
!A29) ;
VGR_WRITE_BCSR_1 = (!BrdContRegCs_B & !DVal_B & R_B_W & !A27 & !A28 & A29)
;
VGR_WRITE_BCSR_2 = (!BrdContRegCs_B & !DVal_B & R_B_W & !A27 & A28 & !A29)
;
VGR_WRITE_BCSR_3 = (!BrdContRegCs_B & !DVal_B & R_B_W & !A27 & A28 & A29)
;
VGR_WRITE_BCSR_4 = (!BrdContRegCs_B & !DVal_B & R_B_W & A27 & !A28 & !A29)
;
VGR_READ_BCSR_0 = (!BrdContRegCs_B & !R_B_W & !A27 & !A28 & !A29) ;
VGR_READ_BCSR_1 = (!BrdContRegCs_B & !R_B_W & !A27 & !A28 & A29) ;
VGR_READ_BCSR_2 = (!BrdContRegCs_B & !R_B_W & !A27 & A28 & !A29) ;
VGR_READ_BCSR_3 = (!BrdContRegCs_B & !R_B_W & !A27 & A28 & A29) ;
VGR_READ_BCSR_4 = (!BrdContRegCs_B & !R_B_W & A27 & !A28 & !A29) ;
"******************************************************************************
"******************************************************************************
"* BCSR 0 definitions.
"******************************************************************************
"******************************************************************************
L2CACHE_INHIBITED = 0 ;
L2CACHE_FLUSHED = 0 ;
L2CACHE_LOCKED = 0 ;
L2CACHE_CLEARED = 0 ;
SIGNAL_LAMP_ON = 0 ;
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"***********************************************
"******* Power On Defaults Assignments *********
"***********************************************
L2CACHE_INH_PON_DEFAULT = L2CACHE_INHIBITED ;
L2CACHE_FLUSH_PON_DEFAULT = !L2CACHE_FLUSHED ;
L2CACHE_LOCK_PON_DEFAULT = !L2CACHE_LOCKED ;
L2CACHE_CLEAR_PON_DEFAULT = !L2CACHE_CLEARED ;
SIGNAL_LAMP0_PON_DEFAULT = !SIGNAL_LAMP_ON ;
SIGNAL_LAMP1_PON_DEFAULT = !SIGNAL_LAMP_ON ;
"*******************************************
"******* Data Bits Assignments *************
"*******************************************
L2CACHE_INH_DATA_BIT = [D2] ;
L2CACHE_FLUSH_DATA_BIT = [D3] ;
L2CACHE_LOCK_DATA_BIT = [D4] ;
L2CACHE_CLEAR_DATA_BIT = [D5] ;
SIGNAL_LAMP0_DATA_BIT = [D6] ;
SIGNAL_LAMP1_DATA_BIT = [D7] ;
"******************************************************************************
"******************************************************************************
"* BCSR 1 definitions.
"******************************************************************************
"******************************************************************************
BCSR_BOOT = 0 ;" bcsrConfEn = 0 Hard Reset Conf Word from BCSR
MEMORY_BOOT = 1 ;" bcsrConfEn = 1 Hard Reset Conf from EEPROM/FLASH
FLASH_BOOT = 0 ;" boot_device_B = 0
EEPROM_BOOT = 1 ;" boot_device_B = 1
ATM_ENABLED = 0 ;
ATM_RESET_ACTIVE = 0 ;
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FETH1_ENABLED = 0 ;
FETH1_RESET_ACTIVE = 0 ;
RS232_1_ENABLE = 0 ;
RS232_2_ENABLE = 0 ;
"***********************************************
"******* Power On Defaults Assignments *********
"***********************************************
ATM_ENABLE_PON_DEFAULT = !ATM_ENABLED ;
ATM_RESET_PON_DEFAULT = !ATM_RESET_ACTIVE ;
FETH1_ENABLE_PON_DEFAULT = !FETH1_ENABLED ;
FETH1_RESET_PON_DEFAULT = !FETH1_RESET_ACTIVE ;
RS232_1_ENABLE_PON_DEFAULT = !RS232_1_ENABLE ;
RS232_2_ENABLE_PON_DEFAULT = !RS232_2_ENABLE ;
"*******************************************
"******* Data Bits Assignments *************
"*******************************************
CONF_WORD_DATA_BIT =
[D0] ;
BOOT_DEVICE_DATA_BIT = [D1] ;
ATM_ENABLE_DATA_BIT = [D2] ;
ATM_RESET_DATA_BIT =
[D3] ;
FETH1_ENABLE_DATA_BIT = [D4] ;
FETH1_RESET_DATA_BIT = [D5] ;
RS232_1_ENABLE_DATA_BIT = [D6] ;
RS232_2_ENABLE_DATA_BIT = [D7] ;
"******************************************************************************
"******************************************************************************
"* BCSR 3 definitions.
"******************************************************************************
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"******************************************************************************
USB_ENABLED = 0 ;
USB_SPEED_HIGH = 0 ;
USB_VCCO_ON = 1 ;
FETH2_ENABLED = 0 ;
FETH2_RESET_ACTIVE = 0 ;
ATM16_ENABLED = 0 ;
ATM_SINGLE_PHY_ENABLED = 0 ;
"***********************************************
"******* Power On Defaults Assignments *********
"***********************************************
USB_ENABLE_PON_DEFAULT = !USB_ENABLED ;
USB_SPEED_PON_DEFAULT = USB_SPEED_HIGH ;
USB_VCCO_PON_DEFAULT = !USB_VCCO_ON ;
FETH2_ENABLE_PON_DEFAULT = !FETH2_ENABLED ;
FETH2_RESET_PON_DEFAULT = !FETH2_RESET_ACTIVE ;
ATM16_ENABLE_PON_DEFAULT = !ATM16_ENABLED ;
ATM_SINGLE_PHY_ENABLE_PON_DEFAULT = ATM_SINGLE_PHY_ENABLED ;
"*******************************************
"******* Data Bits Assignments *************
"*******************************************
USB_ENABLE_DATA_BIT =
USB_SPEED_DATA_BIT =
USB_VCCO_DATA_BIT =
[D0] ;
[D1] ;
[D2] ;
[D3] ;
[D4] ;
[D5] ;
FETH2_ENABLE_DATA_BIT =
FETH2_RESET_DATA_BIT =
ATM16_ENABLE_DATA_BIT =
ATM_SINGLE_PHY_ENABLE_DATA_BIT = [D6] ;
LOCAL_BUS_DATA_BIT =
[D7] ;
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"******************************************************************************
"* PCI Interrupt Register Access definitions
"******************************************************************************
IntReg_ADD = 0 ;
IntMaskReg_ADD = 1 ;
"VGR_WRITE_IntReg = (!IntContCs_B & !DVal_B & R_B_W & !A27 & !A28 & !A29) ;
VGR_WRITE_IntMaskReg = (!IntContCs_B & !DVal_B & R_B_W & !A27 & !A28 & A29) ;
VGR_READ_IntReg = (!IntContCs_B & !R_B_W & !A27 & !A28 & !A29) ;
VGR_READ_IntMaskReg = (!IntContCs_B & !R_B_W & !A27 & !A28 & A29) ;
"******************************************************************************
"* Interrupt Request Definitions.
"******************************************************************************
"IrqOe = (Slot0IntA #
" Slot0IntB #
" Slot0IntC #
" Slot0IntD #
" Slot1IntA #
" Slot1IntB #
" Slot1IntC #
" Slot1IntD #
" Slot2IntA #
" Slot2IntB #
" Slot2IntC #
" Slot2IntD) ;
"******************************************************************************
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"******************************************************************************
"* PCI Interrupt Register definitions.
"******************************************************************************
"******************************************************************************
Slot0IntA_Active = 1 ; " PCI Slot 0 Interrupt A asserted
Slot0IntB_Active = 1 ; " PCI Slot 0 Interrupt B asserted
Slot0IntC_Active = 1 ; " PCI Slot 0 Interrupt C asserted
Slot0IntD_Active = 1 ; " PCI Slot 0 Interrupt D asserted
Slot1IntA_Active = 1 ; " PCI Slot 1 Interrupt A asserted
Slot1IntB_Active = 1 ; " PCI Slot 1 Interrupt B asserted
Slot1IntC_Active = 1 ; " PCI Slot 1 Interrupt C asserted
Slot1IntD_Active = 1 ; " PCI Slot 1 Interrupt D asserted
Slot2IntA_Active = 1 ; " PCI Slot 2 Interrupt A asserted
Slot2IntB_Active = 1 ; " PCI Slot 2 Interrupt B asserted
Slot2IntC_Active = 1 ; " PCI Slot 2 Interrupt C asserted
Slot2IntD_Active = 1 ; " PCI Slot 2 Interrupt D asserted
"***********************************************
"******* Power On Defaults Assignments *********
"***********************************************
Slot0IntA_PON_DEFAULT = !Slot0IntA_Active ;
Slot0IntB_PON_DEFAULT = !Slot0IntB_Active ;
Slot0IntC_PON_DEFAULT = !Slot0IntC_Active ;
Slot0IntD_PON_DEFAULT = !Slot0IntD_Active ;
Slot1IntA_PON_DEFAULT = !Slot1IntA_Active ;
Slot1IntB_PON_DEFAULT = !Slot1IntB_Active ;
Slot1IntC_PON_DEFAULT = !Slot1IntC_Active ;
Slot1IntD_PON_DEFAULT = !Slot1IntD_Active ;
Slot2IntA_PON_DEFAULT = !Slot2IntA_Active ;
Slot2IntB_PON_DEFAULT = !Slot2IntB_Active ;
Slot2IntC_PON_DEFAULT = !Slot2IntC_Active ;
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Slot2IntD_PON_DEFAULT = !Slot2IntD_Active ;
"*******************************************
"******* Data Bits Assignments *************
"*******************************************
Slot0IntA_DATA_BIT = [D0] ;
Slot0IntB_DATA_BIT = [D1] ;
Slot0IntC_DATA_BIT = [D2] ;
Slot0IntD_DATA_BIT = [D3] ;
Slot1IntA_DATA_BIT = [D4] ;
Slot1IntB_DATA_BIT = [D5] ;
Slot1IntC_DATA_BIT = [D6] ;
Slot1IntD_DATA_BIT = [D7] ;
Slot2IntA_DATA_BIT = [D8] ;
Slot2IntB_DATA_BIT = [D9] ;
Slot2IntC_DATA_BIT = [D10] ;
Slot2IntD_DATA_BIT = [D11] ;
"******************************************************************************
"******************************************************************************
"* PCI Interrupt Mask Register definitions.
"******************************************************************************
"******************************************************************************
Slot0IntAMask_Active = 1 ; " PCI Slot 0 Interrupt A Masked
Slot0IntBMask_Active = 1 ; " PCI Slot 0 Interrupt B Masked
Slot0IntCMask_Active = 1 ; " PCI Slot 0 Interrupt C Masked
Slot0IntDMask_Active = 1 ; " PCI Slot 0 Interrupt D Masked
Slot1IntAMask_Active = 1 ; " PCI Slot 1 Interrupt A Masked
Slot1IntBMask_Active = 1 ; " PCI Slot 1 Interrupt B Masked
Slot1IntCMask_Active = 1 ; " PCI Slot 1 Interrupt C Masked
Slot1IntDMask_Active = 1 ; " PCI Slot 1 Interrupt D Masked
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Slot2IntAMask_Active = 1 ; " PCI Slot 2 Interrupt A Masked
Slot2IntBMask_Active = 1 ; " PCI Slot 2 Interrupt B Masked
Slot2IntCMask_Active = 1 ; " PCI Slot 2 Interrupt C Masked
Slot2IntDMask_Active = 1 ; " PCI Slot 2 Interrupt D Masked
"***********************************************
"******* Power On Defaults Assignments *********
"***********************************************
Slot0IntAMask_PON_DEFAULT = Slot0IntAMask_Active ;
Slot0IntBMask_PON_DEFAULT = Slot0IntBMask_Active ;
Slot0IntCMask_PON_DEFAULT = Slot0IntCMask_Active ;
Slot0IntDMask_PON_DEFAULT = Slot0IntDMask_Active ;
Slot1IntAMask_PON_DEFAULT = Slot1IntAMask_Active ;
Slot1IntBMask_PON_DEFAULT = Slot1IntBMask_Active ;
Slot1IntCMask_PON_DEFAULT = Slot1IntCMask_Active ;
Slot1IntDMask_PON_DEFAULT = Slot1IntDMask_Active ;
Slot2IntAMask_PON_DEFAULT = Slot2IntAMask_Active ;
Slot2IntBMask_PON_DEFAULT = Slot2IntBMask_Active ;
Slot2IntCMask_PON_DEFAULT = Slot2IntCMask_Active ;
Slot2IntDMask_PON_DEFAULT = Slot2IntDMask_Active ;
"*******************************************
"******* Data Bits Assignments *************
"*******************************************
Slot0IntAMask_DATA_BIT = [D0];
Slot0IntBMask_DATA_BIT = [D1];
Slot0IntCMask_DATA_BIT = [D2];
Slot0IntDMask_DATA_BIT = [D3];
Slot1IntAMask_DATA_BIT = [D4];
Slot1IntBMask_DATA_BIT = [D5];
Slot1IntCMask_DATA_BIT = [D6];
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Slot1IntDMask_DATA_BIT = [D7];
Slot2IntAMask_DATA_BIT = [D8];
Slot2IntBMask_DATA_BIT = [D9];
Slot2IntCMask_DATA_BIT = [D10];
Slot2IntDMask_DATA_BIT = [D11];
"******************************************************************************
"* Flash Declarations.
"******************************************************************************
FLASH_ENABLE_ACTIVE = 0 ;
" the presence detect encoding for the below is fictional
" needs to be updated with real data.
CP29020 = (F_PD == 8) ; " 1 X 2 MByte bank
SM73228XU1 = (F_PD == 2) ; " 1 X 8 MByte bank
SM73248XU2 = (F_PD == 1) ; " 2 X 8 MByte banks
SM73288XU4 = (F_PD == 0) ; " 4 X 8 MByte banks
FLASH_BANK1 = ( CP29020 #
SM73228XU1 #
(SM73248XU2 & !A8) #
(SM73288XU4 & !A7 & !A8) ) ;
FLASH_BANK2 = ( (SM73248XU2 & A8) #
(SM73288XU4 & !A7 & A8) ) ;
FLASH_BANK3 = ( A7 & !A8 & SM73288XU4 ) ;
FLASH_BANK4 = ( A7 & A8 & SM73288XU4 ) ;
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"******************************************************************************
"* ATM UNI Declarations.
"******************************************************************************
"******************************************************************************
"* Reset Declarations.
"******************************************************************************
HARD_RESET_ACTIVE = 0 ;
SOFT_RESET_ACTIVE = 0 ;
HARD_RESET_ASSERTED = (SyncHardReset_B.fb == HARD_RESET_ACTIVE) ;
"******************************************************************************
"* data buffers enable.
"******************************************************************************
BUFFER_DISABLED = 1 ;
BUFFER_ENABLED = !BUFFER_DISABLED ;
BUFFER_HOLD_OFF = (HoldOffCnt.fb != 0) ; " the delay is required for read as well
" since a fast device (eg bcsr) may
" content with the flash/eeprom
END_OF_FLASH_EEPROM_READ = !DVal_B & (!Cs0_B # !Cs4_B) & !R_B_W &
DSyncHardReset_B.fb ;
" end of flash/eeprom read cycle.
" not during hard reset config
END_OF_PCI_INT_CONT_READ = !DVal_B & !IntContCs_B & !R_B_W ;
" end of PCI Interrupt Controller read cycle.
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END_OF_ATM_READ = !DVal_B & !AtmUniCsIn_B & !R_B_W ; " end of atm uni m/p i/f
read cycle
END_OF_OTHER_CYCLE = (!DVal_B & Cs0_B & Cs4_B & AtmUniCsIn_B &
IntContCs_B #
!DVal_B & !AtmUniCsIn_B & R_B_W #
!DVal_B & !ToolCs1_B & R_B_W #
!DVal_B & !ToolCs2_B & R_B_W #
!DVal_B & (!Cs0_B # !Cs4_B) & R_B_W #
!DVal_B & !IntContCs_B & R_B_W) ;
" another access or atm uni write or tool 1 write or tool 2 write or
" flash/eeprom write PCI int cont write
"******************************************************************************
"* Hard Reset Configuration Logic
"******************************************************************************
HRESET_CFG_IN_BCSR = (bcsrConfEn == 1); " HRESET Conf Word in BCSR
HRESET_BOOT_IN_FLASH = ((bcsrConfEn == 0) & (boot_device_B == 0));
" HRESET Conf Word and Boot Code in FLASH
BOOT_IN_FLASH = ((bcsrConfEn == 1) & (boot_device_B == 0));
" HRESET Conf Word in BCSR and Boot Code in FLASH
HRESET_BOOT_IN_EEPROM = ((bcsrConfEn == 0) & (boot_device_B == 1));
" HRESET Conf Word and Boot Code in EEPROM
BOOT_IN_EEPROM = ((bcsrConfEn == 1) & (boot_device_B == 1));
" HRESET Conf Word in BCSR and Boot Code in EEPROM
HARD_RESET_ASSERTION = ( (HardReset_B == 0) & (SyncHardReset_B.fb == 0) &
(DSyncHardReset_B.fb == 1) );
CS0_ASSERTED = (Cs0_B == 0);
CS4_ASSERTED = (Cs4_B == 0);
FIRST_CFG_BYTE_READ = (CS0_ASSERTED & !DSyncHardReset_B.fb & (ConfAdd
== 0) &
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HRESET_CFG_IN_BCSR & !R_B_W);
SCND_CFG_BYTE_READ = (CS0_ASSERTED & !DSyncHardReset_B.fb & (ConfAdd
== 1) &
HRESET_CFG_IN_BCSR & !R_B_W);
THIRD_CFG_BYTE_READ = (CS0_ASSERTED & !DSyncHardReset_B.fb & (ConfAdd
== 2) &
HRESET_CFG_IN_BCSR & !R_B_W);
FORTH_CFG_BYTE_READ = (CS0_ASSERTED & !DSyncHardReset_B.fb & (ConfAdd
== 3) &
HRESET_CFG_IN_BCSR & !R_B_W);
"******************************************************************************
"* Equations, state diagrams.
*
"******************************************************************************
"*
*
"* #######
*
"* #
#### #
#
## #####
#
#
#### # # ####
# ## # #
# # # # ####
# # # #
# # ## #
*
"* #
#
# # # # #
# # # #
#
#
*
"* #####
"* #
#
#
#
#
#
#
*
# # # # # ######
# # # # #
#
#
#
#
*
"* #
#
#
#
#
#
*
"* ####### ### # #### #
"*
#
#
#### # # ####
*
*
"******************************************************************************
"******************************************************************************
equations
ClockedContReg.clk = SYSCLK ;
ClockedContReg.ar = 0;
ClockedContReg.ap = 0;
DrivenContReg.oe = ^hffff ;
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"******************************************************************************
"******************************************************************************
"* BCSR 0
"******************************************************************************
"******************************************************************************
equations
"******************************************************************************
state_diagram L2Inh_B
state L2CACHE_INHIBITED:
if (VGR_WRITE_BCSR_0 &
(L2CACHE_INH_DATA_BIT.pin == !L2CACHE_INHIBITED) &
(!PON_RESET # (L2CACHE_INH_PON_DEFAULT != L2CACHE_INHIBITED)) #
(PON_RESET & (L2CACHE_INH_PON_DEFAULT == !L2CACHE_INHIBITED)) ) then
!L2CACHE_INHIBITED
else
L2CACHE_INHIBITED ;
state !L2CACHE_INHIBITED:
if (VGR_WRITE_BCSR_0 &
(L2CACHE_INH_DATA_BIT.pin == L2CACHE_INHIBITED) &
(!PON_RESET # (L2CACHE_INH_PON_DEFAULT != !L2CACHE_INHIBITED)) #
(PON_RESET & (L2CACHE_INH_PON_DEFAULT == L2CACHE_INHIBITED)) ) then
L2CACHE_INHIBITED
else
!L2CACHE_INHIBITED ;
"******************************************************************************
state_diagram L2Flush_B
state L2CACHE_FLUSHED:
if (VGR_WRITE_BCSR_0 &
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(L2CACHE_FLUSH_DATA_BIT.pin == !L2CACHE_FLUSHED) &
(!PON_RESET # (L2CACHE_FLUSH_PON_DEFAULT != L2CACHE_FLUSHED)) #
(PON_RESET & (L2CACHE_FLUSH_PON_DEFAULT == !L2CACHE_FLUSHED)) )
then
!L2CACHE_FLUSHED
else
L2CACHE_FLUSHED ;
state !L2CACHE_FLUSHED:
if (VGR_WRITE_BCSR_0 &
(L2CACHE_FLUSH_DATA_BIT.pin == L2CACHE_FLUSHED) &
(!PON_RESET # (L2CACHE_FLUSH_PON_DEFAULT != !L2CACHE_FLUSHED)) #
(PON_RESET & (L2CACHE_FLUSH_PON_DEFAULT == L2CACHE_FLUSHED)) )
then
L2CACHE_FLUSHED
else
!L2CACHE_FLUSHED ;
"******************************************************************************
state_diagram L2Lock_B
state L2CACHE_LOCKED:
if (VGR_WRITE_BCSR_0 &
(L2CACHE_LOCK_DATA_BIT.pin == !L2CACHE_LOCKED) &
(!PON_RESET # (L2CACHE_LOCK_PON_DEFAULT != L2CACHE_LOCKED)) #
(PON_RESET & (L2CACHE_LOCK_PON_DEFAULT == !L2CACHE_LOCKED)) ) then
!L2CACHE_LOCKED
else
L2CACHE_LOCKED ;
state !L2CACHE_LOCKED:
if (VGR_WRITE_BCSR_0 &
(L2CACHE_LOCK_DATA_BIT.pin == L2CACHE_LOCKED) &
(!PON_RESET # (L2CACHE_LOCK_PON_DEFAULT != !L2CACHE_LOCKED)) #
(PON_RESET & (L2CACHE_LOCK_PON_DEFAULT == L2CACHE_LOCKED)) ) then
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L2CACHE_LOCKED
else
!L2CACHE_LOCKED ;
"******************************************************************************
state_diagram L2Clear_B
state L2CACHE_CLEARED:
if (VGR_WRITE_BCSR_0 &
(L2CACHE_CLEAR_DATA_BIT.pin == !L2CACHE_CLEARED) &
(!PON_RESET # (L2CACHE_CLEAR_PON_DEFAULT != L2CACHE_CLEARED)) #
(PON_RESET & (L2CACHE_CLEAR_PON_DEFAULT == !L2CACHE_CLEARED)) )
then
!L2CACHE_CLEARED
else
L2CACHE_CLEARED ;
state !L2CACHE_CLEARED:
if (VGR_WRITE_BCSR_0 &
(L2CACHE_CLEAR_DATA_BIT.pin == L2CACHE_CLEARED) &
(!PON_RESET # (L2CACHE_CLEAR_PON_DEFAULT != !L2CACHE_CLEARED)) #
(PON_RESET & (L2CACHE_CLEAR_PON_DEFAULT == L2CACHE_CLEARED)) )
then
L2CACHE_CLEARED
else
!L2CACHE_CLEARED ;
"******************************************************************************
state_diagram SignaLamp0_B
state SIGNAL_LAMP_ON:
if (VGR_WRITE_BCSR_0 &
(SIGNAL_LAMP0_DATA_BIT.pin == !SIGNAL_LAMP_ON) &
(!PON_RESET # (SIGNAL_LAMP0_PON_DEFAULT != SIGNAL_LAMP_ON)) #
(PON_RESET & (SIGNAL_LAMP0_PON_DEFAULT == !SIGNAL_LAMP_ON)) ) then
!SIGNAL_LAMP_ON
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else
SIGNAL_LAMP_ON ;
state !SIGNAL_LAMP_ON:
if (VGR_WRITE_BCSR_0 &
(SIGNAL_LAMP0_DATA_BIT.pin == SIGNAL_LAMP_ON) &
(!PON_RESET # (SIGNAL_LAMP0_PON_DEFAULT != !SIGNAL_LAMP_ON)) #
(PON_RESET & (SIGNAL_LAMP0_PON_DEFAULT == SIGNAL_LAMP_ON)) ) then
SIGNAL_LAMP_ON
else
!SIGNAL_LAMP_ON ;
"******************************************************************************
state_diagram SignaLamp1_B
state SIGNAL_LAMP_ON:
if (VGR_WRITE_BCSR_0 &
(SIGNAL_LAMP1_DATA_BIT.pin == !SIGNAL_LAMP_ON) &
(!PON_RESET # (SIGNAL_LAMP1_PON_DEFAULT != SIGNAL_LAMP_ON)) #
(PON_RESET & (SIGNAL_LAMP1_PON_DEFAULT == !SIGNAL_LAMP_ON)) ) then
!SIGNAL_LAMP_ON
else
SIGNAL_LAMP_ON ;
state !SIGNAL_LAMP_ON:
if (VGR_WRITE_BCSR_0 &
(SIGNAL_LAMP1_DATA_BIT.pin == SIGNAL_LAMP_ON) &
(!PON_RESET # (SIGNAL_LAMP1_PON_DEFAULT != !SIGNAL_LAMP_ON)) #
(PON_RESET & (SIGNAL_LAMP1_PON_DEFAULT == SIGNAL_LAMP_ON)) ) then
SIGNAL_LAMP_ON
else
!SIGNAL_LAMP_ON ;
"******************************************************************************
"******************************************************************************
"* BCSR1 State Machines
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"******************************************************************************
"******************************************************************************
state_diagram AtmEn_B
state ATM_ENABLED:
if (VGR_WRITE_BCSR_1 &
(ATM_ENABLE_DATA_BIT.pin == !ATM_ENABLED) &
(!PON_RESET # (ATM_ENABLE_PON_DEFAULT != ATM_ENABLED)) #
(PON_RESET & (ATM_ENABLE_PON_DEFAULT == !ATM_ENABLED)) ) then
!ATM_ENABLED
else
ATM_ENABLED ;
state !ATM_ENABLED:
if (VGR_WRITE_BCSR_1 &
(ATM_ENABLE_DATA_BIT.pin == ATM_ENABLED) &
(!PON_RESET # (ATM_ENABLE_PON_DEFAULT != !ATM_ENABLED)) #
(PON_RESET & (ATM_ENABLE_PON_DEFAULT == ATM_ENABLED)) ) then
ATM_ENABLED
else
!ATM_ENABLED ;
"******************************************************************************
state_diagram AtmRst_B
state ATM_RESET_ACTIVE:
if (VGR_WRITE_BCSR_1 &
(ATM_RESET_DATA_BIT.pin == !ATM_RESET_ACTIVE) &
(!PON_RESET # (ATM_RESET_PON_DEFAULT != ATM_RESET_ACTIVE)) #
(PON_RESET & (ATM_RESET_PON_DEFAULT == !ATM_RESET_ACTIVE)) ) then
!ATM_RESET_ACTIVE
else
ATM_RESET_ACTIVE ;
state !ATM_RESET_ACTIVE:
if (VGR_WRITE_BCSR_1 &
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(ATM_RESET_DATA_BIT.pin == ATM_RESET_ACTIVE) &
(!PON_RESET # (ATM_RESET_PON_DEFAULT != !ATM_RESET_ACTIVE)) #
(PON_RESET & (ATM_RESET_PON_DEFAULT == ATM_RESET_ACTIVE)) ) then
ATM_RESET_ACTIVE
else
!ATM_RESET_ACTIVE ;
"******************************************************************************
state_diagram FEthEn1_B
state FETH1_ENABLED:
if (VGR_WRITE_BCSR_1 &
(FETH1_ENABLE_DATA_BIT.pin == !FETH1_ENABLED) &
(!PON_RESET # (FETH1_ENABLE_PON_DEFAULT != FETH1_ENABLED)) #
(PON_RESET & (FETH1_ENABLE_PON_DEFAULT == !FETH1_ENABLED)) ) then
!FETH1_ENABLED
else
FETH1_ENABLED ;
state !FETH1_ENABLED:
if (VGR_WRITE_BCSR_1 &
(FETH1_ENABLE_DATA_BIT.pin == FETH1_ENABLED) &
(!PON_RESET # (FETH1_ENABLE_PON_DEFAULT != !FETH1_ENABLED)) #
(PON_RESET & (FETH1_ENABLE_PON_DEFAULT == FETH1_ENABLED)) ) then
FETH1_ENABLED
else
!FETH1_ENABLED ;
"******************************************************************************
state_diagram FEthRst1_B
state FETH1_RESET_ACTIVE:
if (VGR_WRITE_BCSR_1 &
(FETH1_RESET_DATA_BIT.pin == !FETH1_RESET_ACTIVE) &
(!PON_RESET # (FETH1_RESET_PON_DEFAULT != FETH1_RESET_ACTIVE)) #
(PON_RESET & (FETH1_RESET_PON_DEFAULT == !FETH1_RESET_ACTIVE)) )
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then
!FETH1_RESET_ACTIVE
else
FETH1_RESET_ACTIVE ;
state !FETH1_RESET_ACTIVE:
if (VGR_WRITE_BCSR_1 &
(FETH1_RESET_DATA_BIT.pin == FETH1_RESET_ACTIVE) &
(!PON_RESET # (FETH1_RESET_PON_DEFAULT != !FETH1_RESET_ACTIVE)) #
(PON_RESET & (FETH1_RESET_PON_DEFAULT == FETH1_RESET_ACTIVE)) )
then
FETH1_RESET_ACTIVE
else
!FETH1_RESET_ACTIVE ;
"******************************************************************************
state_diagram RS232En1_B
state RS232_1_ENABLE:
if (VGR_WRITE_BCSR_1 &
(RS232_1_ENABLE_DATA_BIT.pin == !RS232_1_ENABLE) &
(!PON_RESET # (RS232_1_ENABLE_PON_DEFAULT != RS232_1_ENABLE)) #
(PON_RESET & (RS232_1_ENABLE_PON_DEFAULT == !RS232_1_ENABLE)) ) then
!RS232_1_ENABLE
else
RS232_1_ENABLE ;
state !RS232_1_ENABLE:
if (VGR_WRITE_BCSR_1 &
(RS232_1_ENABLE_DATA_BIT.pin == RS232_1_ENABLE) &
(!PON_RESET # (RS232_1_ENABLE_PON_DEFAULT != !RS232_1_ENABLE)) #
(PON_RESET & (RS232_1_ENABLE_PON_DEFAULT == RS232_1_ENABLE)) ) then
RS232_1_ENABLE
else
!RS232_1_ENABLE ;
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"******************************************************************************
state_diagram RS232En2_B
state RS232_2_ENABLE:
if (VGR_WRITE_BCSR_1 &
(RS232_2_ENABLE_DATA_BIT.pin == !RS232_2_ENABLE) &
(!PON_RESET # (RS232_2_ENABLE_PON_DEFAULT != RS232_2_ENABLE)) #
(PON_RESET & (RS232_2_ENABLE_PON_DEFAULT == !RS232_2_ENABLE)) ) then
!RS232_2_ENABLE
else
RS232_2_ENABLE ;
state !RS232_2_ENABLE:
if (VGR_WRITE_BCSR_1 & (Atm16_B & AtmMultiPHY_B) &
(RS232_2_ENABLE_DATA_BIT.pin == RS232_2_ENABLE) &
(!PON_RESET # (RS232_2_ENABLE_PON_DEFAULT != !RS232_2_ENABLE)) #
(PON_RESET & (RS232_2_ENABLE_PON_DEFAULT == RS232_2_ENABLE)) ) then
RS232_2_ENABLE
else
!RS232_2_ENABLE ;
"******************************************************************************
"******************************************************************************
"* BCSR3 State Machines
"******************************************************************************
"******************************************************************************
state_diagram USBEn_B
state USB_ENABLED:
if (VGR_WRITE_BCSR_3 &
(USB_ENABLE_DATA_BIT.pin == !USB_ENABLED) &
(!PON_RESET # (USB_ENABLE_PON_DEFAULT != USB_ENABLED)) #
(PON_RESET & (USB_ENABLE_PON_DEFAULT == !USB_ENABLED)) ) then
!USB_ENABLED
else
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USB_ENABLED ;
state !USB_ENABLED:
if (VGR_WRITE_BCSR_3 & Atm16_B &
(USB_ENABLE_DATA_BIT.pin == USB_ENABLED) &
(!PON_RESET # (USB_ENABLE_PON_DEFAULT != !USB_ENABLED)) #
(PON_RESET & (USB_ENABLE_PON_DEFAULT == USB_ENABLED)) ) then
USB_ENABLED
else
!USB_ENABLED ;
"******************************************************************************
state_diagram USBHiSpd_B
state USB_SPEED_HIGH:
if (VGR_WRITE_BCSR_3 &
(USB_SPEED_DATA_BIT.pin == !USB_SPEED_HIGH) &
(!PON_RESET # (USB_SPEED_PON_DEFAULT != USB_SPEED_HIGH)) #
(PON_RESET & (USB_SPEED_PON_DEFAULT == !USB_SPEED_HIGH)) ) then
!USB_SPEED_HIGH
else
USB_SPEED_HIGH ;
state !USB_SPEED_HIGH:
if (VGR_WRITE_BCSR_3 &
(USB_SPEED_DATA_BIT.pin == USB_SPEED_HIGH) &
(!PON_RESET # (USB_SPEED_PON_DEFAULT != !USB_SPEED_HIGH)) #
(PON_RESET & (USB_SPEED_PON_DEFAULT == USB_SPEED_HIGH)) ) then
USB_SPEED_HIGH
else
!USB_SPEED_HIGH ;
"******************************************************************************
state_diagram USBVccO
state USB_VCCO_ON:
if (VGR_WRITE_BCSR_3 &
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(USB_VCCO_DATA_BIT.pin == !USB_VCCO_ON) &
(!PON_RESET # (USB_VCCO_PON_DEFAULT != USB_VCCO_ON)) #
(PON_RESET & (USB_VCCO_PON_DEFAULT == !USB_VCCO_ON)) ) then
!USB_VCCO_ON
else
USB_VCCO_ON ;
state !USB_VCCO_ON:
if (VGR_WRITE_BCSR_3 &
(USB_VCCO_DATA_BIT.pin == USB_VCCO_ON) &
(!PON_RESET # (USB_VCCO_PON_DEFAULT != !USB_VCCO_ON)) #
(PON_RESET & (USB_VCCO_PON_DEFAULT == USB_VCCO_ON)) ) then
USB_VCCO_ON
else
!USB_VCCO_ON ;
"******************************************************************************
state_diagram FEthEn2_B
state FETH2_ENABLED:
if (VGR_WRITE_BCSR_3 &
(FETH2_ENABLE_DATA_BIT.pin == !FETH2_ENABLED) &
(!PON_RESET # (FETH2_ENABLE_PON_DEFAULT != FETH2_ENABLED)) #
(PON_RESET & (FETH2_ENABLE_PON_DEFAULT == !FETH2_ENABLED)) ) then
!FETH2_ENABLED
else
FETH2_ENABLED ;
state !FETH2_ENABLED:
if (VGR_WRITE_BCSR_3 &
(FETH2_ENABLE_DATA_BIT.pin == FETH2_ENABLED) &
(!PON_RESET # (FETH2_ENABLE_PON_DEFAULT != !FETH2_ENABLED)) #
(PON_RESET & (FETH2_ENABLE_PON_DEFAULT == FETH2_ENABLED)) ) then
FETH2_ENABLED
else
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!FETH2_ENABLED ;
"******************************************************************************
state_diagram FEthRst2_B
state FETH2_RESET_ACTIVE:
if (VGR_WRITE_BCSR_3 &
(FETH2_RESET_DATA_BIT.pin == !FETH2_RESET_ACTIVE) &
(!PON_RESET # (FETH2_RESET_PON_DEFAULT != FETH2_RESET_ACTIVE)) #
(PON_RESET & (FETH2_RESET_PON_DEFAULT == !FETH2_RESET_ACTIVE)) )
then
!FETH2_RESET_ACTIVE
else
FETH2_RESET_ACTIVE ;
state !FETH2_RESET_ACTIVE:
if (VGR_WRITE_BCSR_3 &
(FETH2_RESET_DATA_BIT.pin == FETH2_RESET_ACTIVE) &
(!PON_RESET # (FETH2_RESET_PON_DEFAULT != !FETH2_RESET_ACTIVE)) #
(PON_RESET & (FETH2_RESET_PON_DEFAULT == FETH2_RESET_ACTIVE)) )
then
FETH2_RESET_ACTIVE
else
!FETH2_RESET_ACTIVE ;
"******************************************************************************
state_diagram Atm16_B
state ATM16_ENABLED:
if (VGR_WRITE_BCSR_3 &
(ATM16_ENABLE_DATA_BIT.pin == !ATM16_ENABLED) &
(!PON_RESET # (ATM16_ENABLE_PON_DEFAULT != ATM16_ENABLED)) #
(PON_RESET & (ATM16_ENABLE_PON_DEFAULT == !ATM16_ENABLED)) ) then
!ATM16_ENABLED
else
ATM16_ENABLED ;
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state !ATM16_ENABLED:
if (VGR_WRITE_BCSR_3 & (USBEn_B & RS232En2_B) &
(ATM16_ENABLE_DATA_BIT.pin == ATM16_ENABLED) &
(!PON_RESET # (ATM16_ENABLE_PON_DEFAULT != !ATM16_ENABLED)) #
(PON_RESET & (ATM16_ENABLE_PON_DEFAULT == ATM16_ENABLED)) ) then
ATM16_ENABLED
else
!ATM16_ENABLED ;
"******************************************************************************
state_diagram AtmSinglePHY_B
state ATM_SINGLE_PHY_ENABLED:
if (VGR_WRITE_BCSR_3 & RS232En2_B &
(ATM_SINGLE_PHY_ENABLE_DATA_BIT.pin == !ATM_SINGLE_PHY_ENABLED) &
(!PON_RESET
# (ATM_SINGLE_PHY_ENABLE_PON_DEFAULT != ATM_SINGLE_PHY_ENABLED))
#
(PON_RESET
& (ATM_SINGLE_PHY_ENABLE_PON_DEFAULT ==
!ATM_SINGLE_PHY_ENABLED)) ) then
!ATM_SINGLE_PHY_ENABLED
else
ATM_SINGLE_PHY_ENABLED ;
state !ATM_SINGLE_PHY_ENABLED:
if (VGR_WRITE_BCSR_3 &
(ATM_SINGLE_PHY_ENABLE_DATA_BIT.pin == ATM_SINGLE_PHY_ENABLED) &
(!PON_RESET
# (ATM_SINGLE_PHY_ENABLE_PON_DEFAULT !=
!ATM_SINGLE_PHY_ENABLED)) #
(PON_RESET
& (ATM_SINGLE_PHY_ENABLE_PON_DEFAULT ==
ATM_SINGLE_PHY_ENABLED)) ) then
ATM_SINGLE_PHY_ENABLED
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else
!ATM_SINGLE_PHY_ENABLED ;
"******************************************************************************
equations
AtmDis_B = !AtmEn_B ;
Atm8_B = !Atm16_B ;
AtmMultiPHY_B = !AtmSinglePHY_B ;
USBDis_B = !USBEn_B ;
USBLowSpd_B = !USBHiSpd_B ;
FEthDis1_B = !FEthEn1_B ;
FEthDis2_B = !FEthEn2_B ;
FEthMDSel1 = (!FEthEn1_B # !FEthEn2_B) & (!Atm16_B # !USBEn_B) ;
FEthMDSel2 = !FEthEn1_B # !FEthEn2_B # !Atm16_B # !USBEn_B ;
RS232Dis1_B = !RS232En1_B ;
RS232Dis2_B = !RS232En2_B ;
Local_Bus_B = !PCI_Mode_B ;
"******************************************************************************
"******************************************************************************
"******************************************************************************
"* PCI Interrupt Register
"******************************************************************************
"******************************************************************************
equations
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IntReg.clk = SYSCLK ;
IntReg.ar = 0 ;
IntReg.ap = 0 ;
"******************************************************************************
state_diagram Slot0IntA
state Slot0IntA_Active:
if ( ((HardReset_B == 0) & (Slot0IntA_PON_DEFAULT == !Slot0IntA_Active)) #
(!(HardReset_B == 0) & ((PCI_INTA_B & !Slot0IntAMask.fb) #
Slot0IntAMask.fb)) )
then
!Slot0IntA_Active
else
Slot0IntA_Active ;
state !Slot0IntA_Active:
if ( ((HardReset_B == 0) & (Slot0IntA_PON_DEFAULT == Slot0IntA_Active)) #
(!(HardReset_B == 0) & !PCI_INTA_B & !Slot0IntAMask.fb) )
then
Slot0IntA_Active
else
!Slot0IntA_Active ;
"******************************************************************************
state_diagram Slot0IntB
state Slot0IntB_Active:
if ( ((HardReset_B == 0) & (Slot0IntB_PON_DEFAULT == !Slot0IntB_Active)) #
(!(HardReset_B == 0) & ((PCI_INTB_B & !Slot0IntBMask.fb) #
Slot0IntBMask.fb)) )
then
!Slot0IntB_Active
else
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Slot0IntB_Active ;
state !Slot0IntB_Active:
if ( ((HardReset_B == 0) & (Slot0IntB_PON_DEFAULT == Slot0IntB_Active)) #
(!(HardReset_B == 0) & !PCI_INTB_B & !Slot0IntBMask.fb) )
then
Slot0IntB_Active
else
!Slot0IntB_Active ;
"******************************************************************************
state_diagram Slot0IntC
state Slot0IntC_Active:
if ( ((HardReset_B == 0) & (Slot0IntC_PON_DEFAULT == !Slot0IntC_Active)) #
(!(HardReset_B == 0) & ((PCI_INTC_B & !Slot0IntCMask.fb) #
Slot0IntCMask.fb)) )
then
!Slot0IntC_Active
else
Slot0IntC_Active ;
state !Slot0IntC_Active:
if ( ((HardReset_B == 0) & (Slot0IntC_PON_DEFAULT == Slot0IntC_Active)) #
(!(HardReset_B == 0) & !PCI_INTC_B & !Slot0IntCMask.fb) )
then
Slot0IntC_Active
else
!Slot0IntC_Active ;
"******************************************************************************
state_diagram Slot0IntD
state Slot0IntD_Active:
if ( ((HardReset_B == 0) & (Slot0IntD_PON_DEFAULT == !Slot0IntD_Active)) #
(!(HardReset_B == 0) & ((PCI_INTD_B & !Slot0IntDMask.fb) #
Slot0IntDMask.fb)) )
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then
!Slot0IntD_Active
else
Slot0IntD_Active ;
state !Slot0IntD_Active:
if ( ((HardReset_B == 0) & (Slot0IntD_PON_DEFAULT == Slot0IntD_Active)) #
(!(HardReset_B == 0) & !PCI_INTD_B & !Slot0IntDMask.fb) )
then
Slot0IntD_Active
else
!Slot0IntD_Active ;
"******************************************************************************
state_diagram Slot1IntA
state Slot1IntA_Active:
if ( ((HardReset_B == 0) & (Slot1IntA_PON_DEFAULT == !Slot1IntA_Active)) #
(!(HardReset_B == 0) & ((PCI_INTD_B & !Slot1IntAMask.fb) #
Slot1IntAMask.fb)) )
then
!Slot1IntA_Active
else
Slot1IntA_Active ;
state !Slot1IntA_Active:
if ( ((HardReset_B == 0) & (Slot1IntA_PON_DEFAULT == Slot1IntA_Active)) #
(!(HardReset_B == 0) & !PCI_INTD_B & !Slot1IntAMask.fb) )
then
Slot1IntA_Active
else
!Slot1IntA_Active ;
"******************************************************************************
state_diagram Slot1IntB
state Slot1IntB_Active:
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if ( ((HardReset_B == 0) & (Slot1IntB_PON_DEFAULT == !Slot1IntB_Active)) #
(!(HardReset_B == 0) & ((PCI_INTA_B & !Slot1IntBMask.fb) #
Slot1IntBMask.fb)) )
then
!Slot1IntB_Active
else
Slot1IntB_Active ;
state !Slot1IntB_Active:
if ( ((HardReset_B == 0) & (Slot1IntB_PON_DEFAULT == Slot1IntB_Active)) #
(!(HardReset_B == 0) & !PCI_INTA_B & !Slot1IntBMask.fb) )
then
Slot1IntB_Active
else
!Slot1IntB_Active ;
"******************************************************************************
state_diagram Slot1IntC
state Slot1IntC_Active:
if ( ((HardReset_B == 0) & (Slot1IntC_PON_DEFAULT == !Slot1IntC_Active)) #
(!(HardReset_B == 0) & ((PCI_INTB_B & !Slot1IntCMask.fb) #
Slot1IntCMask.fb)) )
then
!Slot1IntC_Active
else
Slot1IntC_Active ;
state !Slot1IntC_Active:
if ( ((HardReset_B == 0) & (Slot1IntC_PON_DEFAULT == Slot1IntC_Active)) #
(!(HardReset_B == 0) & !PCI_INTB_B & !Slot1IntCMask.fb) )
then
Slot1IntC_Active
else
!Slot1IntC_Active ;
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"******************************************************************************
state_diagram Slot1IntD
state Slot1IntD_Active:
if ( ((HardReset_B == 0) & (Slot1IntD_PON_DEFAULT == !Slot1IntD_Active)) #
(!(HardReset_B == 0) & ((PCI_INTC_B & !Slot1IntDMask.fb) #
Slot1IntDMask.fb)) )
then
!Slot1IntD_Active
else
Slot1IntD_Active ;
state !Slot1IntD_Active:
if ( ((HardReset_B == 0) & (Slot1IntD_PON_DEFAULT == Slot1IntD_Active)) #
(!(HardReset_B == 0) & !PCI_INTC_B & !Slot1IntDMask.fb) )
then
Slot1IntD_Active
else
!Slot1IntD_Active ;
"******************************************************************************
state_diagram Slot2IntA
state Slot2IntA_Active:
if ( ((HardReset_B == 0) & (Slot2IntA_PON_DEFAULT == !Slot2IntA_Active)) #
(!(HardReset_B == 0) & ((PCI_INTC_B & !Slot2IntAMask.fb) #
Slot2IntAMask.fb)) )
then
!Slot2IntA_Active
else
Slot2IntA_Active ;
state !Slot2IntA_Active:
if ( ((HardReset_B == 0) & (Slot2IntA_PON_DEFAULT == Slot2IntA_Active)) #
(!(HardReset_B == 0) & !PCI_INTC_B & !Slot2IntAMask.fb) )
then
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Slot2IntA_Active
else
!Slot2IntA_Active ;
"******************************************************************************
state_diagram Slot2IntB
state Slot2IntB_Active:
if ( ((HardReset_B == 0) & (Slot2IntB_PON_DEFAULT == !Slot2IntB_Active)) #
(!(HardReset_B == 0) & ((PCI_INTD_B & !Slot2IntBMask.fb) #
Slot2IntBMask.fb)) )
then
!Slot2IntB_Active
else
Slot2IntB_Active ;
state !Slot2IntB_Active:
if ( ((HardReset_B == 0) & (Slot2IntB_PON_DEFAULT == Slot2IntB_Active)) #
(!(HardReset_B == 0) & !PCI_INTD_B & !Slot2IntBMask.fb) )
then
Slot2IntB_Active
else
!Slot2IntB_Active ;
"******************************************************************************
state_diagram Slot2IntC
state Slot2IntC_Active:
if ( ((HardReset_B == 0) & (Slot2IntC_PON_DEFAULT == !Slot2IntC_Active)) #
(!(HardReset_B == 0) & ((PCI_INTA_B & !Slot2IntCMask.fb) #
Slot2IntCMask.fb)) )
then
!Slot2IntC_Active
else
Slot2IntC_Active ;
state !Slot2IntC_Active:
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if ( ((HardReset_B == 0) & (Slot2IntC_PON_DEFAULT == Slot2IntC_Active)) #
(!(HardReset_B == 0) & !PCI_INTA_B & !Slot2IntCMask.fb) )
then
Slot2IntC_Active
else
!Slot2IntC_Active ;
"******************************************************************************
state_diagram Slot2IntD
state Slot2IntD_Active:
if ( ((HardReset_B == 0) & (Slot2IntD_PON_DEFAULT == !Slot2IntD_Active)) #
(!(HardReset_B == 0) & ((PCI_INTB_B & !Slot2IntDMask.fb) #
Slot2IntDMask.fb)) )
then
!Slot2IntD_Active
else
Slot2IntD_Active ;
state !Slot2IntD_Active:
if ( ((HardReset_B == 0) & (Slot2IntD_PON_DEFAULT == Slot2IntD_Active)) #
(!(HardReset_B == 0) & !PCI_INTB_B & !Slot2IntDMask.fb) )
then
Slot2IntD_Active
else
!Slot2IntD_Active ;
"******************************************************************************
"******************************************************************************
"* PCI Interrupt Mask Register
"******************************************************************************
"******************************************************************************
equations
IntMaskReg.clk = SYSCLK ;
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IntMaskReg.ar = 0 ;
IntMaskReg.ap = 0 ;
"******************************************************************************
state_diagram Slot0IntAMask
state Slot0IntAMask_Active:
if (VGR_WRITE_IntMaskReg &
(Slot0IntAMask_DATA_BIT.pin == !Slot0IntAMask_Active) &
(!(HardReset_B == 0) # (Slot0IntAMask_PON_DEFAULT == !Slot0IntAMask_Active))
#
((HardReset_B == 0) & (Slot0IntAMask_PON_DEFAULT == !Slot0IntAMask_Active)) )
then
!Slot0IntAMask_Active
else
Slot0IntAMask_Active ;
state !Slot0IntAMask_Active:
if (VGR_WRITE_IntMaskReg &
(Slot0IntAMask_DATA_BIT.pin == Slot0IntAMask_Active) &
(!(HardReset_B == 0) # (Slot0IntAMask_PON_DEFAULT == Slot0IntAMask_Active))
#
((HardReset_B == 0) & (Slot0IntAMask_PON_DEFAULT == Slot0IntAMask_Active)) )
then
Slot0IntAMask_Active
else
!Slot0IntAMask_Active ;
"******************************************************************************
state_diagram Slot0IntBMask
state Slot0IntBMask_Active:
if (VGR_WRITE_IntMaskReg &
(Slot0IntBMask_DATA_BIT.pin == !Slot0IntBMask_Active) &
(!(HardReset_B == 0) # (Slot0IntBMask_PON_DEFAULT == !Slot0IntBMask_Active))
#
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((HardReset_B == 0) & (Slot0IntBMask_PON_DEFAULT == !Slot0IntBMask_Active)) )
then
!Slot0IntBMask_Active
else
Slot0IntBMask_Active ;
state !Slot0IntBMask_Active:
if (VGR_WRITE_IntMaskReg &
(Slot0IntBMask_DATA_BIT.pin == Slot0IntBMask_Active) &
(!(HardReset_B == 0) # (Slot0IntBMask_PON_DEFAULT == Slot0IntBMask_Active))
#
((HardReset_B == 0) & (Slot0IntBMask_PON_DEFAULT == Slot0IntBMask_Active)) )
then
Slot0IntBMask_Active
else
!Slot0IntBMask_Active ;
"******************************************************************************
state_diagram Slot0IntCMask
state Slot0IntCMask_Active:
if (VGR_WRITE_IntMaskReg &
(Slot0IntCMask_DATA_BIT.pin == !Slot0IntCMask_Active) &
(!(HardReset_B == 0) # (Slot0IntCMask_PON_DEFAULT == !Slot0IntCMask_Active))
#
((HardReset_B == 0) & (Slot0IntCMask_PON_DEFAULT == !Slot0IntCMask_Active)) )
then
!Slot0IntCMask_Active
else
Slot0IntCMask_Active ;
state !Slot0IntCMask_Active:
if (VGR_WRITE_IntMaskReg &
(Slot0IntCMask_DATA_BIT.pin == Slot0IntCMask_Active) &
(!(HardReset_B == 0) # (Slot0IntCMask_PON_DEFAULT == Slot0IntCMask_Active))
#
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((HardReset_B == 0) & (Slot0IntCMask_PON_DEFAULT == Slot0IntCMask_Active)) )
then
Slot0IntCMask_Active
else
!Slot0IntCMask_Active ;
"******************************************************************************
state_diagram Slot0IntDMask
state Slot0IntDMask_Active:
if (VGR_WRITE_IntMaskReg &
(Slot0IntDMask_DATA_BIT.pin == !Slot0IntDMask_Active) &
(!(HardReset_B == 0) # (Slot0IntDMask_PON_DEFAULT == !Slot0IntDMask_Active))
#
((HardReset_B == 0) & (Slot0IntDMask_PON_DEFAULT == !Slot0IntDMask_Active)) )
then
!Slot0IntDMask_Active
else
Slot0IntDMask_Active ;
state !Slot0IntDMask_Active:
if (VGR_WRITE_IntMaskReg &
(Slot0IntDMask_DATA_BIT.pin == Slot0IntDMask_Active) &
(!(HardReset_B == 0) # (Slot0IntDMask_PON_DEFAULT == Slot0IntDMask_Active))
#
((HardReset_B == 0) & (Slot0IntDMask_PON_DEFAULT == Slot0IntDMask_Active)) )
then
Slot0IntDMask_Active
else
!Slot0IntDMask_Active ;
"******************************************************************************
state_diagram Slot1IntAMask
state Slot1IntAMask_Active:
if (VGR_WRITE_IntMaskReg &
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(Slot1IntAMask_DATA_BIT.pin == !Slot1IntAMask_Active) &
(!(HardReset_B == 0) # (Slot1IntAMask_PON_DEFAULT == !Slot1IntAMask_Active))
#
((HardReset_B == 0) & (Slot1IntAMask_PON_DEFAULT == !Slot1IntAMask_Active)) )
then
!Slot1IntAMask_Active
else
Slot1IntAMask_Active ;
state !Slot1IntAMask_Active:
if (VGR_WRITE_IntMaskReg &
(Slot1IntAMask_DATA_BIT.pin == Slot1IntAMask_Active) &
(!(HardReset_B == 0) # (Slot1IntAMask_PON_DEFAULT == Slot1IntAMask_Active))
#
((HardReset_B == 0) & (Slot1IntAMask_PON_DEFAULT == Slot1IntAMask_Active)) )
then
Slot1IntAMask_Active
else
!Slot1IntAMask_Active ;
"******************************************************************************
state_diagram Slot1IntBMask
state Slot1IntBMask_Active:
if (VGR_WRITE_IntMaskReg &
(Slot1IntBMask_DATA_BIT.pin == !Slot1IntBMask_Active) &
(!(HardReset_B == 0) # (Slot1IntBMask_PON_DEFAULT == !Slot1IntBMask_Active))
#
((HardReset_B == 0) & (Slot1IntBMask_PON_DEFAULT == !Slot1IntBMask_Active)) )
then
!Slot1IntBMask_Active
else
Slot1IntBMask_Active ;
state !Slot1IntBMask_Active:
if (VGR_WRITE_IntMaskReg &
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(Slot1IntBMask_DATA_BIT.pin == Slot1IntBMask_Active) &
(!(HardReset_B == 0) # (Slot1IntBMask_PON_DEFAULT == Slot1IntBMask_Active))
#
((HardReset_B == 0) & (Slot1IntBMask_PON_DEFAULT == Slot1IntBMask_Active)) )
then
Slot1IntBMask_Active
else
!Slot1IntBMask_Active ;
"******************************************************************************
state_diagram Slot1IntCMask
state Slot1IntCMask_Active:
if (VGR_WRITE_IntMaskReg &
(Slot1IntCMask_DATA_BIT.pin == !Slot1IntCMask_Active) &
(!(HardReset_B == 0) # (Slot1IntCMask_PON_DEFAULT == !Slot1IntCMask_Active))
#
((HardReset_B == 0) & (Slot1IntCMask_PON_DEFAULT == !Slot1IntCMask_Active)) )
then
!Slot1IntCMask_Active
else
Slot1IntCMask_Active ;
state !Slot1IntCMask_Active:
if (VGR_WRITE_IntMaskReg &
(Slot1IntCMask_DATA_BIT.pin == Slot1IntCMask_Active) &
(!(HardReset_B == 0) # (Slot1IntCMask_PON_DEFAULT == Slot1IntCMask_Active))
#
((HardReset_B == 0) & (Slot1IntCMask_PON_DEFAULT == Slot1IntCMask_Active)) )
then
Slot1IntCMask_Active
else
!Slot1IntCMask_Active ;
"******************************************************************************
state_diagram Slot1IntDMask
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state Slot1IntDMask_Active:
if (VGR_WRITE_IntMaskReg &
(Slot1IntDMask_DATA_BIT.pin == !Slot1IntDMask_Active) &
(!(HardReset_B == 0) # (Slot1IntDMask_PON_DEFAULT == !Slot1IntDMask_Active))
#
((HardReset_B == 0) & (Slot1IntDMask_PON_DEFAULT == !Slot1IntDMask_Active)) )
then
!Slot1IntDMask_Active
else
Slot1IntDMask_Active ;
state !Slot1IntDMask_Active:
if (VGR_WRITE_IntMaskReg &
(Slot1IntDMask_DATA_BIT.pin == Slot1IntDMask_Active) &
(!(HardReset_B == 0) # (Slot1IntDMask_PON_DEFAULT == Slot1IntDMask_Active))
#
((HardReset_B == 0) & (Slot1IntDMask_PON_DEFAULT == Slot1IntDMask_Active)) )
then
Slot1IntDMask_Active
else
!Slot1IntDMask_Active ;
"******************************************************************************
state_diagram Slot2IntAMask
state Slot2IntAMask_Active:
if (VGR_WRITE_IntMaskReg &
(Slot2IntAMask_DATA_BIT.pin == !Slot2IntAMask_Active) &
(!(HardReset_B == 0) # (Slot2IntAMask_PON_DEFAULT == !Slot2IntAMask_Active))
#
((HardReset_B == 0) & (Slot2IntAMask_PON_DEFAULT == !Slot2IntAMask_Active)) )
then
!Slot2IntAMask_Active
else
Slot2IntAMask_Active ;
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state !Slot2IntAMask_Active:
if (VGR_WRITE_IntMaskReg &
(Slot2IntAMask_DATA_BIT.pin == Slot2IntAMask_Active) &
(!(HardReset_B == 0) # (Slot2IntAMask_PON_DEFAULT == Slot2IntAMask_Active))
#
((HardReset_B == 0) & (Slot2IntAMask_PON_DEFAULT == Slot2IntAMask_Active)) )
then
Slot2IntAMask_Active
else
!Slot2IntAMask_Active ;
"******************************************************************************
state_diagram Slot2IntBMask
state Slot2IntBMask_Active:
if (VGR_WRITE_IntMaskReg &
(Slot2IntBMask_DATA_BIT.pin == !Slot2IntBMask_Active) &
(!(HardReset_B == 0) # (Slot2IntBMask_PON_DEFAULT == !Slot2IntBMask_Active))
#
((HardReset_B == 0) & (Slot2IntBMask_PON_DEFAULT == !Slot2IntBMask_Active)) )
then
!Slot2IntBMask_Active
else
Slot2IntBMask_Active ;
state !Slot2IntBMask_Active:
if (VGR_WRITE_IntMaskReg &
(Slot2IntBMask_DATA_BIT.pin == Slot2IntBMask_Active) &
(!(HardReset_B == 0) # (Slot2IntBMask_PON_DEFAULT == Slot2IntBMask_Active))
#
((HardReset_B == 0) & (Slot2IntBMask_PON_DEFAULT == Slot2IntBMask_Active)) )
then
Slot2IntBMask_Active
else
!Slot2IntBMask_Active ;
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"******************************************************************************
state_diagram Slot2IntCMask
state Slot2IntCMask_Active:
if (VGR_WRITE_IntMaskReg &
(Slot2IntCMask_DATA_BIT.pin == !Slot2IntCMask_Active) &
(!(HardReset_B == 0) # (Slot2IntCMask_PON_DEFAULT == !Slot2IntCMask_Active))
#
((HardReset_B == 0) & (Slot2IntCMask_PON_DEFAULT == !Slot2IntCMask_Active)) )
then
!Slot2IntCMask_Active
else
Slot2IntCMask_Active ;
state !Slot2IntCMask_Active:
if (VGR_WRITE_IntMaskReg &
(Slot2IntCMask_DATA_BIT.pin == Slot2IntCMask_Active) &
(!(HardReset_B == 0) # (Slot2IntCMask_PON_DEFAULT == Slot2IntCMask_Active))
#
((HardReset_B == 0) & (Slot2IntCMask_PON_DEFAULT == Slot2IntCMask_Active)) )
then
Slot2IntCMask_Active
else
!Slot2IntCMask_Active ;
"******************************************************************************
state_diagram Slot2IntDMask
state Slot2IntDMask_Active:
if (VGR_WRITE_IntMaskReg &
(Slot2IntDMask_DATA_BIT.pin == !Slot2IntDMask_Active) &
(!(HardReset_B == 0) # (Slot2IntDMask_PON_DEFAULT == !Slot2IntDMask_Active))
#
((HardReset_B == 0) & (Slot2IntDMask_PON_DEFAULT == !Slot2IntDMask_Active)) )
then
!Slot2IntDMask_Active
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else
Slot2IntDMask_Active ;
state !Slot2IntDMask_Active:
if (VGR_WRITE_IntMaskReg &
(Slot2IntDMask_DATA_BIT.pin == Slot2IntDMask_Active) &
(!(HardReset_B == 0) # (Slot2IntDMask_PON_DEFAULT == Slot2IntDMask_Active))
#
((HardReset_B == 0) & (Slot2IntDMask_PON_DEFAULT == Slot2IntDMask_Active)) )
then
Slot2IntDMask_Active
else
!Slot2IntDMask_Active ;
"******************************************************************************
"******************************************************************************
" External Read Registers' Chip-Selects
"******************************************************************************
"******************************************************************************
equations
Bcsr2Cs_B.oe = H ;
Bcsr4Cs_B.oe = H ;
!Bcsr2Cs_B = VGR_READ_BCSR_2 ;
!Bcsr4Cs_B = VGR_READ_BCSR_4 ;
"******************************************************************************
"******************************************************************************
"* Read Registers.
"* All registers have read capabilty. (BCSR2 and BCSR4 are read externally)
"******************************************************************************
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"******************************************************************************
equations
DataOe = VGR_READ_BCSR_0 #
VGR_READ_BCSR_1 #
VGR_READ_BCSR_3 #
(HRESET_CFG_IN_BCSR & CS0_ASSERTED & !DSyncHardReset_B.fb) ;
Data.oe = DataOe.fb ;
when (VGR_READ_BCSR_0) then
Data = ReadBcsr0 ;
else when (VGR_READ_BCSR_1) then
Data = ReadBcsr1 ;
else when (VGR_READ_BCSR_3) then
Data = ReadBcsr3 ;
else when (FIRST_CFG_BYTE_READ) then
Data = CfgByte0;
else when (SCND_CFG_BYTE_READ) then
Data = CfgByte1;
else when (THIRD_CFG_BYTE_READ) then
Data = CfgByte2;
else when (FORTH_CFG_BYTE_READ) then
Data = CfgByte3;
DataPCIOe = VGR_READ_IntReg #
VGR_READ_IntMaskReg ;
DataPCI.oe = DataPCIOe.fb ;
when (VGR_READ_IntReg) then
DataPCI = IntReg.fb ;
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else when (VGR_READ_IntMaskReg) then
DataPCI = IntMaskReg.fb ;
"********************* brd_ctl ********************************************
"******************************************************************************
"******************************************************************************
"* Reset Logic
"******************************************************************************
"******************************************************************************
"******************************************************************************
equations
Reset.oe = ResetEn ;
Reset = 0 ;" open drain
RstDeb1 = !( Rst1 & (!( RstDeb1.com & Rst0) ) ) ; " Reset push-button debouncer
AbrDeb1 = !( Abr1 & (!( AbrDeb1.com & Abr0) ) ) ; " Abort push-button debouncer
HardResetEn = RstDeb1.com & AbrDeb1.com ;" both buttons are depressed;
SoftResetEn = RstDeb1.com & !AbrDeb1.com ;" only reset button depressed
TransRst.oe = 7 ;" transceivers' reset, always enabled.
!AtmRstOut_B = !AtmRst_B.fb # !HardReset_B ;
!FEthRstOut1_B = !FEthRst1_B.fb # !HardReset_B ;
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!FEthRstOut2_B = !FEthRst2_B.fb # !HardReset_B ;
"******************************************************************************
"* Hard reset configuration
"******************************************************************************
"equations
"RstConf_B.oe = H;
"RstConf_B = L;
"******************************************************************************
"* NMI generation
"******************************************************************************
equations
NMI_B.oe = NMIEn ;
NMI_B = 0 ;" O.D.
NMIEn = !RstDeb1.com & AbrDeb1.com ;" only abort button depressed
"******************************************************************************
"* local data buffers enable
"******************************************************************************
equations
SyncHardReset_B.clk = SYSCLK ;
SyncHardReset_B.ar = 0;
SyncHardReset_B.ap = 0;
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DSyncHardReset_B.clk = SYSCLK ;
DSyncHardReset_B.ar = 0;
DSyncHardReset_B.ap = 0;
SyncHardReset_B := HardReset_B ;
DSyncHardReset_B := SyncHardReset_B.fb ;
DataBufEn_B.oe = H ;
!DataBufEn_B = ( !Cs0_B # " covers also hard reset config
!Cs4_B #
!BrdContRegCs_B #
!IntContCs_B #
!AtmUniCsOut_B # " provides data-hold for write
!ToolCs1_B #
!ToolCs2_B ) &
( !BUFFER_HOLD_OFF ) ;
ToolDataBufEn_B.oe = H ;
!ToolDataBufEn_B = ( !ToolCs1_B #
!ToolCs2_B ) &
( !BUFFER_HOLD_OFF ) ;
"******************************************************************************
"* local data buffers disable (data contention protection)
"******************************************************************************
"* Since with Voyager, hard-reset conf is read from flash/eeprom during HRESET
"* asserted and since these are all consequitive read cycles and since
"* the cycles following hard reset are also reads (boot) the hold-off
"* state machine may be left in NO_HOLD_OFF for HRESET_B asserted duration
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"* without warrying about contention between flash and data buffers.
equations
HoldOffCnt.clk = SYSCLK ;
HoldOffCnt.ar = 0;
HoldOffCnt.ap = 0;
HoldOffTc = (HoldOffCnt.fb == 3) ;
when ( (((END_OF_FLASH_EEPROM_READ # END_OF_ATM_READ )
& (HoldOffCnt.fb == 0)) #
(HoldOffCnt.fb != 0)) & !(HoldOffCnt.fb == 4) & DSyncHardReset_B.fb ) then
HoldOffCnt := HoldOffCnt.fb + 1 ;
else
HoldOffCnt := 0 ;
"******************************************************************************
"* Flash/EEPROM Chip Selects
"******************************************************************************
equations
FlashCsOut.oe = ^hf ;
!FlashCs1_B = CS0_ASSERTED & FLASH_BANK1 & HRESET_BOOT_IN_FLASH #
CS0_ASSERTED & FLASH_BANK1 & BOOT_IN_FLASH &
DSyncHardReset_B.fb #
CS4_ASSERTED & FLASH_BANK1 & (HRESET_BOOT_IN_EEPROM #
BOOT_IN_EEPROM);
!FlashCs2_B = CS0_ASSERTED & FLASH_BANK2 & HRESET_BOOT_IN_FLASH #
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CS0_ASSERTED & FLASH_BANK2 & BOOT_IN_FLASH &
DSyncHardReset_B.fb #
CS4_ASSERTED & FLASH_BANK2 & (HRESET_BOOT_IN_EEPROM #
BOOT_IN_EEPROM);
!FlashCs3_B = CS0_ASSERTED & FLASH_BANK3 & HRESET_BOOT_IN_FLASH #
CS0_ASSERTED & FLASH_BANK3 & BOOT_IN_FLASH &
DSyncHardReset_B.fb #
CS4_ASSERTED & FLASH_BANK3 & (HRESET_BOOT_IN_EEPROM #
BOOT_IN_EEPROM);
!FlashCs4_B = CS0_ASSERTED & FLASH_BANK4 & HRESET_BOOT_IN_FLASH #
CS0_ASSERTED & FLASH_BANK4 & BOOT_IN_FLASH &
DSyncHardReset_B.fb #
CS4_ASSERTED & FLASH_BANK4 & (HRESET_BOOT_IN_EEPROM #
BOOT_IN_EEPROM);
EEpromCs_B.oe = H ;
!EEpromCs_B = CS0_ASSERTED & HRESET_BOOT_IN_EEPROM #
CS0_ASSERTED & BOOT_IN_EEPROM & DSyncHardReset_B.fb #
CS4_ASSERTED & (HRESET_BOOT_IN_FLASH # BOOT_IN_FLASH) ;
"******************************************************************************
"* ATM UNI Chip Select
"******************************************************************************
equations
AtmUniCsOut_B.oe = H ;
!AtmUniCsOut_B = !AtmUniCsIn_B;
"******************************************************************************
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"* Power On Reset
"******************************************************************************
equations
S_PORIn_B.clk = SYSCLK ;
S_PORIn_B.ar = 0;
S_PORIn_B.ap = 0;
S_PORIn_B := PORIn_B ;
"******************************************************************************
"******************************************************************************
"* Generating Interrupt Request to the PQ2.
"******************************************************************************
"******************************************************************************
equations
PCI_Interrupt = (Slot0IntA #
Slot0IntB #
Slot0IntC #
Slot0IntD #
Slot1IntA #
Slot1IntB #
Slot1IntC #
Slot1IntD #
Slot2IntA #
Slot2IntB #
Slot2IntC #
Slot2IntD) ;
PCI_IRQ_B.oe = PCI_Interrupt ; " Open-Drain output
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!PCI_IRQ_B = PCI_Interrupt ; " Interrupt Request shows after OE
"******************************************************************************
"* Auxiliary functions
"******************************************************************************
equations
KeepPinsConnected = TEA_B & BCTL1 # KeepPinsConnected.com;
"******************************************************************************
"*
*
"* #######
*
"* # ###### #### #####
*
"* #
#
#
#
*
*
"* # ##### ####
#
*
"* #
"* #
#
#
#
#
#
#
#
*
"* # ###### ####
"*
#
*
*
"* #
#
*
"* # # ###### #### ##### #### ##### ####
*
"* # # #
#
#
#
#
#
# # # #
*
"* # # ##### #
#
#
# # # ####
*
"* # # #
"* # #
#
#
#
#
# #####
#
*
#
#
#
#
# # # #
#
*
"* # ###### ####
"*
#### # # ####
*
*
"******************************************************************************
END
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7.2.2 U41 - Power switch debounce
MODULE Power_Debouncer
TITLE 'MPC8280 Power Debouncer'
"******************************************************************************
"* Device declaration.
*
"******************************************************************************
"******************************************************************************
"* #######
*
"* #
#
# ##### ###### ##### #
#
##
#
####
*
"* #
# #
##
#
#
#
# ## # # # #
#
*
"* #####
"* #
#
##### # # # # # # # #
##### # # # ###### #
####
*
##
#
#
#
#
#
#
*
*
"* #
# #
# # # ## # # #
#
#
"* ####### #
#
###### # # # # # # ###### ####
*
"******************************************************************************
"******************************************************************************
"* Pins declaration.
*
"******************************************************************************
"* System i/f pins
"******************************************************************************
SYSCLK
PIN 5 ;
ChasisPowerIn_B PIN 15 ; "Chassis Power Switch
PowerOn_B PIN 16 istype 'reg' ; " Power Supply Power-On
"******************************************************************************
"* ###
*
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"* #
#
# ##### ###### ##### #
#
##
#
####
*
*
*
"* # ## #
"* # # # #
"* # # # #
"* # # ##
#
#
#
#
#
#
# ## # # # #
#
##### # # # # # # # #
####
*
#
#
##### # # # ###### #
# # # ## # # #
#
*
*
#
#
"* ###
#
#
#
###### # # # # # # ###### ####
"******************************************************************************
"******************************************************************************
"* Chassis Power Switch Buffer.
"******************************************************************************
Power_Buffer NODE istype 'reg,buffer' ;
"******************************************************************************
"* Creating internal clock generator.
"******************************************************************************
inv1 NODE istype 'com,keep' ;
inv2 NODE istype 'com,keep' ;
inv3 NODE istype 'com,keep' ;
inv4 NODE istype 'com,keep' ;
inv5 NODE istype 'com,keep' ;
counter0,
counter1,
counter2,
counter3,
counter4,
counter5,
counter6,
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counter7,
countera0,
countera1,
countera2,
countera3,
countera4,
countera5,
countera6,
countera7,
counterb0,
counterb1,
counterb2,
counterb3,
counterb4,
counterb5,
counterb6,
counterb7
NODE istype 'reg,buffer' ;
"******************************************************************************
"* #####
*
"* # # #### # # #### ##### ##
#
# #####
*
"* #
"* #
"* #
#
#
#
# ## # #
#
# # ## #
# # # #
###### # # #
#
*
# # # # ####
#
#
#
*
# # # #
#
#
#
*
"* # # # # # ## #
#
#
#
#
# # ##
# #
#
*
"* ##### #### # # ####
#
#
#
*
"*
*
"* ######
*
"* # # ###### #### #
## #####
# # #
# # # #####
*
"* # # #
#
# #
#
*
"* # # ##### #
#
#
*
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"* # # #
"* # # #
#
#
#
###### #####
# # #
*
# #
#
*
"* ###### ###### #### ###### # # #
"*
#
*
*
"* ## #####
#
#### #
# ## #
# # # #
#
*
"* # #
#
#
#
#
#
#
*
"* #
#
*
"* ######
#
#
#
# # # #
# # ##
*
"* #
"* #
#
#
#
#
#
#
#
*
#### #
#
*
"******************************************************************************
H, L, X, Z = 1, 0, .X., .Z. ;
C, D, U = .C., .D., .U. ;
"******************************************************************************
"* SIMULATION = 1 ;
"******************************************************************************
"* Signal groups
"******************************************************************************
counter = [counter7,counter6,counter5,counter4,
counter3,counter2,counter1,counter0] ;
countera = [countera7,countera6,countera5,countera4,
countera3,countera2,countera1,countera0] ;
counterb = [counterb7,counterb6,counterb5,counterb4,
counterb3,counterb2,counterb1,counterb0] ;
"******************************************************************************
"* ATX Power Declarations.
"******************************************************************************
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PowerOn = 0 ;
PowerOff = 1 ;
"******************************************************************************
"* Equations, state diagrams.
"******************************************************************************
*
"*
*
"* #######
*
"* #
#### #
#
## #####
#
#
#### # # ####
# ## # #
# # # # ####
# # # #
# # ## #
*
"* #
#
# # # # #
# # # #
#
#
*
"* #####
"* #
#
#
#
#
#
#
*
# # # # # ######
# # # # #
#
#
#
#
*
"* #
#
#
#
#
#
*
"* ####### ### # #### #
"*
#
#
#### # # ####
*
*
"******************************************************************************
"******************************************************************************
equations
"******************************************************************************
"******************************************************************************
"* Generating PowerOn signal to the ATX Power Supply.
"******************************************************************************
"******************************************************************************
equations
inv1 = !inv5.com ;" generating internal clock oscilator
inv2 = !inv1.com ;
inv3 = !inv2.com ;
inv4 = !inv3.com ;
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inv5 = !inv4.com ;
counter.ar = 0 ;
counter.ap = 0 ;
counter.clk = !inv5.com ;
when ( counter.fb == 255 ) then counter := 0 else counter := counter + 1 ;
countera.ar = 0 ;
countera.ap = 0 ;
countera.clk = ( counter.fb == 0 ) ;
when ( countera.fb == 255 ) then countera := 0 else countera := countera + 1 ;
counterb.ar = 0 ;
counterb.ap = 0 ;
counterb.clk = ( countera.fb == 0 ) ;
when ( counterb.fb == 255 ) then counterb := 0 else counterb := counterb + 1 ;
Power_Buffer.ar = 0 ;
Power_Buffer.ap = 0 ;
Power_Buffer.clk = ( counterb.fb == 0 ) ;
Power_Buffer := ChasisPowerIn_B ;
PowerOn_B.oe = H ;
PowerOn_B.ar = 0 ;
PowerOn_B.ap = 0 ;
PowerOn_B.clk = ( counterb.fb == 0 ) ;
PowerOn_B := !Power_Buffer.fb ;
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"******************************************************************************
"*
*
"* #######
*
"* # ###### #### #####
*
"* #
#
#
#
*
*
"* # ##### ####
#
*
"* #
"* #
#
#
#
#
#
#
#
*
"* # ###### ####
"*
#
*
*
"* #
#
*
"* # # ###### #### ##### #### ##### ####
*
"* # # #
#
#
#
#
#
# # # #
*
"* # # ##### #
#
#
# # # ####
*
"* # # #
"* # #
#
#
#
#
# #####
#
*
#
#
#
#
# # # #
#
*
"* # ###### ####
"*
#### # # ####
*
*
"******************************************************************************
@ifdef SIMULATION {
}
END
7.3
Schematics and Bill Of Materials
This sectoin shows the schematicds of the PQ2FADS-ZU and the Bill Of Materials.
7.3.1 Schematics
Following are the schematics of the board.
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1 1 A
1 0 A
1 1 B
1 0 B
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1 0
1 0
1 0
1 0
1 0
1 0
1 0
1 0
1 0
1 0
1 0
1 0
1 0
1 0
1 0
1 0
1 0
1 0
1 0
1 0
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7.3.2 Bill of Materials
The following is the Bill Of Materials for the PQ2FADS-ZU including the L2Cache option.
Figure 7-1. PQ2FADS-ZU Bill of Materials
Item
Quan-
tity
Reference
Value
0.01UF-2KV
47uF
Part Number
202S49W103KV4E
TAJD476K016
Manufacturer
1
2
4
"C1,C2,C3,C6"
JOHANSON
DIELECTRIC
19
"C4,C5,C9,C18,C23,C35,C39,"
"C41,C42,C53,C84,C97,C98,"
"C106,C138,C140,C282,C287,"
C326
AVX
3
321
"C7,C8,C12,C13,C14,C15,"
100nF
0603YC104KAT2A
AVX
"C16,C17,C19,C20,C21,C22,"
"C24,C31,C32,C33,C36,C37,"
"C38,C40,C43,C44,C45,C46,"
"C47,C48,C49,C50,C52,C54,"
"C55,C56,C57,C58,C59,C60,"
"C61,C62,C63,C64,C65,C66,"
"C67,C68,C69,C70,C71,C72,"
"C73,C74,C75,C79,C80,C81,"
"C83,C85,C86,C87,C88,C89,"
"C90,C91,C92,C93,C94,C95,"
"C96,C101,C102,C103,C104,"
"C105,C107,C108,C109,C110,"
"C111,C112,C113,C114,C115,"
"C116,C117,C118,C119,C120,"
"C128,C129,C130,C131,C132,"
"C133,C134,C135,C136,C137,"
"C142,C145,C146,C148,C149,"
"C150,C151,C152,C153,C156,"
"C157,C158,C159,C160,C161,"
"C167,C168,C169,C173,C174,"
"C175,C176,C177,C178,C179,"
"C180,C181,C182,C183,C184,"
"C185,C186,C187,C188,C189,"
"C190,C191,C194,C195,C196,"
"C197,C198,C199,C200,C201,"
"C202,C203,C204,C205,C206,"
"C207,C208,C209,C210,C211,"
"C212,C213,C218,C219,C220,"
"C221,C222,C227,C228,C229,"
"C230,C231,C232,C233,C234,"
"C235,C236,C237,C238,C239,"
"C240,C241,C242,C246,C251,"
"C252,C253,C254,C255,C256,"
"C257,C258,C259,C260,C261,"
"C262,C263,C268,C269,C270,"
"C271,C272,C273,C274,C275,"
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Figure 7-1. PQ2FADS-ZU Bill of Materials
"C276,C277,C280,C281,C283,"
"C288,C292,C294,C295,C296,"
"C300,C301,C302,C306,C309,"
"C310,C311,C314,C315,C316,"
"C317,C318,C319,C320,C321,"
"C322,C323,C324,C325,C328,"
"C329,C330,C331,C332,C333,"
"C334,C335,C336,C337,C338,"
"C339,C340,C341,C342,C343,"
"C344,C345,C346,C347,C348,"
"C349,C350,C351,C352,C353,"
"C354,C355,C356,C357,C358,"
"C359,C360,C361,C362,C363,"
"C364,C365,C366,C367,C368,"
"C369,C370,C371,C372,C373,"
"C374,C375,C376,C379,C380,"
"C381,C382,C383,C384,C385,"
"C386,C387,C388,C389,C392,"
"C393,C394,C395,C396,C397,"
"C398,C399,C400,C401,C402,"
"C403,C404,C405,C406,C407,"
"C408,C409,C410,C411,C412,"
"C413,C414,C415,C416,C417,"
"C418,C419,C420,C421,C422,"
"C423,C424,C443,C445,C446"
4
5
19
55
"C10,C11,C26,C27,C28,C29,"
"C30,C34,C51,C76,C77,C100,"
"C155,C164,C170,C307,C327,"
"C444,C447"
10uF
10nF
TAJC106K025R
AVX
AVX
"C25,C143,C144,C147,C154,"
"C162,C163,C165,C166,C171,"
"C172,C192,C193,C214,C215,"
"C216,C217,C223,C224,C225,"
"C226,C243,C244,C245,C247,"
"C248,C249,C250,C264,C265,"
"C266,C267,C278,C279,C284,"
"C285,C286,C289,C290,C291,"
"C297,C298,C299,C303,C304,"
"C305,C308,C312,C313,C377,"
"C378,C390,C391,C441,C442"
06035C103KAT2A
6
7
8
9
1
1
C78
C82
C99
100uF
68uF-16V
1uF
TAJD107K016R
AVX
TAJD686M020R
B45196H5105K109
AVX12065C102KA
AVX
1
SIEMENS
AVX
24
"C121,C122,C123,C124,C125,"
"C126,C127,C139,C425,C426,"
"C427,C428,C429,C430,C431,"
"C432,C433,C434,C435,C436,"
"C437,C438,C439,C440"
1nF
10
11
2
1
"C141,C448"
C293
100nF-500V
1500pF
501S43W104MV4E
12065A152JAT00J
JOHANSON
AVX
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Figure 7-1. PQ2FADS-ZU Bill of Materials
12
13
14
15
3
1
5
9
"D1,D2,D3"
LL4004
LL4004G
TSC
F1
SMD150/33-2
GND_Bridge254
JUMPER1x3
SMD150/33-2
PD-999-11-11010
87156-0303
RAYCHEM
PRECIDIP
MOLEX
"JP1,JP6,JP8,JP12,JP13"
"JP2,JP3,JP4,JP5,JP7,JP9,"
"JP10,JP11,JP14"
16
17
7
"J1,J2,J3,J4,J5,J6,J7"
GND_Bridge
LED_GREEN
PD-999-11-11210
KPT-3216SGD
PRECIDIP
18
"LD1,LD2,LD3,LD4,LD5,LD6,"
"LD7,LD8,LD9,LD16,LD17,"
"LD21,LD22,LD23,LD25,LD26,"
"LD27,LD28"
KINGBRIGHT
18
7
"LD10,LD11,LD12,LD13,LD15,"
"LD19,LD24"
LED_YELLOW
KPT-3216YD
KINGBRIGHT
19
20
21
22
23
2
1
"LD14,LD20"
LD18
LED_RED
KPT-3216ID
KINGBRIGHT
KINGBRIGHT
FAIR RITE
MURATA
LED_RED
KPT-3216YD
2
"L2,L1"
BEAD_FERRITE
NFM60R30T222T1
BLM18AG121SN1
2743021447
4
"L3,L4,L21,L22"
NFM60R30T222T1
BLM18AG121SN1
17
"L5,L6,L7,L8,L9,L10,L11,"
"L12,L13,L14,L15,L16,L17,"
"L18,L19,L20,L23"
MURATA
24
25
26
27
28
29
30
1
1
P1
RS232-PORT2
787616-1
8LE009009D306H
787616-1
EDA
P2
AMP
2
"P4,P3"
"P5,P6"
"P7,P25"
"P8,P9,P10"
RJ45
43202-8110
QSE-020-01-L-D-A
23762
MOLEX
SAMTEC
ERNI
AMP
2
QSE-020-01-L-D-A
23762
2
3
PCI_CONNECTOR
MICTOR38
145154-4
11
"P11,P12,P13,P14,P16,P17,"
"P18,P23,P28,P29,P30"
2-767004-2
AMP
31
32
33
34
35
1
4
1
1
1
P15
COP/JTAG
CON10AP
SMB Straight
CON6AP
LPH-16SA-SG
KCC
"P19,P20,P22,P26"
TSM-10501-SDV-AP
82SMB-50-0-1/111
HEADER 3x2 SMT
39-29-9202
SAMTEC
SUHNER
SAMTEC
MOLEX
P21
P24
P27
ATX_Power_Connect
or
36
37
1
2
P31
DNR-25PCB-SG
MMDF2P02HD
DNR-25PCB-SG
MMDF2P02HD
KCC_Keltron
"Q2,Q1"
ON SEMI-
CONDUCTOR
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Figure 7-1. PQ2FADS-ZU Bill of Materials
38
39
2
"Q4,Q3"
MMDF4N01HD
MMDF4N01HD
ON SEMI-
CONDUCTOR
29
"RN1,RN2,RN3,RN4,RN25,"
22
CRA3A4E220JT
AVX
"RN26,RN27,RN43,RN44,RN45,"
"RN46,RN47,RN48,RN49,RN50,"
"RN51,RN52,RN56,RN57,RN60,"
"RN66,RN67,RN70,RN71,RN74,"
"RN81,RN91,RN92,RN105"
40
35
"RN5,RN15,RN16,RN17,RN18,"
"RN20,RN21,RN23,RN24,RN28,"
"RN29,RN30,RN32,RN40,RN41,"
"RN42,RN53,RN54,RN75,RN82,"
"RN83,RN84,RN85,RN86,RN87,"
"RN88,RN89,RN90,RN96,"
10K
RS8A1002J
ROHM
"RN100,RN101,RN102,RN103,"
"RN104,RN106"
41
42
43
8
6
"RN6,RN7,RN8,RN9,RN10,"
"RN11,RN12,RN13"
10
CRA06S0803100JR
CRA06S0803000RT
DALE
AVX
"RN14,RN63,RN68,RN72,RN73," 33
RN77
14
"RN19,RN22,RN55,RN58,RN59,"
"RN61,RN62,RN64,RN65,RN69,"
"RN95,RN97,RN98,RN99"
0
DALE
44
45
4
6
"RN31,RN33,RN34,RN35"
470
CRA06S0803 471
JRT1
DALE
DALE
"RN36,RN37,RN38,RN39,RN93," 43
RN94
CRA06S0803430JRT
46
47
48
4
2
"RN76,RN78,RN79,RN80"
"RP1,RP2"
33
CRA06S0803330JR
3362P-1-102
DALE
1K
10K
BOURNS
83
"R1,R38,R48,R49,R50,R51,"
"R59,R122,R135,R141,R142,"
"R143,R145,R146,R157,R158,"
"R160,R161,R167,R169,R173,"
"R174,R175,R177,R183,R184,"
"R185,R191,R199,R201,R207,"
"R208,R211,R214,R215,R217,"
"R218,R219,R220,R221,R223,"
"R228,R229,R230,R231,R245,"
"R246,R247,R248,R253,R254,"
D11010KFCS
ROEDER-
STEIN
"R267,R279,R293,R306,R307,"
"R318,R319,R328,R332,R341,"
"R342,R343,R344,R347,R353,"
"R356,R368,R379,R383,R384,"
"R389,R390,R396,R406,R407,"
"R420,R421,R422,R428,R431,"
"R432,R433"
206
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Figure 7-1. PQ2FADS-ZU Bill of Materials
49
50
8
4
"R2,R3,R4,R5,R128,R129,"
"R130,R131"
75
D11075RFCS
DRALORIK
"R6,R15,R18,R19"
49R9
D2549R9FCS
ROEDER-
STEIN
51
52
4
9
"R7,R13,R14,R17"
78R7
33R2
D2578R7FCS
D11 33R2FCS
D2578R7FCS
"R8,R9,R10,R20,R24,R295,"
"R303,R305,R312"
ROEDER-
STEIN
53
54
2
"R12,R11"
158
CRCW0603-1580F
D1122R1FCS
DALE
25
"R16,R21,R26,R27,R67,R68,"
"R69,R70,R202,R203,R209,"
"R210,R270,R274,R282,R292,"
"R297,R308,R309,R310,R311,"
"R329,R330,R333,R334"
22R1
ROEDER-
STEIN
55
53
"R22,R23,R25,R28,R29,R30,"
"R35,R36,R37,R41,R42,R43,"
"R45,R46,R47,R85,R95,R100,"
"R162,R163,R170,R179,R180,"
"R194,R195,R205,R216,R224,"
"R225,R226,R227,R233,R234,"
"R235,R236,R237,R251,R252,"
"R255,R256,R263,R264,R265,"
"R266,R275,R276,R277,R287,"
"R300,R301,R320,R324,R331"
4K7
D1104K7FCS
ROEDER-
STEIN
56
52
"R31,R33,R39,R40,R44,R91,"
"R94,R96,R97,R116,R117,"
"R119,R120,R121,R148,R204,"
1K
D11001KFCS
DRALORIK
"R212,R213,R239,R240,R259,"
"R260,R261,R268,R269,R271,"
"R272,R273,R285,R286,R288,"
"R289,R337,R338,R348,R352,"
"R354,R358,R369,R378,R386,"
"R387,R391,R392,R394,R395,"
"R397,R405,R416,R419,R429,"
R430
57
1
R32
2K2
D2502K2FCS
ROEDER-
STEIN
58
59
2
"R178,R34"
510
330
CRCW0603-5100F
DALE
28
"R52,R53,R54,R55,R56,R57,"
"R58,R62,R64,R89,R90,R92,"
"R93,R102,R103,R106,R108,"
"R372,R373,R375,R377,R400,"
"R401,R402,R409,R423,R424,"
R427
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Figure 7-1. PQ2FADS-ZU Bill of Materials
60
61
27
28
"R60,R79,R110,R111,R112,"
"R113,R115,R118,R192,R238,"
"R257,R258,R290,R294,R299,"
"R304,R313,R321,R322,R323,"
"R339,R370,R371,R380,R382,"
"R388,R393"
0
D11000RFCS
ROEDER-
STEIN
"R61,R63,R65,R66,R86,R87,"
"R88,R101,R104,R105,R107,"
"R109,R359,R360,R361,R362,"
"R363,R364,R365,R374,R376,"
"R398,R399,R408,R410,R411,"
"R425,R426"
220
62
63
19
2
"R71,R72,R73,R75,R76,R77,"
"R78,R80,R81,R82,R83,R84,"
"R232,R242,R262,R278,R280,"
"R281,R413"
43R2
D1143R2FCS
ROEDER-
STEIN
"R114,R74"
0R005
WSL2512 0.005ohm
1%
DALE
AVX
64
65
1
R98
110
330
CR32111J-T
D25330RJCS
21
"R99,R123,R124,R125,R127,"
"R132,R140,R147,R155,R156,"
"R164,R168,R171,R176,R181,"
"R189,R196,R197,R200,R206,"
R415
ROEDER-
STEIN
66
67
2
"R126,R136"
1K
D25001KFCS
D25150RFCS
DRALORIK
10
"R133,R159,R165,R166,R172,"
"R186,R187,R412,R417,R418"
150
ROEDER-
STEIN
68
12
"R134,R139,R190,R198,R335,"
"R336,R340,R345,R346,R351,"
"R366,R367"
1K5
D2501K5FCS
ROEDER-
STEIN
69
70
2
1
"R138,R137"
24R3
330
D2524R3FCS
D25 330RJCS
ROEDER-
STEIN
R144
ROEDER-
STEIN
71
72
1
4
R149
220
D25220RJCS
D1151R1FCS
DRALORIK
"R150,R151,R284,R357"
51R1
ROEDER-
STEIN
73
74
75
3
2
2
"R152,R153,R154"
"R182,R188"
150
D25 150RJCS
D25 06K8FCS
D2502R7FCS
ROEDER-
STEIN
6K8 1%
2R7
ROEDER-
STEIN
"R193,R222"
ROEDER-
STEIN
208
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Figure 7-1. PQ2FADS-ZU Bill of Materials
76
1
R241
47K
D25047KFCS
ROEDER-
STEIN
77
78
3
1
"R243,R249,R250"
R244
20
D25020RFCS
DRALORIK
0R5
D250R50FCS
D25010RFCS
xxx
ROEDER-
STEIN
79
80
2
4
"R326,R283"
10
ROEDER-
STEIN
"R291,R296,R298,R302"
300
ROEDER-
STEIN
81
82
4
4
"R314,R315,R325,R327"
"R316,R317,R349,R350"
15
0
D25 015RFCS
D25000RFCS
DRALORIK
ROEDER-
STEIN
83
84
1
1
R355
R381
300
5K6
CR0805-JW-301
D2505K6FCS
BOURNS
ROEDER-
STEIN
85
86
87
88
1
1
1
1
R385
R403
R404
R414
3K
D25-03KJ-S
DRALORIK
DALE
172
21R5
243
CRCW0603-1720F
CRCW0603-21R5F
D25243RFCS
DALE
ROEDER-
STEIN
89
90
91
92
93
94
98
99
1
1
1
2
1
1
1
2
SW1
POWER-ON_RESET
ABORT
KS12-R23-CQE
KS12-R21-CQE
KS12-R22-CQE
90HBW04SR
90HBW08S
C&K
SW2
C&K
SW3
SOFT-RESET
SW_DIP-4/SM
SW_DIP-8/SM
E101MD1ABE
HFBR-5805
C&K
"SW5,SW4"
SW6
GRAYHIL
GRAYHIL
C&K
SW7
E101MD1ABE
HFBR-5805
U1
AGILENT
"U26,U2"
74ACT541
74ACT541DW
ON SEMI-
CONDUCTOR
100
101
102
103
104
105
106
2
1
1
2
6
1
1
"U4,U3"
MAX3241ECAI
MIC5209-2.5BS
PDIUSBP11A
TG22-3506
MAX3241ECAI
MIC5209-2.5BS
PDIUSBP11A
TG22-3506ND
MC74LCX125DT
MPC947FA
U5
MICREL
U6
PHILIPS
"U7,U8"
HALO
"U9,U17,U36,U48,U51,U53"
74LCX125
MOTOROLA
MOTOROLA
PMC SIERRA
U10
U11
MPC947
PM5384-NI
PM5384-NI
MOTOROLA
PQ2FADS-ZU User’s Manual
209
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Figure 7-1. PQ2FADS-ZU Bill of Materials
107
108
2
"U12,U13"
DM9161
DM9161E
DAVICOM
SEIKO
11
"U14,U21,U23,U24,U30,U33,"
"U34,U40,U57,U66,U70"
IDT74CBTLV3257PG IDT74CBTLV3257PG
109
1
U15
S-80828ANMP
S-80828ANMP-EDR-
T2
110
111
2
"U59,U16"
IDTQS3VH16233-PV
IDTQS34XV245Q3
IDTQS3VH16233-PV
IDTQS34XV245Q3
IDT
IDT
12
"U18,U19,U20,U22,U25,U29,"
"U61,U62,U63,U65,U67,U68"
112
113
114
115
1
1
1
2
U27
MPC8285
U28
SN74LVT8980ADWR SN74LVT8980ADWR
U31
MIC29500BT
MIC29500-3.3BT
MICREL
"U69,U32"
MT48LC2M32B2TG-
6
MT48LC2M32B2TG-6 MICRON
116
117
118
119
120
121
122
123
124
1
2
3
1
1
1
3
1
1
U35
M4A3_192/96
MPC2605
M4A3-192/96-6VC
MPC2605ZP66
LATTICE
MOTOROLA
MOTOROLA
MOTOROLA
VANTIS
"U37,U71"
"U38,U43,U44"
U39
74LCX541
MC74LCX541DT
MPC9448FA
MPC9448
U41
M4A5-64/32-VC48
SN74ALVCH162260
74LCX16244
M4A5-64/32-7VC48
SN74ALVCH162260
MC74LCX16244DT
EPM3064ATC100-10
MC74LCX16245DT
U42
TI
"U45,U77,U78"
U46
MOTOROLA
ALTERA
EPM3064ATC100-10
74LCX16245
U47
ON SEMI-
CONDUCTOR
125
126
1
1
U49
U50
74LVXZ161284MTD
LM317D2T
74LVXZ161284MTD
LM317D2T
TI
ON SEMI-
CONDUCTOR
127
128
1
1
U52
U54
AT28HC64B-70JC
FLASH_SIMM80
AT28HC64B-70JC
ATMEL
SM73228XG1JHBG0
SMART MOD-
ULAR TECH-
NOLOGIES
129
1
U55
74LCX74D
MC74LCX74D
ON Semicon-
ductor
130
131
132
3
1
3
"U56,U60,U64"
U58
CY2309ZC-1H
PI3B33X257B
CY2309ZC-1H
PI3B33X257B
Cypress
Pericom
"U72,U73,U74"
MT48LC4M32B2TG-
6
MT48LC4M32B2TG-6 MICRON
210
PQ2FADS-ZU User’s Manual
MOTOROLA
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Figure 7-1. PQ2FADS-ZU Bill of Materials
133
134
135
136
137
138
2
2
1
1
1
1
"U76,U75"
74ALVT16245
74ALVT16245DL
74ALVT16373DL
PHILIPS
"U79,U80"
74ALVT16373
PHILIPS
M-TRON
M-TRON
M-TRON
M-TRON
X1
X2
X3
X4
M216TCN50.00
M218TCN-19.44MHz
M216TCN-48.00MHz
66MHz-3V3
M216TCN50.00
M218TCN-19.44MHz
M216TCN-48.00MHz
M3H16FCD-3V3-
66MHz
139
140
1
1
X5
X6
40MHz-3V3
M3H16FCD-3V3-
40MHz
M-TRON
1.10933E+12
1.10933E+12
PRECIDIP
MOTOROLA
PQ2FADS-ZU User’s Manual
211
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212
PQ2FADS-ZU User’s Manual
MOTOROLA
For More Information On This Product,
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