PUMA68S4000/M-025 概述
x32 SRAM Module
X32 SRAM模块\n
PUMA68S4000/M-025 数据手册
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PDF下载128K x 32 SRAM MODULE
PUMA 68S4000/A - 020/025/35/45
11403 West Bernado Court, Suite 100, San Diego, CA 92127.
Tel No: (001) 858 674 2233, Fax No: (001) 858 674 2230
Issue 4.4 : December 1999
Description
Features
•
Fast Access Times of 20 ,25, 35 and 45 ns.
JEDEC 68 'J' leaded plastic surface mount Substrate
Industrial or Military Grade.
The PUMA68S4000/A is a 4Mbit CMOS High
Speed Static RAM organised as 128K x 32 in a
JEDEC 68 pin surface mount PLCC, available with
access times of 20, 25, 35, and 45ns. The output
width is user configurable as 8 , 16 or 32 bits using
four Chip Selects (CS1~4).
•
•
•
•
•
Upgradeable footprint.
User Configurable as 8 / 16 / 32 bit wide output.
The device features multiple ground pins for
maximum noise immunity and TTL compatible
inputsandoutputs. ThePUMA68S4000/Aoffersa
dramatic space saving advantage over four
standard 128Kx8 devices.
Operating Power
Low Power Standby
-L Version
(32-BIT)
(TTL)
(CMOS)
4.00 W (Max)
1.43 W (Max)
44 mW (Max)
•
•
•
Fully Static operation.
Multiple ground pins for maximum noise immunity.
Single 5V±10% Power supply.
Block Diagram
Pin Definition
(PUMA 68 S4000A page 2)
(PUMA 68 S4000A page 2)
A0-A16
OE
WE
9
8
7
6
5
4
3
2
1 68 67 66 65 64 63 62 61
D16
D17
D18
D19
D20
D21
D22
D23
GND
D24
D25
D26
D27
D28
D29
D30
D31
D0
D1
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
60
59
58
57
56
55
54
53
52
51
50
49
48
47
46
45
44
128Kx8
SRAM
128Kx8
SRAM
128Kx8
SRAM
128Kx8
SRAM
D2
D3
D4
CS1
CS2
D5
PUMA 68S4000
D6
CS3
CS4
D0-7
D8-15
D16-23
D24-31
D7
VIEW
FROM
ABOVE
GND
D8
D9
D10
D11
D12
D13
D14
D15
27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43
Pin Functions
Address Inputs
A0 - A16
D0 - D31
CS1~4
WE1~4
OE
Data Input/Output
Chip Select
Write Enable
Output Enable
No Connect
Power (+5V)
Ground
Package Details
Plastic 68 J-Leaded JEDEC PLCC
NC
VCC
GND
PUMA 68S4000/A - 020/025/35/45
ISSUE 4.4 : December 1999
PUMA 68 S4000A Pinout and Block Diagram.
A0 ~A16
/OE
/WE4
/WE3
/WE2
/WE1
128K x 8
SRAM
128K x 8
SRAM
128K x 8
SRAM
128K x 8
SRAM
/CS1
/CS2
/CS3
/CS4
D0~7
D8~15
D16~23
D24~31
9
8
7
6
5
4
3
2
1 68 67 66 65 64 63 62 61
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
60
59
58
57
56
55
54
53
52
51
50
49
48
47
46
45
44
D16
D17
D18
D19
D20
D21
D22
D23
GND
D24
D25
D26
D27
D28
D29
D30
D31
D0
D1
D2
D3
D4
D5
D6
D7
PUMA 68S4000A
VIEW
FROM
ABOVE
GND
D8
D9
D10
D11
D12
D13
D14
D15
27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43
2
PUMA 68S4000/A - 020/025/35/45
ISSUE 4.4 : December 1999
DC OPERATING CONDITIONS
Absolute Maximum Ratings (1)
Parameter
Symbol
Min
Typ
Max
Unit
(2)
Voltage on any pin relative to VSS
Power Dissipation
VT
-0.5
-
-
-
-
7.0
4.0
150
V
PT
W
oC
Storage Temperature
TSTG
-65
Notes : (1) Stresses above those listed may cause permanent damage to the device. This is a stress rating only
and functional operation of the device at those or any other conditions above those indicated in the
operational sections of this specification is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect device reliability.
(2) VT can be -3.0V pulse of less than 10ns.
Recommended Operating Conditions
Parameter
Symbol
Min
Typ
Max
Unit
Supply Voltage
VCC
VIH
VIL
TA
4.5
2.2
-0.3
0
5.0
5.5
VCC+0.3
0.8
V
V
Input High Voltage
Input Low Voltage
Operating Temperature (Commercial)
(Industrial)
-
-
-
-
-
V
oC
70
TAI
TAM
-40
-55
85
oC (Suffix I)
oC (Suffix M)
(Military)
125
DC Electrical Characteristics (VCC=5V±10%, TA = -55oC to +125oC)
Parameter
Symbol Test Condition
Min Typ max Unit
Input Leakage Current
Output Leakage Current
ILI1
ILO
VIN=0V to VCC
VI/O=0V to VCC
-20
-40
-
-
20
40
µA
µA
Operating Supply Current(2) 32 bit ICC32 CS(1)=VIL, II/O=0mA, f=fmax
16 bit ICC16 As above.
-
-
-
-
-
-
840
540
400
mA
mA
mA
8 bit ICC8
As above.
Standby Supply Current
(TTL) ISB
CS(1)=VIH, f=fmax, VIN=VILor VIH
-
-
-
-
260
8
mA
mA
-L Version (CMOS) ISB1
CS≥VCC-0.2V, 0.2V≥VIN≥VCC-0.2V,f=0
IOL = 8.0mA,VCC=Min
IOH = -4.0mA,VCC=Min
Output Voltage Low
Output Voltage High
VOL
VOH
-
-
-
0.4
-
V
V
2.4
Notes: (1) CS1~4 inputs operate simultaneously for 32 bit mode, in pairs for 16 bit mode and singly for 8 bit
mode.
(2) At f=fmax address and data inputs are cycling at max frequency.
3
PUMA 68S4000/A - 020/025/35/45
ISSUE 4.4 : December 1999
Capacitance (VCC=5V±10%,TA=25oC)
Note: Capacitance calculated, not measured.
Parameter
Symbol
Test Condition
min
typ
max
Unit
Input Capacitance Address,OE,WE
CIN1
CI/O
VIN =0V
VI/O=0V
-
-
-
-
34
42
pF
pF
Output Capacitance 8-bit mode (worst case)
AC Test Conditions
Output Load
166Ω
I/O Pin
* Input pulse levels: 0V to 3.0V
* Input rise and fall times: 3ns
1.76V
* Input and Output timing reference levels: 1.5V
* Output load: see diagram
30pF
* VCC=5V±10%
Operation Truth Table
CS1 CS2 CS3 CS4 OE WE SUPPLY CURRENT
MODE
L
H
H
H
L
H
L
L
H
H
H
L
H
L
H
L
H
H
L
H
L
H
L
H
H
L
H
L
H
H
L
H
H
L
H
H
H
L
H
L
X
X
X
X
X
X
X
L
L
L
L
L
L
L
L
L
L
ICC8
ICC8
Write D0~7
Write D8~15
Write D16~23
Write D24~31
Write D0~15
Write D16~31
Write D0~31
Read D0~7
Read D8~15
Read D16~23
Read D24~31
Read D0~15
Read D16~31
Read D0~31
D0~31 High-Z
D0~31 Standby
ICC8
ICC8
ICC16
L
L
ICC16
L
L
ICC32
H
H
L
H
H
L
L
X
H
H
H
H
L
H
L
L
X
H
H
H
H
H
H
H
H
H
X
ICC8
ICC8
ICC8
ICC8
ICC16
L
L
H
X
ICC16
ICC32
X
H
X
H
ICC32/ICC16/ICC8
ISB,ISB1
Notes : H = VIH : L =VIL : X = VIH or VIL
Low Vcc Data Retention Characteristics - L version only
Parameter
Symbol
VDR
ICCDR1
tCDR
tR
Test Condition
min
typ
max
Unit
VCC for Data Retention
Data Retention Current
Data Retention Time
CS=VCC-0.2V
2.0
-
-
-
-
-
-
2.2
-
V
(1)
VCC = 2.0V, CS > VCC-0.2V, VIN >0V
See Retention Waveform
See Retention Waveform
mA
ns
ns
0
tRC
Operation Recovery Time
-
4
PUMA 68S4000/A - 020/025/35/45
ISSUE 4.4 : December 1999
AC OPERATING CONDITIONS
Read Cycle
-020
-025
-35
-45
Parameter
Symbol min max min max min max min max Unit
Read Cycle Time
tRC
20
-
-
20
20
10
-
25
-
-
35
-
-
45
-
-
ns
ns
ns
ns
ns
ns
ns
ns
ns
Address Access Time
tAA
25
25
12
-
35
35
15
-
45
45
17
-
Chip Select Access Time
tACS
tOE
-
-
-
-
Output Enable to Output Valid
Output Hold from Address Change
Chip Selection to Output in Low Z
Output Enable to Output in Low Z
Chip Deselection to O/P in High Z
Output Disable to Output in High Z
-
-
-
-
tOH
3
3
0
0
0
3
3
0
0
0
3
3
0
0
0
3
3
0
0
0
tCLZ
tOLZ
tCHZ
tOHZ
-
-
-
-
-
-
-
-
9
10
10
12
12
15
15
8
Write Cycle
-020
-025
-35
-45
Parameter
Symbol min max min max min max min max Unit
Write Cycle Time
tWC
tCW
tAW
tAS
20
15
15
0
-
-
25
20
20
0
-
-
35
25
25
0
-
-
45
35
35
0
-
-
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Chip Selection to End of Write
Address Valid to End of Write
Address Setup Time
-
-
-
-
-
-
-
-
Write Pulse Width
tWP
tWR
tWHZ
tDW
tDH
12
0
-
15
0
-
17
0
-
20
0
-
Write Recovery Time
-
-
-
-
Write to Output in High Z
Data to Write Time Overlap
Data Hold from Write Time
Output active from end of write
0
10
-
0
12
-
0
15
-
0
15
-
10
0
12
0
15
0
15
0
-
-
-
-
tOW
3
-
3
-
3
-
3
-
5
PUMA 68S4000/A - 020/025/35/45
ISSUE 4.4 : December 1999
Read Cycle Timing Waveform(1,2)
t RC
Address
OE
tAA
tOE
tOLZ
tOH
CS1~4
Dout
Don't
care.
tACS
tCLZ (4,5)
tOHZ (3)
Data Valid
tCHZ (3,4,5)
AC Read Characteristics Notes
(1) WE is High for Read Cycle.
(2) All read cycle timing is referenced from the last valid address to the first transition address.
(3) tCHZ and tOHZ are defined as the time at which the outputs achieve open circuit conditions and are not
referenced to output voltage levels.
(4) At any given temperature and voltage condition, tCHZ (max) is less than tCLZ (min) both for a given module
and from module to module.
(5) These parameters are sampled and not 100% tested.
Write Cycle No.1 Timing Waveform(1,4)
tWC
Address
tWR(7)
tAS(6)
OE
tAW
tCW
CS1~4
Don't
Care
WE
tOHZ(3,9)
tOW
tWP(2)
(8)
High-Z
Dout
Din
tDW
Data Valid
tDH
High-Z
6
PUMA 68S4000/A - 020/025/35/45
ISSUE 4.4 : December 1999
Write Cycle No.2 Timing Waveform (1,5)
tWC
Address
tAS(6)
tWR(7)
tCW
CS1~4
tAW
tWP(2)
WE
tOH
Don't
Care
tWHZ(3,9)
tOW
(4)
(8)
High-Z
tDW
Data Valid
Dout
tDH
High-Z
Din
AC Write Characteristics Notes
(1) All write cycle timing is referenced from the last valid address to the first transition address.
(2) All writes occur during the overlap of CS1~4 and WE low.
(3) If OE, CS1~4, and WE are in the Read mode during this period, the I/O pins are low impedance state.
Inputs of opposite phase to the output must not be applied because bus contention can occur.
(4) Dout is the Read data of the new address.
(5) OE is continuously low.
(6) Address is valid prior to or coincident with CS1~4 and WE low, too avoid inadvertant writes.
(7) CS1~4 or WE must be high during address transitions.
(8) When CS1~4 are low : I/O pins are in the output state. Input signals of opposite phase leading to the
output should not be applied.
(9) Defined as the time at which the outputs achieve open circuit conditions and are not referenced to
output voltage levels. These parameters are sampled and not 100% tested.
Data Retetnion Waveform
DATA RETENTION MODE
Vcc
4.5V
4.5V
2.2V
tCDR
tR
2.2V
VDR
CS1~4 > Vcc -0.2V
CS1~4
0V
7
PUMA 68S4000/A - 020/025/35/45
ISSUE 4.4 : December 1999
Package Information
Dimensions in mm(inches)
Plastic 68 Pin JEDEC Surface mount PLCC
25.27 (0.995) sq.
25.02 (0.985) sq.
5.08
(0.200) max
0.10 (0.004)
1.27
(0.050) typ.
0.46
(0.018) typ.
0.90 (0.035) typ.
Ordering Information
PUMA 68S4000/AM - 020
Speed
020
025
35
=
=
=
=
20ns
25ns
35ns
45ns
45
Temperature range
Blank
=
=
=
Commercial Temperature
Industrial Temperature
Military Temperature
I
M
/WE Option
Blank
A
=
=
Single/WE
/WE1~4
Memory Organisation
S4000
=
128K x 32 SRAM
configurable as 256K x 16
and 512K x 8
Package
PUMA 68
=
68 pin "J" Leaded PLCC
Note :
Although this data is believed to be accurate the information contained herein is not intended to and does not create any
warranty of merchantibility or fitness for aparticular purpose.
Our products are subject to a constant process of development. Data may be changed without notice.
Products are not authorised for use as critical components in life support devices without the express written approval
of a company director.
8
PUMA 68S4000/A - 020/025/35/45
ISSUE 4.4 : December 1999
Co Planarity
Specified as +/- 2 thou max.
Visual Inspection Standard
All devices inspected to ANSI/J-STD-001B Class 2 standard
Moisture Sensitivity
Devices are moisture sensitive.
Shelf Life in Sealed Bag 12 months at <40OC and <90% relative humidity (RH).
After this bag has been opened, devices that will be subjected to infrared reflow, vapour phase reflow, or
equivalent processing (peak package body temp 220OC) must be :
A : Mounted within 72 Hours at factory conditions of <30OC/60% RH
OR
B : Stored at <20% RH
Iftheseconditionsarenotmetorindicatorcardis>20%whenreadat23OC +/-5% devicesrequirebaking
as specified below.
If baking is required, devices may be baked for :-
A : 24 hours at 125OC +/-5% for high temperature device containers
OR
B : 192 hours at 40OC +5OC/-0OC and <5% RH for low temperature device containers.
Packaging Standard
Devices packaged in dry nitrogen, JED-STD-020.
Packaged in trays as standard.
Tape and reel available for shipment quantities exceeding 200pcs upon request.
Soldering Recomendations
IR/Convection - Ramp Rate
Temp. exceeding 183OC 150 secs. max.
Peak Temperature
225OC
Time within 5OC of peak 20 secs max.
6OC/sec max.
Ramp down
6OC/sec max.
Vapour Phase - Ramp up rate
6OC/sec max.
215 - 219OC
Peak Temperature
Time within 5OC of peak 60 secs max.
Ramp down
6OC/sec max.
The above conditions must not be exceeded.
Note : The above recommendations are based on standard industry practice. Failure to comply with
theaboverecommendationsinvalidatesproductwarranty.
9
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