Pm25LD512-SCE [ETC]
512Kbit/1 Mbit / 2 Mbit Single Operating Voltage Serial Flash Memory With 100 MHz Dual-Output SPI Bus;
| 型号： | Pm25LD512-SCE |
| 厂家： | 
ETC |
| 描述： | 512Kbit/1 Mbit / 2 Mbit Single Operating Voltage Serial Flash Memory With 100 MHz Dual-Output SPI Bus |
| 文件： | 总33页 (文件大小：652K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
512Kbit/1 Mbit / 2 Mbit Single Operating Voltage Serial
Flash Memory With 100 MHz Dual-Output SPI Bus
Pm25LD512/010/ 020
FEATURES
• Low Power Consumption
- Typical 10 mA active read current
- Typical 15 mA program/erase current
• Single Power Supply Operation
- Low voltage range: 2.3 V – 3.6 V
• Memory Organization
• Hardware Write Protection
- Protect and unprotect the device from write
operation by Write Protect (WP#) Pin
- Pm25LD512: 64K x 8 (512 Kbit)
- Pm25LD010: 128K x 8 (1 Mbit)
- Pm25LD020: 256K x 8 (2 Mbit)
• Software Write Protection
• Cost Effective Sector/Block Architecture
- 512Kb : Uniform 4KByte sectors / Two uniform
32KByte blocks
- 1Mb : Uniform 4KByte sectors / Four uniform
32KByte blocks
- The Block Protect (BP2, BP1, BP0) bits allow
partial or entire memory to be configured as read-
only
• High Product Endurance
- Guaranteed 200,000 program/erase cycles per
single sector
- 2Mb : Uniform 4KByte sectors / Four uniform
64KByte blocks
- Minimum 20 years data retention
• Low standby current 1uA (Typ)
• Serial Peripheral Interface (SPI) Compatible
- Supports single- or dual-output
- Supports SPI Modes 0 and 3
- Maximum 33 MHz clock rate for normal read
- Maximum 100 MHz clock rate for fast read
• Industrial Standard Pin-out and Package
- 8-pin 150mil SOIC
- 8-pin 208mil SOIC for Pm25LD040
- 8-pin 300mil PDIP for Pm25LD040
- 8-contact WSON
- 8-pin TSSOP
- Lead-free (Pb-free), halogen-free package
• Page Program (up to 256 Bytes) Operation
- Typical 2 ms per page program
• Sector, Block or Chip Erase Operation
- Maximum 10 ms sector, block or chip erase
GENERAL DESCRIPTION
The Pm25LD512/010/020 are 512Kbit/ 1Mbit / 2Mbit Serial Peripheral Interface (SPI) Flash memories, providing
single- or dual-output. The devices are designed to support a 33 MHz clock rate in normal read mode, and 100
MHz in fast read, the fastest in the industry. The devices use a single low voltage power supply, wide operating
voltage ranging from 2.3 Volt to 3.6 Volt, to perform read, erase and program operations. The devices can be
programmed in standard EPROM programmers.
The Pm25LD512/010/020 are accessed through a 4-wire SPI Interface consisting of Serial Data Input/Output
(SlO), Serial Data Output (SO), Serial Clock (SCK), and Chip Enable (CE#) pins. They comply with all
recognized command codes and operations. The dual-output fast read operation provides and effective serial
data rate of 200MHz.
The devices support page program mode, where 1 to 256 bytes data can be programmed into the memory in
one program operation. These devices are divided into uniform 4 KByte sectors or uniform 32 KByte
blocks.(Pm25LD020 is uniform 4 KByte sectors or uniform 64 KByte).
The Pm25LD512/010/020 are manufactured on pFLASH™’s advanced non-volatile technology. The devices are
offered in 8-pin SOIC 150mil, 8-contact WSON and 8-pin TSSOP. The devices operate at wide temperatures
between -40°C to +105°C.
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DRAFT Date: August, 2010, Rev:0.4
Pm25LD512/010/ 020
PRODUCT ORDERING INFORMATION
Pm25LDxxx - S C E
Environmental Attribute
E = Lead-free (Pb-free) and Halogen- free
package
Temperature Range
C = Commercial Grade (-40°C to +105°C)
Package Type
S = 8-pin SOIC 150mil (8S)
B = 8-pin SOIC 208mil (8B)
P = 8-pin PDIP 300 mil (8P)
K = 8-contact WSON (8K)
pFlash Device Number
Pm25LD512/010/020
Part Number
Operating Frequency (MHz) Package
Temperature Range
Pm25LD512-SCE
8S
100
100
Pm25LD010-SCE
Pm25LD020-SCE
Pm25LD512-KCE
150mil SOIC
8K WSON
(Back Side
Metal)
Pm25LD010-KCE
Pm25LD020-KCE
Pm25LD040-PCE
Pm25LD040-BCE
Pm25LD512-DCE
Pm25LD010-DCE
Pm25LD020-DCE
Commercial Grade
(-40oC to +105oC)
8P 300mil PDIP
100
100
8B 208mil SOIC
8-pin TSSOP
100
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DRAFT Date: August, 2010, Rev:0.4
Pm25LD512/010/ 020
CONNECTION DIAGRAMS
CE#
SO
1
2
8
7
Vcc
8 Vcc
CE#
SO
1
2
7
HOLD#
6 SCK
SIO
HOLD#
3
4
WP#
GND
WP#
GND
3
4
6
5
SCK
SIO
5
8-Contact WSON
8-Pin SOIC
1
2
3
4
8
7
6
5
Vcc
CE#
SO
HOLD#
Vcc
CE#
SO
1
2
3
8
7
WP#
GND
SCK
SIO
HOLD#
SCK
WP#
GND
6
5
8-Pin TSSOP
4
SIO
8-Pin PDIP
PIN DESCRIPTIONS
SYMBOL TYPE
DESCRIPTION
CE#
INPUT
Chip Enable: CE# low activates the devices internal circuitries for
device operation. CE# high deselects the devices and switches into
standby mode to reduce the power consumption. When a device is not
selected, data will not be accepted via the serial input pin (SlO), and the
serial output pin (SO) will remain in a high impedance state.
Serial Data Clock
SCK
SIO
SO
INPUT
INPUT/OUTPUT Serial Data Input/Output
OUTPUT
Serial Data Output
GND
Vcc
Ground
Device Power Supply
WP#
INPUT
Write Protect: A hardware program/erase protection for all or part of a
memory array. When the WP# pin is low, memory array write-protection depends
on the setting of BP2, BP1 and BP0 bits in the Status Register. When the WP# is
high, the devices are not write-protected.
HOLD#
INPUT
Hold: Pause serial communication by the master device without resetting
the serial sequence.
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DRAFT Date: August, 2010, Rev:0.4
Pm25LD512/010/ 020
BLOCK DIAGRAM
SIO
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DRAFT Date: August, 2010, Rev:0.4
Pm25LD512/010/ 020
SPI MODES DESCRIPTION
Multiple Pm25LD512/010/020 devices can be
connected on the SPI serial bus and controlled by a
The difference between these two modes is the clock
polarity when the SPI master is in Stand-by mode: the
SPI Master, i.e. microcontroller, as shown in Figure 1. serial clock remains at “0” (SCK = 0) for Mode 0 and
The devices support either of two SPI modes:
Mode 0 (0, 0)
the clock remains at “1” (SCK = 1) for Mode 3. Please
refer to Figure 2. For both modes, the input data is
latched on the rising edge of Serial Clock (SCK), and
the output data is available from the falling edge of
SCK.
Mode 3 (1, 1)
Figure 1. Connection Diagram among SPI Master and SPI Slaves (Memory Devices)
SDIO
SPI Interface with
(0,0) or (1,1)
SDI
SCK
SCK
CE#
SO SIO
SCK
SO
SCK
CE#
SIO
SO SIO
SPI Master
(i.e. Microcontroller)
SPI Memory
Device
SPI Memory
Device
SPI Memory
Devic
e
CS3
CS2
CS1
WP#
CE# WP#
WP#
HOLD#
HOLD#
HOLD#
Note: 1. The Write Protect (WP#) and Hold (HOLD#) signals should be driven high or low as
Figure 2. SPI Modes Supported
SCK
Mode 0 (0, 0)
SCK
Mode 3 (1, 1)
SIO
Input mode
MSb
SO
MSb
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DRAFT Date: August, 2010, Rev:0.4
Pm25LD512/010/ 020
SYSTEM CONFIGURATION
The Pm25LD512/010/020 devices are designed to interface directly with the synchronous Serial Peripheral
Interface (SPI) of the Motorola MC68HCxx series of microcontrollers or any SPI interface-equipped system
controllers. The devices have two superset features that can be enabled through specific software instructions
and the Configuration Register:
Block Size
(Kbytes)
Sector Size
(Kbytes)
Memory Density
Block No.
Sector No.
Address Range
Sector 0(1)
000000h - 000FFFh
001000h - 001FFFh
:
4
4
:
Sector 1
Block 0
32
32
:
Sector 7
007000h - 007FFFh
008000h - 008FFFh
009000h - 009FFFh
000000h - 006FFFh
00F000h - 00FFFFh
010000h - 017FFFh
018000h - 01FFFFh
4
4
512 Kbit
1 Mbit
Sector 8
Sector 9
4
Block 1
:
:
Sector 15
4
"
"
Block 2
Block 3
32
32
"
"
Block
Size
Sector
Size
Memory Density
Block No.
Sector No.
Address Range
(KBytes)
(KBytes)
Sector 0
Sector 1
4
4
:
000000h - 000FFFh
001000h - 001FFFh
:
Block 0
Block 1
64
64
:
Sector 15
Sector 16
Sector 17
4
4
4
:
00F000h - 00FFFFh
010000h - 010FFFh
011000h - 011FFFh
:
2 Mbit
:
Sector 31
4
:
4
01F000h - 01FFFFh
:
030000h – 03FFFFh
:
:
:
:
Block 3
64
Table 1-1. Block/Sector Addresses of Pm25LD512/010/020
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Pm25LD512/010/ 020
REGISTERS (CONTINUED)
STATUS REGISTER
Refer to Tables 5 and 6 for Status Register Format and are allowed. The WEL bit is set by a Write Enable
Status Register Bit Definitions.
(WREN) instruction. Each write register, program and
erase instruction must be preceded by a WREN
instruction. The WEL bit can be reset by a Write
Disable (WRDI) instruction. It will automatically be the
The BP0, BP1, BP2, and SRWD are volatile memory
cells that can be written by a Write Status Register
(WRSR) instruction. The default value of the BP2, BP1, reset after the completion of a write instruction.
BP0 were set to “0” and SRWD bits was set to “0” at
BP2, BP1, BP0 bits: The Block Protection (BP2, BP1,
changed by device power-up or power-down, and can BP0) bits are used to define the portion of the memory
factory. Once a “0” or “1”is written, it will not be
only be altered by the next WRSR instruction. The
Status Register can be read by the Read Status
area to be protected. Refer to Tables 7, 8 and 9 for the
Block Write Protection bit settings. When a defined
Register (RDSR). Refer to Table 10 for Instruction Set. combination of BP2, BP1 and BP0 bits are set, the
corresponding memory area is protected. Any program
The function of Status Register bits are described as
follows:
or erase operation to that area will be inhibited. Note:
a Chip Erase (CHIP_ER) instruction is executed
successfully only if all the Block Protection Bits are set
as “0”s.
WIP bit: The Write In Progress (WIP) bit is read-only,
and can be used to detect the progress or completion
of a program or erase operation. When the WIP bit is
“0”, the device is ready for a write status register,
program or erase operation. When the WIP bit is “1”,
the device is busy.
SRWD bit: The Status Register Write Disable (SRWD)
bit operates in conjunction with the Write Protection
(WP#) signal to provide a Hardware Protection Mode.
When the SRWD is set to “0”, the Status Register is
not write-protected. When the SRWD is set to “1” and
the WP# is pulled low (VIL), the volatile bits of Status
Register (SRWD, BP2, BP1, BP0) become read-only,
and a WRSR instruction will be ignored. If the SRWD is
set to “1” and WP# is pulled high (VIH), the Status
WEL bit: The Write Enable Latch (WEL) bit indicates
the status of the internal write enable latch. When the
WEL is “0”, the write enable latch is disabled, and all
write operations, including write status register, page
program, sector erase, block and chip erase operations Register can be changed by a WRSR instruction.
are inhibited. When the WEL bit is “1”, write operations
Table 5. Status Register Format
Bit 7
SRWD1
0
Bit 6
Bit 5
Bit 4
BP2
0
Bit 3
BP1
0
Bit 2
BP0
0
Bit 1
WEL
0
Bit 0
WIP
0
Reserved
Default (flash bit)
0
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DRAFT Date: August, 2010, Rev:0.4
Pm25LD512/010/ 020
REGISTERS (CONTINUED)
Table 6. Status Register Bit Definition
Read- Non-Volatile
Bit
Name
Definition
/Write
bit
Write In Progress Bit:
Bit 0
WIP
"0" indicates the device is ready
R
No
"1" indicates a write cycle is in progress and the device is busy
Write Enable Latch:
Bit 1
WEL
"0" indicates the device is not write enabled
"1" indicates the device is write enabled (default)
Block Protection Bit: (See Table 7 and Table 8 for details)
"0" indicates the specific blocks are not write-protected (default) R/W
"1" indicates the specific blocks are write-protected
R/W
No
Bit 2
Bit 3
Bit 4
BP0
BP1
BP2
N/A
Yes
Bits 5 - 6
Reserved: Always "0"s
N/A
Status Register Write Disable: (See Table 9 for details)
Bit 7
SRWD "0" indicates the Status Register is not write-protected (default)
"1" indicates the Status Register is write-protected
R/W
Yes
Table 8. Block Write Protect Bits for Pm25LD512/010/020
Status Register Bits Protected Memory Area
BP1
BP0
Pm25LD512A
Pm25LD010A
Pm25LD020
0
0
None
None
None
Upper quarter (Block 3) Upper quarter (Block 3)
018000h - 01FFFFh 030000h - 03FFFFh
Upper half (Block 2 & 3) Upper half (Block 2 & 3)
0
1
1
1
0
1
None
None
010000h - 01FFFFh
All Blocks
020000h - 03FFFFh
All Blocks
All Blocks
000000h - 00FFFFh
000000h - 01FFFFh
000000h - 03FFFFh
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DRAFT Date: August, 2010, Rev:0.4
Pm25LD512/010/ 020
REGISTERS (CONTINUED)
PROTECTION MODE
Table 9. Hardware Write Protection on Status
Register
The Pm25LD512/010/020 have two types of write-
protection mechanisms: hardware and software.
These are used to prevent irrelevant operation in a
possibly noisy environment and protect the data
integrity.
SRWD
WP#
Low
Low
High
High
Status Register
Writable
0
1
0
1
Protected
Writable
HARDWARE WRITE-PROTECTION
The devices provide two hardware write-protection
features:
Writable
a. When inputting a program, erase or write status
register instruction, the number of clock pulse is
checked to determine whether it is a multiple of eight
before the executing. Any incomplete instruction
command sequence will be ignored.
b. The Write Protection (WP#) pin provides a
hardware write protection method for BP2, BP1, BP0
and SRWD in the Status Register. Refer to the
STATUS REGISTER description.
c. Write inhibit is 1.8V, all write sequence will be
ignored when Vcc drop to 1.8V and lower
SOFTWARE WRITE PROTECTION
The Pm25LD512/010/020 also provides two software
write protection features:
a. Before the execution of any program, erase or write
status register instruction, the Write Enable Latch
(WEL) bit must be enabled by executing a Write
Enable (WREN) instruction. If the WEL bit is not
enabled first, the program, erase or write register
instruction will be ignored.
b. The Block Protection (BP2, BP1, BP0) bits allow part
or the whole memory area to be write-protected.
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Pm25LD512/010/ 020
DEVICE OPERATION
The Pm25LD512/010/020 utilize an 8-bit instruction
instruction code and is followed by address bytes, data
register. Refer to Table 10 Instruction Set for details of bytes, or both address bytes and data bytes,
the Instructions and Instruction Codes. All instructions, depending on the type of instruction. CE# must be
addresses, and data are shifted in with the most
driven high (VIH) after the last bit of the instruction
significant bit (MSB) first on Serial Data Input (SI). The sequence has been shifted in.
input data on SI is latched on the rising edge of Serial
Clock (SCK) after Chip Enable (CE#) is driven low (VIL). The timing for each instruction is illustrated in the
Every instruction sequence starts with a one-byte
following operational descriptions.
Table 10. Instruction Set
Instruction Name
Hex
Operation
Command Maximum
Code
Cycle
4 Bytes
1 Byte
Frequency
100 MHz
100 MHz
RDID
JEDEC ID READ
ABh Read Manufacturer and Product ID
9Fh Read Manufacturer and Product ID by JEDEC ID
Command
RDMDID
WREN
WRDI
RDSR
WRSR
90h
06h
04h
05h
01h
03h
Read Manufacturer and Device ID
Write Enable
Write Disable
Read Status Register
Write Status Register
Read Data Bytes from Memory at Normal Read Mode 4 Bytes
4 Bytes
1 Byte
1 Byte
1 Byte
2 Bytes
100 MHz
100 MHz
100 MHz
100 MHz
100 MHz
33 MHz
READ
FAST_READ
FRDO
0Bh Read Data Bytes from Memory at Fast Read Mode
3Bh Fast Read Dual Output
5 Bytes
5 Bytes
100 MHz
100 MHz
PAGE_ PROG
02h
Page Program Data Bytes Into Memory
4 Bytes + 50 MHz
256B
SECTOR_ER
D7h/ Sector Erase
20h
4 Bytes
100 MHz
BLOCK_ER
CHIP_ER
D8h Block Erase
C7h/ Chip Erase
60h
4 Bytes
1 Byte
100 MHz
100 MHz
HOLD OPERATION
HOLD# is used in conjunction with CE# to select
the Pm25LD512/010/020. When the devices are
selected and a serial sequence is underway,
HOLD# can be used to pause the serial
communication with the master device without
resetting the serial sequence. To pause, HOLD# is
brought low while the SCK signal is low. To resume
serial communication, HOLD# is brought high while
the SCK signal is low (SCK may still toggle during
HOLD). Inputs to SlO will be ignored while SO is in
the high impedance state.
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DRAFT Date: August, 2010, Rev:0.4
Pm25LD512/010/ 020
DEVICE OPERATION (CONTINUED)
RDID COMMAND (READ PRODUCT
IDENTIFICATION) OPERATION
The Read Product Identification (RDID) instruction is
for reading out the old style of 8-bit Electronic
Signature, whose values are shown as table of ID
Definitions. This is not same as RDID or JEDEC ID
instruction. It’s not recommended to use for new
design. For new design, please use RDID or JEDEC ID
instruction.
The RDES instruction code is followed by three dummy
bytes, each bit being latched-in on SI during the rising
edge of SCK. Then the Device ID is shifted out on SO
with the MSB first, each bit been shifted out during the
falling edge of SCK. The RDES instruction is ended by
CE# goes high. The Device ID outputs repeatedly if
continuously send the additional clock cycles on SCK
while CE# is at low.
Table 11. Product Identification
Product Identification
Data
First Byte
9Dh
7Fh
Manufacturer ID
Second Byte
Device ID 1
05h
Device ID:
Device ID 2
20h
Pm25LD512
Pm25LD010
Pm25LD020
10h
21h
11h
22h
Figure 3. Read Product Identification Sequence
CE#
0
1
7
8
9
38 39
46 47
54
31
SCK
SI
INSTRUCTION
1010 1011b
3 Dummy Bytes
HIGH IMPEDANCE
SO
Device ID1
Device ID1
Device ID1
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DRAFT Date: August, 2010, Rev:0.4
Pm25LD512/010/ 020
DEVICE OPERATION (CONTINUED)
JEDEC ID READ COMMAND (READ PRODUCT IDENTIFICATION BY JEDEC ID)
OPERATION
The JEDEC ID READ instruction allows the user to
by the first Manufacturer ID (9Dh) and the Device ID
read the manufacturer and product ID of devices. Refer (22h, in the case of the Pm25LD020), each bit shifted
to Table 11 Product Identification for pFlash
Manufacturer ID and Device ID. After the JEDEC ID
out during the falling edge of SCK. If CE# stays low
after the last bit of the Device ID is shifted out, the
READ command is input, the second Manufacturer ID Manufacturer ID and Device ID will loop until CE# is
(7Fh) is shifted out on SO with the MSB first, followed pulled high.
Figure 4. Read Product Identification by JEDEC ID READ Sequence
CE#
0
15 16
7
8
23 24
31
SCK
SI
INSTRUCTION
1001 1111b
HIGH IMPEDANCE
SO
Manufacture ID2
Manufacture ID1
Device ID2
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Pm25LD512/010/ 020
DEVICE OPERATION (CONTINUED)
RDMDID COMMAND (READ DEVICE MANUFACTURER AND DEVICE ID)
OPERATION
The RDMDID instruction allows the user to read the
the Device ID (22h, in the case of the Pm25LD020),
manufacturer and product ID of devices. Refer to Table and is shifted out on SO with the MSB first, each bit
11 Product Identification for pFlash Manufacturer ID
and Device ID. The RDMDID command is input,
followed by a 24-bit address pointing to an ID table.
shifted out during the falling edge of SCK. If CE# stays
low after the last bit of the Device ID is shifted out, the
Manufacturer ID and Device ID will loop until CE# is
The table contains the first Manufacturer ID (9Dh) and pulled high.
Figure 5. Read Product Identification by RDMDID READ Sequence
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DRAFT Date: August, 2010, Rev:0.4
Pm25LD512/010/ 020
Note :
(1) ADDRESS A0 = 0, will output the 1st manufacture ID (9Dh) first -> device ID1 -> 2nd manufacture ID (7Fh)
ADDRESS A0 = 1, will output the device ID1 -> 1st manufacture ID (9D) -> 2nd manufacture ID (7Fh)
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DRAFT Date: August, 2010, Rev:0.4
Pm25LD512/010/ 020
DEVICE OPERATION (CONTINUED)
WRITE ENABLE OPERATION
The Write Enable (WREN) instruction is used to set the block erase, chip erase, page program and write status
Write Enable Latch (WEL) bit. The WEL bit of the
Pm25LD512/010/020 is reset to the write –protected
state after power-up. The WEL bit must be write
enabled before any write operation, including sector,
register operations. The WEL bit will be reset to the
write-protect state automatically upon completion of a
write operation. The WREN instruction is required
before any above operation is executed.
Figure 6. Write Enable Sequence
SIO
WRDI COMMAND (WRITE DISABLE) OPERATION
The Write Disable (WRDI) instruction resets the WEL
bit and disables all write instructions. The WRDI
instruction is not required after the execution of a write
instruction, since the WEL bit is automatically reset.
Figure 7. Write Disable Sequence
SIO
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DRAFT Date: August, 2010, Rev:0.4
Pm25LD512/010/ 020
DEVICE OPERATION (CONTINUED)
RDSR COMMAND (READ STATUS REGISTER) OPERATION
The Read Status Register (RDSR) instruction provides instruction, which can be used to check the progress or
access to the Status Register. During the execution of completion of an operation by reading the WIP bit of
a program, erase or write status register operation, all Status Register.
other instructions will be ignored except the RDSR
Figure 8. Read Status Register Sequence
SIO
WRSR COMMAND (WRITE STATUS REGISTER) OPERATION
The Write Status Register (WRSR) instruction allows
the user to enable or disable the block protection and
status register write protection features by writing “0”s
or “1” s into the volatile BP2, BP1, BP0 and SRWD
bits.
Figure 9. Write Status Register Sequence
SIO
DEVICE OPERATION (CONTINUED)
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DRAFT Date: August, 2010, Rev:0.4
Pm25LD512/010/ 020
READ COMMAND (READ DATA) OPERATION
The Read Data (READ) instruction is used to read
memory data of a Pm25LD512/010/020 under normal
mode running up to 33 MHz.
The first byte data (D7 - D0) addressed is then shifted
out on the SO line, MSb first. A single byte of data, or
up to the whole memory array, can be read out in one
READ instruction. The address is automatically
The READ instruction code is transmitted via the SlO
line, followed by three address bytes (A23 - A0) of the incremented after each byte of data is shifted out. The
first memory location to be read. A total of 24 address read operation can be terminated at any time by driving
bits are shifted in, but only AMS (most significant
CE# high (VIH) after the data comes out. When the
address) - A0 are decoded. The remaining bits (A23 – highest address of the devices is reached, the address
A
MS) are ignored. The first byte addressed can be at
counter will roll over to the 000000h address, allowing
the entire memory to be read in one continuous READ
any memory location. Upon completion, any data on
the Sl will be ignored. Refer to Table 12 for the related instruction.
Address Key.
Table 12. Address Key
Address
AN (AMS – A0)
Don't Care Bits
Pm25LD020
A17 - A0
Pm25LD010
A16 - A0
Pm25LD512
A15 - A0
A23 – A18
A23 – A17
A23 – A16
Figure 12. Read Data Sequence
SIO
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DRAFT Date: August, 2010, Rev:0.4
Pm25LD512/010/ 020
DEVICE OPERATION (CONTINUED)
FAST_READ COMMAND (FAST READ DATA) OPERATION
The FAST_READ instruction is used to read memory
data at up to a 100 MHz clock.
The first byte addressed can be at any memory
location. The address is automatically incremented
The FAST_READ instruction code is followed by three after each byte of data is shifted out. When the highest
address bytes (A23 - A0) and a dummy byte (8 clocks), address is reached, the address counter will roll over to
transmitted via the SI line, with each bit latched-in
the 000000h address, allowing the entire memory to be
during the rising edge of SCK. Then the first data byte read with a single FAST_READ instruction. The
addressed is shifted out on the SO line, with each bit
shifted out at a maximum frequency fCT, during the
falling edge of SCK.
FAST_READ instruction is terminated by driving CE#
high (VIH).
Figure 13. Fast Read Data Sequence
SIO
SIO
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DRAFT Date: August, 2010, Rev:0.4
Pm25LD512/010/ 020
DEVICE OPERATION (CONTINUED)
FRDO COMMAND (FAST READ DUAL OUTPUT) OPERATION
The FRDO instruction is used to read memory data on is output on SO, while simultaneously the second bit is
two output pins each at up to a 100 MHz clock.
output on SIO.
The FRDO instruction code is followed by three
The first byte addressed can be at any memory
address bytes (A23 - A0) and a dummy byte (8 clocks), location. The address is automatically incremented
transmitted via the SI line, with each bit latched-in after each byte of data is shifted out. When the highest
during the rising edge of SCK. Then the first data byte address is reached, the address counter will roll over to
addressed is shifted out on the SO and SIO lines, with the 000000h address, allowing the entire memory to be
each pair of bits shifted out at a maximum frequency
CT, during the falling edge of SCK. The first bit (MSb)
read with a single FRDO instruction. FRDO instruction
is terminated by driving CE# high (VIH).
f
Figure 14. Fast Read Dual-Output Sequence
CE#
9
0
2
3
4
5
8
31
1
6
7
10 11 28
29 30
SCK
SIO
...
3 - BYTE ADDRESS
2
1
INSTRUCTION = 0011 1011b
HIGH IMPEDANCE
23
3
0
...
22
21
SO
CE#
33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48
32
SCK
SIO
2
2
0
1
6
7
6
6
7
4
4
0
1
DATA OUT 1
DATA OUT 2
HIGH IMPEDANCE
SO
5
3
5
3
7
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DRAFT Date: August, 2010, Rev:0.4
Pm25LD512/010/ 020
DEVICE OPERATION (CONTINUED)
PAGE_PROG COMMAND (PAGE PROGRAM) OPERATION
The Page Program (PAGE_PROG) instruction allows
WIP bit in Status Register via a RDSR instruction. If
up to 256 bytes data to be programmed into memory in the WIP bit is “1”, the program operation is still in
a single operation. The destination of the memory to be progress. If WIP bit is “0”, the program operation has
programmed must be outside the protected memory
completed.
area set by the Block Protection (BP2, BP1, BP0) bits.
A PAGE_PROG instruction which attempts to program If more than 256 bytes data are sent to a device, the
into a page that is write-protected will be ignored.
Before the execution of PAGE_PROG instruction, the
address counter rolls over within the same page, the
previously latched data are discarded, and the last 256
Write Enable Latch (WEL) must be enabled through a bytes data are kept to be programmed into the page.
Write Enable (WREN) instruction.
The starting byte can be anywhere within the page.
When the end of the page is reached, the address will
wrap around to the beginning of the same page. If the
data to be programmed are less than a full page, the
data of all other bytes on the same page will remain
unchanged.
The PAGE_PROG instruction code, three address
bytes and program data (1 to 256 bytes) are input via
the SlO line. Program operation will start immediately
after the CE# is brought high, otherwise the
PAGE_PROG instruction will not be executed. The
internal control logic automatically handles the
programming voltages and timing. During a program
operation, all instructions will be ignored except the
RDSR instruction. The progress or completion of the
program operation can be determined by reading the
Note: A program operation can alter “1”s into “0”s, but
an erase operation is required to change “0”s back to
“1”s. A byte cannot be reprogrammed without first
erasing the whole sector or block.
Figure 15. Page Program Sequence
SIO
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DRAFT Date: August, 2010, Rev:0.4
Pm25LD512/010/ 020
DEVICE OPERATION (CONTINUED)
ERASE OPERATION
During an erase operation, all instruction will be
ignored except the Read Status Register (RDSR)
The memory array of the Pm25LD512/010 is organized instruction. The progress or completion of the erase
into uniform 4 KByte sectors or 32 KByte uniform
blocks (a block consists of eight adjacent sectors).
operation can be determined by reading the WIP bit in
the Status Register using a RDSR instruction. If the
Pm25LD020 is organized into uniform 4 KByte sectors WIP bit is “1”, the erase operation is still in progress. If
or 64 KByte uniform blocks (a block consists of sixteen the WIP bit is “0”, the erase operation has been
adjacent sectors)
completed.
Before a byte can be reprogrammed, the sector or
block that contains the byte must be erased (erasing
sets bits to “1”). In order to erase the devices, there are
three erase instructions available: Sector Erase
(SECTOR_ER), Block Erase (BLOCK_ER) and Chip
Erase (CHIP_ER). A sector erase operation allows any
individual sector to be erased without affecting the data
in other sectors. A block erase operation erases any
individual block. A chip erase operation erases the
whole memory array of a device. A sector erase, block
erase or chip erase operation can be executed prior to
any programming operation.
BLOCK_ER COMMAND (BLOCK ERASE)
OPERATION
A Block Erase (BLOCK_ER) instruction erases a 64
KByte block of the Pm25LD512/010/020. Before the
execution of a BLOCK_ER instruction, the Write
Enable Latch (WEL) must be set via a Write Enable
(WREN) instruction. The WEL is reset automatically
after the completion of a block erase operation.
The BLOCK_ER instruction code and three address
bytes are input via SI. Erase operation will start
immediately after the CE# is pulled high, otherwise the
BLOCK_ER instruction will not be executed. The
internal control logic automatically handles the erase
voltage and timing. Refer to Figure 15 for Block Erase
Sequence.
SECTOR_ER COMMAND (SECTOR ERASE)
OPERATION
A SECTOR_ER instruction erases a 4 KByte sector
Before the execution of a SECTOR_ER instruction, the
Write Enable Latch (WEL) must be set via a Write
Enable (WREN) instruction. The WEL bit is reset
automatically after the completion of sector an erase
operation.
CHIP_ER COMMAND (CHIP ERASE) OPERATION
A Chip Erase (CHIP_ER) instruction erases the entire
memory array of a Pm25LD512/010/020. Before the
execution of CHIP_ER instruction, the Write Enable
Latch (WEL) must be set via a Write Enable (WREN)
instruction. The WEL is reset automatically after
completion of a chip erase operation.
A SECTOR_ER instruction is entered, after CE# is
pulled low to select the device and stays low during the
entire instruction sequence The SECTOR_ER
instruction code, and three address bytes are input via
SI. Erase operation will start immediately after CE# is
pulled high. The internal control logic automatically
handles the erase voltage and timing. Refer to Figure
14 for Sector Erase Sequence.
The CHIP_ER instruction code is input via the SI.
Erase operation will start immediately after CE# is
pulled high, otherwise the CHIP_ER instruction will not
be executed. The internal control logic automatically
handles the erase voltage and timing. Refer to Figure
16 for Chip Erase Sequence.
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DRAFT Date: August, 2010, Rev:0.4
Pm25LD512/010/ 020
DEVICE OPERATION (CONTINUED)
Figure 16. Sector Erase Sequence
SIO
Figure 17. Block Erase Sequence
SIO
Figure 18. Chip Erase Sequence
SIO
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DRAFT Date: August, 2010, Rev:0.4
Pm25LD512/010/ 020
ABSOLUTE MAXIMUM RATINGS (1)
Temperature Under Bias
Storage Temperature
-65oC to +125oC
-65oC to +125oC
Standard Package 240oC 3 Seconds
Lead-free Package 260oC 3 Seconds
Surface Mount Lead Soldering Temperature
Input Voltage with Respect to Ground on All Pins (2)
All Output Voltage with Respect to Ground
VCC (2)
-0.5 V to VCC + 0.5 V
-0.5 V to VCC + 0.5 V
-0.5 V to +6.0 V
Notes:
1. Applied conditions greater than those listed in “Absolute Maximum Ratings” may cause permanent damage to
the device. This is a stress rating only. The functional operation of the device conditions that exceed those
indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating
condition for extended periods may affect device reliability.
2. Maximum DC voltage on input or I/O pins is VCC + 0.5 V. During voltage transitions, input or I/O pins may
overshoot VCC by + 2.0 V for a period of time not to exceed 20 ns. Minimum DC voltage on input or I/O pins is
-0.5 V. During voltage transitions, input or I/O pins may undershoot GND by -2.0 V for a period of time not to
exceed 20 ns.
DC AND AC OPERATING RANGE
Part Number
Pm25LD512/010/020
-40oC to105oC
Operating Temperature (Commercial Grade)
Vcc Power Supply
2.3 V – 3.6 V
DC CHARACTERISTICS
Applicable over recommended operating range from:
TAC = -40°C to +105°C, VCC = 2.3 V to 3.6 V (unless otherwise noted).
Symbol
Parameter
Condition
Min
Typ
10
Max
Units
mA
mA
µA
mA
µA
µA
V
ICC1
ICC2
ISB1
ISB2
ILI
Vcc Active Read Current
Vcc Program/Erase Current
Vcc Standby Current CMOS
Vcc Standby Current TTL
Input Leakage Current
Output Leakage Current
Input Low Voltage
VCC = 3.6V at 33 MHz, SO = Open
VCC = 3.6V at 33 MHz, SO = Open
VCC = 3.6V, CE# = VCC
15
15
30
10
VCC = 3.6V, CE# = VIH to VCC
3
VIN = 0V to VCC
VIN = 0V to VCC, TAC = 0oC to 85oC
1
1
ILO
VIL
-0.5
0.8
VIH
VOL
VOH
Input HIgh Voltage
0.7VCC
VCC + 0.3
0.45
V
Output Low Voltage
IOL = 2.1 mA
2.3V < VCC < 3.6V
V
Output High Voltage
VCC - 0.2
V
IOH = -100 µA
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DRAFT Date: August, 2010, Rev:0.4
Pm25LD512/010/ 020
AC CHARACTERISTICS
Applicable over recommended operating range from T
A
= -40°C to +105°C, VCC = 2.3 V to 3.6 V
CL = 1 TTL Gate and 10 pF (unless otherwise noted).
Symbol
Parameter
Min
0
Typ
Max
100
33
8
Units
MHz
MHz
ns
f
f
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
CT
Clock Frequency for fast read mode
Clock Frequency for read mode
Input Rise Time
C
0
RI
FI
Input Fall Time
8
ns
CKH
CKL
CEH
CS
CH
DS
DH
HS
HD
V
SCK High Time
4
4
ns
SCK Low Time
ns
CE# High Time
25
10
5
ns
CE# Setup Time
ns
CE# Hold Time
ns
Data In Setup Time
Data in Hold Time
Hold Setup Time
2
ns
2
ns
15
15
ns
Hold Time
ns
Output Valid
8
ns
OH
LZ
Output Hold Time Normal Mode
Hold to Output Low Z
Hold to Output High Z
Output Disable Time
Secter/Block/Chip Erase Time
Page Program Time
0
ns
200
200
100
10
ns
HZ
DIS
EC
PP
VCS
ns
ns
ms
ms
µs
2
5
V
CC Set-up Time
50
tw
Write Status Register time (flash bit)
10
ms
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DRAFT Date: August, 2010, Rev:0.4
Pm25LD512/010/ 020
AC CHARACTERISTICS (CONTINUED)
SERIAL INPUT/OUTPUT TIMING (1)
SIO
Note: 1. For SPI Mode 0 (0,0)
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DRAFT Date: August, 2010, Rev:0.4
Pm25LD512/010/ 020
AC CHARACTERISTICS (CONTINUED)
HOLD TIMING
PIN CAPACITANCE (f = 1 MHz, T = 25°C )
Typ
4
Max
6
Units
pF
Conditions
CIN
V
IN = 0 V
COUT
8
12
pF
VOUT = 0 V
Note: These parameters are characterized but not 100% tested.
OUTPUT TEST LOAD
INPUT TEST WAVEFORMS
AND MEASUREMENT LEVEL
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DRAFT Date: August, 2010, Rev:0.4
Pm25LD512/010/ 020
POWER-UP AND POWER-DOWN
At Power-up and Power-down, the device must not be is not guaranteed if, by this time, Vcc is still below
selected (CE# must follow the voltage applied on Vcc) Vcc(min). No Write Status Register, Program or Erase
until Vcc reaches the correct value:
instructions should be sent until the later of:
- Vcc(min) at Power-up, and then for a further delay of - tPUW after Vcc passed the VWI threshold
tVCE
- tVCE after Vcc passed the Vcc(min) level
- Vss at Power-down
Usually a simple pull-up resistor on CE# can be used
At Power-up, the device is in the following state:
to insure safe and proper Power-up and Power-down. - The device is in the Standby mode
To avoid data corruption and inadvertent write
- The Write Enable Latch (WEL) bit is reset
operations during power up, a Power On Reset (POR)
circuit is included. The logic inside the device is held
reset while Vcc is less than the POR threshold value
At Power-down, when Vcc drops from the operating
voltage, to below the Vwi, all write operations are
(Vwi) during power up, the device does not respond to disabled
any instruction until a time delay of tPUW has elapsed and the device does not respond to any write
after the moment that Vcc rised above the VWI
instruction.
threshold. However, the correct operation of the device
Vcc
Vcc(max)
All Write Commands are Rejected
Chip Selection Not Allowed
Vcc(min)
Reset State
tVCE
Read Access Allowed
Device fully accessible
V (write inhibit)
tPUW
Time
Symbol
Parameter
Vcc(min) to CE# Low
Min.
Max.
Unit
*1
tVCE
10
us
*1
tPUW
Power-Up time delay to Write instruction
Write Inhibit Voltage
1
10
ms
V
*1
1.6
1.8
VWI
Note : *1. These parameters are characterized only.
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DRAFT Date: August, 2010, Rev:0.4
Pm25LD512/010/ 020
PROGRAM/ERASE PERFORMANCE
Parameter
Unit Typ Max Remarks
Sector Erase Time
Block Erase Time
Chip Erase Time
ms
ms
ms
10
10
10
5
From writing erase command to erase completion
From writing erase command to erase completion
From writing erase command to erase completion
From writing program command to program completion
Page Programming Time ms
2
Note: These parameters are characterized and are not 100% tested.
RELIABILITY CHARACTERISTICS
Parameter
Min
200,000
20
Typ
Unit
Cycles
Years
Volts
Volts
mA
Test Method
Endurance
JEDEC Standard A117
JEDEC Standard A103
JEDEC Standard A114
JEDEC Standard A115
JEDEC Standard 78
Data Retention
ESD – Human Body Model
ESD – Machine Model
Latch-Up
2,000
200
100 + ICC1
Note: These parameters are characterized and are not 100% tested.
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DRAFT Date: August, 2010, Rev:0.4
Pm25LD512/010/ 020
PACKAGE TYPE INFORMATION
`
8S
8-Pin JEDEC 150mil Broad Small Outline Integrated Circuit (SOIC) Package
(measure in millimeters)
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DRAFT Date: August, 2010, Rev:0.4
Pm25LD512/010/ 020
PACKAGE TYPE INFORMATION (CONTINUED)
8K
8-Contact Ulta-Thin Small Outline No-Lead (WSON) Package (measure in millimeters)
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DRAFT Date: August, 2010, Rev:0.4
Pm25LD512/010/ 020
PACKAGE TYPE INFORMATION (CONTINUED)
PACKAGE TYPE INFORMATION (CONTINUED)
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DRAFT Date: August, 2010, Rev:0.4
Pm25LD512/010/ 020
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DRAFT Date: August, 2010, Rev:0.4
Pm25LD512/010/ 020
REVISION HISTORY
Date
Revision No.
Description of Changes
Page No.
March, 2009
September, 2009
0.0
0.1
Preliminary Product Specification
All
1,10
1. Modify the program frequency to 50MHz
2. Improve Erase time from 15ms to 10ms.
1. Modify the tHS, tHD to 15ns
1. fix the erase time
1. change the operation voltage spec
2.3V~2.8V
October, 2009
October, 2009
November, 2009
0.2
0.3
0.31
24
All
August, 2010
0.4
1. Modify the operation voltage 2.3V~3.6V
2. Modify the write inhibit 1.6V~1.8V
ALL
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DRAFT Date: August, 2010, Rev:0.4
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