QL2003-0PL84I [ETC]
Field Programmable Gate Array (FPGA) ; 现场可编程门阵列（FPGA）的\n
| 型号： | QL2003-0PL84I |
| 厂家： | 
ETC |
| 描述： | Field Programmable Gate Array (FPGA)
|
| 文件： | 总10页 (文件大小：184K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
QL2003
3.3V and 5.0V pASIC 2 FPGA
Combining Speed, Density, Low Cost and Flexibility
Rev. C
pASIC 2
HIGHLIGHTS
Ultimate Verilog/VHDL Silicon Solution
-Abundant, high-speed interconnect eliminates manual routing
-Flexible logic cell provides high efficiency and performance
-Design tools produce fast, efficient Verilog/VHDL synthesis
Speed, Density, Low Cost and Flexibility in One Device
-16-bit counter speeds exceeding 200 MHz
3
-3,000 usable ASIC gates, 5,000 usable PLD gates, 118 I/Os
-3-layer metal ViaLink process for small die sizes
-100% routable and pin-out maintainable
… 3,000
usable ASIC gates,
118 I/O pins
Advanced Logic Cell and I/O Capabilities
-Complex functions (up to 16 inputs) in a single logic cell
-High synthesis gate utilization from logic cell fragments
-Full IEEE Standard JTAG boundary scan capability
-Individually-controlled input/feedback registers and OEs on all I/O pins
Other Important Family Features
-3.3V and 5.0V operation with low standby power
-I/O pin-compatibility between different devices in the same packages
-PCI compliant (at 5.0V), full speed 33 MHz implementations
-High design security provided by security fuses
QL2003
Block Diagram
192
Logic
Cells
3-5
QL2003
The QL2003 is a 3,000 usable ASIC gate, 5,000 usable PLD gate member of
the pASIC 2 family of FPGAs. pASIC 2 FPGAs employ a unique
combination of architecture, technology, and software tools to provide high
speed, high usable density, low price, and flexibility in the same devices.
The flexibility and speed make pASIC 2 devices an efficient and high
performance silicon solution for designs described using HDLs such as
Verilog and VHDL, as well as schematics.
PRODUCT
SUMMARY
The QL2003 contains 192 logic cells. With 118 maximum I/Os, the
QL2003 is available in 84-PLCC, 100-pin TQFP and 144-pin TQFP
packages.
Software support for the complete pASIC families, including the QL2003, is
available through three basic packages. The turnkey QuickWorks package
provides the most complete FPGA software solution from design entry to
logic synthesis (by Synplicity, Inc.), to place and route, to simulation. The
QuickToolsTM and QuickChipTM packages provide a solution for designers
who use Cadence, Mentor, Synopsys, Viewlogic, Veribest, or other third-
party tools for design entry, synthesis, or simulation.
FEATURES
Total of 118 I/O Pins
- 110 bidirectional input/output pins, PCI-compliant at 5.0V
in -1/-2 speed grades
- 4 high-drive input-only pins
- 4 high-drive input/distributed network pins
Four Low-Skew (less than 0.5ns) Distributed Networks
- Two array networks available to logic cell flip-flop clock, set, and
reset - each driven by an input-only pin
- Two global clock/control networks available to F1 logic input, and
logic cell flip-flop clock, set, reset; input and I/O register clock, reset,
enable; and output enable controls - each driven by an input-only pin,
or any input or I/O pin, or any logic cell output or I/O cell feedback
High Performance
- Input + logic cell + output delays under 6 ns
- Datapath speeds exceeding 225 MHz
- Counter speeds over 200 MHz
3-6
QL2003
PINOUT DIAGRAM
84-PIN PLCC
3
3-7
QL2003
PINOUT DIAGRAMS
100-PIN TQFP
PIN # 76
PIN # 1
pASIC
QL2003-1PF100C
PIN # 51
PIN # 109
PIN # 26
144-PIN TQFP
PIN # 1
pASIC
QL2003-1PF144C
PIN # 73
PIN # 37
3-8
QL2003
100 and 144 TQFP Pinout Table
144
TQFP TQFP
100
144
TQFP TQFP
100
144
TQFP TQFP
100
144
TQFP TQFP
100
144
TQFP TQFP
100
Function
Function
Function
Function
Function
1
2
NC
3
I/O
I/O
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
NC
NC
22
NC
23
NC
24
25
26
27
28
29
NC
30
31
NC
32
33
NC
34
35
36
NC
37
38
39
40
41
42
GND
I/O
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
NC
43
I/O
I/O
88
89
60
61
62
63
64
65
66
67
NC
68
NC
69
NC
70
71
NC
NC
72
NC
73
74
75
76
77
78
79
80
NC
81
I/O
I
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
82
83
I/O
I/O
2
3
I/O
I/O
44
I/O
90
ACLK / I
VCC
I
NC
84
I/O
4
4
I/O
I/O
45
I/O
91
I/O
5
NC
5
I/O
I/O
NC
NC
46
I/O
92
NC
NC
85
I/O
6
I/O
I/O
I/O
93
GCLK / I
VCC
I/O
I/O
7
NC
6
VCC
I/O
I/O
I/O
94
GND
I/O
3
8
I/O
NC
NC
NC
47
GND
I/O
95
NC
86
9
NC
7
I/O
TDI
I/O
96
I/O
I/O
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
I/O
I/O
NC
97
I/O
87
I/O
NC
NC
8
I/O
I/O
I/O
I/O
88
GND
I/O
I/O
I/O
48
I/O
98
I/O
89
I/O
VCC
I/O
49
TRSTB
TMS
I/O
99
I/O
90
I/O
NC
9
I/O
50
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
I/O
91
I/O
GND
I/O
I/O
51
I/O
92
VCC
I/O
10
11
12
13
14
15
16
17
18
NC
19
NC
20
21
I/O
52
I/O
GND
I/O
NC
93
I
I/O
53
I/O
I/O
ACLK / I
VCC
I
I/O
54
I/O
I/O
NC
94
I/O
I/O
55
I/O
I/O
I/O
I/O
NC
NC
NC
56
I/O
I/O
NC
NC
95
I/O
GCLK / I
VCC
I/O
GND
I/O
VCC
I/O
I/O
I/O
I/O
I/O
I/O
I/O
TCK
STM
I/O
NC
96
GND
I/O
I/O
I/O
NC
57
I/O
I/O
GND
I/O
I/O
97
I/O
I/O
NC
58
I/O
I/O
98
I/O
I/O
I/O
I/O
I/O
99
I/O
I/O
I/O
NC
59
I/O
VCC
I/O
100
1
TDO
I/O
I/O
VCC
GND
3-9
QL2003
PIN DESCRIPTIONS
Description
Pin
Function
TDI
Test Data In for JTAG
Hold HIGH during normal operation. Connect to
VCC if not used for JTAG.
TRSTB
TMS
Active low Reset for JTAG
Test Mode Select for JTAG
Test Clock for JTAG
Hold LOW during normal operation. Connect to
ground if not used for JTAG.
Hold HIGH during normal operation. Connect to
VCC if not used for JTAG.
TCK
Hold HIGH or LOW during normal operation.
Connect to VCC or ground if not used for JTAG.
TDO
Test data out for JTAG
Special Test Mode
Output that must be left unconnected if not used for JTAG.
Must be grounded during normal operation.
Can be configured as either or both.
STM
I/ACLK
High-drive input and/or array
network driver
I/GCLK
High-drive input and/or global
network driver
Can be configured as either or both.
I
High-drive input
Input/Output pin
Power supply pin
Ground pin
Use for input signals with high fanout.
Can be configured as an input and/or output.
Connect to 3.3V supply.
I/O
VCC
GND
Connect to ground.
ORDERING
INFORMATION
QL 2003 - 1 PF100 C
QuickLogic
pASIC device
Operating Range
C = Commercial
I = Industrial
pASIC 2 device
part number
Package Code
PL84 = 84-pin PLCC
PF100 = 100-pin TQFP
PF144 = 144-pin TQFP
Speed Grade
X = quick
0 = fast
1 = faster
2 = fastest
3-10
QL2003
ABSOLUTE MAXIMUM RATINGS
Supply Voltage ……………….. -0.5 to 7.0V
Input Voltage ……….… -0.5 to VCC +0.5V
ESD Pad Protection ….…………… ±2000V
DC Input Current ….……………… ±20 mA
Latch-up Immunity ………………. ±200 mA
Storage Temperature……..…….. -65°C to + 150°C
Lead Temperature ………….…………...…. 300°C
5 Volt OPERATING RANGE
Symbol
Parameter
Industrial
Commercial
Unit
3
Min
Max
5.5
85
Min
4.75
0
Max
5.25
70
VCC
TA
TC
Supply Voltage
Ambient Temperature
Case Temperature
4.5
-40
V
°C
°C
-X Speed Grade
0.4
0.4
0.4
0.4
2.75
2.00
1.61
1.35
0.46
0.46
0.46
0.46
2.55
1.85
1.50
1.25
K
Delay Factor
-0 Speed Grade
-1 Speed Grade
-2 Speed Grade
DC CHARACTERISTICS over 5V operating range
Symbol
VIH
VIL
Parameter
Input HIGH Voltage
Input LOW Voltage
Conditions
Min
2.0
Max Unit
V
V
V
V
V
V
V
0.8
IOH = -4 mA
IOH = -24 mA/-16 mA [1]
IOH = -10 µA
IOL = 24 mA/16 mA [1]
IOL = 10 µA
VI = VCC or GND
VI = VCC or GND
3.7
2.4
VCC-0.1
VOH
VOL
Output HIGH Voltage
Output LOW Voltage
0.45
0.1
10
II
IOZ
CI
Input Leakage Current
3-State Output Leakage Current
Input Capacitance [2]
-10
-10
µA
µA
pF
10
10
IOS
Output Short Circuit Current [3]
VO = GND
VO = VCC
VI, VIO = VCC or GND
-15
40
2 (typ)
-120 mA
210
10
mA
mA
ICC
D.C. Supply Current [4]
Notes:
[1]
-24 mA IOH and 24 mA IOL apply only to -1/-2 commercial grade devices. These speed grades are
also PCI-compliant. All other devices have -16 mA IOH and 16 mA IOL specifications.
Capacitance is sample tested only.
Only one output at a time. Duration should not exceed 30 seconds.
For -0/-1/-2 commercial grade devices only. Maximum ICC is 20 mA for -X commercial grade
devices and 15mA for all industrial grade devices. For AC conditions, contact QuickLogic customer
engineering.
[2]
[3]
[4]
3-11
QL2003
3.3 Volt OPERATING RANGE
Symbol
Parameter
Industrial
Commercial
Unit
Min
3.0
-40
Max
3.6
85
Min
3.0
0
Max
3.6
70
VCC
TA
Supply Voltage
Ambient Temperature
-0 Speed Grade
V
°C
0.56
0.56
0.56
2.74
2.21
1.85
0.61
0.61
0.61
2.65
2.14
1.79
K
Delay Factor
-1 Speed Grade
-2 Speed Grade
DC CHARACTERISTICS over 3.3V operating range
Symbol
VIH
VIL
Parameter
Conditions
Min
2.0
Max Unit
Input HIGH Voltage
Input LOW Voltage
Output HIGH Voltage
V
V
0.8
VOH
IOH = -2.4 mA
IOH = -10 µA
IOL = 4 mA
IOL = 10 µA
5.5V > VI > VCC
2.4
VCC-0.1
V
V
VOL
IIH
Output LOW Voltage
0.4
0.1
12
V
V
mA
Input High Current Sink
(for tolerance to 5V devices)
Input Leakage Current
3-State Output Leakage Current
Input Capacitance [5]
II
IOZ
CI
VI = VCC or GND
VI = VCC or GND
-10
-10
10
10
10
-70
130
3
µA
µA
pF
mA
mA
mA
IOS
Output Short Circuit Current [6]
VO = GND
VO = VCC
VI, VIO = VCC or GND
-10
25
0.5 (typ)
ICC
D.C. Supply Current [7]
Notes:
[5]
[6]
[7]
Capacitance is sample tested only.
Only one output at a time. Duration should not exceed 30 seconds.
For commercial grade devices only. Maximum ICC is 5 mA for all industrial grade devices. For AC
conditions, contact QuickLogic customer engineering.
3-12
QL2003
AC CHARACTERISTICS at VCC = 5V, TA = 25°C (K = 1.00)
Propagation delays depend on routing, fanout, load capacitance, supply voltage, junction temperature,
and process variation. The AC Characteristics are a design guide to provide initial timing estimates at
nominal conditions. Worst case estimates are obtained when nominal propagation delays are multiplied
by the appropriate Delay Factor, K, as specified in the Delay Factor table (Operating Range). The
QuickChip/QuickTools/QuickWorks software incorporates data sheet AC Characteristics into the
design database for precise path analysis or simulation results following place and route.
Logic Cells
3
Propagation Delays (ns)
Symbol
tPD
tSU
tH
tCLK
tCWHI
tCWLO
tSET
tRESET
tSW
Parameter
Fanout [8]
1
2
3
4
8
Combinatorial Delay [9]
Setup Time [9]
Hold Time
Clock to Q Delay
Clock High Time
Clock Low Time
Set Delay
Reset Delay
Set Width
Reset Width
1.4
1.8
0.0
0.8
2.0
2.0
1.4
1.2
1.9
1.8
1.7
1.8
0.0
1.1
2.0
2.0
1.7
1.5
1.9
1.8
2.0
1.8
0.0
1.4
2.0
2.0
2.0
1.8
2.3
1.8
0.0
1.7
2.0
2.0
2.3
2.1
1.9
1.8
3.5
1.8
0.0
2.9
2.0
2.0
3.5
3.3
1.9
1.8
1.9
1.8
tRW
Input-Only Cells
Symbol
Propagation Delays (ns)
Parameter
Fanout [8]
1
2
3
4
8
12
24
tIN
tINI
High Drive Input Delay
2.5
2.6
4.8
0.0
0.9
0.8
4.1
0.0
2.6
2.7
4.8
0.0
1.0
0.9
4.1
0.0
2.6
2.7
4.8
0.0
1.0
0.9
4.1
0.0
2.7
2.8
4.8
0.0
1.1
1.0
4.1
0.0
3.5
3.6
4.8
0.0
1.9
1.8
4.1
0.0
4.6 5.8
4.7 5.9
4.8 4.8
0.0 0.0
3.0 4.2
2.9 4.1
4.1 4.1
0.0 0.0
High Drive Input, Inverting Delay
Input Register Set-Up Time
Input Register Hold Time
Input Register Clock To Q
Input Register Reset Delay
tISU
tIH
tlCLK
tlRST
tlESU
tlEH
Input Register clock Enable Set-Up Time
Input Register Clock Enable Hold Time
Notes:
[8] Stated timing for worst case Propagation Delay over process variation at VCC=5.0V and TA=25°C.
Multiply by the appropriate Delay Factor, K, for speed grade, voltage and temperature settings as
specified in the Operating Range.
[9] These limits are derived from a representative selection of the slowest paths through the pASIC 2 logic
cell including typical net delays. Worst case delay values for specific paths should be determined from
timing analysis of your particular design.
3-13
QL2003
Clock Cells
Symbol
Propagation Delays (ns)
Loads per Half Column [10]
Parameter
Array Clock Delay
Global Clock Pin Delay
Global Clock Buffer Delay
1
2
3
4
8
10
13
tACK
tGCKP
tGCKB
2.2
1.2
1.5
2.2
1.2
1.6
2.3
1.2
1.6
2.4
1.2
1.7
2.5
1.2
1.8
2.6
1.2 1.2
1.9 2.0
I/O Cells
Symbol
Propagation Delays (ns)
Parameter
Fanout [8]
1
2
3
4
8
10
4.6
4.8
0.0
3.6
3.5
4.1
0.0
tI/O
tISU
Input Delay (bidirectional pad)
Input Register Set-Up Time
1.8
4.8
0.0
0.8
0.7
4.1
0.0
2.1
4.8
0.0
1.1
1.0
4.1
0.0
2.4
4.8
0.0
1.4
1.3
4.1
0.0
2.7
4.8
0.0
1.7
1.6
4.1
0.0
3.9
4.8
0.0
2.9
2.8
4.1
0.0
tIH
Input Register Hold Time
tlOCLK
tlORST
tlESU
tlEH
Input Register Clock To Q
Input Register Reset Delay
Input Register clock Enable Set-Up Time
Input Register Clock Enable Hold Time
Propagation Delays (ns)
Symbol
Parameter
Output Load Capacitance (pF)
30
2.6
2.8
2.1
2.6
2.9
3.3
50
3.0
3.3
2.6
3.3
75
3.6
3.9
3.1
4.1
100
4.1
4.5
3.7
4.9
150
5.2
5.7
4.8
6.5
tOUTLH
tOUTHL
tPZH
tPZL
tPHZ
Output Delay Low to High
Output Delay High to Low
Output Delay Tri-state to High
Output Delay Tri-state to Low
Output Delay High to Tri-State [11]
Output Delay Low to Tri-State [11]
tPLZ
Notes:
[10] The array distributed networks consist of 48 half columns and the global distributed networks consist of
52 half columns, each driven by an independent buffer. The number of half columns used does not affect
clock buffer delay. The array clock has up to 10 loads per half column. The global clock has up to 13
loads per half column.
[11] The following loads are used for tPXZ:
tPHZ
1KΩ
5 pF
1KΩ
tPLZ
5 pF
3-14
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