QL2009-1PF144I [ETC]
3.3V and 5.0V pASIC? 2 FPGA Combining Speed, Density, Low Cost and Flexibility; 3.3V和5.0V pASIC ? 2 FPGA的结合速度,密度,低成本和灵活性![QL2009-1PF144I](http://pdffile.icpdf.com/pdf1/p00043/img/icpdf/QL2009_223146_icpdf.jpg)
型号: | QL2009-1PF144I |
厂家: | ![]() |
描述: | 3.3V and 5.0V pASIC? 2 FPGA Combining Speed, Density, Low Cost and Flexibility |
文件: | 总12页 (文件大小:274K) |
中文: | 中文翻译 | 下载: | 下载PDF数据表文档文件 |
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QL2009
3.3V and 5.0V pASIC 2 FPGA
Combining Speed, Density, Low Cost and Flexibility
Rev. C
pASIC 2
HIGHLIGHTS
Ultimate Verilog/VHDL Silicon Solution
-Abundant, high-speed interconnect eliminates manual routing
-Flexible logic cell provides high efficiency and performance
-Design tools produce fast, efficient Verilog/VHDL synthesis
3
Speed, Density, Low Cost and Flexibility in One Device
-16-bit counter speeds exceeding 200 MHz
-9,000 usable ASIC gates, 16,000 usable PLD gates, 225 I/Os
-3-layer metal ViaLink process for small die sizes
-100% routable and pin-out maintainable
… 9,000
usable ASIC gates,
225 I/O pins
Advanced Logic Cell and I/O Capabilities
-Complex functions (up to 16 inputs) in a single logic cell
-High synthesis gate utilization from logic cell fragments
-Full IEEE Standard JTAG boundary scan capability
-Individually-controlled input/feedback registers and OEs on all I/O pins
Other Important Family Features
-3.3V and 5.0V operation with low standby power
-I/O pin-compatibility between different devices in the same packages
-PCI compliant (at 5.0V), full speed 33 MHz implementations
-High design security provided by security fuses
QL2009
Block Diagram
672
Logic
Cells
3-35
QL2009
The QL2009 is a 9,000 usable ASIC gate,16,000 usable PLD gate member of
the pASIC 2 family of FPGAs. pASIC 2 FPGAs employ a unique combination
of architecture, technology, and software tools to provide high speed, high
usable density, low price, and flexibility in the same devices. The flexibility
and speed make pASIC 2 devices an efficient and high performance silicon
solution for designs described using HDLs such as Verilog and VHDL, as well
as schematics.
PRODUCT
SUMMARY
The QL2009 contains 672 logic cells. With 225 maximum I/Os, the QL2009
is available in 144-pin TQFP, 208-PQFP, and 256-pin PBGA packages.
Software support for the complete pASIC families, including the QL2009, is
available through three basic packages. The turnkey QuickWorks package
provides the most complete FPGA software solution from design entry to logic
synthesis (by Synplicity, Inc.), to place and route, to simulation. The
QuickToolsTM and QuickChipTM packages provide a solution for designers
who use Cadence, Mentor, Synopsys, Viewlogic, Veribest, or other third-party
tools for design entry, synthesis, or simulation.
FEATURES
Total of 225 I/O Pins
- 217 bidirectional input/output pins, PCI-compliant at 5.0V
in -1/-2 speed grades
- 4 high-drive input-only pins
- 4 high-drive input/distributed network pins
Four Low-Skew (less than 0.5ns) Distributed Networks
- Two array networks available to logic cell flip-flop clock, set, and
reset - each driven by an input-only pin
- Two global clock/control networks available to F1 logic input, and
logic cell flip-flop clock, set, reset; input and I/O register clock, reset,
enable; and output enable controls - each driven by an input-only pin, or
any input or I/O pin, or any logic cell output or I/O cell feedback
High Performance
- Input + logic cell + output delays under 6 ns
- Datapath speeds exceeding 225 MHz
- Counter speeds over 200 MHz
3-36
QL2009
PINOUT DIAGRAMS
144-PIN TQFP
PIN # 109
PIN # 1
3
pASIC
QL2009-1PF144C
PIN # 73
PIN # 37
PIN # 157
208-PIN PQFP
PIN # 1
pASIC
QL2009-1PQ208C
PIN # 105
PIN # 53
3-37
QL2009
PQFP 208 and TQFP 144 Pinout Table
208
144
Function
208
144
Function
208
144
Function
208
144
Function
208
144
Function
PQFP TQFP
PQFP TQFP
PQFP TQFP
PQFP TQFP
PQFP TQFP
1
NC
1
I/O
I/O
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
30
31
NC
32
NC
33
NC
34
35
36
37
38
39
NC
40
NC
NC
41
42
43
NC
44
45
NC
46
47
48
NC
49
NC
50
51
52
NC
53
54
55
56
NC
57
58
59
GND
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
TDI
I/O
I/O
I/O
I/O
GND
I/O
VCC
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
GND
I/O
I/O
I/O
I/O
GND
I/O
I/O
I/O
I/O
VCC
I/O
85
86
60
61
I/O
I/O
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
87
88
GND
I/O
169
170
171
172
173
174
175
176
177
178
179
180
181
182
183
184
185
186
187
188
189
190
191
192
193
194
195
196
197
198
199
200
201
202
203
204
205
206
207
208
117
118
119
120
NC
I/O
I/O
2
3
2
I/O
87
NC
62
I/O
89
I
I/O
4
3
I/O
88
I/O
90
ACLK / I
VCC
I
I/O
5
NC
4
I/O
89
63
I/O
91
I/O
6
I/O
90
NC
NC
64
I/O
92
NC
I/O
7
5
I/O
91
I/O
93
GCLK / I
VCC
I/O
121
NC
I/O
8
NC
6
I/O
92
I/O
94
I/O
9
I/O
93
NC
65
I/O
95
122
123
124
NC
GND
I/O
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
7
VCC
I/O
94
I/O
NC
96
I/O
NC
NC
8
95
66
GND
I/O
I/O
I/O
GND
I/O
96
67
NC
97
I/O
I/O
97
NC
NC
68
VCC
I/O
I/O
125
126
127
128
129
NC
I/O
NC
9
I/O
98
98
I/O
GND
I/O
I/O
99
I/O
NC
99
I/O
NC
10
11
12
13
NC
14
15
16
17
18
19
20
21
22
23
NC
24
NC
25
NC
26
27
28
NC
NC
29
I/O
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
69
I/O
I/O
I/O
I/O
NC
70
I/O
NC
100
NC
101
102
103
104
NC
105
106
NC
107
NC
108
109
110
111
NC
112
113
NC
NC
114
115
116
NC
I/O
I/O
I/O
I/O
I/O
I/O
I/O
71
TRSTB
TMS
I/O
VCC
I/O
130
131
132
NC
VCC
I/O
I/O
72
I/O
NC
73
GND
I/O
I/O
I/O
I/O
I/O
GND
I/O
NC
74
I/O
I/O
133
134
NC
I/O
I/O
I/O
I/O
I
75
I/O
I/O
I/O
ACLK / I
VCC
I
76
I/O
I/O
135
136
NC
I/O
77
I/O
I/O
I/O
NC
78
I/O
I/O
I/O
GCLK / I
VCC
I/O
I/O
I/O
137
NC
I/O
79
VCC
I/O
I/O
I/O
80
TCK
STM
I/O
138
139
NC
GND
I/O
I/O
NC
81
GND
I/O
I/O
VCC
I/O
I/O
82
I/O
I/O
140
NC
I/O
NC
83
I/O
I/O
I/O
I/O
I/O
I/O
141
142
NC
I/O
I/O
NC
84
I/O
GND
I/O
I/O
I/O
I/O
I/O
I/O
85
I/O
VCC
I/O
143
144
TDO
I/O
I/O
NC
86
I/O
VCC
I/O
I/O
I/O
NC
I/O
I/O
3-38
QL2009
PINOUT DIAGRAM
256-PIN PBGA
3
pASIC
QL2009-1PB256C
TOP
PIN A1
CORNER
19 17 15 13 11
9
7
5
3
1
A
B
C
D
E
F
G
H
J
K
L
M
N
P
R
T
U
V
W
Y
BOTTOM
3-39
QL2009
PBGA 256 Pinout Table
256
Function
256
Function
256
Function
256
Function
256
Function
256
Function
PBGA
PBGA
PBGA
PBGA
PBGA
PBGA
A1
A2
VSS
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
TCK
I/O
TDO
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
STM
I/O
I/O
I/O
I/O
C4
C5
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
VSS
I/O
VCC
I/O
VSS
I/O
I/O
VCC
I/O
VSS
I/O
VCC
I/O
VSS
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
E19
E20
F1
I/O
I/O
L2
L3
ACLK / I
I
T17
T18
T19
T20
U1
I/O
I/O
I/O
I/O
I/O
I/O
I/O
VSS
I/O
VCC
I/O
VSS
I/O
VCC
I/O
I/O
VSS
I/O
VCC
I/O
VSS
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
V20
W1
I/O
I/O
I/O
TDI
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
TRSTB
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
A3
C6
I/O
L4
GCLK / I
VCC
I/O
W2
A4
C7
F2
I/O
L17
L18
L19
L20
M1
W3
A5
C8
F3
I/O
W4
A6
C9
F4
VCC
VCC
I/O
I/O
U2
W5
A7
C10
C11
C12
C13
C14
C15
C16
C17
C18
C19
C20
D1
F17
F18
F19
F20
G1
I/O
U3
W6
A8
I/O
U4
W7
A9
I/O
M2
I/O
U5
W8
A10
A11
A12
A13
A14
A15
A16
A17
A18
A19
A20
B1
I/O
M3
I/O
U6
W9
I/O
M4
I/O
U7
W10
W11
W12
W13
W14
W15
W16
W17
W18
W19
W20
Y1
G2
I/O
M17
M18
M19
M20
N1
I/O
U8
G3
I/O
I/O
U9
G4
I/O
I/O
U10
U11
U12
U13
U14
U15
U16
U17
U18
U19
U20
V1
G17
G18
G19
G20
H1
I/O
I/O
I/O
I/O
I/O
N2
I/O
I/O
N3
I/O
D2
I/O
N4
VSS
VSS
I/O
D3
H2
I/O
N17
N18
N19
N20
P1
D4
H3
I/O
B2
D5
H4
VSS
VSS
I/O
I/O
B3
D6
H17
H18
H19
H20
J1
I/O
Y2
B4
D7
I/O
Y3
B5
D8
I/O
P2
I/O
Y4
B6
D9
I/O
P3
I/O
V2
Y5
B7
D10
D11
D12
D13
D14
D15
D16
D17
D18
D19
D20
E1
I/O
P4
I/O
V3
Y6
B8
J2
I/O
P17
P18
P19
P20
R1
I/O
V4
Y7
B9
J3
I/O
I/O
V5
Y8
B10
B11
B12
B13
B14
B15
B16
B17
B18
B19
B20
C1
J4
I/O
I/O
V6
Y9
J17
J18
J19
J20
K1
I/O
I/O
V7
Y10
Y11
Y12
Y13
Y14
Y15
Y16
Y17
Y18
Y19
Y20
I/O
I/O
V8
I/O
R2
I/O
V9
GCLK / I
I/O
R3
I/O
V10
V11
V12
V13
V14
V15
V16
V17
V18
R4
VCC
VCC
I/O
K2
I/O
R17
R18
R19
R20
T1
K3
I/O
K4
VCC
I
I/O
E2
K17
K18
K19
K20
I/O
E3
ACLK / I
I
I/O
E4
T2
I/O
C2
E17
I/O
T3
I/O
C3
I/O
E18
I/O
L1
I
T4
I/O
V19
TMS
3-40
QL2009
PIN DESCRIPTIONS
Description
Pin
Function
TDI
Test Data In for JTAG
Hold HIGH during normal operation. Connect to
VCC if not used for JTAG.
TRSTB
TMS
Active low Reset for JTAG
Test Mode Select for JTAG
Test Clock for JTAG
Hold LOW during normal operation. Connect to
ground if not used for JTAG.
Hold HIGH during normal operation. Connect to
VCC if not used for JTAG.
TCK
Hold HIGH or LOW during normal operation.
Connect to VCC or ground if not used for JTAG.
3
TDO
Test data out for JTAG
Special Test Mode
Output that must be left unconnected if not used for JTAG.
Must be grounded during normal operation.
Can be configured as either or both.
STM
I/ACLK
High-drive input and/or array
network driver
I/GCLK
High-drive input and/or global
network driver
Can be configured as either or both.
I
High-drive input
Input/Output pin
Power supply pin
Ground pin
Use for input signals with high fanout.
Can be configured as an input and/or output.
Connect to 3.3V supply.
I/O
VCC
GND
Connect to ground.
ORDERING
QL 2009 - 1 PQ208 C
INFORMATION
QuickLogic
pASIC device
Operating Range
C = Commercial
I = Industrial
pASIC 2 device
part number
Package Code
PF144 = 144-pin TQFP
PQ208 = 208-pin PQFP
PB256 = 256-pin PBGA
Speed Grade
X = quick
0 = fast
1 = faster
2 = fastest
3-41
QL2009
ABSOLUTE MAXIMUM RATINGS
Supply Voltage ……………….. -0.5 to 7.0V
Input Voltage ……….… -0.5 to VCC +0.5V
ESD Pad Protection ….…………… ±2000V
DC Input Current ….……………… ±20 mA
Latch-up Immunity ………………. ±200 mA
Storage Temperature……..…….. -65°C to + 150°C
Lead Temperature ………….………………. 300°C
5 Volt OPERATING RANGE
Symbol
Parameter
Industrial
Commercial
Unit
Min
4.5
-40
Max
5.5
85
Min
4.75
0
Max
5.25
70
VCC
TA
TC
Supply Voltage
Ambient Temperature
Case Temperature
V
°C
°C
-X Speed Grade
0.4
0.4
0.4
0.4
2.75
2.00
1.61
1.35
0.46
0.46
0.46
0.46
2.55
1.85
1.50
1.25
K
Delay Factor
-0 Speed Grade
-1 Speed Grade
-2 Speed Grade
DC CHARACTERISTICS over 5V operating range
Symbol
VIH
VIL
Parameter
Input HIGH Voltage
Input LOW Voltage
Conditions
Min
2.0
Max Unit
V
V
V
V
V
V
V
0.8
IOH = -4 mA
IOH = -24 mA/-16 mA [1]
IOH = -10 µA
IOL = 24 mA/16 mA [1]
IOL = 10 µA
VI = VCC or GND
VI = VCC or GND
3.7
2.4
VCC-0.1
VOH
VOL
Output HIGH Voltage
Output LOW Voltage
0.45
0.1
10
II
IOZ
CI
Input Leakage Current
3-State Output Leakage Current
Input Capacitance [2]
-10
-10
µA
µA
pF
10
10
IOS
Output Short Circuit Current [3]
VO = GND
VO = VCC
VI, VIO = VCC or GND
-15
40
2 (typ)
-120 mA
210
10
mA
mA
ICC
D.C. Supply Current [4]
Notes:
[1]
-24 mA IOH and 24 mA IOL apply only to -1/-2 commercial grade devices. These speed grades are
also PCI-compliant. All other devices have -16 mA IOH and 16 mA IOL specifications.
Capacitance is sample tested only.
Only one output at a time. Duration should not exceed 30 seconds.
For -0/-1/-2 commercial grade devices only. Maximum ICC is 20 mA for -X commercial grade
devices and 15mA for all industrial grade devices. For AC conditions, contact QuickLogic customer
engineering.
[2]
[3]
[4]
3-42
QL2009
3.3 Volt OPERATING RANGE
Symbol
Parameter
Industrial
Commercial
Unit
Min
3.0
-40
Max
3.6
85
Min
3.0
0
Max
3.6
70
VCC
TA
Supply Voltage
Ambient Temperature
-0 Speed Grade
V
°C
0.56
0.56
0.56
2.74
2.21
1.85
0.61
0.61
0.61
2.65
2.14
1.79
K
Delay Factor
-1 Speed Grade
-2 Speed Grade
DC CHARACTERISTICS over 3.3V operating range
3
Symbol
VIH
VIL
Parameter
Conditions
Min
2.0
Max Unit
Input HIGH Voltage
Input LOW Voltage
Output HIGH Voltage
V
V
0.8
VOH
IOH = -2.4 mA
IOH = -10 µA
IOL = 4 mA
IOL = 10 µA
5.5V > VI > VCC
2.4
VCC-0.1
V
V
VOL
IIH
Output LOW Voltage
0.4
0.1
12
V
V
mA
Input High Current Sink
(for tolerance to 5V devices)
Input Leakage Current
3-State Output Leakage Current
Input Capacitance [5]
II
IOZ
CI
VI = VCC or GND
VI = VCC or GND
-10
-10
10
10
10
-70
130
3
µA
µA
pF
mA
mA
mA
IOS
Output Short Circuit Current [6]
VO = GND
VO = VCC
VI, VIO = VCC or GND
-10
25
0.5 (typ)
ICC
D.C. Supply Current [7]
Notes:
[5]
[6]
[7]
Capacitance is sample tested only.
Only one output at a time. Duration should not exceed 30 seconds.
For commercial grade devices only. Maximum ICC is 5 mA for all industrial grade devices. For AC
conditions, contact QuickLogic customer engineering.
3-43
QL2009
AC CHARACTERISTICS at VCC = 5V, TA = 25°C (K = 1.00)
Propagation delays depend on routing, fanout, load capacitance, supply voltage, junction temperature,
and process variation. The AC Characteristics are a design guide to provide initial timing estimates at
nominal conditions. Worst case estimates are obtained when nominal propagation delays are multiplied
by the appropriate Delay Factor, K, as specified in the Delay Factor table (Operating Range). The
QuickChip/QuickTools/QuickWorks software incorporates data sheet AC Characteristics into the
design database for precise path analysis or simulation results following place and route.
Logic Cells
Propagation Delays (ns)
Symbol
tPD
tSU
tH
tCLK
tCWHI
tCWLO
tSET
tRESET
tSW
Parameter
Fanout [8]
1
2
3
2.0
1.8
0.0
1.4
2.0
2.0
2.0
4
8
Combinatorial Delay [9]
Setup Time [9]
Hold Time
Clock to Q Delay
Clock High Time
Clock Low Time
Set Delay
Reset Delay
Set Width
Reset Width
1.4
1.8
0.0
0.8
2.0
2.0
1.4
1.2
1.9
1.8
1.7
1.8
0.0
1.1
2.0
2.0
1.7
1.5
1.9
1.8
2.3
1.8
0.0
1.7
2.0
2.0
2.3
2.1
1.9
1.8
3.5
1.8
0.0
2.9
2.0
2.0
3.5
3.3
1.9
1.8
1.8
1.9
1.8
tRW
Input-Only Cells
Symbol
Propagation Delays (ns)
Parameter
Fanout [8]
1
2
3
4
8
12
24
tIN
tINI
High Drive Input Delay
2.5
2.6
4.8
0.0
0.9
0.8
4.1
0.0
2.6
2.7
4.8
0.0
1.0
0.9
4.1
0.0
2.6
2.7
4.8
0.0
1.0
0.9
4.1
0.0
2.7
2.8
4.8
0.0
1.1
1.0
4.1
0.0
3.5
3.6
4.8
0.0
1.9
1.8
4.1
0.0
4.6 5.8
4.7 5.9
4.8 4.8
0.0 0.0
3.0 4.2
2.9 4.1
4.1 4.1
0.0 0.0
High Drive Input, Inverting Delay
Input Register Set-Up Time
Input Register Hold Time
Input Register Clock To Q
Input Register Reset Delay
tISU
tIH
tlCLK
tlRST
tlESU
tlEH
Input Register clock Enable Set-Up Time
Input Register Clock Enable Hold Time
Notes:
[8] Stated timing for worst case Propagation Delay over process variation at VCC=5.0V and TA=25°C.
Multiply by the appropriate Delay Factor, K, for speed grade, voltage and temperature settings as
specified in the Operating Range.
[9] These limits are derived from a representative selection of the slowest paths through the pASIC 2 logic
cell including typical net delays. Worst case delay values for specific paths should be determined from
timing analysis of your particular design.
3-44
QL2009
Clock Cells
Symbol
Propagation Delays (ns)
Loads per Half Column [10]
Parameter
Array Clock Delay
Global Clock Pin Delay
Global Clock Buffer Delay
1
2
3
4
8
10
13
tACK
tGCKP
tGCKB
2.2
1.2
1.5
2.2
1.2
1.6
2.3
1.2
1.6
2.4
1.2
1.7
2.5
1.2
1.8
2.6
1.2 1.2
1.9 2.0
I/O Cells
Symbol
3
Propagation Delays (ns)
Parameter
Fanout [8]
1
2
3
4
8
10
4.6
4.8
0.0
3.6
3.5
4.1
0.0
tI/O
tISU
Input Delay (bidirectional pad)
Input Register Set-Up Time
1.8
4.8
0.0
0.8
0.7
4.1
0.0
2.1
4.8
0.0
1.1
1.0
4.1
0.0
2.4
4.8
0.0
1.4
1.3
4.1
0.0
2.7
4.8
0.0
1.7
1.6
4.1
0.0
3.9
4.8
0.0
2.9
2.8
4.1
0.0
tIH
Input Register Hold Time
tlOCLK
tlORST
tlESU
tlEH
Input Register Clock To Q
Input Register Reset Delay
Input Register clock Enable Set-Up Time
Input Register Clock Enable Hold Time
Propagation Delays (ns)
Symbol
Parameter
Output Load Capacitance (pF)
30
2.6
2.8
2.1
2.6
2.9
3.3
50
3.0
3.3
2.6
3.3
75
3.6
3.9
3.1
4.1
100
4.1
4.5
3.7
4.9
150
5.2
5.7
4.8
6.5
tOUTLH
tOUTHL
tPZH
tPZL
tPHZ
Output Delay Low to High
Output Delay High to Low
Output Delay Tri-state to High
Output Delay Tri-state to Low
Output Delay High to Tri-State [11]
Output Delay Low to Tri-State [11]
tPLZ
Notes:
[10] The array distributed networks consist of 48 half columns and the global distributed networks consist of
52 half columns, each driven by an independent buffer. The number of half columns used does not affect
clock buffer delay. The array clock has up to 10 loads per half column. The global clock has up to 13
loads per half column.
[11] The following loads are used for tPXZ:
tPHZ
1KΩ
5 pF
1KΩ
tPLZ
5 pF
3-45
QL2009
3-46
相关型号:
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