QL30252PQ208M_技术文档

QL3025 pASIC 3 FPGA Data Sheet

25,000 Usable PLD Gate pASIC 3 FPGA Combining High Performance

and High Density

• • • • • •

Four Low-Skew Distributed

Networks

Device Highlights

• Two array clock/control networks available

to the logic cell flip-flop clock, set and reset

inputs — each driven by an input-only pin

High Performance & High Density

• 25,000 Usable PLD Gates with 204 I/Os

• 300 MHz 16-bit Counters,

• Two global clock/control networks available

to the logic cell; F1, clock set, reset inputs

and the input, I/O register clock, reset, and

enable inputs as well as the output enable

control — each driven by an input-only or

I/O pin, or any logic cell output or I/O cell

feedback

400 MHz Datapaths

• 0.35 µm four-layer metal non-volatile

CMOS process for smallest die sizes

Easy to Use / Fast Development

Cycles

• 100% routable with 100% utilization and

High Performance

complete pin-out stability

• Input + logic cell + output total delays

• Variable-grain logic cells provide high

under 6 ns

performance and 100% utilization

• Data path speeds over 400 MHz

• Counter speeds over 300 MHz

• Comprehensive design tools include high

quality Verilog/VHDL synthesis

Advanced I/O Capabilities

• Interfaces with both 3.3 V and 5.0 V devices

• PCI compliant with 3.3 V and 5.0 V buses

for -1/-2/-3/-4 speed grades

• Full JTAG boundary scan

• I/O Cells with individually controlled

Registered Input Path and Output Enables

Total of 204 I/O Pins

• 196 bidirectional input/output pins,

PCI-compliant for 5.0 V and 3.3 V buses for

-1/-2/-3/-4 speed grades

• Four High Drive input-only pins

• Four High Drive input-only/distributed

network pins

Figure 1: 672 pASIC 3 Logic Cells

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1

QL3025 pASIC 3 FPGA Data Sheet Rev E

Architecture Overview

The QL3025 is a 25,000 usable PLD gate member of the pASIC 3 family of FPGAs.

pASIC 3 FPGAs are fabricated on a 0.35 µm four-layer metal process using QuickLogic^'s

patented ViaLink^technology to provide a unique combination of high performance, high

density, low cost, and extreme ease-of-use.

The QL3025 contains 672 logic cells. With a maximum of 204 I/Os, the QL3025 is

available in 144-pin TQFP, 208-pin PQFP, and 256-pin PBGA packages.

Software support for the complete pASIC 3 family, including the QL3025, is available

through three basic packages. The turnkey QuickWorks^package provides the most

complete FPGA software solution from design entry to logic synthesis, to place and route,

to simulation. The QuickTools^TMfor Workstations package provides a solution for designers

who use Cadence^, Exemplar^TM, Mentor^, Synopsys^, Synplicity^, Viewlogic^TM, Aldec^TM,

or other third-party tools for design entry, synthesis, or simulation.

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2

QL3025 pASIC 3 FPGA Data Sheet Rev E

Electrical Specifications

AC Characteristics at V_CC= 3.3 V, TA = 25°C (K = 1.00)

To calculate delays, multiply the appropriate K factor from Table 7 by the numbers provided

in Table 1 through Table 5.

Table 1: Logic Cells

Symbol

Parameter

Propagation Delays (ns) Fanout^a

1

2

3

4

8

t_PD

t_SU

Combinatorial Delay ^b

Setup Time ^b

Hold Time

1.4

1.7

0.0

0.7

1.2

1.0

0.8

1.9

1.8

1.7

0.0

1.0

1.2

1.3

1.1

1.9

1.8

1.9

1.7

0.0

1.2

1.5

1.3

1.9

1.8

2.2

1.7

0.0

1.5

1.2

1.8

1.6

1.9

1.8

3.2

1.7

0.0

2.5

1.2

2.8

2.6

1.9

1.8

t_H

t_CLK

t_CWHI

t_CWLO

t_SET

t_RESET

t_SW

Clock to Q Delay

Clock High Time

Clock Low Time

Set Delay

Reset Delay

Set Width

t_RW

Reset Width

a. Stated timing for worst case Propagation Delay over process variation at V_CC= 3.3 V and

TA = 25°C. Multiply by the appropriate Delay Factor, K, for speed grade, voltage, and temperature

settings as specified in Table 7.

b. These limits are derived from a representative selection of the slowest paths through the

pASIC 3 logic cell including typical net delays. Worst case delay values for specific paths should

be determined from timing analysis of your particular design.

Table 2: Input-Only/Clock Cells

Symbol

Parameter

Propagation Delays (ns) Fanout ^a

1

2

3

4

8

12 24

t_IN

t_INI

t_ISU

t_IH

High Drive Input Delay

High Drive Input, Inverting Delay

Input Register Set-Up Time

Input Register Hold Time

Input Register Clock To Q

Input Register Reset Delay

1.5 1.6 1.8 1.9 2.4 2.9 4.4

1.6 1.7 1.9 2.0 2.5 3.0 4.5

3.1 3.1 3.1 3.1 3.1 3.1 3.1

0.0 0.0 0.0 0.0 0.0 0.0 0.0

0.7 0.8 1.0 1.1 1.6 2.1 3.6

0.6 0.7 0.9 1.0 1.5 2.0 3.5

t_lCLK

t_lRST

t_lESU

t_lEH

Input Register clock Enable Set-Up Time 2.3 2.3 2.3 2.3 2.3 2.3 2.3

Input Register Clock Enable Hold Time 0.0 0.0 0.0 0.0 0.0 0.0 0.0

a. Stated timing for worst case Propagation Delay over process variation at V_CC= 3.3 V and

TA = 25°C. Multiply by the appropriate Delay Factor, K, for speed grade, voltage, and tempera-

ture settings as specified in Table 7.

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3

QL3025 pASIC 3 FPGA Data Sheet Rev E

Table 3: Clock Cells

Symbol

Parameter

Propagation Delays (ns) Loads per Half Column ^a

1

2

3

4

8

10

11

t_ACK

t_GCKP

t_GCKB

Array Clock Delay

Global Clock Pin Delay

Global Clock Buffer Delay

1.2

0.7

0.8

1.2

0.7

0.8

1.3

0.7

0.9

1.3

0.7

0.9

1.5

0.7

1.1

1.6

0.7

1.2

1.7

0.7

1.3

a. The array distributed networks consist of 40 half columns and the global distributed networks con-

sist of 44 half columns, each driven by an independent buffer. The number of half columns used

does not affect clock buffer delay. The array clock has up to eight loads per half column. The glo-

bal clock has up to 11 loads per half column.

Table 4: Input-Only I/O Cells

Symbol

Parameter

Propagation Delays (ns) Fanout ^a

1

2

3

4

8

10

t_I/O

t_ISU

Input Delay (bidirectional pad)

Input Register Set-Up Time

1.3

3.1

0.0

0.7

0.6

2.3

0.0

1.6

3.1

0.0

1.0

0.9

2.3

0.0

1.8

3.1

0.0

1.2

1.1

2.3

0.0

2.1

3.1

0.0

1.5

1.4

2.3

0.0

3.1

0.0

2.5

2.4

2.3

0.0

3.6

3.1

0.0

3.0

2.9

2.3

0.0

t_IH

Input Register Hold Time

t_lOCLK

t_lORST

t_lESU

t_lEH

Input Register Clock To Q

Input Register Reset Delay

Input Register clock Enable Set-Up Time

Input Register Clock Enable Hold Time

a. Stated timing for worst case Propagation Delay over process variation at V_CC= 3.3 V and

TA = 25°C. Multiply by the appropriate Delay Factor, K, for speed grade, voltage, and temperature

settings as specified in Table 7.

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4

QL3025 pASIC 3 FPGA Data Sheet Rev E

Table 5: Output-Only I/O Cells

Propagation Delays (ns) Output Load

Symbol

Parameter

Capacitance (pF)

30

50

2.5

2.6

1.7

2.0

-

75

3.1

3.2

2.2

2.6

-

100

3.6

3.7

2.8

3.1

-

150

4.7

4.8

3.9

4.2

-

t_OUTLH

t_OUTHL

t_PZH

Output Delay Low to High

Output Delay High to Low

2.1

2.2

1.2

1.6

2.0

1.2

Output Delay Tri-state to High

Output Delay Tri-state to Low

Output Delay High to Tri-State ^a

Output Delay Low to Tri-State

t_PZL

t_PHZ

t_PLZ

-

a. The following loads presented in Figure 2 are used for t_PXZ

:

t_PHZ

1ΚΩ

5 pF

1ΚΩ

t_PLZ

5 pF

Figure 2: Loads used for t_PXZ

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5

QL3025 pASIC 3 FPGA Data Sheet Rev E

DC Characteristics

The DC specifications are provided in Table 6 through Table 8.

Table 6: Absolute Maximum Ratings

Parameter

V_CCVoltage

Value

-0.5 V to 4.6 V

-0.5 V to 7.0 V

-0.5 V to V_CCIO+0.5 V

200 mA

Parameter

Value

20 mA

DC Input Current

ESD Pad Protection

Storage Temperature

Lead Temperature

V_CCIOVoltage

Input Voltage

Latch-up Immunity

2000 V

-65°C to +150°C

300°C

Table 7: Operating Range

Military

Symbol

Parameter

Industrial

Commercial

Unit

Min

Max

3.6

5.5

-

Min

Max

3.6

Min

3.0

0

Max

3.6

V_CC

V_CCIO

TA

Supply Voltage

3.0

-55

-

3.0

V

I/O Input Tolerance Voltage

Ambient Temperature

Case Temperature

5.5

5.25

70

V

-40

85

°C

TC

125

-

°C

-0 Speed Grade

-

0.43

1.90

1.54

1.28

0.90

0.82

0.46

1.85

1.50

1.25

0.88

0.80

n/a

-1 Speed Grade 0.42

-2 Speed Grade 0.42

-3 Speed Grade

1.64

1.37

K

Delay Factor

-4 Speed Grade

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6

QL3025 pASIC 3 FPGA Data Sheet Rev E

Table 8: DC Characteristics

Symbol

V_IH

Parameter

Input HIGH Voltage

Input LOW Voltage

Conditions

Min

Max

Units

V

0.5 V_CCV_CCIO+ 0.5

V_IL

-0.5

2.4

0.3 V_CC

V

I_OH= -12 mA

I_OH= -500 µA

I_OL= 16 mA^a

I_OL= 1.5 mA

V

V_OH

Output HIGH Voltage

Output LOW Voltage

0.9 V_CC

V

0.45

0.1 V_CC

10

V

V_OL

V

I_I

I or I/O Input Leakage Current

3-State Output Leakage Current

Input Capacitance^b

V_I= V_CCIOor GND

-10

µA

pF

mA

µA

I_OZ

C_I

10

V_O= GND

V_O= V_CC

-15

40

-180

210

2

I_OS

Output Short Circuit Current^c

D.C. Supply Current^d

I_CC

V_I, V_IO= V_CCIOor GND 0.50 (typ)

0

I_CCIOD.C. Supply Current on V_CCIO

100

a. Applies only to -1/-2/-3/-4 commercial grade devices. These speed grades are also PCI-compliant. All

other devices have 8 mA IOL specifications.

b. Capacitance is sample tested only. Clock pins are 12 pF maximum.

c. Only one output at a time. Duration should not exceed 30 seconds.

d. For -1/-2/-3/-4 commercial grade devices only. Maximum I_CCis 3 mA for -0 commercial grade and all

industrial grade devices, and 5 mA for all military grade devices. For AC conditions, contact QuickLog-

ic customer applications group. (See Contact Information).

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7

QL3025 pASIC 3 FPGA Data Sheet Rev E

Kv and Kt Graphs

Voltage Factor vs. Supply Voltage

1.1000

1.0800

1.0600

1.0400

1.0200

1.0000

0.9800

0.9600

0.9400

0.9200

3

3.1

3.2

3.3

3.4

3.5

3.6

Supply Voltage (V)

Figure 3: Voltage Factor vs. Supply Voltage

Temperature Factor vs. Operating Temperature

1.15

1.10

1.05

1.00

0.95

0.90

0.85

-60

-40

-20

0

20

40

60

80

Junction Temperature C

Figure 4: Temperature Factor vs. Operating Temperature

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8

QL3025 pASIC 3 FPGA Data Sheet Rev E

Power-up Sequencing

V_CCIO

V_CC

(V_CCIO-V_{CC MAX}

)

V_CC

400 us

Time

Figure 5: Power-up Requirements

The following requirements must be met when powering up the device (refer to Figure 5):

• When ramping up the power supplies keep (V_CCIO-V_CC)_MAX

≤ 500 mV. Deviation from

this recommendation can cause permanent damage to the device.

• V_CCIOmust lead V_CCwhen ramping the device.

• The power supply must take greater than or equal to 400 µs to reach V_CC. Ramping to

V_CC/V_CCIOearlier than 400 µs can cause the device to behave improperly.

An internal diode is present in-between V_CCand V_CCIO, as shown in Figure 6.

V

CCIO

CC

Internal Logic

Cells, RAM

blocks, etc

IO Cells

Figure 6: Internal Diode Between V_CCand V_CCIO

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9

QL3025 pASIC 3 FPGA Data Sheet Rev E

JTAG

TCK

TAp Controller

State Machine

(16 States)

Instruction Decode

&

Control Logic

TMS

TRSTB

Instruction Register

Mux

RDI

TDO

Mux

Boundary-Scan Register

(Data Register)

Bypass

Register

Internal

Register

I/O Registers

User Defined Data Register

Figure 7: JTAG Block Diagram

Microprocessors and Application Specific Integrated Circuits (ASICs) pose many design

challenges, not the least of which concerns the accessibility of test points. The Joint Test

Access Group (JTAG) formed in response to this challenge, resulting in IEEE standard

1149.1, the Standard Test Access Port and Boundary Scan Architecture.

The JTAG boundary scan test methodology allows complete observation and control of the

boundary pins of a JTAG-compatible device through JTAG software. A Test Access Port

(TAP) controller works in concert with the Instruction Register (IR); these allow users to run

three required tests, along with several user-defined tests.

JTAG tests allow users to reduce system debug time, reuse test platforms and tools, and reuse

subsystem tests for fuller verification of higher level system elements.

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QL3025 pASIC 3 FPGA Data Sheet Rev E

The 1149.1 standard requires the following three tests:

• Extest Instruction. The Extest instruction performs a PCB interconnect test. This test

places a device into an external boundary test mode, selecting the boundary scan

register to be connected between the TAP's Test Data In (TDI) and Test Data Out (TDO)

pins. Boundary scan cells are preloaded with test patterns (via the Sample/Preload

Instruction), and input boundary cells capture the input data for analysis.

• Sample/Preload Instruction. This instruction allows a device to remain in its

functional mode, while selecting the boundary scan register to be connected between

the TDI and TDO pins. For this test, the boundary scan register can be accessed via a

data scan operation, allowing users to sample the functional data entering and leaving

the device.

• Bypass Instruction. The Bypass instruction allows data to skip a device's boundary

scan entirely, so the data passes through the bypass register. The Bypass instruction

allows users to test a device without passing through other devices. The bypass register

is connected between the TDI and TDO pins, allowing serial data to be transferred

through a device without affecting the operation of the device.

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11

QL3025 pASIC 3 FPGA Data Sheet Rev E

Pin Descriptions

Table 9: Pin Descriptions

Function

Description

Hold HIGH during normal operation. Connect to

V_CCif not used for JTAG.

TDI

Test Data In for JTAG

Hold LOW during normal operation. Connect to

ground if not used for JTAG.

TRSTB

TMS

Active low Reset for JTAG

Test Mode Select for JTAG

Test Clock for JTAG

Hold HIGH during normal operation. Connect to

V_CCif not used for JTAG.

Hold HIGH or LOW during normal operation.

Connect to V_CCor ground if not used for JTAG.

TCK

Output that must be left unconnected if not used for

JTAG.

TDO

STM

Test data out for JTAG

Special Test Mode

Must be grounded during normal operation.

Can be configured as either or both.

High-drive input and/or array

network driver

I/ACLK

High-drive input and/or global

network driver

I/GCLK

Can be configured as either or both.

I

High-drive input

Input/Output pin

Power supply pin

Use for input signals with high fanout.

Can be configured as an input and/or output.

Connect to 3.3 V supply.

I/O

V_CC

Connect to 5.0 V supply if 5 V input tolerance is

required, otherwise connect to 3.3 V supply.

V_CCIO

GND

Input voltage tolerance pin

Ground pin

Connect to ground.

Ordering Information

QL 3025 - 1 PQ208 C

QuickLogic device

pASIC 3 device

part number

Operating Range

C = Commercial

I = Industrial

M = Military

Speed Grade

0 = Quick

1 = Fast

2 = Faster

3 = Faster

*4 = Wow

Package Code

PF144 = 144-pin TQFP

PQ208 = 208-pin PQFP

PB256 = 256-pin PBGA

* Contact QuickLogic regarding availability. (See Contact Information)

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12

QL3025 pASIC 3 FPGA Data Sheet Rev E

144 TQFP Pinout Diagram

Pin 109

Pin 1

pASIC 3

QL3025-1PF144C

Pin 37

Pin 73

Figure 8: Top View of 144 Pin TQFP

208 PQFP Pinout Diagram

Pin 157

Pin 1

pASIC 3

QL3025-1PQ208C

Pin 53

Pin 105

Figure 9: Top View of 208 Pin PQFP

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QL3025 pASIC 3 FPGA Data Sheet Rev E

144 TQFP & 208 PQFP Pinout Table

Table 10: 144 TQFP & 208 PQFP Pinout Table

208

144

208

144

208

144

208

144

208

144

Function

PQFP TQFP

I/O

GND

I/O

TDI

I/O

GND

I/O

V_CC

I/O

GND

I/O

GND

I/O

V_CCIO

I/O

GND

I/O

1

NC

1

43

44

45

46

47

48

49

50

51

52

53

54

55

56

57

58

59

60

61

62

63

64

65

66

67

68

69

70

71

72

73

74

75

76

77

78

79

80

81

82

83

84

30

31

NC

32

NC

33

NC

34

35

36

37

38

39

NC

40

NC

41

42

43

NC

44

45

NC

46

47

48

NC

49

NC

50

51

52

NC

53

54

55

56

NC

57

58

59

85

86

60

61

127

128

129

130

131

132

133

134

135

136

137

138

139

140

141

142

143

144

145

146

147

148

149

150

151

152

153

154

155

156

157

158

159

160

161

162

163

164

165

166

167

168

87

88

169

170

171

172

173

174

175

176

177

178

179

180

181

182

183

184

185

186

187

188

189

190

191

192

193

194

195

196

197

198

199

200

201

202

203

204

205

206

207

208

117

118

119

120

NC

2

I/O

I

I/O

3

2

87

NC

62

89

I/O

ACLK / I

V_CC

I

I/O

4

3

88

90

5

NC

4

I/O

89

63

I/O

91

I/O

6

I/O

90

NC

64

I/O

92

NC

I/O

GCLK / I

V_CC

I/O

7

5

91

93

121

NC

I/O

8

NC

6

92

94

I/O

GND

I/O

9

93

NC

65

95

122

123

124

NC

V_CC

I/O

10

11

12

13

14

15

16

17

18

19

20

21

22

23

24

25

26

27

28

29

30

31

32

33

34

35

36

37

38

39

40

41

42

7

94

NC

96

NC

8

95

66

GND

I/O

GND

I/O

96

67

NC

97

V_CC

I/O

97

NC

68

125

126

127

128

129

NC

I/O

GND

I/O

NC

9

98

I/O

99

NC

99

I/O

NC

10

11

12

13

NC

14

15

16

17

18

19

20

21

22

23

NC

24

NC

25

NC

26

27

28

NC

29

100

101

102

103

104

105

106

107

108

109

110

111

112

113

114

115

116

117

118

119

120

121

122

123

124

125

126

69

I/O

NC

70

I/O

NC

100

NC

101

102

103

104

NC

105

106

NC

107

NC

108

109

110

111

NC

112

113

NC

114

115

116

NC

I/O

TRSTB

TMS

I/O

V_CC

I/O

V_CCIO

I/O

71

130

131

132

NC

I/O

72

I/O

GND

I/O

NC

73

I/O

GND

I/O

NC

74

I/O

133

134

NC

I/O

I

I/O

75

ACLK / I

V_CC

I

I/O

76

135

136

NC

I/O

77

NC

78

I/O

GCLK / I

V_CC

I/O

137

NC

I/O

V_CC

I/O

79

TCK

STM

I/O

GND

I/O

80

138

139

NC

I/O

GND

I/O

NC

81

I/O

V_CC

I/O

82

I/O

140

NC

I/O

NC

83

I/O

141

142

NC

I/O

GND

I/O

NC

84

I/O

V_CC

I/O

TDO

I/O

85

143

144

I/O

NC

86

I/O

V_CC

I/O

NC

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14

QL3025 pASIC 3 FPGA Data Sheet Rev E

256 PBGA Pinout Diagram

pASIC 3

QL3025-1PB256C

BOTTOM View

PIN A1

CORNER

20 18 16 14 12 10

19 17 15 13 11

8

6

4

2

9

7

5

3

1

Figure 10: 256-Pin PBGA Pinout Diagram

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15

QL3025 pASIC 3 FPGA Data Sheet Rev E

256 PBGA Pinout Table

Table 11: 256 PBGA Pinout Table

256

PBGA

Function 256 Function 256 Function 256 Function 256 Function 256 Function

VSS

I/O

TCK

I/O

TDO

I/O

NC

STM

NC

I/O

V_CCIO

I/O

VSS

I/O

V_CC

I/O

VSS

I/O

V_CC

I/O

VSS

I/O

V_CC

I/O

VSS

I/O

NC

I/O

ACLK / I

I

I/O

TDI

I/O

TRSTB

I/O

NC

I/O

NC

A1

C4

C5

E19

E20

F1

L2

L3

T17

T18

T19

T20

U1

V20

W1

A2

A3

C6

I/O

L4

GCLK / I

V_CC

I/O

NC

I/O

W2

A4

C7

F2

I/O

L17

L18

L19

L20

M1

W3

I/O

A5

C8

F3

W4

V_CC

NC

I/O

A6

C9

F4

U2

W5

I/O

A7

C10

C11

C12

C13

C14

C15

C16

C17

C18

C19

C20

D1

F17

F18

F19

F20

G1

U3

W6

I/O

VSS

I/O

A8

U4

W7

A9

M2

I/O

U5

W8

A10

A11

A12

A13

A14

A15

A16

A17

A18

A19

A20

B1

I/O

M3

I/O

U6

V_CC

I/O

W9

I/O

NC

I/O

M4

U7

W10

W11

W12

W13

W14

W15

W16

W17

W18

W19

W20

Y1

NC

I/O

VSS

I/O

G2

M17

M18

M19

M20

N1

U8

G3

U9

I/O

V_CC

I/O

G4

U10

U11

U12

U13

U14

U15

U16

U17

U18

U19

U20

V1

G17

G18

G19

G20

H1

I/O

NC

I/O

VSS

I/O

N2

I/O

N3

I/O

VSS

I/O

V_CC

I/O

D2

N4

I/O

D3

H2

N17

N18

N19

N20

P1

D4

H3

I/O

VSS

I/O

VSS

I/O

B2

D5

H4

I/O

B3

D6

H17

H18

H19

H20

J1

Y2

I/O

B4

D7

Y3

I/O

B5

D8

P2

Y4

I/O

NC

I/O

B6

D9

P3

V2

Y5

B7

D10

D11

D12

D13

D14

D15

D16

D17

D18

D19

D20

E1

I/O

P4

I/O

V3

Y6

I/O

B8

J2

P17

P18

P19

P20

R1

V4

Y7

NC

I/O

B9

J3

V5

Y8

NC

I/O

B10

B11

B12

B13

B14

B15

B16

B17

B18

B19

B20

C1

J4

V6

Y9

NC

I/O

J17

J18

J19

J20

K1

V7

Y10

Y11

Y12

Y13

Y14

Y15

Y16

Y17

Y18

Y19

Y20

NC

I/O

V8

I/O

R2

V9

I/O

GCLK / I

I/O

R3

V10

V11

V12

V13

V14

V15

V16

V17

V18

V19

V_CC

I/O

R4

I/O

V_CCIO

I/O

K2

R17

R18

R19

R20

T1

I/O

K3

K4

V_CC

I

I/O

E2

K17

K18

K19

K20

L1

ACLK / I

I

NC

I/O

E3

I/O

E4

T2

NC

I

I/O

C2

E17

E18

T3

NC

TMS

C3

T4

•

www.quicklogic.com

16

QL3025 pASIC 3 FPGA Data Sheet Rev E

Contact Information

Telephone: 408 990 4000 (US)

416 497 8884 (Canada)

44 1932 57 9011 (Europe)

49 89 930 86 170 (Germany)

852 8106 9091 (Asia)

81 45 470 5525 (Japan)

info@quicklogic.com

E-mail:

Support:

Web site:

support@quicklogic.com

http://www.quicklogic.com/

Revision History

Table 12: Revision History

Revision

Date

Comments

First release.

A

B

C

D

not avail.

not avail

May 2001

Update of AC/DC Specs and reformat

Added Kfactor, Power-up, JTAG and mechanical

drawing information. Reformatted.

E

June 2002

Copyright Information

The information contained in this product brief, and the accompanying software programs

are protected by copyright. All rights are reserved by QuickLogic Corporation. QuickLogic

Corporation reserves the right to make periodic modifications of this product without

obligation to notify any person or entity of such revision. Copying, duplicating, selling, or

otherwise distributing any part of this product without the prior written consent of an

authorized representative of QuickLogic is prohibited.

QuickLogic, QuickWorks, pASIC, and ViaLink are registered trademarks of QuickLogic

Corporation.

Verilog is a registered trademark of Cadence Design Systems, Inc.

All trademarks and registered trademarks are the property of their respective owners.

•

www.quicklogic.com

17


型号：	QL30252PQ208M
厂家：	ETC
描述：	25,000 Usable PLD Gate pASIC 3 FPGA Combining High Performance and High Density 25000可使用的PLD门pASIC 3 FPGA结合高性能和高密度栅
文件：	总17页 (文件大小：532K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

QL30252PQ208M [ETC]

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