QL3040-1PQ208I [ETC]
Field Programmable Gate Array (FPGA) ; 现场可编程门阵列(FPGA)的\n型号: | QL3040-1PQ208I |
厂家: | ETC |
描述: | Field Programmable Gate Array (FPGA)
|
文件: | 总10页 (文件大小:221K) |
中文: | 中文翻译 | 下载: | 下载PDF数据表文档文件 |
QL3040 - pASIC 3 FPGATM
40,000 Usable PLD Gate pASIC 3 FPGA Combining High Performance and High Density
QL3040 - pASIC 3 FPGA
D
EVICE
H
IGHLIGHTS
Device Highlights
Device Highlights
High Performance & High Density
■ 40,000 Usable PLD Gates with 252 I/Os
■ 16-bit counter speeds over 300 MHz, data path speeds over
400 MHz
■ 0.35um four-layer metal non-volatile CMOS process for
smallest die sizes
Easy to Use / Fast Development Cycles
■ 100% routable with 100% utilization and complete
pin-out stability
■ Variable-grain logic cells provide high performance and
100% utilization
■ Comprehensive design tools include high quality
Verilog/VHDL synthesis
FIGURE 1. 1,008 Logic Cells
Advanced I/O Capabilites
■ Interfaces with both 3.3V and 5.0V devices
■ PCI compliant with 3.3V and 5.0V buses for -1/-2/-3/-4
speed grades
P
RODUCT
S
UMMARY
■ Full JTAG boundary scan
Product Summary
■ Registered I/O cells with individually controlled clocks and
The QL3040 is a 40,000 usable PLD gate member of
the pASIC 3 family of FPGAs. pASIC 3 FPGAs are
fabricated on a 0.35mm four-layer metal process
using QuickLogic’s patented ViaLink technology to
provide a unique combination of high performance,
high density, low cost, and extreme ease-of-use.
output enables
Total of 252 I/O Pins
■ 244 bidirectional input/output pins, PCI-compliant for 5.0V and
3.3V buses for -1/-2/-3/-4 speed grades
■ 8 high-drive input/distributed network pins
The QL3040 contains 1,008 logic cells. With a
maximum of 252 I/Os, the QL3040 is available in
208-PQFP and 456-pin PBGA packages.
Eight Low-Skew Distributed Networks
■ Two array clock/control networks available to the logic cell flip-
flop clock, set and reset inputs - each driven by an input-only pin
■ Six global clock/control networks available to the logic cell F1,
clock set and reset inputs and the input and I/O register clock,
reset and enable inputs as well as the output enable control - each
driven by an input-only or I/O pin, or any logic cell output or I/O
cell feedback
Software support for the complete pASIC 3 family,
including the QL3040, is available through three basic
packages. The turnkey QuickWorks“ package
provides the most complete FPGA software solution
from design entry to logic synthesis, to place and
route, to simulation. The QuickChipTM and
QuickToolsTM packages provide a solution for
designers who use Cadence, Exemplar, Mentor,
Synopsys, Synplicity, Viewlogic, Veribest, or other
third-party tools for design entry, synthesis, or
simulation.
High Performance
■ Input + logic cell + output total delays under 6 ns
■ Data path speeds over 400 MHz
■ Counter speeds over 300 MHz
QL3040 Rev D
8-267
QL3040 - pASIC 3 FPGATM
208-PIN PQFP PINOUT
D
IAGRAM
208-Pin PQFP Pinout Diagrams
Pin #157
Pin #1
pASIC
QL3040-1PQ208C
Pin #53
Pin #105
FIGURE 2. 208-Pin PQFP
8-268
2
QL3040 - pASIC 3 FPGATM
208 PQFP PINOUT
TABLE
208 PQFP Pinout Table
208
Function
208
Function
208
Function
208
Function
208
Function
PQFP
PQFP
PQFP
PQFP
125
126
127
128
NC
PQFP
208
1
I/O
I/O
43
44
45
46
47
48
NC
49
50
51
52
53
54
NC
NC
55
56
NC
57
58
59
60
61
62
63
64
NC
65
66
67
NC
68
69
70
NC
71
NC
72
73
74
NC
75
76
77
78
79
80
81
82
83
GND
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
TDI
I/O
I/O
I/O
I/O
I/O
I/O
I/O
GND
I/O
VCC
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
GND
I/O
VCC
I/O
I/O
I/O
GND
I/O
I/O
I/O
I/O
VCCIO
84
85
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
GND
I/O
VCC
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
TRSTB
TMS
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
VCC
I/O
GND
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
168
169
NC
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
GND
I/O
I/O
I/O
I/O
I/O
GND
VCC
I/O
I/O
I/O
I/O
VCCIO
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
GND
I/O
VCC
I/O
I/O
I/O
I/O
I/O
TDO
2
I/O
86
GND
I/O
3
I/O
87
170
171
172
173
174
175
NC
4
I/O
88
I/O
5
I/O
89
129
130
131
132
133
134
135
136
NC
GCLK/I
ACLK/I
VCC
GCLK/I
GCLK/I
VCC
I/O
NC
6
I/O
90
I/O
91
7
I/O
92
8
I/O
NC
93
9
I/O
176
177
178
179
NC
10
11
12
13
14
NC
15
16
17
18
19
20
NC
21
22
23
24
25
26
27
28
29
30
31
32
NC
33
NC
34
35
36
NC
37
38
39
NC
40
41
42
VCC
I/O
94
95
I/O
GND
I/O
96
I/O
97
137
NC
I/O
I/O
98
GND
I/O
180
181
182
NC
I/O
99
138
139
140
141
142
NC
I/O
100
NC
101
NC
102
NC
NC
103
104
105
NC
106
107
108
109
NC
110
111
112
113
114
115
116
117
NC
118
119
120
121
NC
122
123
124
I/O
I/O
I/O
I/O
I/O
183
184
185
186
187
188
NC
I/O
I/O
I/O
I/O
I/O
143
144
145
NC
I/O
I/O
I/O
I/O
VCC
I/O
I/O
GND
I/O
146
147
148
149
150
151
152
153
154
155
156
157
158
NC
I/O
189
190
191
192
193
194
NC
GND
I/O
GCLK/I
GCLK/I
VCC
GCLK/I
GCLK/I
VCC
I/O
I/O
I/O
I/O
I/O
I/O
195
196
197
198
NC
I/O
I/O
I/O
GND
I/O
I/O
TCK
STM
I/O
I/O
199
200
201
202
203
204
205
206
207
I/O
I/O
159
160
161
162
163
164
165
166
NC
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
GND
I/O
I/O
I/O
VCC
I/O
I/O
VCC
I/O
I/O
167
I/O
8-269
QL3040 - pASIC 3 FPGATM
456-PIN PBGA
P
INOUT
DIAGRAM
456-Pin PBGA Pinout Diagram
pASIC
QL3040-1PB456C
TOP
Pin A1 Corner
20 18
19
16
14
12
10
8
6
4
2
17
15
13
11
9
7
5
3
1
A
B
C
D
E
F
G
H
J
K
L
M
N
P
R
T
U
V
W
Y
BOTTOM
8-270
2
QL3040 - pASIC 3 FPGATM
PBGA 456 PINOUT
TABLE
PBGA 456 Pinout Table
456
Function
456
Function
456
Function
456
Function
456
Function
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10
A11
A12
A13
A14
A15
A16
A17
A18
A19
A20
A21
A22
A23
A24
A25
A26
B1
B2
B3
B4
B5
B6
B7
B8
B9
B10
B11
B12
B13
B14
B15
B16
B17
B18
B19
B20
B21
B22
B23
B24
B25
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
NC
I/O
I/O
VCCIO
I/O
I/O
NC
I/O
NC
I/O
I/O
I/O
NC
I/O
NC
I/O
I/O
I/O
I/O
NC
I/O
NC
NC
NC
NC
NC
I/O
NC
NC
I/O
I/O
NC
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
NC
I/O
I/O
B26
C1
C2
C3
C4
C5
C6
C7
C8
STM
I/O
I/O
I/O
TDO
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
NC
NC
I/O
I/O
I/O
I/O
I/O
I/O
TCK
NC
I/O
I/O
I/O
GND
NC
NC
I/O
I/O
GND
I/O
D25
D26
E1
E2
E3
E4
E5
E6
E7
I/O
I/O
I/O
I/O
I/O
H4
H5
I/O
NC
NC
NC
I/O
NC
I/O
I/O
I/O
I/O
NC
GND
NC
NC
I/O
I/O
I/O
NC
NC
I/O
I/O
VCC
GND
I/O
I/O
NC
I/O
I/O
I/O
I/O
I/O
NC
M14
M15
M16
M22
M23
M24
M25
M26
N1
N2
N3
N4
N5
N11
N12
N13
N14
N15
N16
N22
N23
N24
N25
N26
P1
GND/THERM
GND/THERM
GND/THERM
NC
NC
I/O
I/O
I/O
GCLK/I
I/O
I/O
GCLK/I
VCC
GND/THERM
GND/THERM
GND/THERM
GND/THERM
GND/THERM
GND/THERM
GND
H22
H23
H24
H25
H26
J1
J2
J3
J4
J5
J22
J23
J24
J25
J26
K1
K2
K3
K4
K5
K22
K23
K24
K25
K26
L1
L2
L3
L4
L5
L11
L12
L13
L14
L15
L16
L22
L23
L24
L25
L26
M1
M2
M3
M4
M5
M11
M12
M13
I/O
GND
VCC
GND
NC
GND
I/O
GND
GND
VCC
GND
GND
GND
NC
GND
NC
GND
VCC
GND
I/O
I/O
I/O
I/O
I/O
I/O
NC
NC
VCC
VCC
NC
I/O
I/O
I/O
I/O
I/O
I/O
C9
E8
E9
C10
C11
C12
C13
C14
C15
C16
C17
C18
C19
C20
C21
C22
C23
C24
C25
C26
D1
D2
D3
D4
D5
D6
D7
D8
D9
D10
D11
D12
D13
D14
D15
D16
D17
D18
D19
D20
D21
D22
D23
D24
E10
E11
E12
E13
E14
E15
E16
E17
E18
E19
E20
E21
E22
E23
E24
E25
E26
F1
F2
F3
F4
F5
F22
F23
F24
F25
F26
G1
I/O
I/O
NC
I/O
I/O
I/O
NC
I/O
P2
P3
P4
P5
NC
P11
P12
P13
P14
P15
P16
P22
P23
P24
P25
P26
R1
R2
R3
R4
R5
R11
R12
R13
R14
R15
R16
GND/THERM
GND/THERM
GND/THERM
GND/THERM
GND/THERM
GND/THERM
NC
GCLK / I
GCLK / I
NC
ACLK / I
NC
I/O
I/O
NC
GND/THERM
GND/THERM
GND/THERM
GND/THERM
GND/THERM
GND/THERM
NC
I/O
I/O
NC
I/O
ACLK / I
GCLK/I
I/O
NC
GND
I/O
GND
I/O
I/O
GND
I/O
I/O
GND
I/O
NC
NC
I/O
GND
I/O
G2
G3
G4
G5
G22
G23
G24
G25
G26
H1
I/O
NC
GND
NC
I/O
I/O
I/O
NC
I/O
NC
GND/THERM
GND/THERM
GND/THERM
GND/THERM
GND/THERM
GND/THERM
GND/THERM
GND/THERM
GND/THERM
H2
H3
NC
(continued next page)
8-271
QL3040 - pASIC 3 FPGATM
PBGA 456 Pinout Table
(Continued from previous page)
456
Function
456
Function
456
Function
456
Function
R22
R23
R24
R25
R26
T1
T2
T3
T4
T5
T11
T12
T13
T14
T15
T16
T22
T23
T24
T25
T26
U1
U2
U3
U4
U5
U22
U23
U24
U25
U26
V1
VCC
NC
NC
I/O
GCLK / I
I/O
I/O
I/O
I/O
VCC
GND/THERM
GND/THERM
GND/THERM
GND/THERM
GND/THERM
GND/THERM
GND
I/O
Y1
Y2
Y3
Y4
Y5
Y22
Y23
Y24
NC
I/O
NC
I/O
I/O
GND
I/O
NC
I/O
I/O
I/O
I/O
NC
NC
VCC
VCC
NC
I/O
I/O
AC6
AC7
AC8
NC
NC
NC
NC
NC
I/O
AE5
AE6
AE7
AE8
AE9
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
NC
NC
TMS
I/O
I/O
I/O
NC
I/O
NC
I/O
I/O
I/O
I/O
I/O
I/O
NC
I/O
I/O
NC
NC
I/O
I/O
I/O
NC
I/O
I/O
I/O
I/O
I/O
I/O
I/O
AC9
AC10
AC11
AC12
AC13
AC14
AC15
AC16
AC17
AC18
AC19
AC20
AC21
AC22
AC23
AC24
AC25
AC26
AD1
AD2
AD3
AD4
AD5
AD6
AD7
AD8
AD9
AD10
AD11
AD12
AD13
AD14
AD15
AD16
AD17
AD18
AD19
AD20
AD21
AD22
AD23
AD24
AD25
AD26
AE1
AE10
AE11
AE12
AE13
AE14
AE15
AE16
AE17
AE18
AE19
AE20
AE21
AE22
AE23
AE24
AE25
AE26
AF1
AF2
AF3
AF4
AF5
AF6
AF7
AF8
AF9
AF10
AF11
AF12
AF13
AF14
AF15
AF16
AF17
AF18
AF19
AF20
AF21
AF22
AF23
AF24
AF25
AF26
NC
I/O
Y25
Y26
VCCIO
NC
NC
NC
NC
I/O
I/O
I/O
NC
GND
NC
I/O
I/O
I/O
NC
I/O
I/O
I/O
I/O
I/O
I/O
NC
I/O
NC
I/O
I/O
I/O
I/O
I/O
I/O
I/O
AA1
AA2
AA3
AA4
AA5
AA22
AA23
AA24
AA25
AA26
AB1
AB2
AB3
AB4
AB5
AB6
AB7
AB8
AB9
AB10
AB11
AB12
AB13
AB14
AB15
AB16
AB17
AB18
AB19
AB20
AB21
AB22
AB23
AB24
AB25
AB26
AC1
AC2
I/O
NC
I/O
NC
I/O
I/O
I/O
GND
NC
I/O
I/O
I/O
I/O
I/O
I/O
NC
NC
NC
GND
NC
I/O
NC
I/O
I/O
I/O
I/O
I/O
NC
NC
I/O
I/O
NC
I/O
I/O
I/O
GND
VCC
NC
NC
NC
VCC
GND
NC
V2
V3
V4
V5
I/O
GND
VCC
I/O
V22
V23
V24
V25
V26
W1
W2
W3
W4
W5
W22
W23
NC
VCC
GND
NC
VCC
GND
I/O
NC
I/O
I/O
I/O
NC
NC
I/O
I/O
TRSTB
NC
I/O
I/O
TDI
I/O
W24
W25
W26
I/O
I/O
NC
AC3
AC4
AC5
NC
GND
NC
AE2
AE3
AE4
I/O
I/O
I/O
Note: NC pins must be left unconnected on printed circuit board.
8-272
2
QL3040 - pASIC 3 FPGATM
Pin Descriptions
Pin Descriptions
P
IN
DESCRIPTIONS
Pin
Function
Description
TDI
Test Data In for JTAG
Hold HIGH during normal operation. Connect to
VCC if not used for JTAG.
TRSTB
TMS
TCK
Active low Reset for JTAG
Test Mode Select for JTAG
Test Clock for JTAG
Hold LOW during normal operation. Connect to
ground if not used for JTAG.
Hold HIGH during normal operation. Connect to
VCC if not used for JTAG.
Hold HIGH or LOW during normal operation.
Connect to VCC or ground if not used for JTAG.
TDO
Test data out for JTAG
Output that must be left unconnected if not used for
JTAG.
STM
Special Test Mode
Must be grounded during normal operation.
Can be configured as either or both.
I/ACLK
High-drive input and/or
array network driver
I/GCLK
High-drive input and/or
global network driver
Can be configured as either or both.
I
High-drive input
Use for input signals with high fanout.
Can be configured as an input and/or output.
Connect to 3.3V supply.
I/O
Input/Output pin
VCC
VCCIO
Power supply pin
Input voltage tolerance pin
Connect to 5.0 volt supply if 5 volt input tolerance is
required, otherwise connect to 3.3V supply.
GND
Ground pin
Connect to ground.
Ordering Information
QL 3040 - 1 PQ208 C
QuickLogic
pASIC device
Operating Range
C = Commercial
I = Industrial
pASIC 3 device
part number
*M = Military
Package Code
PQ208 = 208-pin PQFP
PB456 = 456-pin PBGA
Speed Grade
0 = quick
1 = fast
2 = faster
3 = faster
*4 = fastest
* Contact QuickLogic regarding availability.
8-273
QL3040 - pASIC 3 FPGATM
Absolute Maximum Ratings
VCC Voltage . . . . . . . . . . . . . . . . . . . -0.5 to 4.6V
DC Input Current . . . . . . . . . . . . . . . . . . . 20 mA
ESD Pad Protection . . . . . . . . . . . . . . . . . 2000V
Storage Temperature . . . . . . . . . -65°C to +150°C
Lead Temperature . . . . . . . . . . . . . . . . . . . 300°C
VCCIO Voltage . . . . . . . . . . . . . . . . . -0.5 to 7.0V
Input Voltage . . . . . . . . . . . . -0.5 to VCCIO +0.5V
Latch-up Immunity . . . . . . . . . . . . . . . . . 200 mA
Operating Range
Symbol
Parameter
Supply Voltage
Military
Industrial
Commercial
Unit
Min
Max
3.6
5.5
Min
3.0
3.0
-40
Max
3.6
5.5
85
Min
3.0
3.0
0
Max
3.6
5.25
70
VCC
3.0
3.0
-55
V
V
°C
°C
VCCIO I/O Input Tolerance Voltage
TA
TC
Ambient Temperature
Case Temperature
125
-0 Speed Grade
0.43 1.90
0.43 1.54
0.43 1.28
0.43 0.90
0.43 0.82
0.46
0.46
0.46
0.46
0.46
1.85
1.50
1.25
0.88
0.80
K
Delay Factor
-1 Speed Grade
-2 Speed Grade
-3 Speed Grade
-4 Speed Grade
0.42
0.42
N/A
N/A
1.64
1.37
N/A
N/A
DC Characteristics
Symbol
VIH
VIL
Parameter
Input HIGH Voltage
Input LOW Voltage
Output HIGH Voltage
Conditions
Min
Max
Unit
V
V
V
V
0.5VCC VCCIO+0.5
-0.5
2.4
0.3VCC
VOH
IOH = -12 mA
IOH = -500 µA
IOL = 16 mA [1]
IOL = 1.5 mA
0.9VCC
VOL
Output LOW Voltage
0.45
0.1VCC
10
10
10
-180
210
2
V
V
II
IOZ
CI
I or I/O Input Leakage Current
3-State Output Leakage Current VI = VCCIO or GND
Input Capacitance [2]
VI = VCCIO or GND
-10
-10
µA
µA
pF
mA
mA
mA
µA
IOS
Output Short Circuit Current [3]
VO = GND
VO = VCC
VI, VIO = VCCIO or GND 0.50 (typ)
0
-15
40
ICC
ICCIO
D.C. Supply Current [4]
D.C. Supply Current on VCCIO
100
Notes:
[1] Applies only to -1/-2/-3/-4 commercial grade devices. These speed grades are also PCI-compliant. All
other devices have 8 mA IOL specifications.
[2] Capacitance is sample tested only. Clock pins are 12 pF maximum.
[3] Only one output at a time. Duration should not exceed 30 seconds.
[4] For -1/-2/-3/-4 commercial grade devices only. Maximum ICC is 3 mA for -0 commercial grade and all
industrial grade devices, and 5 mA for all military grade devices. For AC conditions, contact QuickLogic
customer engineering.
8-274
2
QL3040 - pASIC 3 FPGATM
AC Characteristics at VCC = 3.3V, TA = 25°C (K = 1.00)
(To calculate delays, multiply the appropriate K factor in the "Operating Range" section by the following numbers.)
Logic Cells
Propagation Delays (ns)
Symbol
tPD
tSU
tH
tCLK
tCWHI
tCWLO
tSET
tRESET
tSW
Parameter
Fanout [5]
3
1
2
4
8
Combinatorial Delay [6]
Setup Time [6]
Hold Time
Clock to Q Delay
Clock High Time
Clock Low Time
Set Delay
Reset Delay
Set Width
Reset Width
1.4
1.7
0.0
0.7
1.2
1.2
1.0
0.8
1.9
1.8
1.7
1.7
0.0
1.0
1.2
1.2
1.3
1.1
1.9
1.8
1.9
1.7
0.0
1.2
1.2
1.2
1.5
1.3
2.2
1.7
0.0
1.5
1.2
1.2
1.8
1.6
1.9
1.8
3.2
1.7
0.0
2.5
1.2
1.2
2.8
2.6
1.9
1.8
1.9
1.8
tRW
Input-Only/Clock Cells
Propagation Delays (ns)
Symbol
Parameter
Fanout [5]
1
2
3
4
8
12
24
tIN
tINI
High Drive Input Delay
High Drive Input, Inverting Delay
Input Register Set-Up Time
Input Register Hold Time
Input Register Clock To Q
Input Register Reset Delay
Input Register clock Enable Set-Up Time
Input Register Clock Enable Hold Time
1.5
1.6
3.1
0.0
0.7
0.6
2.3
0.0
1.6
1.7
3.1
0.0
0.8
0.7
2.3
0.0
1.8
1.9
3.1
0.0
1.0
0.9
2.3
0.0
1.9
2.0
3.1
0.0
1.1
1.0
2.3
0.0
2.4
2.5
3.1
0.0
1.6
1.5
2.3
0.0
2.9 4.4
3.0 4.5
3.1 3.1
0.0 0.0
2.1 3.6
2.0 3.5
2.3 2.3
0.0 0.0
tISU
tIH
tlCLK
tlRST
tlESU
tlEH
Notes:
[5] Stated timing for worst case Propagation Delay over process variation at VCC=3.3V and TA=25×C. Multi-
ply by the appropriate Delay Factor, K, for speed grade, voltage and temperature settings as specified in the
Operating Range.
[6] These limits are derived from a representative selection of the slowest paths through the pASIC 3 logic cell
including typical net delays. Worst case delay values for specific paths should be determined from timing
analysis of your particular design.
8-275
QL3040 - pASIC 3 FPGATM
Clock Cells
Propagation Delays (ns)
Loads per Half Column [7]
Symbol
Parameter
Array Clock Delay
Global Clock Pin Delay
Global Clock Buffer Delay
1
2
3
4
8
10
1.6
0.7
1.2
11
1.7
0.7
1.3
tACK
tGCKP
tGCKB
1.2
0.7
0.8
1.2
0.7
0.8
1.3
0.7
0.9
1.3
0.7
0.9
1.5
0.7
1.1
I/O Cells
Propagation Delays (ns)
Symbol
Parameter
Fanout [5]
1
2
3
4
8
10
tI/O
tISU
tIH
tlOCLK
tlORST
tlESU
tlEH
Input Delay (bidirectional pad)
Input Register Set-Up Time
Input Register Hold Time
Input Register Clock To Q
Input Register Reset Delay
1.3
3.1
0.0
0.7
0.6
2.3
0.0
1.6
3.1
0.0
1.0
0.9
2.3
0.0
1.8
3.1
0.0
1.2
1.1
2.3
0.0
2.1
3.1
0.0
1.5
1.4
2.3
0.0
3.1
3.1
0.0
2.5
2.4
2.3
0.0
3.6
3.1
0.0
3.0
2.9
2.3
0.0
Input Register clock Enable Set-Up Time
Input Register Clock Enable Hold Time
Propagation Delays (ns)
Symbol
Parameter
Output Load Capacitance (pF)
30
2.1
2.2
1.2
1.6
2.0
1.2
50
2.5
2.6
1.7
2.0
75
3.1
3.2
2.2
2.6
100
3.6
3.7
2.8
3.1
150
4.7
4.8
3.9
4.2
tOUTLH
tOUTHL
tPZH
tPZL
tPHZ
Output Delay Low to High
Output Delay High to Low
Output Delay Tri-state to High
Output Delay Tri-state to Low
Output Delay High to Tri-State [8]
Output Delay Low to Tri-State [8]
tPLZ
Notes:
[7] The array distributed networks consist of 40 half columns and the global distributed networks consist of 44
half columns, each driven by an independent buffer. The number of half columns used does not affect clock
buffer delay. The array clock has up to 8 loads per half column. The global clock has up to 11 loads per half
column.
[8] The following loads are used for tPXZ:
tPHZ
1KΩ
5 pF
1KΩ
tPLZ
5 pF
8-276
2
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