QL4036-2PF144M [ETC]
Field Programmable Gate Array (FPGA) ; 现场可编程门阵列（FPGA）的\n
| 型号： | QL4036-2PF144M |
| 厂家： | 
ETC |
| 描述： | Field Programmable Gate Array (FPGA)
|
| 文件： | 总12页 (文件大小：199K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
QL4036 - QuickRAMTM
36,000 Usable PLD Gate QuickRAM ESP Combining Performance, Density, and Embedded RAM
QL4036 - QuickRAM
D
EVICE
HIGHLIGHTS
Device Highlights
High Performance & High Density
■ 36,000 Usable PLD Gates with 204 I/Os
672
High Speed
Logic Cells
14 RAM
Blocks
}
■ 300 MHz 16-bit Counters, 400 MHz Datapaths,
160+ MHz FIFOs
■ 0.35µm four-layer metal non-volatile CMOS process for
smallest die sizes
Interface
FIGURE 1. QuickRAM Block Diagram
High Speed Embedded SRAM
■ 14 dual-port RAM modules, organized in user-config-
urable 1,152 bit blocks
A
RCHITECTURE
O
VERVIEW
■ 5ns access times, each port independently accessible
■ Fast and effecient for FIFO, RAM, and ROM functions
Architecture Overview
The QuickRAM family of ESPs (Embedded Standard
Products) offers FPGA logic in combination with Dual-
Port SRAM modules. The QL4036 is a 36,000
usable PLD gate member of the QuickRAM family of
ESPs. QuickRAM ESPs are fabricated on a 0.35mm
four-layer metal process using QuickLogic’s patented
ViaLinkTM technology to provide a unique combina-
tion of high performance, high density, low cost, and
extreme ease-of-use.
Easy to Use / Fast Development Cycles
■ 100% routable with 100% utilization and complete
pin-out stability
■ Variable-grain logic cells provide high performance and
100% utilization
■ Comprehensive design tools include high quality
Verilog/VHDL synthesis
The QL4036 contains 672 logic cells and 14 dual
port RAM modules (see Figure 1). Each RAM module
has 1,152 RAM bits, for a total of 16,128 bits. RAM
Modules are Dual Port (one read port, one write port)
and can be configured into one of four modes: 64
(deep) x18 (wide), 128x9, 256x4, or 512x2 (see Fig-
ure 2). With a maximum of 204 I/Os, the QL4036 is
available in 144-pin TQFP, 208-pin PQFP and 256-
pin PBGA packages.
Advanced I/O Capabilities
■ Interfaces with both 3.3V and 5.0V devices
■ PCI compliant with 3.3V and 5.0V busses for -1/-2/-3/-4
speed grades
■ Full JTAG boundary scan
■ Registered I/O cells with individually controlled clocks and
output enables
Designers can cascade multiple RAM modules to
increase the depth or width allowed in single modules
by connecting corresponding address lines together
and dividing the words between modules (see Figure
3). This approach allows up to 512-deep configura-
tions as large as 16 bits wide in the smallest Quick-
RAM device and 44 bits wide in the largest device.
6-31
QL4036 Rev F
QL4036 - QuickRAMTM
P
RODUCT
S
UMMARY
Product Summary
Product Summary
Total of 204 I/O Pins
■ 196 bi-directional input/output pins, PCI-compliant for
5.0 volt and 3.3 volt buses for -1/-2/-3/-4 speed grades
■ 8 high-drive input/distributed network pins
Eight Low-Skew Distributed Networks
■ Two array clock/controlnetworks available to the logic
cell flip-flop clock, set and reset inputs - each driven by
and input-only pin
■ Six global clock/control networks available to the logic
cell F1, clock, set and reset inputs and the input and I/O
register clock, reset and enable inputs as well as the out-
put enable control - each driven by an input-only or I/O
pin, or any logic cell output or I/O cell feedback
FIGURE 2. QuickRAM Module
Software support for the complete QuickRAM fam-
ily, including the QL4016, is available through two
basic packages. The turnkey QuickWorksTM pack-
age provides the most complete ESP software solu-
tion from design entry to logic synthesis, to place and
route, to simulation. The QuickToolsTM packages
provides a solution for designers who use Cadence,
Exemplar, Mentor, Syn-opsys, Synplicity, Viewlogic,
Veribest, or other third-party tools for design entry,
synthesis, or simulation.
High Performance
■ Input + logic cell + output total delays under 6 ns
■ Data path speeds over 400 MHz
■ Counter speeds over 300 MHz
■ FIFO speeds over 160+ MHz
The QuickLogic variable grain logic cell features up
to 16 simultaneous inputs and 5 outs within a cell
that can be fragmented into 5 independent cells.
Each cell has a fan-in of 29 including register and
control lines (see Figure 4).
QS
A1
A2
A3
AZ
A4
A5
A6
OS
OP
B1
B2
OZ
C1
C2
MP
WDATA
WADDR
RDATA
RADDR
RAM
Module
(1,152 bits)
MS
QZ
D1
D2
E1
E2
NP
NS
NZ
FZ
F1
F2
F3
F4
F5
F6
QC
QR
RAM
Module
(1,152 bits)
WDATA
RDATA
FIGURE 4. Logic Cell
FIGURE 3. QuickRAM Module bits
6-32
QL4036 - QuickRAMTM
Pin #109
Pin #1
QuickRAM
QL4036-1PF144C
Pin #73
Pin #37
Pin #1
144 Pin TQFP
Pinout Diagram
Pin #157
QuickRAM
QL4036-1PQ208C
Pin #105
Pin #53
208 Pin PQFP/CQFP
Pinout Diagram
6-33
QL4036 - QuickRAMTM
208 PQFP & 144 TQFP
P
INOUT
TABLE
208 PQFP and 144 TQFP Pinout Table
208
144
Function
208
144
Function
208
144
Function
208
144
Function
208
144
Function
PQFP TQFP
PQFP TQFP
PQFP TQFP
PQFP TQFP
PQFP TQFP
1
NC
1
I/O
I/O
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
30
31
NC
32
NC
33
NC
34
35
36
37
38
39
NC
40
NC
NC
41
42
43
NC
44
45
NC
46
47
48
NC
49
NC
50
51
52
NC
53
54
55
56
NC
57
58
59
GND
I/O
85
86
60
61
I/O
I/O
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
87
88
GND
I/O
169
170
171
172
173
174
175
176
177
178
179
180
181
182
183
184
185
186
187
188
189
190
191
192
193
194
195
196
197
198
199
200
201
202
203
204
205
206
207
208
117
118
119
120
NC
I/O
I/O
2
3
2
I/O
I/O
87
NC
62
I/O
89
GCLK / I
ACLK / I
VCC
GCLK / I
GCLK / I
VCC
I/O
I/O
4
3
I/O
I/O
88
I/O
90
I/O
5
NC
4
I/O
I/O
89
63
I/O
91
I/O
6
I/O
I/O
90
NC
NC
64
I/O
92
NC
I/O
7
5
I/O
I/O
91
I/O
93
121
NC
I/O
8
NC
6
I/O
I/O
92
I/O
94
I/O
9
I/O
I/O
93
NC
65
I/O
95
122
123
124
NC
GND
I/O
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
7
VCC
I/O
I/O
94
I/O
NC
96
I/O
NC
NC
8
I/O
95
66
GND
I/O
I/O
I/O
GND
I/O
TDI
I/O
96
67
NC
97
I/O
I/O
97
NC
NC
68
VCC
I/O
I/O
125
126
127
128
129
NC
I/O
NC
9
I/O
I/O
98
98
I/O
GND
I/O
I/O
I/O
99
I/O
NC
99
I/O
NC
10
11
12
13
NC
14
15
16
17
18
19
20
21
22
23
NC
24
NC
25
NC
26
27
28
NC
NC
29
I/O
I/O
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
69
I/O
I/O
I/O
I/O
GND
I/O
NC
70
I/O
NC
100
NC
101
102
103
104
NC
105
106
NC
107
NC
108
109
110
111
NC
112
113
NC
NC
114
115
116
NC
I/O
I/O
I/O
I/O
I/O
I/O
I/O
VCC
I/O
71
TRSTB
TMS
I/O
VCC
I/O
130
131
132
NC
VCCIO
I/O
I/O
72
I/O
I/O
NC
73
GND
I/O
I/O
I/O
I/O
I/O
I/O
GND
I/O
I/O
NC
74
I/O
I/O
133
134
NC
I/O
I/O
I/O
I/O
I/O
GCLK / I
ACLK / I
VCC
GCLK / I
GCLK / I
VCC
I/O
I/O
75
I/O
I/O
I/O
I/O
76
I/O
I/O
135
136
NC
I/O
I/O
77
I/O
I/O
I/O
I/O
NC
78
I/O
I/O
I/O
I/O
I/O
I/O
137
NC
I/O
I/O
79
VCC
I/O
I/O
I/O
GND
I/O
80
TCK
STM
I/O
138
139
NC
GND
I/O
I/O
NC
81
GND
I/O
I/O
I/O
VCC
I/O
I/O
I/O
82
I/O
I/O
140
NC
I/O
I/O
NC
83
I/O
I/O
I/O
I/O
GND
I/O
I/O
I/O
141
142
NC
I/O
I/O
NC
84
I/O
GND
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
85
I/O
VCC
I/O
143
144
TDO
I/O
I/O
I/O
NC
86
I/O
VCC
I/O
VCCIO
I/O
I/O
I/O
NC
I/O
I/O
TABLE 1: 208 PQFP and 144 TQFP Pinout Table
6-34
QL4036 - QuickRAMTM
P
INOUT
DIAGRAM
Pinout Diagram
QuickRAM
QL4036-1PB256C
256 Pin PBGA
TOP
Pin A1 Corner
20 18
19
16 14
17 15
12
10
8
6
4
2
13
11
9
7
5
3
1
A
B
C
D
E
F
G
H
J
K
L
M
N
P
R
T
U
V
W
Y
Bottom
PBGA 256 Pinout Table
6-35
QL4036 - QuickRAMTM
PBGA 256 PINOUT
TABLE
256
Function
256
Function
256
Function
256
Function
256
Function
256
Function
PBGA
PBGA
PBGA
PBGA
PBGA
PBGA
A1
A2
VSS
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
TCK
I/O
TDO
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
NC
STM
NC
I/O
I/O
I/O
I/O
C4
C5
I/O
I/O
E19
E20
F1
I/O
I/O
L2
L3
ACLK / I
GCLK / I
GCLK / I
VCC
I/O
T17
T18
T19
T20
U1
I/O
I/O
V20
W1
W2
W3
W4
W5
W6
W7
W8
W9
W10
W11
W12
W13
W14
W15
W16
W17
W18
W19
W20
Y1
I/O
I/O
I/O
TDI
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
TRSTB
I/O
NC
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
NC
A3
C6
I/O
I/O
L4
NC
I/O
A4
C7
I/O
F2
I/O
L17
L18
L19
L20
M1
M2
M3
M4
M17
M18
M19
M20
N1
A5
C8
I/O
F3
I/O
I/O
A6
C9
VCCIO
I/O
F4
VCC
VCC
NC
I/O
U2
I/O
A7
C10
C11
C12
C13
C14
C15
C16
C17
C18
C19
C20
D1
F17
F18
F19
F20
G1
I/O
U3
I/O
A8
I/O
I/O
U4
VSS
I/O
A9
I/O
I/O
I/O
U5
A10
A11
A12
A13
A14
A15
A16
A17
A18
A19
A20
B1
I/O
I/O
I/O
U6
VCC
I/O
I/O
I/O
NC
U7
I/O
G2
NC
NC
U8
VSS
I/O
I/O
G3
I/O
I/O
U9
I/O
G4
I/O
I/O
U10
U11
U12
U13
U14
U15
U16
U17
U18
U19
U20
V1
VCC
I/O
I/O
G17
G18
G19
G20
H1
I/O
I/O
I/O
I/O
I/O
I/O
I/O
NC
N2
I/O
VSS
I/O
I/O
I/O
N3
I/O
D2
I/O
I/O
N4
VSS
VSS
I/O
VCC
I/O
D3
I/O
H2
I/O
N17
N18
N19
N20
P1
D4
VSS
I/O
H3
I/O
VSS
I/O
B2
D5
H4
VSS
VSS
I/O
I/O
B3
D6
VCC
I/O
H17
H18
H19
H20
J1
I/O
I/O
Y2
B4
D7
I/O
I/O
Y3
B5
D8
VSS
I/O
I/O
P2
I/O
I/O
Y4
B6
D9
I/O
P3
I/O
V2
NC
I/O
Y5
B7
D10
D11
D12
D13
D14
D15
D16
D17
D18
D19
D20
E1
I/O
I/O
P4
I/O
V3
Y6
B8
VCC
I/O
J2
I/O
P17
P18
P19
P20
R1
I/O
V4
I/O
Y7
B9
J3
NC
I/O
V5
I/O
Y8
B10
B11
B12
B13
B14
B15
B16
B17
B18
B19
B20
C1
VSS
I/O
J4
I/O
NC
V6
I/O
Y9
J17
J18
J19
J20
K1
NC
I/O
V7
I/O
Y10
Y11
Y12
Y13
Y14
Y15
Y16
Y17
Y18
Y19
Y20
VCC
I/O
I/O
NC
V8
I/O
I/O
R2
I/O
V9
I/O
VSS
I/O
GCLK / I
I/O
R3
I/O
V10
V11
V12
V13
V14
V15
V16
V17
V18
V19
I/O
R4
VCC
VCC
I/O
I/O
I/O
K2
I/O
R17
R18
R19
R20
T1
VCCIO
I/O
I/O
K3
I/O
NC
I/O
K4
VCC
GCLK / I
ACLK / I
GCLK / I
NC
I/O
I/O
E2
K17
K18
K19
K20
L1
I/O
I/O
E3
I/O
NC
I/O
E4
I/O
T2
I/O
I/O
C2
E17
E18
I/O
T3
I/O
I/O
C3
I/O
GCLK / I
T4
NC
TMS
6-36
QL4036 - QuickRAMTM
P
IN
D
ESCRIPTION
Pin Description
Pin
Function
Description
Hold HIGH during normal operation. Connects to serial
PROM data in for RAM initialization. Connect to VCC if
unused.
TDI/RSI
Test Data In for JTAG /
RAM init. Serial Data In
Hold LOW during normal operation. Connects to serial
PROM reset for RAM initialization. Connect to GND if
unused.
TRSTB/RRO
Active low Reset for JTAG /
RAM init. reset out
Hold HIGH during normal operation. Connect to VCC if
not used for JTAG.
TMS
Test Mode Select for JTAG
Test Clock for JTAG
Hold HIGH or LOW during normal operation. Connect to
VCC or ground if not used for JTAG.
TCK
Connect to serial PROM clock for RAM initialization. Must
be left unconnected if not used for JTAG or RAM
initialization.
TDO/RCO
Test data out for JTAG /
RAM init. clock out
Must be grounded during normal operation.
Can be configured as either or both.
STM
Special Test Mode
I/ACLK
High-drive input and/or
array network driver
Can be configured as either or both.
I/GCLK
High-drive input and/or
global network driver
Use for input signals with high fanout.
Can be configured as an input and/or output.
Connect to 3.3V supply.
I
High-drive input
I/O
Input/Output pin
VCC
VCCIO
Power supply pin
Connect to 5.0 volt supply if 5 volt input tolerance is
required, otherwise connect to 3.3V supply.
Input voltage tolerance pin
Connect to ground.
GND
Ground pin
Available on 456-PBGA only. Connect to ground plane on
PCB if heat sinking desired. Otherwise may be left
unconnected.
GND/THERM
Ground/Thermal pin
Ordering Information
QL 4036 - 1 PQ208 C
QuickLogic
device
Operating Range
C = Commercial
I = Industrial
QuickRAM device
part number
M = Military
Speed Grade
0 = quick
1 = fast
2 = faster
3 = faster
*4 = wow
Package Code
PF144 = 144-pin TQFP
CF208 = 208-pin CQFP
PQ208 = 208-pin PQFP
PB256 = 256-pin PBGA
* Contact QuickLogic regarding availability.
6-37
QL4036 - QuickRAMTM
Absolute Maximum Ratings
VCC Voltage..................................-0.5 to 4.6V
DC Input Current.................................. 20 mA
ESD Pad Protection.............................. 2000V
Storage Temperature .............. -65°C to +150°C
Lead Temperature ........................... .......300°C
VCCIO Voltage...................................-0.5 to 7.0V
Input Voltage .........................-0.5 to VCCIO+0.5V
Latch-up Immunity .................................. 200mA
Operating Range
Symbol
Parameter
Supply Voltage
Military
Industrial
Commercial
Unit
Min
Max
3.6
5.5
Min
3.0
3.0
-40
Max
3.6
5.5
85
Min
3.0
3.0
0
Max
3.6
5.25
70
VCC
3.0
3.0
-55
V
V
°C
°C
VCCIO I/O Input Tolerance Voltage
TA
TC
Ambient Temperature
Case Temperature
125
2.03
1.64
1.37
N/A
-0 Speed Grade
0.42
0.42
0.42
N/A
0.43 1.90
0.43 1.54
0.43 1.28
0.43 0.90
0.43 0.82
0.46
0.46
0.46
0.46
0.46
1.85
1.50
1.25
0.88
0.80
K
Delay Factor
-1 Speed Grade
-2 Speed Grade
-3 Speed Grade
-4 Speed Grade
N/A
N/A
DC Characteristics
Symbol
VIH
VIL
Parameter
Input HIGH Voltage
Input LOW Voltage
Output HIGH Voltage
Conditions
Min
Max
Unit
V
V
V
V
0.5VCC VCCIO+0.5
-0.5
2.4
0.3VCC
VOH
IOH = -12 mA
IOH = -500 µA
IOL = 16 mA [1]
IOL = 1.5 mA
0.9VCC
VOL
Output LOW Voltage
0.45
0.1VCC
10
10
10
-180
210
2
V
V
II
IOZ
CI
I or I/O Input Leakage Current
3-State Output Leakage Current VI = VCCIO or GND
Input Capacitance [2]
VI = VCCIO or GND
-10
-10
µA
µA
pF
mA
mA
mA
µA
IOS
Output Short Circuit Current [3]
VO = GND
VO = VCC
VI, VIO = VCCIO or GND 0.50 (typ)
0
-15
40
ICC
ICCIO
D.C. Supply Current [4]
D.C. Supply Current on VCCIO
100
Notes:
[1] Applies only to -1/-2/-3/-4 commercial grade devices. These speed grades are also PCI-compliant. All
other devices have 8 mA IOL specifications.
[2]Capacitance is sample tested only. Clock pins are 12 pF maximum.
[3]Only one output at a time. Duration should not exceed 30 seconds.
[4]For -1/-2/-3/-4 commercial grade devices only. Maximum ICC is 3 mA for -0 commercial grade and all
industrial grade devices, and 5 mA for all military grade devices. For AC conditions, contact QuickLogic
customer engineering.
6-38
QL4036 - QuickRAMTM
AC CHARACTERISTICS at VCC = 3.3V, TA = 25°C (K = 1.00)
(To calculate delays, multiply the appropriate K factor in the "Operating Range" section by the following numbers.)
Logic Cells
Propagation Delays (ns)
Symbol
tPD
tSU
tH
tCLK
tCWHI
tCWLO
tSET
tRESET
tSW
Parameter
Fanout [5]
1
2
3
1.9
1.7
0.0
1.2
1.2
1.2
1.5
4
8
Combinatorial Delay [6]
Setup Time [6]
Hold Time
Clock to Q Delay
Clock High Time
Clock Low Time
Set Delay
Reset Delay
Set Width
Reset Width
1.4
1.7
0.0
0.7
1.2
1.2
1.0
0.8
1.9
1.8
1.7
1.7
0.0
1.0
1.2
1.2
1.3
1.1
1.9
1.8
2.2
1.7
0.0
1.5
1.2
1.2
1.8
1.6
1.9
1.8
3.2
1.7
0.0
2.5
1.2
1.2
2.8
2.6
1.9
1.8
1.3
1.9
1.8
tRW
RAM Cell Synchronous Write Timing
Propagation Delays (ns)
Fanout
Symbol
Parameter
1
2
3
4
8
TSWA
THWA
TSWD
THWD
TSWE
THWE
TWCRD
WA Setup Time to WCLK
WA Hold Time to WCLK
WD Setup Time to WCLK
WD Hold Time to WCLK
WE Setup Time to WCLK
WE Hold Time to WCLK
WCLK to RD (WA=RA) [5]
1.0
0.0
1.0
0.0
1.0
0.0
5.0
1.0
0.0
1.0
0.0
1.0
0.0
5.3
1.0
0.0
1.0
0.0
1.0
0.0
5.6
1.0
0.0
1.0
0.0
1.0
0.0
5.9
1.0
0.0
1.0
0.0
1.0
0.0
7.1
Notes:
[5]Stated timing for worst case Propagation Delay over process variation at VCC=3.3V and TA=25°C. Multiply by
the appropriate Delay Factor, K, for speed grade, voltage and temperature settings as specified in the Operating
Range.
[6]These limits are derived from a representative selection of the slowest paths through the QuickRAM logic cell
including typical net delays. Worst case delay values for specific paths should be determined from timing anal-
ysis of your particular design.
6-39
QL4036 - QuickRAMTM
RAM Cell Synchronous Read Timing
Propagation Delays (ns)
Fanout
Symbol
TSRA
THRA
TSRE
THRE
TRCRD
Parameter
1
2
3
4
8
RA Setup Time to RCLK
RA Hold Time to RCLK
RE Setup Time to RCLK
RE Hold Time to RCLK
RCLK to RD [5]
1.0
0.0
1.0
0.0
4.0
1.0
0.0
1.0
0.0
4.3
1.0
0.0
1.0
0.0
4.6
1.0
0.0
1.0
0.0
4.9
1.0
0.0
1.0
0.0
6.1
RAM Cell Asynchronous Read Timing
Propagation Delays (ns)
Fanout
Symbol
Parameter
1
2
3
4
8
RPDRD
RA to RD [5]
3.0
3.3
3.6
3.9
5.1
Input-Only/Clock Cells
Propagation Delays (ns)
Symbol
Parameter
Fanout [5]
1
2
3
4
8
12
24
TIN
TINI
High Drive Input Delay
1.5
1.6
3.1
0.0
0.7
0.6
2.3
1.6
1.7
3.1
0.0
0.8
0.7
2.3
1.8
1.9
3.1
0.0
1.0
0.9
2.3
1.9
2.0
3.1
0.0
1.1
1.0
2.3
2.4
2.5
3.1
0.0
1.6
1.5
2.3
2.9 4.4
3.0 4.5
3.1 3.1
0.0 0.0
2.1 3.6
2.0 3.5
2.3 2.3
High Drive Input, Inverting Delay
Input Register Set-Up Time
Input Register Hold Time
Input Register Clock To Q
Input Register Reset Delay
Input Register Clock Enable Setup Time
TISU
TIH
TlCLK
TlRST
TlESU
TlEH
Input Register Clock Enable Hold Time
0.0
0.0
0.0
0.0
0.0
0.0 0.0
Clock Cells
Propagation Delays (ns)
Symbol
Parameter
Array Clock Delay
Global Clock Pin Delay
Global Clock Buffer Delay
Loads per Half Column [7]
1
2
3
4
8
10
1.6
0.7
1.2
11
1.7
0.7
1.3
tACK
tGCKP
tGCKB
1.2
0.7
0.8
1.2
0.7
0.8
1.3
0.7
0.9
1.3
0.7
0.9
1.5
0.7
1.1
Notes:
[7]The array distributed networks consist of 40 half columns and the global distributed networks consist of 44
half columns, each driven by an independent buffer. The number of half columns used does not affect
clock buffer delay. The array clock has up to 8 loads per half column. The global clock has up to 11 loads
per half column.
6-40
QL4036 - QuickRAMTM
I/O Cell Input Delays
Propagation Delays (ns)
Fanout [5]
Symbol
Parameter
1
2
3
4
8
10
tI/O
Input Delay (bidirectional pad)
Input Register Set-Up Time
1.3
3.1
0.0
0.7
0.6
2.3
0.0
1.6
3.1
0.0
1.0
0.9
2.3
0.0
1.8
3.1
0.0
1.2
1.1
2.3
0.0
2.1
3.1
0.0
1.5
1.4
2.3
0.0
3.1
3.1
0.0
2.5
2.4
2.3
0.0
3.6
3.1
0.0
3.0
2.9
2.3
0.0
TISU
TIH
Input Register Hold Time
TlOCLK
TlORST
TlESU
TlEH
Input Register Clock To Q
Input Register Reset Delay
Input Register clock Enable Set-Up Time
Input Register Clock Enable Hold Time
I/O Cell Output Delays
Propagation Delays (ns)
Symbol
Parameter
Output Delay Low to High
Output Load Capacitance (pF)
30
50
75
100
3.6
3.7
2.8
3.1
150
4.7
4.8
3.9
4.2
TOUTLH
TOUTHL
TPZH
2.1
2.2
1.2
1.6
2.0
1.2
2.5
2.6
1.7
2.0
3.1
3.2
2.2
2.6
Output Delay High to Low
Output Delay Tri-state to High
Output Delay Tri-state to Low
Output Delay High to Tri-State [8]
Output Delay Low to Tri-State [8]
TPZL
TPHZ
TPLZ
Notes:
[8]The following loads are used for tPXZ
tPHZ
1KΩ
5 pF
1KΩ
tPLZ
5 pF
6-41
QL4036 - QuickRAMTM
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6-42
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