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QL4090-0PB456I [ETC]

Field Programmable Gate Array (FPGA) ; 现场可编程门阵列（FPGA）的\n
QL4090-0PB456I
型号： QL4090-0PB456I
厂家： ETC    ETC
描述：

Field Programmable Gate Array (FPGA)
现场可编程门阵列（FPGA）的\n

现场可编程门阵列 可编程逻辑 栅 时钟
文件： 总12页 (文件大小：282K)
中文：  中文翻译
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QL4090 - QuickRAMTM  
90,000 Usable PLD Gate QuickRAM ESP Combining Performance, Density, and Embedded RAM  
QL4090 - QuickRAM  
D
EVICE  
HIGHLIGHTS  
Device Highlights  
High Performance & High Density  
■ 90,000 Usable PLD Gates with 316 I/Os  
1,584  
High Speed  
Logic Cells  
22  
RAM  
Blocks  
■ 300 MHz 16-bit Counters, 400 MHz Datapaths,  
}
160+ MHz FIFOs  
■ 0.35µm four-layer metal non-volatile CMOS process for  
smallest die sizes  
Interface  
High Speed Embedded SRAM  
■ 22 dual-port RAM modules, organized in user-config-  
FIGURE 1. QuickRAM Block Diagram  
urable 1,152 bit blocks  
■ 5ns access times, each port independently accessible  
■ Fast and effecient for FIFO, RAM, and ROM functions  
A
RCHITECTURE  
O
VERVIEW  
Architecture Overview  
The QuickRAM family of ESPs (Embedded Standard  
Products) offers FPGA logic in combination with Dual-  
Port SRAM modules. The QL4090 is a 90,000  
usable PLD gate member of the QuickRAM family of  
ESPs. QuickRAM ESPs are fabricated on a 0.35mm  
four-layer metal process using QuickLogic’s patented  
ViaLinkTM technology to provide a unique combina-  
tion of high performance, high density, low cost, and  
extreme ease-of-use.  
Easy to Use / Fast Development Cycles  
■ 100% routable with 100% utilization and complete  
pin-out stability  
■ Variable-grain logic cells provide high performance and  
100% utilization  
■ Comprehensive design tools include high quality  
Verilog/VHDL synthesis  
Advanced I/O Capabilities  
■ Interfaces with both 3.3 volt and 5.0 bolt devices  
The QL4090 contains 1,584 logic cells and 22 dual  
port RAM modules (see Figure 1). Each RAM module  
has 1,152 RAM bits, for a total of 25,344 bits. RAM  
Modules are Dual Port (one read port, one write port)  
and can be configured into one of four modes: 64  
(deep) x18 (wide), 128x9, 256x4, or 512x2 (see Fig-  
ure 2). With a maximum of 204 I/Os, the QL4090 is  
available in 208-PQFP, 240-pin PQFP and 456-pin  
PBGA packages.  
■ PCI compliant with 3.3V and 5.0V busses for -1/-2/-3/-4  
speed grades  
■ Full JTAG boundary scan  
■ Registered I/O cells with individually controlled clocks and  
output enables  
Designers can cascade multiple RAM modules to  
increase the depth or width allowed in single modules  
by connecting corresponding address lines together  
and dividing the words between modules (see Figure  
3). This approach allows up to 512-deep configura-  
tions as large as 16 bits wide in the smallest Quick-  
RAM device and 44 bits wide in the largest device.  
6-55  
QL4090 Rev G  
QL4090 - QuickRAMTM  
P
RODUCT  
S
UMMARY  
Product Summary  
Product Summary  
Total of 316 I/O Pins  
■ 308 bi-directional input/output pins, PCI-compliant for  
5.0 volt and 3.3 volt buses for -1/-2/-3/-4 speed grades  
■ 8 high-drive input/distributed network pins  
Eight Low-Skew Distributed Networks  
■ Two array clock/controlnetworks available to the logic  
cell flip-flop clock, set and reset inputs - each driven by  
and input-only pin  
■ Six global clock/control networks available to the logic  
cell F1, clock, set and reset inputs and the input and I/O  
register clock, reset and enable inputs as well as the out-  
put enable control - each driven by an input-only or I/O  
pin, or any logic cell output or I/O cell feedback  
FIGURE 2. QuickRAM Module  
Software support for the complete QuickRAM fam-  
ily, including the QL4016, is available through two  
basic packages. The turnkey QuickWorksTM pack-  
age provides the most complete ESP software solu-  
tion from design entry to logic synthesis, to place and  
route, to simulation. The QuickToolsTM for Worksta-  
tions package provides a solution for designers who  
use Cadence, Exemplar, Mentor, Syn-opsys, Synplic-  
ity, Viewlogic, Veribest, or other third-party tools for  
design entry, synthesis, or simulation.  
High Performance  
■ Input + logic cell + output total delays under 6 ns  
■ Data path speeds over 400 MHz  
■ Counter speeds over 300 MHz  
■ FIFO speeds over 160+ MHz  
The QuickLogic variable grain logic cell features up  
to 16 simultaneous inputs and 5 outs within a cell  
that can be fragmented into 5 independent cells.  
Each cell has a fan-in of 29 including register and  
control lines (see Figure 4).  
QS  
A1  
A2  
A3  
AZ  
A4  
A5  
A6  
OS  
OP  
B1  
WDATA  
WADDR  
RDATA  
RADDR  
B2  
OZ  
C1  
C2  
MP  
RAM  
Module  
(1,152 bits)  
MS  
QZ  
D1  
D2  
E1  
E2  
NP  
NS  
NZ  
FZ  
F1  
F2  
F3  
F4  
F5  
F6  
RAM  
Module  
(1,152 bits)  
QC  
QR  
WDATA  
RDATA  
FIGURE 4. Logic Cell  
FIGURE 3. QuickRAM Module bits  
6-56  
QL4090 - QuickRAMTM  
Pin #157  
Pin #1  
QuickRAM  
QL4090-1PQ208C  
Pin #105  
Pin #53  
208 Pin PQFP/CQFP  
Pinout Diagram  
Pin #181  
Pin #1  
QuickRAM  
QL4090-1PQ240C  
Pin #121  
Pin #61  
240 Pin PQFP  
Pinout Diagram  
6-57  
QL4090 - QuickRAMTM  
PQFP 208/240  
P
INOUT  
TABLE  
QFP 208/240 Pinout Table  
240  
PQFP  
208  
PQFP  
Function  
240  
PQFP  
208  
PQFP  
Function  
240  
PQFP  
208  
PQFP  
Function  
240  
PQFP  
208  
PQFP  
Function  
240  
PQFP  
208  
PQFP  
Function  
1
208  
1
I/O  
I/O  
51  
52  
53  
54  
55  
56  
57  
58  
59  
60  
NC  
NC  
61  
62  
63  
64  
65  
66  
67  
68  
69  
70  
71  
72  
73  
74  
75  
76  
77  
78  
79  
80  
81  
82  
83  
NC  
84  
85  
86  
87  
88  
89  
90  
91  
92  
93  
94  
95  
96  
97  
43  
44  
45  
46  
47  
48  
NC  
49  
50  
51  
52  
53  
54  
NC  
NC  
55  
56  
NC  
57  
58  
59  
60  
61  
62  
63  
64  
NC  
65  
66  
67  
NC  
68  
69  
70  
NC  
71  
NC  
72  
73  
74  
NC  
75  
76  
77  
78  
79  
80  
81  
82  
83  
GND  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
TDI  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
GND  
I/O  
VCC  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
GND  
I/O  
VCC  
I/O  
I/O  
I/O  
GND  
I/O  
I/O  
I/O  
I/O  
VCCIO  
98  
84  
85  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
GND  
I/O  
VCC  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
TRSTB  
TMS  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
VCC  
I/O  
GND  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
145  
146  
147  
148  
149  
150  
151  
152  
153  
154  
155  
156  
157  
158  
159  
160  
161  
162  
163  
164  
165  
166  
167  
168  
169  
170  
171  
172  
173  
174  
175  
176  
177  
178  
179  
180  
NC  
125  
126  
127  
128  
NC  
I/O  
I/O  
194  
195  
196  
197  
198  
199  
200  
201  
202  
203  
204  
205  
206  
207  
208  
209  
210  
211  
212  
213  
214  
215  
216  
217  
218  
219  
220  
221  
222  
223  
224  
225  
226  
227  
228  
229  
230  
231  
232  
233  
234  
235  
236  
237  
238  
239  
240  
168  
169  
NC  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
GND  
I/O  
I/O  
I/O  
I/O  
I/O  
GND  
VCC  
I/O  
I/O  
I/O  
I/O  
VCCIO  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
GND  
I/O  
VCC  
I/O  
I/O  
I/O  
I/O  
I/O  
TDO  
2
99  
3
2
I/O  
100  
101  
102  
103  
104  
105  
106  
107  
108  
109  
110  
NC  
86  
GND  
I/O  
4
3
I/O  
87  
170  
171  
172  
173  
174  
175  
NC  
5
4
I/O  
88  
I/O  
6
5
I/O  
89  
129  
130  
131  
132  
133  
134  
135  
136  
NC  
GLCK/I  
ACLK/I  
VCC  
GLCK/I  
GLCK/I  
VCC  
I/O  
7
NC  
6
I/O  
90  
8
I/O  
91  
9
7
I/O  
92  
10  
11  
12  
13  
14  
15  
16  
17  
18  
19  
20  
21  
22  
23  
24  
25  
26  
27  
28  
29  
30  
31  
32  
33  
34  
35  
36  
37  
38  
39  
40  
41  
42  
43  
44  
45  
46  
47  
48  
49  
50  
8
I/O  
NC  
93  
9
I/O  
176  
177  
178  
179  
NC  
10  
11  
12  
13  
14  
NC  
15  
16  
17  
18  
19  
20  
NC  
21  
22  
23  
24  
25  
26  
27  
28  
29  
30  
31  
32  
NC  
33  
NC  
34  
35  
36  
NC  
37  
38  
39  
NC  
40  
41  
42  
VCC  
I/O  
94  
95  
I/O  
GND  
I/O  
96  
I/O  
111  
NC  
97  
137  
NC  
I/O  
I/O  
98  
GND  
I/O  
180  
181  
182  
NC  
I/O  
NC  
99  
138  
139  
140  
141  
142  
NC  
I/O  
112  
113  
114  
115  
116  
117  
118  
119  
120  
121  
122  
123  
124  
125  
126  
127  
128  
129  
130  
131  
132  
133  
134  
135  
136  
137  
138  
139  
140  
141  
142  
143  
144  
100  
NC  
101  
NC  
102  
NC  
NC  
103  
104  
105  
NC  
106  
107  
108  
109  
NC  
110  
111  
112  
113  
114  
115  
116  
117  
NC  
118  
119  
120  
121  
NC  
122  
123  
124  
I/O  
I/O  
I/O  
I/O  
I/O  
183  
184  
185  
186  
187  
188  
NC  
I/O  
I/O  
I/O  
I/O  
I/O  
143  
144  
145  
NC  
I/O  
I/O  
I/O  
I/O  
VCC  
I/O  
I/O  
GND  
I/O  
146  
147  
148  
149  
150  
151  
152  
153  
154  
155  
156  
157  
158  
NC  
I/O  
189  
190  
191  
192  
193  
194  
NC  
GND  
I/O  
GCLK/I  
ACLK/I  
VCC  
GCLK/I  
GCLK/I  
VCC  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
195  
196  
197  
198  
NC  
I/O  
I/O  
I/O  
GND  
I/O  
I/O  
181  
182  
183  
184  
185  
186  
187  
188  
189  
190  
191  
192  
193  
TCK  
STM  
I/O  
I/O  
199  
200  
201  
202  
203  
204  
205  
206  
207  
I/O  
I/O  
159  
160  
161  
162  
163  
164  
165  
166  
NC  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
GND  
I/O  
I/O  
I/O  
VCC  
I/O  
I/O  
VCC  
I/O  
I/O  
167  
I/O  
TABLE 1: PQFP 208/240 Pinout Table  
6-58  
QL4090 - QuickRAMTM  
P
INOUT  
DIAGRAM  
Pinout Diagram  
QuickRAM  
QL4090-1PB456C  
456 Pin PBGA  
TOP  
PIN A1  
CORNER  
Bottom  
6-59  
QL4090 - QuickRAMTM  
PBGA 456 PINOUT  
TABLE  
PBGA 456 Pinout Table  
456  
Function  
456  
Function  
456  
Function  
456  
Function  
456  
Function  
A1  
A2  
A3  
A4  
A5  
A6  
A7  
A8  
A9  
A10  
A11  
A12  
A13  
A14  
A15  
A16  
A17  
A18  
A19  
A20  
A21  
A22  
A23  
A24  
A25  
A26  
B1  
B2  
B3  
B4  
B5  
B6  
B7  
B8  
B9  
B10  
B11  
B12  
B13  
B14  
B15  
B16  
B17  
B18  
B19  
B20  
B21  
B22  
B23  
B24  
B25  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
VCCIO  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
B26  
C1  
C2  
C3  
C4  
C5  
C6  
C7  
C8  
STM  
I/O  
I/O  
I/O  
TDO  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
TCK  
I/O  
I/O  
I/O  
I/O  
GND  
I/O  
NC  
I/O  
I/O  
GND  
I/O  
I/O  
D25  
D26  
E1  
E2  
E3  
E4  
E5  
E6  
E7  
I/O  
I/O  
I/O  
I/O  
I/O  
H4  
H5  
I/O  
NC  
NC  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
NC  
GND  
NC  
NC  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
VCC  
GND  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
NC  
M14  
M15  
M16  
M22  
M23  
M24  
M25  
M26  
N1  
N2  
N3  
N4  
N5  
N11  
N12  
N13  
N14  
N15  
N16  
N22  
N23  
N24  
N25  
N26  
P1  
GND/THERM  
GND/THERM  
GND/THERM  
NC  
NC  
I/O  
I/O  
I/O  
GCLK/I  
I/O  
I/O  
GCLK/I  
VCC  
GND/THERM  
GND/THERM  
GND/THERM  
GND/THERM  
GND/THERM  
GND/THERM  
GND  
H22  
H23  
H24  
H25  
H26  
J1  
J2  
J3  
J4  
J5  
J22  
J23  
J24  
J25  
J26  
K1  
K2  
K3  
K4  
K5  
K22  
K23  
K24  
K25  
K26  
L1  
L2  
L3  
L4  
L5  
L11  
L12  
L13  
L14  
L15  
L16  
L22  
L23  
L24  
L25  
L26  
M1  
I/O  
GND  
VCC  
GND  
NC  
GND  
I/O  
GND  
GND  
VCC  
GND  
GND  
GND  
NC  
GND  
NC  
GND  
VCC  
GND  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
NC  
VCC  
VCC  
NC  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
C9  
E8  
E9  
C10  
C11  
C12  
C13  
C14  
C15  
C16  
C17  
C18  
C19  
C20  
C21  
C22  
C23  
C24  
C25  
C26  
D1  
D2  
D3  
D4  
D5  
D6  
D7  
D8  
D9  
D10  
D11  
D12  
D13  
D14  
D15  
D16  
D17  
D18  
D19  
D20  
D21  
D22  
D23  
D24  
E10  
E11  
E12  
E13  
E14  
E15  
E16  
E17  
E18  
E19  
E20  
E21  
E22  
E23  
E24  
E25  
E26  
F1  
F2  
F3  
F4  
F5  
F22  
F23  
F24  
F25  
F26  
G1  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
P2  
P3  
P4  
P5  
NC  
P11  
P12  
P13  
P14  
P15  
P16  
P22  
P23  
P24  
P25  
P26  
R1  
R2  
R3  
R4  
R5  
R11  
R12  
R13  
R14  
R15  
R16  
GND/THERM  
GND/THERM  
GND/THERM  
GND/THERM  
GND/THERM  
GND/THERM  
NC  
GCLK / I  
GCLK / I  
I/O  
ACLK / I  
I/O  
I/O  
I/O  
NC  
GND/THERM  
GND/THERM  
GND/THERM  
GND/THERM  
GND/THERM  
GND/THERM  
NC  
I/O  
I/O  
I/O  
I/O  
ACLK / I  
GCLK/I  
I/O  
NC  
GND  
GND  
I/O  
I/O  
GND  
I/O  
I/O  
GND  
I/O  
I/O  
NC  
I/O  
GND  
I/O  
G2  
G3  
G4  
G5  
G22  
G23  
G24  
G25  
G26  
H1  
I/O  
NC  
GND  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
M2  
M3  
M4  
M5  
M11  
M12  
M13  
NC  
GND/THERM  
GND/THERM  
GND/THERM  
GND/THERM  
GND/THERM  
GND/THERM  
GND/THERM  
GND/THERM  
GND/THERM  
H2  
H3  
I/O  
(continued next page)  
Note: NC pins must be left unconnected on printed circuit board  
6-60  
QL4090 - QuickRAMTM  
PBGA 456 Pinout Table  
(continued from previous page)  
456  
Function  
456  
Function  
456  
Function  
456  
Function  
R22  
R23  
R24  
R25  
R26  
T1  
T2  
T3  
T4  
T5  
T11  
T12  
T13  
T14  
T15  
T16  
T22  
T23  
T24  
T25  
T26  
U1  
U2  
U3  
U4  
U5  
U22  
U23  
U24  
U25  
U26  
V1  
VCC  
NC  
I/O  
I/O  
GCLK / I  
I/O  
I/O  
I/O  
Y1  
Y2  
Y3  
Y4  
Y5  
Y22  
Y23  
Y24  
I/O  
I/O  
I/O  
I/O  
I/O  
GND  
I/O  
I/O  
I/O  
I/O  
AC6  
AC7  
AC8  
NC  
I/O  
I/O  
NC  
I/O  
I/O  
NC  
I/O  
VCCIO  
NC  
I/O  
I/O  
NC  
I/O  
I/O  
I/O  
NC  
GND  
I/O  
I/O  
I/O  
I/O  
NC  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
AE5  
AE6  
AE7  
AE8  
AE9  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
NC  
TMS  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
AC9  
AC10  
AC11  
AC12  
AC13  
AC14  
AC15  
AC16  
AC17  
AC18  
AC19  
AC20  
AC21  
AC22  
AC23  
AC24  
AC25  
AC26  
AD1  
AD2  
AD3  
AD4  
AD5  
AD6  
AD7  
AD8  
AD9  
AD10  
AD11  
AD12  
AD13  
AD14  
AD15  
AD16  
AD17  
AD18  
AD19  
AD20  
AD21  
AD22  
AD23  
AD24  
AD25  
AD26  
AE1  
AE10  
AE11  
AE12  
AE13  
AE14  
AE15  
AE16  
AE17  
AE18  
AE19  
AE20  
AE21  
AE22  
AE23  
AE24  
AE25  
AE26  
AF1  
AF2  
AF3  
AF4  
AF5  
AF6  
AF7  
AF8  
AF9  
AF10  
AF11  
AF12  
AF13  
AF14  
AF15  
AF16  
AF17  
AF18  
AF19  
AF20  
AF21  
AF22  
AF23  
AF24  
AF25  
AF26  
I/O  
VCC  
GND/THERMAL  
GND/THERMAL  
GND/THERMAL  
GND/THERMAL  
GND/THERMAL  
GND/THERMAL  
GND  
I/O  
Y25  
Y26  
AA1  
AA2  
AA3  
AA4  
AA5  
AA22  
AA23  
AA24  
AA25  
AA26  
AB1  
AB2  
AB3  
AB4  
AB5  
AB6  
AB7  
AB8  
AB9  
AB10  
AB11  
AB12  
AB13  
AB14  
AB15  
AB16  
AB17  
AB18  
AB19  
AB20  
AB21  
AB22  
AB23  
AB24  
AB25  
AB26  
AC1  
AC2  
I/O  
I/O  
NC  
NC  
VCC  
VCC  
NC  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
GND  
NC  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
NC  
NC  
GND  
NC  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
NC  
NC  
I/O  
I/O  
I/O  
GND  
VCC  
NC  
NC  
NC  
VCC  
GND  
NC  
I/O  
GND  
VCC  
I/O  
NC  
VCC  
GND  
NC  
VCC  
GND  
I/O  
V2  
V3  
V4  
V5  
V22  
V23  
V24  
V25  
V26  
W1  
W2  
W3  
W4  
W5  
W22  
W23  
I/O  
I/O  
I/O  
TRSTB  
I/O  
I/O  
I/O  
TDI  
I/O  
I/O  
I/O  
I/O  
I/O  
W24  
W25  
W26  
I/O  
I/O  
I/O  
AC3  
AC4  
AC5  
NC  
GND  
I/O  
AE2  
AE3  
AE4  
I/O  
I/O  
I/O  
Note: NC pins must be left unconnected on printed circuit board  
6-61  
QL4090 - QuickRAMTM  
P
IN  
D
ESCRIPTION  
Pin Description  
Pin  
Function  
Description  
Hold HIGH during normal operation. Connects to serial  
PROM data in for RAM initialization. Connect to VCC if  
unused.  
TDI/RSI  
Test Data In for JTAG /  
RAM init. Serial Data In  
Hold LOW during normal operation. Connects to serial  
PROM reset for RAM initialization. Connect to GND if  
unused.  
TRSTB/RRO  
Active low Reset for JTAG /  
RAM init. reset out  
Hold HIGH during normal operation. Connect to VCC if  
not used for JTAG.  
TMS  
Test Mode Select for JTAG  
Test Clock for JTAG  
Hold HIGH or LOW during normal operation. Connect to  
VCC or ground if not used for JTAG.  
TCK  
Connect to serial PROM clock for RAM initialization. Must  
be left unconnected if not used for JTAG or RAM  
initialization.  
TDO/RCO  
Test data out for JTAG /  
RAM init. clock out  
Must be grounded during normal operation.  
Can be configured as either or both.  
STM  
Special Test Mode  
I/ACLK  
High-drive input and/or  
array network driver  
Can be configured as either or both.  
I/GCLK  
High-drive input and/or  
global network driver  
Use for input signals with high fanout.  
Can be configured as an input and/or output.  
Connect to 3.3V supply.  
I
High-drive input  
I/O  
Input/Output pin  
VCC  
VCCIO  
Power supply pin  
Connect to 5.0 volt supply if 5 volt input tolerance is  
required, otherwise connect to 3.3V supply.  
Input voltage tolerance pin  
Connect to ground.  
GND  
Ground pin  
Available on 456-PBGA only. Connect to ground plane on  
PCB if heat sinking desired. Otherwise may be left  
unconnected.  
GND/THERM  
Ground/Thermal pin  
Ordering Information  
QL 4090 - 1 PQ208 C  
QuickLogic  
device  
Operating Range  
C = Commercial  
I = Industrial  
QuickRAM device  
part number  
M = Military  
Speed Grade  
0 = quick  
1 = fast  
2 = faster  
3 = faster  
*4 = wow  
Package Code  
PQ208 = 208-pin PQFP  
CF208 = 208-pin CQFP  
PQ240 = 240-pin PQFP  
PB456 = 456-pin PBGA  
* Contact QuickLogic regarding availability.  
6-62  
QL4090 - QuickRAMTM  
Absolute Maximum Ratings  
VCC Voltage.......................................-0.5 to 4.6V  
DC Input Current.................................. 20 mA  
ESD Pad Protection.............................. 2000V  
Storage Temperature .............. -65°C to +150°C  
Lead Temperature ........................... .......300°C  
VCCIO Voltage...................................-0.5 to 7.0V  
Input Voltage .........................-0.5 to VCCIO+0.5V  
Latch-up Immunity .................................. 200mA  
Operating Range  
Symbol  
Parameter  
Supply Voltage  
Military  
Industrial  
Commercial  
Unit  
Min  
Max  
3.6  
5.5  
Min  
3.0  
3.0  
-40  
Max  
3.6  
5.5  
85  
Min  
3.0  
3.0  
0
Max  
3.6  
5.25  
70  
VCC  
3.0  
3.0  
-55  
V
V
°C  
°C  
VCCIO I/O Input Tolerance Voltage  
TA  
TC  
Ambient Temperature  
Case Temperature  
125  
2.03  
1.64  
1.37  
N/A  
-0 Speed Grade  
0.42  
0.42  
0.42  
N/A  
0.43 1.90  
0.43 1.54  
0.43 1.28  
0.43 0.90  
0.43 0.82  
0.46  
0.46  
0.46  
0.46  
0.46  
1.85  
1.50  
1.25  
0.88  
0.80  
K
Delay Factor  
-1 Speed Grade  
-2 Speed Grade  
-3 Speed Grade  
-4 Speed Grade  
N/A  
N/A  
DC Characteristics  
Symbol  
VIH  
VIL  
Parameter  
Input HIGH Voltage  
Input LOW Voltage  
Output HIGH Voltage  
Conditions  
Min  
Max  
Unit  
V
V
V
V
0.5VCC VCCIO+0.5  
-0.5  
2.4  
0.3VCC  
VOH  
IOH = -12 mA  
IOH = -500 µA  
IOL = 16 mA [1]  
IOL = 1.5 mA  
0.9VCC  
VOL  
Output LOW Voltage  
0.45  
0.1VCC  
10  
10  
10  
-180  
210  
2
V
V
II  
IOZ  
CI  
I or I/O Input Leakage Current  
3-State Output Leakage Current VI = VCCIO or GND  
Input Capacitance [2]  
VI = VCCIO or GND  
-10  
-10  
µA  
µA  
pF  
mA  
mA  
mA  
µA  
IOS  
Output Short Circuit Current [3]  
VO = GND  
VO = VCC  
VI, VIO = VCCIO or GND 0.50 (typ)  
0
-15  
40  
ICC  
ICCIO  
D.C. Supply Current [4]  
D.C. Supply Current on VCCIO  
100  
Notes:  
[1] Applies only to -1/-2/-3/-4 commercial grade devices. These speed grades are also PCI-compliant. All  
other devices have 8 mA IOL specifications.  
[2]Capacitance is sample tested only. Clock pins are 12 pF maximum.  
[3]Only one output at a time. Duration should not exceed 30 seconds.  
[4]For -1/-2/-3/-4 commercial grade devices only. Maximum ICC is 3 mA for -0 commercial grade and all  
industrial grade devices, and 5 mA for all military grade devices. For AC conditions, contact QuickLogic  
customer engineering.  
6-63  
QL4090 - QuickRAMTM  
AC CHARACTERISTICS at VCC = 3.3V, TA = 25°C (K = 1.00)  
(To calculate delays, multiply the appropriate K factor in the "Operating Range" section by the following numbers.)  
Logic Cells  
Propagation Delays (ns)  
Symbol  
tPD  
tSU  
tH  
tCLK  
tCWHI  
tCWLO  
tSET  
tRESET  
tSW  
Parameter  
Fanout [5]  
1
2
3
1.9  
1.7  
0.0  
1.2  
1.2  
1.2  
1.5  
4
8
Combinatorial Delay [6]  
Setup Time [6]  
Hold Time  
Clock to Q Delay  
Clock High Time  
Clock Low Time  
Set Delay  
Reset Delay  
Set Width  
Reset Width  
1.4  
1.7  
0.0  
0.7  
1.2  
1.2  
1.0  
0.8  
1.9  
1.8  
1.7  
1.7  
0.0  
1.0  
1.2  
1.2  
1.3  
1.1  
1.9  
1.8  
2.2  
1.7  
0.0  
1.5  
1.2  
1.2  
1.8  
1.6  
1.9  
1.8  
3.2  
1.7  
0.0  
2.5  
1.2  
1.2  
2.8  
2.6  
1.9  
1.8  
1.3  
1.9  
1.8  
tRW  
RAM Cell Synchronous Write Timing  
Propagation Delays (ns)  
Fanout  
Symbol  
Parameter  
1
2
3
4
8
TSWA  
THWA  
TSWD  
THWD  
TSWE  
THWE  
TWCRD  
WA Setup Time to WCLK  
WA Hold Time to WCLK  
WD Setup Time to WCLK  
WD Hold Time to WCLK  
WE Setup Time to WCLK  
WE Hold Time to WCLK  
WCLK to RD (WA=RA) [5]  
1.0  
0.0  
1.0  
0.0  
1.0  
0.0  
5.0  
1.0  
0.0  
1.0  
0.0  
1.0  
0.0  
5.3  
1.0  
0.0  
1.0  
0.0  
1.0  
0.0  
5.6  
1.0  
0.0  
1.0  
0.0  
1.0  
0.0  
5.9  
1.0  
0.0  
1.0  
0.0  
1.0  
0.0  
7.1  
Notes:  
[5]Stated timing for worst case Propagation Delay over process variation at VCC=3.3V and TA=25°C. Multiply by  
the appropriate Delay Factor, K, for speed grade, voltage and temperature settings as specified in the Operating  
Range.  
[6]These limits are derived from a representative selection of the slowest paths through the QuickRAM logic cell  
including typical net delays. Worst case delay values for specific paths should be determined from timing anal-  
ysis of your particular design.  
6-64  
QL4090 - QuickRAMTM  
RAM Cell Synchronous Read Timing  
Propagation Delays (ns)  
Fanout  
Symbol  
TSRA  
THRA  
TSRE  
THRE  
TRCRD  
Parameter  
1
2
3
4
8
RA Setup Time to RCLK  
RA Hold Time to RCLK  
RE Setup Time to RCLK  
RE Hold Time to RCLK  
RCLK to RD [5]  
1.0  
0.0  
1.0  
0.0  
4.0  
1.0  
0.0  
1.0  
0.0  
4.3  
1.0  
0.0  
1.0  
0.0  
4.6  
1.0  
0.0  
1.0  
0.0  
4.9  
1.0  
0.0  
1.0  
0.0  
6.1  
RAM Cell Asynchronous Read Timing  
Propagation Delays (ns)  
Fanout  
Symbol  
Parameter  
1
2
3
4
8
RPDRD  
RA to RD [5]  
3.0  
3.3  
3.6  
3.9  
5.1  
Input-Only/Clock Cells  
Propagation Delays (ns)  
Symbol  
Parameter  
Fanout [5]  
1
2
3
4
8
12  
24  
TIN  
TINI  
High Drive Input Delay  
1.5  
1.6  
3.1  
0.0  
0.7  
0.6  
2.3  
1.6  
1.7  
3.1  
0.0  
0.8  
0.7  
2.3  
1.8  
1.9  
3.1  
0.0  
1.0  
0.9  
2.3  
1.9  
2.0  
3.1  
0.0  
1.1  
1.0  
2.3  
2.4  
2.5  
3.1  
0.0  
1.6  
1.5  
2.3  
2.9 4.4  
3.0 4.5  
3.1 3.1  
0.0 0.0  
2.1 3.6  
2.0 3.5  
2.3 2.3  
High Drive Input, Inverting Delay  
Input Register Set-Up Time  
Input Register Hold Time  
Input Register Clock To Q  
Input Register Reset Delay  
Input Register Clock Enable Setup Time  
TISU  
TIH  
TlCLK  
TlRST  
TlESU  
TlEH  
Input Register Clock Enable Hold Time  
0.0  
0.0  
0.0  
0.0  
0.0  
0.0 0.0  
Clock Cells  
Propagation Delays (ns)  
Symbol  
Parameter  
Array Clock Delay  
Global Clock Pin Delay  
Global Clock Buffer Delay  
Loads per Half Column [7]  
1
2
3
4
8
10  
1.6  
0.7  
1.2  
11  
1.7  
0.7  
1.3  
tACK  
tGCKP  
tGCKB  
1.2  
0.7  
0.8  
1.2  
0.7  
0.8  
1.3  
0.7  
0.9  
1.3  
0.7  
0.9  
1.5  
0.7  
1.1  
Notes:  
[7]The array distributed networks consist of 40 half columns and the global distributed networks consist of 44  
half columns, each driven by an independent buffer. The number of half columns used does not affect  
clock buffer delay. The array clock has up to 8 loads per half column. The global clock has up to 11 loads  
per half column.  
6-65  
QL4090 - QuickRAMTM  
I/O Cell Input Delays  
Propagation Delays (ns)  
Fanout [5]  
Symbol  
Parameter  
1
2
3
4
8
10  
tI/O  
Input Delay (bidirectional pad)  
Input Register Set-Up Time  
1.3  
3.1  
0.0  
0.7  
0.6  
2.3  
0.0  
1.6  
3.1  
0.0  
1.0  
0.9  
2.3  
0.0  
1.8  
3.1  
0.0  
1.2  
1.1  
2.3  
0.0  
2.1  
3.1  
0.0  
1.5  
1.4  
2.3  
0.0  
3.1  
3.1  
0.0  
2.5  
2.4  
2.3  
0.0  
3.6  
3.1  
0.0  
3.0  
2.9  
2.3  
0.0  
TISU  
TIH  
Input Register Hold Time  
TlOCLK  
TlORST  
TlESU  
TlEH  
Input Register Clock To Q  
Input Register Reset Delay  
Input Register clock Enable Set-Up Time  
Input Register Clock Enable Hold Time  
I/O Cell Output Delays  
Propagation Delays (ns)  
Symbol  
Parameter  
Output Delay Low to High  
Output Load Capacitance (pF)  
30  
50  
75  
100  
3.6  
3.7  
2.8  
3.1  
150  
4.7  
4.8  
3.9  
4.2  
TOUTLH  
TOUTHL  
TPZH  
2.1  
2.2  
1.2  
1.6  
2.0  
1.2  
2.5  
2.6  
1.7  
2.0  
3.1  
3.2  
2.2  
2.6  
Output Delay High to Low  
Output Delay Tri-state to High  
Output Delay Tri-state to Low  
Output Delay High to Tri-State [8]  
Output Delay Low to Tri-State [8]  
TPZL  
TPHZ  
TPLZ  
Notes:  
[8]The following loads are used for tPXZ  
tPHZ  
1KΩ  
5 pF  
1KΩ  
tPLZ  
5 pF  
6-66  

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