QL4090-2PB456C_技术文档

QL4090 QuickRAM Data Sheet

90,000 Usable PLD Gate QuickRAM ESP Combining Performance,

Density and Embedded RAM

• • • • • •

Advanced I/O Capabilities

Device Highlights

• Interfaces with both 3.3 V and 5.0 V devices

• PCI compliant with 3.3 V and 5.0 V busses

High Performance & High Density

for -1/-2/-3/-4 speed grades

• 90,000 Usable PLD Gates with 316 I/Os

• Full JTAG boundary scan

• 300 MHz 16-bit Counters, 400 MHz

• I/O Cells with individually controlled

Datapaths, 160+ MHz FIFOs

Registered Input Path and Output Enables

• 0.35µm four-layer metal non-volatile CMOS

process for smallest die sizes

High Speed Embedded SRAM

• 22 dual-port RAM modules, organized in

user-configurable 1,152 bit blocks

• 5 ns access times, each port independently

22

RAM

Blocks

1,584

High Speed

Logic Cells

accessible

• Fast and efficient for FIFO, RAM, and ROM

functions

Easy to Use / Fast Development

Cycles

Interface

• 100% routable with 100% utilization and

Figure 1: QuickRAM Block Diagram

complete pin-out stability

• Variable-grain logic cells provide high

performance and 100% utilization

• Comprehensive design tools include high

quality Verilog/VHDL synthesis

•

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1

QL4090 QuickRAM Data Sheet Rev H

Architecture Overview

The QuickRAM^TMfamily of ESPs (Embedded Standard Products) offers FPGA logic in

combination with Dual-Port SRAM modules. The QL4090 is a 90,000 usable PLD gate

member of the QuickRAM family of ESPs. QuickRAM ESPs are fabricated on a 0.35 µm

four-layer metal process using QuickLogic's patented ViaLink^TMtechnology to provide a

unique combination of high performance, high density, low cost, and extreme ease-of-use.

The QL4090 contains 1,584 logic cells and 22 Dual Port RAM modules (see Figure 1). Each

RAM module has 1,152 RAM bits, for a total of 25,344 bits. RAM Modules are Dual Port

(one read port, one write port) and can be configured into one of four modes: 64 (deep) x18

(wide), 128x9, 256x4, or 512x2 (see Figure 4). With a maximum of 82 I/Os, the QL4090

is available in 208-pin PQFP, 208-pin CQFP 240-pin PQFP and 456-pin PBGA packages.

Designers can cascade multiple RAM modules to increase the depth or width allowed in

single modules by connecting corresponding address lines together and dividing the words

between modules (see Figure 2). This approach allows up to 512-deep configurations as

large as 16 bits wide in the smallest QuickRAM device and 44 bits wide in the largest device.

Software support for the complete QuickRAM family, including the QL4090, is available

through two basic packages. The turnkey QuickWorks^TMpackage provides the most

complete ESP software solution from design entry to logic synthesis, to place and route, to

simulation. The QuickTools^TMpackages provides a solution for designers who use Cadence,

Exemplar, Mentor, Synopsys, Synplicity, Viewlogic, Aldec, or other third-party tools for

design entry, synthesis, or simulation.

The QuickLogic variable grain logic cell features up to 16 simultaneous inputs and 5 outputs

within a cell that can be fragmented into 5 independent cells. Each cell has a fan-in of 29

including register and control lines (see Figure 3).

WDATA

WADDR

RDATA

RADDR

RAM

Module

(1,152 bits)

RAM

Module

(1,152 bits)

WDATA

RDATA

Figure 2: QuickRAM Module Bits

•

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2

QL4090 QuickRAM Data Sheet Rev H

Product Summary

Total of 316 I/O Pins

• 308 bi-directional input/output pins, PCI-compliant for 5.0 V and 3.3 V buses for

-1/-2/-3/-4 speed grades

• 8 high-drive input/distributed network pins

Eight Low-Skew Distributed Networks

• Two array clock/control networks available to the logic cell flip-flop clock, set and reset

inputs—each driven by an input-only pin

• Six global clock/control networks available to the logic cell F1, clock, set and reset inputs

and the input and I/O register clock, reset and enable inputs as well as the output enable

control—each driven by an input-only or I/O pin, or any logic cell output or I/O cell

feedback

High Performance Silicon

• Input + logic cell + output total delays under 6 ns

• Data path speeds over 400 MHz

• Counter speeds over 300 MHz

• FIFO speeds over 160+ MHz

•

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3

QL4090 QuickRAM Data Sheet Rev H

AC Characteristics at V_CC= 3.3 V, T_A= 25° C (K = 1.00)

To calculate delays, multiply the appropriate K factor from Table 10: Operating Range by the

following numbers in the tables provided.

QS

A1

A2

A3

AZ

A4

A5

A6

QS

OP

B1

B2

OZ

C1

C2

MP

QZ

MS

D1

D2

E1

E2

NP

NS

NZ

FZ

F1

F2

F3

F4

F5

F6

QC

QR

Figure 3: QuickRAM Logic Cell

Table 1: Logic Cell

Propagation Delays (ns)

Symbol

Parameter

Fanout (5)

1

2

3

4

5

t_PD

Combinatorial Delay^a

Setup Time^a

1.4

1.7

0.0

0.7

1.2

1.0

0.8

1.9

1.8

1.7

0.0

1.0

1.2

1.3

1.1

1.9

1.8

1.9

2.2

1.7

0.0

1.5

1.2

1.8

1.6

1.9

1.8

3.2

1.7

0.0

2.5

1.2

2.8

2.6

1.9

1.8

t_SU

1.7

t_H

Hold Time

0.0

t_CLK

t_CWHI

t_CWLO

t_SET

t_RESET

t_SW

Clock to Q Delay

Clock High Time

Clock Low Time

Set Delay

1.2

1.5

Reset Delay

1.3

Set Width

1.9

t_RW

Reset Width

1.8

a. These limits are derived from a representative selection of the slowest paths through the Quick-

RAM logic cell including typical net delays. Worst case delay values for specific paths should be

determined from timing analysis of your particular design.

•

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4

QL4090 QuickRAM Data Sheet Rev H

[8:0]

WA

RE

RCLK

[17:0]

WD

WE

[8:0]

RA

RD

[17:0]

WCLK

MODE

[1:0]

ASYNCRD

Figure 4: QuickRAM Module

Table 2: RAM Cell Synchronous Write Timing

Propagation Delays (ns)

Symbol

Parameter

Fanout

1

2

3

4

5

t_SWA

t_HWA

t_SWD

t_HWD

t_SWE

WA Setup Time to WCLK

WA Hold Time to WCLK

WD Setup Time to WCLK

WD Hold Time to WCLK

WE Setup Time to WCLK

WE Hold Time to WCLK

WCLK to RD (WA=RA)^a

1.0

0.0

1.0

0.0

1.0

0.0

5.0

1.0

0.0

1.0

0.0

1.0

0.0

5.3

1.0

0.0

1.0

0.0

1.0

0.0

5.6

1.0

0.0

1.0

0.0

1.0

0.0

5.9

1.0

0.0

1.0

0.0

1.0

0.0

7.1

t_HWE

t_WCRD

a. Stated timing for worst case Propagation Delay over process variation at V_CC= 3.3 V and

T_A= 25° C. Multiply by the appropriate Delay Factor, K, for speed grade, voltage and temperature

settings as specified in the Operating Range.

Table 3: RAM Cell Synchronous Read Timing

Propagation Delays (ns)

Symbol

Parameter

Fanout

Logic Cells

t_SRA

1

2

3

4

5

RA Setup Time to RCLK

RA Hold Time to RCLK

RE Setup Time to RCLK

RE Hold Time to RCLK

RCLK to RD^a

1.0

0.0

1.0

0.0

4.0

1.0

0.0

1.0

0.0

4.3

1.0

0.0

1.0

0.0

4.6

1.0

0.0

1.0

0.0

4.9

1.0

0.0

1.0

0.0

6.1

t_HRA

t_SRE

t_HRE

t_RCRD

a. Stated timing for worst case Propagation Delay over process variation at V_CC= 3.3 V and

T_A= 25° C. Multiply by the appropriate Delay Factor, K, for speed grade, voltage and temperature

settings as specified in the Operating Range.

•

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5

QL4090 QuickRAM Data Sheet Rev H

Table 4: RAM Cell Asynchronous Read Timing

Propagation Delays (ns)

Fanout

Symbol

Parameter

1

2

3

4

5

RPDRD

RA to RD^a

3.0

3.3

3.6

3.9

5.1

a. Stated timing for worst case Propagation Delay over process variation at V_CC= 3.3 V and

T_A= 25° C. Multiply by the appropriate Delay Factor, K, for speed grade, voltage and temperature

settings as specified in the Operating Range.

Table 5: Input-Only / Clock Cells

Propagation Delays (ns)

Symbol

Parameter

Fanout

1

2

3

4

8

12 24

t_IN

High Drive Input Delay

1.5 1.6 1.8 1.9 2.4 2.9 4.4

1.6 1.7 .19 2.0 2.5 3.0 4.5

3.1 3.1 3.1 3.1 3.1 3.1 3.1

0.0 0.0 0.0 0.0 0.0 0.0 0.0

0.7 0.8 1.0 1.1 1.6 2.1 3.6

0.6 0.7 0.9 1.0 1.5 2.0 3.5

2.3 2.3 2.3 2.3 2.3 2.3 2.3

0.0 0.0 0.0 0.0 0.0 0.0 0.0

t_INI

High Drive Input, Inverting Delay

Input Register Set-Up Time

t_ISU

t_IH

Input Register Hold Time

t_ICLK

t_IRST

t_IESU

t_IEH

Input Register Clock To Q

Input Register Reset Delay

Input Register Clock Enable Setup Time

Input Register Clock Enable Hold Time

Table 6: Clock Cells

Propagation Delays (ns)

Fanout^a

Symbol

Parameter

1

2

3

4

8

10 11

t_ACK

Array Clock Delay

1.2 1.2 1.3 1.3 1.5 1.6 1.7

0.7 0.7 0.7 0.7 0.7 0.7 0.7

0.8 0.8 0.9 0.9 1.1 1.2 1.3

t_GCKP

t_GCKB

Global Clock Pin Delay

Global Clock Buffer Delay

a. The array distributed networks consist of 40 half columns and the global distributed networks con-

sist of 44 half columns, each driven by an independent buffer. The number of half columns used

does not affect clock buffer delay. The array clock has up to 8 loads per half column. The global

clock has up to 11 loads per half column.

•

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6

QL4090 QuickRAM Data Sheet Rev H

Table 7: I/O Cell Input Delays

Propagation Delays (ns)

Fanout^a

Symbol

Parameter

1

2

3

4

8

10

t_I/O

t_ISU

t_IH

Input Delay (bidirectional pad)

1.3 1.6 1.8 2.1 3.1 3.6

3.1 3.1 3.1 3.1 3.1 3.1

0.0 0.0 0.0 0.0 0.0 0.0

0.7 1.0 1.2 1.5 2.5 3.0

0.6 0.9 1.1 1.4 2.4 2.9

2.3 2.3 2.3 2.3 2.3 2.3

0.0 0.0 0.0 0.0 0.0 0.0

Input Register Set-Up Time

Input Register Hold Time

t_IOCLK

t_IORST

t_IESU

t_IEH

Input Register Clock to Q

Input Register Reset Delay

Input Register Clock Enable Set-Up Time

Input Register Clock Enable Hold Time

a. Stated timing for worst case Propagation Delay over process variation at V_CC= 3.3 V and

T_A= 25° C. Multiply by the appropriate Delay Factor, K, for speed grade, voltage and temperature

settings as specified in the Operating Range.

Table 8: I/O Cell Output Delays

Propagation Delays (ns)

Output Load Capacitance (pF)

Symbol

Parameter

3

50

2.5

2.6

1.7

2.0

-

75

3.1

3.2

2.2

2.6

-

100

3.6

3.7

2.8

3.1

-

150

4.7

4.8

3.9

4.2

-

t_OUTLH

Output Delay Low to High

Output Delay High to Low

Output Delay Tri-state to High

Output Delay Tri-state to Low

Output Delay High to Tri-state^a

2.1

2.2

1.2

1.6

2.0

1.2

t_OUTHL

t_PZH

t_PZL

t_PHZ

t_PLZ

-

a. The following loads are used for t_PXZ

tPHZ

5 pF

1ΚΩ

tPLZ

5 pF

•

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7

QL4090 QuickRAM Data Sheet Rev H

DC Characteristics

The DC specifications are provided in the tables below.

Table 9: Absolute Maximum Ratings

Parameter

V_CCVoltage

Value

-0.5 to 4.6 V

Parameter

Value

20 mA

DC Input Current

ESD Pad Protection

Storage Temperature

Lead Temperature

V_CCIOVoltage

Input Voltage

Latch-up Immunity

-0.5 to 7.0 V

2000 V

-0.5 V to V_CCIO+0.5 V

200 mA

-65° C to +150° C

300° C

Table 10: Operating Range

Military Industrial

Min Max

Symbol

Parameter

Commercial

Unit

Min

Max

3.6

Min

3.0

0

Max

3.6

V_CC

V_CCIO

T_A

Supply Voltage

3.0

-55

-

3.0

3.6

5.5

V

I/O Input Tolerance Voltage

Ambient Temperature

Case Temperature

5.5

5.25

70

V

-

-40

85

°C

T_C

125

2.03

1.64

1.37

-

°C

-0 Speed Grade 0.42

-1 Speed Grade 0.42

-2 Speed Grade 0.42

-3 Speed Grade

0.43

1.90

1.54

1.28

0.90

0.82

0.46

1.85

1.50

1.25

0.88

0.80

n/a

K

Delay Factor

-4 Speed Grade

•

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8

QL4090 QuickRAM Data Sheet Rev H

Table 11: DC Characteristics

Symbol

V_IH

Parameter

Input HIGH Voltage

Input LOW Voltage

Conditions

Min

Max

Units

V

0.5 V_CCV_CCIO+ 0.5

V_IL

-0.5

2.4

0.3V_CC

V

I_OH= -12 mA

I_OH= -500 µA

I_OL= 16 mA^a

I_OL= 1.5 mA

V

V_OH

Output HIGH Voltage

Output LOW Voltage

0.9 V_CC

V

0.45

0.1 V_CC

10

V

V_OL

V

I_I

I or I/O Input Leakage Current

3-State Output Leakage Current

Input Capacitance^b

V_I= V_CCIOor GND

-10

µA

pF

mA

µA

I_OZ

C_I

10

V_O= GND

V_O= V_CC

-15

40

-180

210

2

I_OS

Output Short Circuit Current^c

I_CC

D.C. Supply Current^d

V_I, V_IO= V_CCIOor GND 0.50 (typ)

0

I_CCIO

D.C. Supply Current on V_CCIO

100

a. Applies only to -1/-2/-3/-4 commercial grade devices. These speed grades are also PCI-compliant. All

other devices have 8 mA IOL specifications.

b. Capacitance is sample tested only. Clock pins are 12 pF maximum.

c. Only one output at a time. Duration should not exceed 30 seconds.

d. For -1/-2/-3/-4 commercial grade devices only. Maximum I_CCis 3 mA for -0 commercial grade and all

industrial grade devices. and 5 mA for all military grade devices. For AC conditions, contact QuickLog-

ic customer applications group.

•

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9

QL4090 QuickRAM Data Sheet Rev H

Kv and Kt Graphs

Voltage Factor vs. Supply Voltage

1.1000

1.0800

1.0600

1.0400

1.0200

1.0000

0.9800

0.9600

0.9400

0.9200

3

3.1

3.2

3.3

3.4

3.5

3.6

Supply Voltage (V)

Figure 5: Voltage Factor vs. Supply Voltage

Temperature Factor vs. Operating Temperature

1.15

1.10

1.05

1.00

0.95

0.90

0.85

-60

-40

-20

0

20

40

60

80

Junction Temperature C

Figure 6: Temperature Factor vs. Operating Temperature

•

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10

QL4090 QuickRAM Data Sheet Rev H

Power-up Sequencing

V_CCIO

V_CC

(V_CCIO-V_{CC MAX}

)

V_CC

400 us

Time

Figure 7: Power-up Requirements

The following requirements must be met when powering up the device:

(Refer to Figure 7 above)

• When ramping up the power supplies keep (V_CCIO- V_CC)_MAX

≤ 500 mV. Deviation from

this recommendation can cause permanent damage to the device.

• V_CCIOmust lead V_CCwhen ramping the device.

• The power supply must take greater than or equal to 400 µs to reach V_CC. Ramping to

V_CC/V_CCIOearlier than 400 µs can cause the device to behave improperly.

An internal diode is present in-between V_CCand V_CCIO, as shown in Figure 8.

V

CCIO

CC

Internal Logic

Cells, RAM

blocks, etc

IO Cells

Figure 8: Internal Diode Between V_CCand V_CCIO

•

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11

QL4090 QuickRAM Data Sheet Rev H

JTAG

TCK

TAp Controller

State Machine

(16 States)

Instruction Decode

&

Control Logic

TMS

TRSTB

Instruction Register

Mux

RDI

TDO

Mux

Boundary-Scan Register

(Data Register)

Bypass

Register

Internal

Register

I/O Registers

User Defined Data Register

Figure 9: JTAG Block Diagram

Microprocessors and Application Specific Integrated Circuits (ASICs) pose many design

challenges, not the least of which concerns the accessibility of test points. The Joint Test

Access Group (JTAG) formed in response to this challenge, resulting in IEEE standard

1149.1, the Standard Test Access Port and Boundary Scan Architecture.

The JTAG boundary scan test methodology allows complete observation and control of the

boundary pins of a JTAG-compatible device through JTAG software. A Test Access Port

(TAP) controller works in concert with the Instruction Register (IR); these allow users to run

three required tests, along with several user-defined tests.

JTAG tests allow users to reduce system debug time, reuse test platforms and tools, and reuse

subsystem tests for fuller verification of higher level system elements.

•

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12

QL4090 QuickRAM Data Sheet Rev H

The 1149.1 standard requires the following three tests:

• Extest Instruction. The Extest instruction performs a PCB interconnect test. This test

places a device into an external boundary test mode, selecting the boundary scan

register to be connected between the TAP's Test Data In (TDI) and Test Data Out (TDO)

pins. Boundary scan cells are preloaded with test patterns (via the Sample/Preload

Instruction), and input boundary cells capture the input data for analysis.

• Sample/Preload Instruction. This instruction allows a device to remain in its

functional mode, while selecting the boundary scan register to be connected between

the TDI and TDO pins. For this test, the boundary scan register can be accessed via a

data scan operation, allowing users to sample the functional data entering and leaving

the device.

• Bypass Instruction. The Bypass instruction allows data to skip a device's boundary

scan entirely, so the data passes through the bypass register. The Bypass instruction

allows users to test a device without passing through other devices. The bypass register

is connected between the TDI and TDO pins, allowing serial data to be transferred

through a device without affecting the operation of the device.

•

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13

QL4090 QuickRAM Data Sheet Rev H

Pin Descriptions

Table 12: Pin Descriptions

Function

Description

Hold HIGH during normal operation. Connects to

serial PROM data in for RAM initialization. Connect

to V_CCif unused.

Test Data In for JTAG /RAM

init. Serial Data In

TDI/RSI

Hold LOW during normal operation. Connects to

serial PROM reset for RAM initialization. Connect to

GND if unused.

Active low Reset for JTAG

/RAM init. reset out

TRSTB/RRO

Hold HIGH during normal operation. Connect to

V_CCif not used for JTAG.

TMS

TCK

Test Mode Select for JTAG

Test Clock for JTAG

Hold HIGH or LOW during normal operation.

Connect to V_CCor ground if not used for JTAG.

Connect to serial PROM clock for RAM

initialization. Must be left unconnected if not used for

JTAG or RAM initialization.

Test data out for JTAG /RAM

init. clock out

TDO/RCO

STM

Special Test Mode

Must be grounded during normal operation.

Can be configured as either or both.

High-drive input and/or array

network driver

I/ACLK

High-drive input and/or global

network driver

I/GCLK

Can be configured as either or both.

I

High-drive input

Input/Output pin

Power supply pin

Use for input signals with high fanout.

Can be configured as an input and/or output.

Connect to 3.3 V supply.

I/O

V_CC

Connect to 5.0 V supply if 5 V input tolerance is

required, otherwise connect to 3.3 V supply.

V_CCIO

GND

Input voltage tolerance pin

Ground pin

Connect to ground.

Available on 456-PBGA only. Connect to ground

plane on PCB if heat sinking desired. Otherwise may

be left unconnected.

GND/THERM Ground/Thermal pin

Ordering Information

QL 4090 - 1 PQ208 C

QuickLogic device

QuickRAM device

part number

Operating Range

C = Commercial

I = Industrial

M = Military

Speed Grade

0 = Quick

1 = Fast

Package Code

PQ208 = 208-pin PQFP

CF208 = 208-pin CQFP

PQ240 = 240-pin PQFP

PB456 = 456-pin PBGA

2 = Faster

3 = Faster

*4 = Wow

* Contact QuickLogic regarding availabliity

•

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14

QL4090 QuickRAM Data Sheet Rev H

208 and 240 PQFP Pinout Diagrams

Pin 157

Pin 1

QuickRAM

QL4090-1PQ208C

Pin 53

Pin 105

Figure 10: Top View of 208 Pin PQFP/CQFP

Pin 181

Pin 1

QuickRAM

QL4090-1PQ240C

Pin 61

Pin 121

Figure 11: Top View of 240 Pin PQFP

•

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15

QL4090 QuickRAM Data Sheet Rev H

208 and 240 PQFP Pinout Table

Table 13: 208/240 PQFP Pinout Table

240

208

240

208

240

208

240

PQFP

208

PQFP

240

PQFP

208

PQFP

Function

PQFP PQFP

I/O

GND

I/O

TDI

I/O

GND

I/O

GND

I/O

GND

I/O

GND

1

208

1

51

52

53

54

55

56

57

58

59

60

NC

61

62

63

64

65

66

67

68

69

70

71

72

73

74

75

76

77

78

79

80

81

82

83

NC

84

85

86

87

88

89

90

91

92

93

94

95

96

97

43

44

45

46

47

48

NC

49

50

51

52

53

54

NC

55

56

NC

57

58

59

60

61

62

63

64

NC

65

66

67

NC

68

69

70

NC

71

NC

72

73

74

NC

75

76

77

78

79

80

81

82

83

98

84

85

145

146

147

148

149

150

151

152

153

154

155

156

157

158

159

160

161

162

163

164

165

166

167

168

169

170

171

172

173

174

175

176

177

178

179

180

NC

125

126

127

128

NC

194

195

196

197

198

199

200

201

202

203

204

205

206

207

208

209

210

211

212

213

214

215

216

217

218

219

220

221

222

223

224

225

226

227

228

229

230

231

232

233

234

235

236

237

238

239

240

168

169

NC

2

99

GND

I/O

3

2

100

101

102

103

104

105

106

107

108

109

110

NC

86

4

3

87

170

171

172

173

174

175

NC

5

4

88

I/O

GLCK/I

ACLK/I

6

5

89

129

130

131

132

133

134

135

136

NC

7

NC

6

90

V

8

91

CC

9

7

92

GLCK/I

10

11

12

13

14

15

16

17

18

19

20

21

22

23

24

25

26

27

28

29

30

31

32

33

34

35

36

37

38

39

40

41

42

43

44

45

46

47

48

49

50

8

NC

93

9

V

176

177

178

179

NC

CC

10

11

12

13

14

NC

15

16

17

18

19

20

NC

21

22

23

24

25

26

27

28

29

30

31

32

NC

33

NC

34

35

36

NC

37

38

39

NC

40

41

42

V

94

I/O

GND

I/O

CC

I/O

GND

I/O

95

96

V

111

NC

97

137

NC

CC

I/O

98

I/O

180

181

182

NC

I/O

NC

99

138

139

140

141

142

NC

I/O

112

113

114

115

116

117

118

119

120

121

122

123

124

125

126

127

128

129

130

131

132

133

134

135

136

137

138

139

140

141

142

143

144

100

NC

101

NC

102

NC

103

104

105

NC

106

107

108

109

NC

110

111

112

113

114

115

116

117

NC

118

119

120

121

NC

122

123

124

I/O

V

CC

I/O

183

184

185

186

187

188

NC

I/O

V

I/O

143

144

145

NC

CC

I/O

GND

I/O

V

CCIO

I/O

TRSTB

TMS

I/O

V

I/O

GND

I/O

CC

I/O

GND

I/O

146

147

148

149

150

151

152

153

154

155

156

157

158

NC

189

190

191

192

193

194

NC

I/O

GND

I/O

GCLK/I

ACLK/I

I/O

V

I/O

CC

GCLK/I

I/O

V

I/O

195

196

197

198

NC

CC

I/O

GND

I/O

V

181

182

183

184

185

186

187

188

189

190

191

192

193

TCK

STM

I/O

CC

I/O

GND

I/O

199

200

201

202

203

204

205

206

207

V

159

160

161

162

163

164

165

166

NC

I/O

V

CC

I/O

GND

I/O

GND

I/O

V

TDO

CC

I/O

V

I/O

CC

I/O

V

167

CCIO

•

www.quicklogic.com

16

QL4090 QuickRAM Data Sheet Rev H

208 and 240 PQFP Mechanical Drawing

Figure 12: 208 PQFP Mechanical Drawing

•

www.quicklogic.com

17

QL4090 QuickRAM Data Sheet Rev H

456 PBGA Pinout Diagram

TOP View

QuickRAM

QL4090-1PB456C

BOTTOM View

PIN A1

CORNER

26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10

9

8

7 6 5 4 3 2 1

A

B

C

D

E

F

G

H

J

K

L

M

N

P

R

T

U

V

W

Y

AA

AB

AC

AD

AE

AF

Figure 13: 456 PBGA Pinout Diagram

•

www.quicklogic.com

18

QL4090 QuickRAM Data Sheet Rev H

456 PBGA Pinout Table

Table 14: 456 PBGA Pinout Table

456

A1

Function

I/O

456

C1

Function

I/O

456

E1

Function

I/O

456

H23

H24

H25

H26

J1

Function

I/O

456

M23

M24

M25

M26

N1

Function

NC

I/O

A2

C2

E2

A3

I/O

C3

I/O

E3

I/O

A4

I/O

C4

TDO

I/O

E4

I/O

GND

I/O

GCLK/I

I/O

A5

C5

E5

A6

I/O

C6

I/O

E6

V

J2

I/O

N2

CC

I/O

GND

NC

I/O

A7

C7

E7

J3

N3

A8

I/O

C8

I/O

E8

J4

NC

N4

GCLK/I

A9

I/O

C9

I/O

E9

GND

I/O

J5

GND

NC

N5

V

CC

I/O

GND/THERM

GND

A10

A11

A12

A13

A14

A15

A16

A17

A18

A19

A20

A21

A22

A23

A24

A25

A26

B1

C10

C11

C12

C13

C14

C15

C16

C17

C18

C19

C20

C21

C22

C23

C24

C25

C26

D1

E10

E11

E12

E13

E14

E15

E16

E17

E18

E19

E20

E21

E22

E23

E24

E25

E26

F1

J22

J23

J24

J25

J26

K1

N11

N12

N13

N14

N15

N16

N22

N23

N24

N25

N26

P1

I/O

GND

NC

V

I/O

CCIO

I/O

STM

I/O

V

I/O

CC

I/O

GND

NC

I/O

K2

I/O

K3

I/O

GND

NC

K4

I/O

V

I/O

K5

CC

I/O

GND

K22

K23

K24

K25

K26

L1

GND

I/O

V

I/O

CC

I/O

GND

I/O

NC

I/O

P2

I/O

P3

I/O

P4

TCK

I/O

P5

NC

L2

I/O

P11

P12

P13

P14

P15

P16

P22

P23

P24

P25

p26

R1

GND/THERM

NC

I/O

L3

B2

D2

I/O

F2

L4

I/O

NC

B3

D3

F3

L5

B4

D4

GND

I/O

F4

L11

L12

L13

L14

L15

L16

L22

L23

L24

L25

L26

M1

GND/THERM

NC

B5

D5

F5

V

CC

B6

D6

NC

I/O

F22

F23

F24

F25

F26

G1

V

CC

B7

D7

NC

I/O

NC

GND

I/O

NC

GCLK / I

I/O

B8

D8

B9

D9

GND

I/O

ACLK/I

B10

B11

B12

B13

B14

B15

B16

B17

B18

B19

B20

B21

B22

B23

B24

B25

B26

D10

D11

D12

D13

D14

D15

D16

D17

D18

D19

D20

D21

D22

D23

D24

D25

D26

I/O

GND

I/O

G2

I/O

R2

I/O

G3

R3

I/O

G4

I/O

R4

NC

GND

I/O

ACLK / I

GCLK/I

I/O

NC

G5

R5

G22

G23

G24

G25

G26

H1

M2

R11

R12

R13

R14

R15

R16

R22

R23

R24

R25

R26

GND/THERM

I/O

M3

GND

I/O

NC

M4

M5

GND

I/O

GND/THERM

NC

M11

M12

M13

M14

M15

M16

M22

NC

I/O

V

H2

CC

GND

I/O

H3

NC

I/O

H4

I/O

H5

I/O

H22

GCLK / I

(Sheet 1 of 2)

•

www.quicklogic.com

19

QL4090 QuickRAM Data Sheet Rev H

Table 14: 456 PBGA Pinout Table (Continued)

456

T1

T2

T3

T4

T5

Function

456

W5

Function

NC

I/O

456

Function

456

AD3

Function

I/O

456

Function

I/O

NC

TMS

I/O

AB15

AB16

AB17

AB18

AB19

AB20

AB21

AB22

AB23

AB24

AB25

AB26

AC1

V

AE17

AE18

AE19

AE20

AE21

AE22

AE23

AE24

AE25

AE26

AF1

CC

I/O

NC

I/O

W22

W23

W24

W25

AD4

AD5

I/O

V

AD6

I/O

CC

V

I/O

GND

NC

I/O

AD7

CC

T11 GND/THERMAL W26

I/O

AD8

I/O

GND/THERMAL

I/O

V

I/O

T12

T13

T14

T15

T16

T22

T23

T24

T25

T26

U1

Y1

Y2

AD9

CC

GND/THERMAL

I/O

GND

I/O

NC

GND

I/O

NC

I/O

NC

I/O

NC

I/O

AD10

AD11

AD12

AD13

AD14

AD15

AD16

AD17

AD18

AD19

AD20

AD21

AD22

AD23

AD24

AD25

AD26

AE1

I/O

GND/THERMAL

Y3

I/O

GND/THERMAL

I/O

Y4

GND/THERMAL

Y5

I/O

GND

I/O

GND

NC

I/O

NC

GND

NC

I/O

GND

I/O

Y22

AF2

Y23

I/O

AF3

Y24

I/O

AC2

I/O

AF4

I/O

Y25

AC3

AF5

Y26

I/O

AC4

I/O

AF6

I/O

AA1

AA2

AA3

AA4

AA5

AA22

AA23

AA24

AA25

AA26

AB1

AB2

AB3

AB4

AB5

AB6

AB7

AB8

AB9

AB10

AB11

AB12

AB13

AB14

AC5

AF7

U2

I/O

AC6

I/O

AF8

NC

I/O

U3

AC7

AF9

U4

AC8

I/O

AF10

AF11

AF12

AF13

AF14

AF15

AF16

AF17

AF18

AF19

AF20

AF21

AF22

AF23

AF24

AF25

AF26

U5

V

AC9

TRSTB

I/O

CC

V

U22

U23

U24

U25

U26

V1

AC10

AC11

AC12

AC13

AC14

AC15

AC16

AC17

AC18

AC19

AC20

AC21

AC22

AC23

AC24

AC25

AC26

AD1

CC

NC

I/O

TDI

I/O

V

AE2

CCIO

I/O

NC

I/O

NC

I/O

NC

GND

I/O

NC

I/O

AE3

V2

I/O

AE4

I/O

V3

AE5

V4

I/O

AE6

I/O

V5

GND

AE7

I/O

V22

V23

V24

V25

V26

W1

W2

W3

W4

V

AE8

I/O

CC

NC

AE9

I/O

AE10

AE11

AE12

AE13

AE14

AE15

AE16

I/O

V

I/O

CC

GND

NC

I/O

GND

AD2

I/O

(Sheet 2 of 2)

•

www.quicklogic.com

20

QL4090 QuickRAM Data Sheet Rev H

456 PBGA Mechanical Drawing

Figure 14: 456 PBGA Mechanical Drawing

•

www.quicklogic.com

21

QL4090 QuickRAM Data Sheet Rev H

Contact Information

Telephone: 408 990 4000 (US)

416 497 8884 (Canada)

44 1932 57 9011 (Europe)

49 89 930 86 170 (Germany)

852 8106 9091 (Asia)

81 45 470 5525 (Japan)

info@quicklogic.com

E-mail:

Support:

Web site:

support@quicklogic.com

http://www.quicklogic.com/

Revision History

Table 15: Revision History

Revision

Date

Comments

A

B

C

D

E

not avail.

May 2000

April 2002

First release.

F

G

Update of AC/DC Specs and reformat

Added Kfactor, Power-up, JTAG and mechanical

drawing information. Reformatted.

H

May 2002

Copyright Information

The information contained in this product brief, and the accompanying software programs

are protected by copyright. All rights are reserved by QuickLogic Corporation. QuickLogic

Corporation reserves the right to make periodic modifications of this product without

obligation to notify any person or entity of such revision. Copying, duplicating, selling, or

otherwise distributing any part of this product without the prior written consent of an

authorized representative of QuickLogic is prohibited.

QuickLogic, pASIC, and ViaLink are registered trademarks, and SpDE and QuickWorks are

trademarks of QuickLogic Corporation.

Verilog is a registered trademark of Cadence Design Systems, Inc.

•

www.quicklogic.com

22


型号：	QL4090-2PB456C
厂家：	ETC
描述：	FPGA\|1584-CELL\|CMOS\|BGA\|456PIN\|PLASTIC 可编程逻辑栅时钟
文件：	总22页 (文件大小：539K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

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