QL7100-7PS484C [ETC]
USER PROGRAMMABLE SPECIAL FUNCTION ASIC|CMOS|BGA|484PIN ; 用户可编程的特殊功能的ASIC | CMOS | BGA | 484PIN\n
| 型号： | QL7100-7PS484C |
| 厂家： | 
ETC |
| 描述： | USER PROGRAMMABLE SPECIAL FUNCTION ASIC|CMOS|BGA|484PIN
|
| 文件： | 总24页 (文件大小：266K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
QL7100 QuickDSP Data Sheet
Combining Embedded DSP Blocks, Performance, Density,
and Embedded RAM
• • • • • •
1.0 Device Highlights
Clock Network
High Speed Customizable Logic
• 9 global clock networks
• 1 dedicated, 8 programmable
• 0.25u, 5 layer metal CMOS process
• 2.5 V Vcc, 2.5 / 3.3 V drive capable I/O
• 256 programmable I/O
• 16 I/O (high drive) networks:
2 banks per I/O
• 960 Logic Cells
• 292,000 max system gates
• 20 Quad-net networks: 5 per quadrant
• Muxed based architecture,
Programmable I/O
non-volatile technology
• Completely customizable for any
• High performance enhanced I/O:
digital applications
less than 3 ns Tco
• Programmable slew rate control
• Programmable I/O standards
Dual Port SRAM
• LVTTL, LVCMOS, PCI, GTL+, SSTL2,
• 36 blocks of dual-port SRAM
and SSTL3
• 2,304 bit dual port high performance
• 8 independent I/O banks
SRAM Blocks
• 3 register configuration: Input, Output, OE
• Total of 82,900 bits
• RAM / ROM / FIFO Wizard for automatic
configuration
Parameterized IP
• Configurable and cascadable
• Free parameterized IP administered with a
• Array sizes of 2, 4, 9, and 18
• < 3 ns access times, 300+ MHz FIFO
DSP Wizard
• Supports multiple and hierarchical IP
instantiations
Applications
• Signal processing operators
• Signal processing functions
• Networking / communications for VoIP
• Speech / voice processing
• Channel coding
Figure 1: Embedded QuickDSP Block Diagram
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QL7100 QuickDSPTM Data Sheet Rev A
1
QL7100 QuickDSP Data Sheet
2.0 AC Characteristics at Vcc = 2.5V, TA=25° C (K=1.00)
The AC Specifications, Logic Cell diagrams and waveforms are provided below.
Figure 2: QuickDSP Logic Cell
Table 1: Logic Cells
Propagation
delay (ns)
Symbol
Parameter
Logic Cells
1
tPD
Combinatorial delay: time taken by the combinatorial circuit to output
0.257
Setup time: the amount of time the synchronous input of the flip flop must be stable before
the active clock edge
tSU
0.22
0
Hold time: the amount of time the synchronous input of the flip flop must be stable after the
active block edge
thl
Clock to out delay: the amount of time the synchronous input of the flip flop must be stable
after the active block edge
tCLK
0.255
tCWHI
Clock High Time: the length of time that the clock stays high
Clock Low Time: the length of time that the clock stays low
0.46
0.46
tCWLO
Set Delay: amount of time between when the flip flop is ”set” (high)
and when Q is consequent “set” (high)
tSET
tRESET
tSW
0.18
0.09
0.3
Reset Delay: amount of time between when the flip flop is ”reset” (low) and when Q is
consequent “reset” (low)
Set Width: length of time that the SET signal remains high
(low if active low)
Reset Width: length of time that the RESET signal remains high
(low if active low)
tRW
0.3
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© 2001 QuickLogic Corporation
QL7100 QuickDSP Data Sheet
Figure 3: Logic Cell Flip Flop
Figure 4: Logic Cell Flip Flop Timings - First Waveform
Figure 5: Logic Cell Flip Flop Timings - Second Waveform
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QL7100 QuickDSPTM Data Sheet Rev A
3
QL7100 QuickDSP Data Sheet
Figure 6: QuickDSP Global Clock Structure
Table 2: QuickDSP Clock Performance
Clock Performance
Global
Dedicated
1.51 ns
2.06 ns
0.55 ns
1.59 ns
1.73 ns
0.14 ns
Macro
I/O
Skew
Table 3: QuickDSP Input Register Cell
Symbol
Input Register Cell Only
tGCKP
Parameter
Propagation delay (ns)
Global clock pin delay
Global clock buffer delay
GCKB
Figure 7: Global Clock Structure Schematic
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© 2001 QuickLogic Corporation
QL7100 QuickDSP Data Sheet
Figure 8: QuickRAM Module
Table 4: RAM Cell Synchronous Write Timing
Propagation
delay (ns)
Symbol
Parameter
RAM Cell Synchronous Write Timing
1
WA Setup Time to WCLK: the amount of time the WRITE ADDRESS
TSWA
THWA
TSWD
THWD
TSWE
THWE
TWCRD
0.675
must be stable before the active edge of the WRITE CLOCK
WA Hold Time to WCLK: the amount of time the WRITE ADDRESS must
be stable after the active edge of the WRITE CLOCK
0
0.654
0
WD Setup Time to WCLK: the amount of time the WRITE DATA must be
stable before the active edge of the WRITE CLOCK
WD Hold Time to WCLK: the amount of time the WRITE DATA must be
stable after the active edge of the WRITE CLOCK
WE Setup Time to WCLK: the amount of time the WRITE ENABLE must
be stable before the active edge of the WRITE CLOCK
0.623
0
WE Hold Time to WCLK: the amount of time the WRITE ENABLE must
be stable after the active edge of the WRITE CLOCK
WCLK to RD (WA=RA) [5]: the amount of time between the active
WRITE CLOCK edge and the time when the data is available at RD
4.38
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QL7100 QuickDSPTM Data Sheet Rev A
5
QL7100 QuickDSP Data Sheet
Figure 9: RAM Cell Synchronous Write Timing
Table 5: RAM Cell Synchronous & Asynchronous Read Timing
Propagation
delay (ns)
Symbol
Parameter
RAM Cell Synchronous Read Timing
1
RA Setup Time to RCLK: the amount of time the READ ADDRESS must
TSRA
THRA
TSRE
0.686
be stable before the active edge of the READ CLOCK
RA Hold Time to RCLK: the amount of time the READ ADDRESS must
be stable after the active edge of the READ CLOCK
0
0.243
0
RE Setup Time to RCLK: the amount of time the READ ENABLE must
be stable before the active edge of the READ CLOCK
RE Hold Time to RCLK: the amount of time the READ ENABLE must be
stable after the active edge of the READ CLOCK
THRE
TRCRD
RCLK to RD [5]: the amount of time between the active READ CLOCK
edge and the time when the data is available at RD
4.38
RAM Cell Synchronous Read Timing
RA to RD [5]: amount of time between when the READ ADDRESS is
input and when the DATA is output
RPDRD
2.06
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© 2001 QuickLogic Corporation
QL7100 QuickDSP Data Sheet
Figure 10: RAM Cell Synchronous & Asynchronous Read Timing
Figure 11: QuickDSP Cell I/O
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QL7100 QuickDSPTM Data Sheet Rev A
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QL7100 QuickDSP Data Sheet
Figure 12: QuickDSP Input Register Cell
Table 6: Input Register Cell
Propagation
delay (ns)
Symbol
Parameter
Input Register Cell Only
1
Input register setup time: the amount of time the synchronous input of
the flip flop must be stable before the active clock edge
tISU
tIH
3.12
Input register hold time: the amount of time the synchronous input of the
flip flop must be stable after the active clock edge
0
Input register clock to Q: the amount of time taken by the flip flop to
output after the active clock edge
tICLK
tIRST
tIESU
tIEH
1.08
0.99
0.37
0
Input register reset delay: amount of time between when the flip flop is
“reset”(low) and when Q is consequently “reset” (low)
Input register clock enable setup time: the amount of time “enable” must
be stable before the active clock edge
Input register clock enable time: the amount of time “enable” must be
stable after the active clock edge
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© 2001 QuickLogic Corporation
QL7100 QuickDSP Data Sheet
Table 7: Standard Input Delays
Propagation
delay (ns)
Symbol
Parameter
Standard
Input Delays
To get the total input delay and this delay to tISU
1
tSID (LVTTL)
LVTTL input delay: Low Voltage TTL for 3.3V applications
0.34
0.42
LVCMOS2 input delay: Low Voltage CMOS for 2.5V and lower
applications
tSID (LVCMOS2)
tSID (GTL+)
tSID (SSTL3)
tSID (SSTL2)
GTL+ input delay: Gunning Transceiver Logic
0.68
0.55
SSTL3 input delay: Stub Series Terminated Logic for 3.3V
SSTL2 input delay: Stub Series Terminated Logic for 2.5V
0.607
Figure 13: QuickDSP Input Register Cell Timing
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QL7100 QuickDSPTM Data Sheet Rev A
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QL7100 QuickDSP Data Sheet
Figure 14: QuickDSP Output Register Cell
Table 8: QuickDSP Output Register Cell
Propagation
delay (ns)
Symbol
Parameter
Output Register Cell Only
1
TOUTLH
TOUTHL
TPZH
Output Delay Low to High (10% of H)
0.40
0.55
Output Delay High to Low (90% of H)
Output Delay Tri-state to High (10% of Z)
Output Delay Tri-state to Low (90% of Z)
Output Delay High to Tri-State
TPZL
TPHZ
3.07
2.53
TPLZ
Output Delay Low to Tri-State
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© 2001 QuickLogic Corporation
QL7100 QuickDSP Data Sheet
Figure 15: QuickDSP Output Register Cell Timing
Table 9: VCCIO = 3.3 V
Fast Slew
Slow Slew
2.8 V/ns
1.0 V/ns
1.0 V/ns
Rising Edge
Falling Edge
2.86 V/ns
Table 10: VCCIO = 2.5 V
Fast Slew
Slow Slew
Rising Edge
Falling Edge
1.7 V/ns
1.9 V/ns
0.6 V/ns
0.6 V/ns
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QL7100 QuickDSPTM Data Sheet Rev A
11
QL7100 QuickDSP Data Sheet
3.0 DC Characteristics
The DC Specifications are provided in the tables below.
Table 11: Absolute Maximum Ratings
VCC Voltage
VCCIO Voltage
-0.5 to 3.6V
-0.5 to 4.6V
2.7V
DC Input Current
ESD Pad Protection
Storage Temperature
20 mA
2000V
-65°C to +150°C
VREF Voltage
-0.5V to VCCIO +0.5V
100 mA
Input Voltage
Latch-up Immunity
Maximum Lead
Temperature
300°C
Table 12: Operating Range
Military Industrial
Symbol
Parameter
Commercial
Unit
Min
Max
2.7
Min
Max
2.7
Min
2.3
2.3
0
Max
2.7
VCC
VCCIO
TA
Supply Voltage
2.3
2.3
-55
2.3
2.3
-40
V
3.6
3.6
3.6
V
I/O Input Tolerance Voltage
Ambient Temperature
Case Temperature
85
70
°C
°C
TC
125
2.3
-4 Speed Grade
0.42
0.42
0.42
0.42
0.43
0.43
0.43
0.43
2.16
1.80
1.26
1.14
0.47
0.46
0.46
0.46
2.11
1.76
1.23
1.11
n/a
n/a
n/a
n/a
-5 Speed Grade
-6 Speed Grade
-7 Speed Grade
1.92
1.35
1.22
K
Delay Factor
Table 13: DC Input and Output Levels
VIL VIH
VMAX
VREF
VOL
VMAX
0.4
VOH
VMIN
24.
IOL
IOH
VMIN VMAX VMIN
VMIN
2.0
VMAX
mA mA
LVTTL
LVCMOS2
GTL+
n/a
n/a
n/a
n/a
-0.3
-0.3
-0.3
-0.3
-0.3
-0.3
0.8
VCCIO-0.3
VCCIO-0.3
VCCIO-0.3
VCCIO-0.5
VCCIO+0.3
VCCIO+0.3
2.0
2.0
40
1.5
7.6
9
-2.0
-2.0
n/a
0.7
1.7
0.7
1.7
0.88
n/a
1.12
n/a
V
REF-2.0
VREF+2.0
0.5xVCC
VREF+0.18
VREF+2.0
0.6
n/a
PCI
0.3xVCC
0.1xVCC
0.74
0.9xVC
1.76
-0.5
-7.6
-8
SSTL2
SSTL3
1.15
1.3
1.35
1.7
V
REF-0.18
VREF-0.2
1.10
1.90
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© 2001 QuickLogic Corporation
QL7100 QuickDSP Data Sheet
4.0 Pin Descriptions
Table 14: Pin Descriptions
Pin
Function
Description
Test Data In for JTAG /RAM init.
Serial Data In
Hold HIGH during normal operation. Connects to serial PROM data in for
RAM initialization. Connect to VCC if unused
TDI/RSI
Active low Reset for JTAG /RAM
init. reset out
Hold LOW during normal operation. Connects to serial PROM reset for
RAM initialization. Connect to GND if unused
TRSTB/RRO
TMS
Test Mode Select for JTAG
Test Clock for JTAG
Hold HIGH during normal operation. Connect to VCC if not used for JTAG
Hold HIGH or LOW during normal operation. Connect to VCC or ground
if not used for JTAG
TCK
Test data out for JTAG /RAM init.
clock out
Connect to serial PROM clock for RAM initialization. Must be left
unconnected if not used for JTAG or RAM initialization
TDO/RCO
I/GCLK
High-drive input and/or global
network driver
Can be configured as either or both
I/O
Input/Output pin
Power supply pin
Can be configured as an input and/or output
Connect to 2.5V supply
VCC
Connect to 3.3 volt supply if 3.3 volt input tolerance is required, otherwise
connect to 2.5V supply
VCCIO
Input voltage tolerance pin
GND
Ground pin
Connect to ground
PLLIN
PLL clock input
Clock input for PLL
DEDCLK
GNDPLL
INREF
Dedicated clock pin
Ground pin for PLL
Differential reference voltage
PLL output pin
Low skew global clock
Connect to GND
Connect to reference voltage or ground if used for non-differential input
Dedicated PLL output pin. Otherwise may be left unconnected
PLLOUT
Can be used as highdrive input or clock to I/O register within the same
bank. Tied low or high if unused
IOCTRL
Highdrive input
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QL7100 QuickDSPTM Data Sheet Rev A
13
QL7100 QuickDSP Data Sheet
4.1 Recommended Unused Pin Terminations for the QuickDSP devices
All unused, general purpose I/O pins can be tied to VCC, GND or HIZ (high impedance) internally using
the Configuration Editor. The option is given in the right-bottom corner of the Configuration window.
The use the Configuration Editor go to: TOOLS/CONFIGURATION PINS.
The rest of the pins should be terminated at the board level in the following manner:
Table 15: Recommended Unused Pin Terminations
Signal Name
Recommended Termination
Unused PLL output pins must be connected to either VCC or GND so that their associated input
buffer never floats. Utilized PLL output pins that route the PLL clock outside of the chip, do not need
to be tied to either VCC or GND.
PLLOUT<x>
IOCTRL<y>
Any unused pins of this type must be connected to either VCC or GND.
Any unused clock pins should be connected to VCC or GND.
CLK/PLLIN<x>
If a PLL module is not used, then the associated PLLRST<x> must be connected to VCC, under
normal operation use it as needed.
PLLRST<x>
INREF<y>
If an I/O bank does not require the use of INREF signal the pin should be connected to GND.
NOTE: x -> number, y -> alphabetical character
QL 7100 - 4 PS672 C
QuickLogic device
Operating Range
C = Commercial
I = Industrial
QuickDSP device
part number
M = Military
Package Code
Speed Grade
4 = Quick
5 = Fast
6 = Faster
7 = Fastest
PT280 = 280-pin FPBGA
PS484 = 484-pin BGA (1.0mm)
PS672 = 672-pin BGA (1.0mm)
PB516 = 516-pin BGA (1.27mm)
Figure 16: Ordering Information
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© 2001 QuickLogic Corporation
QL7100 QuickDSP Data Sheet
5.0 208 PQFP Pinout Diagram
Top
QuickDSP
QL7100-4PQ208C
6.0 208 PQFP Pinout Table
Table 16: 208 PQFP Pinout Table
208 PQFP
Function
PLLRST(3)
VCCPLL(3)
GND
208 PQFP
Function
IO(B)
208 PQFP
Function
IO(C)
208 PQFP
106
Function
VCCPLL(1)
IO(E)
208 PQFP
141
Function
IO(F)
208 PQFP
176
Function
IO(G)
1
2
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
IO(B)
VCCIO(C)
IO(C)
107
142
IO(F)
177
VCCIO(G)
GND
3
IO(B)
108
GND
143
IO(F)
178
4
GND
IOCTRL(B)
INREF(B)
IOCTRL(B)
IO(B)
IO(C)
109
IO(E)
144
IOCTRL(F)
INREF(F)
VCC
179
IO(G)
5
IO(A)
GND
110
IO(E)
145
180
IO(G)
6
IO(A)
VCC
111
VCCIO(E)
IO(E)
146
181
IO(G)
7
IO(A)
IO(C)
112
147
IOCTRL(F)
IO(F)
182
VCC
8
VCCIO(A)
IO(A)
IO(B)
TRSTB
VCC
113
VCC
148
183
TCK
9
VCCIO(B)
IO(B)
114
IO(E)
149
IO(F)
184
VCC
10
11
12
13
14
15
16
17
18
19
20
21
IO(A)
IO(D)
115
IO(E)
150
VCCIO(F)
IO(F)
185
IO(H)
IOCTRL(A)
VCC
VCC
IO(D)
116
IO(E)
151
186
IO(H)
IO(B)
IO(D)
117
IOCTRL(E)
INREF(E)
IOCTRL(E)
IO(E)
152
IO(F)
187
IO(H)
INREF(A)
IOCTRL(A)
IO(A)
IO(B)
GND
118
153
GND
188
GND
GND
VCCIO(D)
IO(D)
119
154
IO(F)
189
VCCIO(H)
IO(H)
TDO
120
155
PLLOUT(3)
GNDPLL(0)
GND
190
IO(A)
PLLOUT(1)
GNDPLL(2)
GND
VCC
121
IO(E)
156
191
IO(H)
IO(A)
IO(D)
122
VCCIO(E)
GND
157
158
192
IOCTRL(H)
IO(H)
IO(A)
IO(D)
123
VCCPLL(0)
PLLRST(0)
GND
193
VCCIO(A)
IO(A)
VCCPLL(2)
PLLRST(2)
VCC
VCC
124
125
IO(E)
159
160
194
INREF(H)
VCC
IO(D)
IO(E)
195
GND
IO(D)
126
IO(E)
161
IO(G)
196
IOCTRL(H)
CLK(5),PLLIN
(3)
22
IO(A)
57
IO(C)
92
IOCTRL(D)
127
162
VCCIO(G)
197
IO(H)
23
24
25
26
TDI
58
59
60
61
GND
IO(C)
93
94
95
96
INREF(D)
IOCTRL(D)
IO(D)
128
129
130
131
CLK(6)
VCC
163
164
165
166
IO(G)
IO(G)
VCC
198
199
200
201
IO(H)
IO(H)
IO(H)
IO(H)
CLK(0)
CLK(1)
VCC
VCCIO(C)
IO(C)
CLK(7)
VCC
IO(D)
IO(G)
CLK(2),PLLIN
(2)
27
62
IO(C)
97
IO(D)
132
CLK(8)
167
IO(G)
202
IO(H)
CLK(3),PLLIN
(1)
28
29
30
63
64
65
IO(C)
IO(C)
IO(C)
98
99
VCCIO(D)
IO(D)
133
134
135
TMS
IO(F)
IO(F)
168
169
170
IO(G)
203
204
205
VCCIO(H)
GND
VCC
IOCTRL(G)
INREF(G)
CLK(4),DEDC
LK,PLLIN(0)
100
IO(D)
IO(H)
31
32
33
34
35
IO(B)
IO(B)
66
67
68
69
70
IO(C)
101
102
103
104
105
GND
136
137
138
139
140
IO(F)
GND
171
172
173
174
175
IOCTRL(G)
IO(G)
206
207
208
PLLOUT(2)
GND
IOCTRL(C)
INREF(C)
IOCTRL(C)
IO(C)
PLLOUT(0)
GND
GND
VCCIO(F)
IO(F)
IO(G)
GNDPLL(3)
VCCIO(B)
IO(B)
GNDPLL(1)
PLLRST(1)
IO(G)
IO(F)
VCC
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QL7100 QuickDSPTM Data Sheet Rev A
15
QL7100 QuickDSP Data Sheet
7.0 280 PBGA Pinout Diagram
Top
QuickDSP
QL7100-4PT280C
Bottom
Pin A1
Corner
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© 2001 QuickLogic Corporation
QL7100 QuickDSP Data Sheet
8.0 280 PBGA Pinout Table
Table 17: 280 PBGA Pinout Table
280 PBGA Function 280 PBGA Function 280 PBGA Function 280 PBGA Function 280 PBGA Function 280 PBGA
Function
CLK<5>/PLLI
A1
PLLOUT<3>
C10
E19
IOCTRL<D>
K16
I/O<C>
R4
I/O<H>
U13
I/O<B>
N<3>
VCCIO<E>
I/O<E>
I/O<E>
I/O<E>
VCCIO<E>
I/O<E>
I/O<E>
I/O<E>
I/O<E>
I/O<G>
I/O<G>
I/O<F>
I/O<F>
I/O<F>
I/O<F>
I/O<F>
A2
A3
GNDPLL<0>
I/O<F>
C11
C12
C13
C14
C15
C16
C17
C18
C19
D1
F1
F2
INREF<G>
IOCTRL<G>
I/O<G>
I/O<G>
GND
K17
K18
K19
L1
I/O<D>
I/O<C>
TRSTB
I/O<H>
I/O<H>
VCCIO<H>
I/O<H>
VCC
R5
R6
GND
GND
U14
U15
U16
U17
U18
U19
V1
IOCTRL<B>
VCCIO<B>
I/O<B>
A4
I/O<F>
F3
R7
VCC
A5
I/O<F>
F4
R8
VCC
TDO
A6
IOCTRL<F>
I/O<F>
F5
L2
R9
GND
PLLRST<2>
I/O<B>
A7
F15
F16
F17
F18
F19
G1
G2
G3
G4
G5
G15
VCC
L3
R10
R11
R12
R13
R14
R15
R16
R17
R18
R19
T1
GND
A8
I/O<F>
IOCTRL<D>
I/O<D>
I/O<D>
I/O<D>
I/O<G>
I/O<G>
IOCTRL<G>
I/O<G>
VCC
L4
VCC
PLLOUT<2>
GNDPLL<3>
GND
A9
I/O<F>
L5
VCC
V2
A10
A11
A12
A13
A14
A15
A16
A17
CLK<7>
I/O<E>
L15
L16
L17
L18
L19
M1
M2
M3
GND
VCC
V3
I/O<C>
VCCIO<C>
I/O<C>
I/O<C>
I/O<H>
I/O<H>
I/O<H>
VCC
V4
I/O<A>
I/O<E>
D2
GND
V5
I/O<A>
I/O<E>
D3
I/O<C>
VCCIO<C>
I/O<C>
I/O<C>
I/O<H>
V6
IOCTRL<A>
I/O<A>
IOCTRL<E>
I/O<E>
D4
V7
D5
V8
I/O<A>
I/O<E>
D6
V9
I/O<A>
I/O<E>
D7
VCC
V10
CLK<1>
CLK<4>DEDC
LK/PLLIN<0>
A18
PLLRST<1>
D8
I/O<F>
G16
I/O<D>
M4
I/O<H>
T2
I/O<H>
V11
A19
B1
B2
B3
B4
B5
B6
B7
GND
PLLRST<0>
GND
D9
CLK<8>
I/O<E>
G17
G18
G19
H1
I/O<D>
I/O<D>
I/O<D>
I/O<G>
I/O<G>
I/O<G>
I/O<G>
VCC
M5
M15
M16
M17
M18
M19
N1
VCC
VCC
T3
T4
T5
T6
T7
T8
T9
T10
I/O<A>
I/O<A>
V12
V13
V14
V15
V16
V17
V18
V19
I/O<B>
I/O<B>
D10
D11
D12
D13
D14
D15
D16
I/O<E>
INREF<C>
I/O<C>
I/O<A>
INREF<B>
I/O<B>
I/O<F>
I/O<E>
IOCTRL<A>
I/O<A>
I/O<F>
INREF<E>
I/O<E>
H2
I/O<C>
I/O<B>
I/O<F>
H3
I/O<C>
I/O<A>
I/O<B>
INREF<F>
I/O<F>
I/O<E>
H4
IOCTRL<H>
I/O<H>
I/O<A>
GNDPLL<2>
GND
I/O<D>
H5
N2
I/O<A>
CLK<3>/PLLI
N<1>
B8
I/O<F>
D17
I/O<D>
H15
VCC
N3
I/O<H>
T11
W1
GND
B9
TMS
CLK<6>
I/O<E>
D18
D19
E1
I/O<D>
I/O<D>
I/O<G>
I/O<G>
VCCIO<G>
I/O<F>
GND
H16
H17
H18
H19
J1
VCC
I/O<D>
I/O<D>
I/O<D>
I/O<G>
I/O<G>
VCCIO<G>
I/O<G>
N4
N5
I/O<H>
VCC
T12
T13
T14
T15
T16
T17
T18
T19
I/O<B>
I/O<B>
W2
W3
W4
W5
W6
W7
W8
W9
PLLRST<3>
I/O<A>
I/O<A>
I/O<A>
I/O<A>
I/O<A>
I/O<A>
TDI
B10
B11
B12
B13
B14
B15
B16
N15
N16
N17
N18
N19
P1
VCC
I/O<B>
I/O<E>
E2
I/O<C>
I/O<B>
IOCTRL<E>
I/O<E>
E3
I/O<C>
I/O<B>
E4
J2
IOCTRL<C>
IOCTRL<C>
I/O<H>
VCCPLL<2>
I/O<B>
I/O<E>
E5
J3
I/O<E>
E6
VCC
J4
I/O<B>
CLK<2>/PLLI
N<2>
B17
VCCPLL<1>
E7
VCC
J5
GND
P2
I/O<H>
U1
I/O<A>
W10
B18
B19
C1
C2
C3
C4
C5
C6
C7
C8
C9
GNDPLL<1>
PLLOUT<0>
I/O<F>
E8
VCC
VCC
J15
J16
J17
J18
J19
K1
VCC
I/O<C>
VCCIO<D>
I/O<D>
I/O<D>
VCC
P3
P4
IOCTRL<H>
INREF<H>
VCC
U2
U3
I/O<A>
VCCPLL<3>
I/O<A>
W11
W12
W13
W14
W15
W16
W17
W18
W19
I/O<B>
I/O<B>
E9
E10
E11
E12
E13
E14
E15
E16
E17
E18
GND
P5
U4
I/O<B>
VCCPLL<0>
I/O<F>
GND
P15
P16
P17
P18
P19
R1
GND
U5
VCCIO<A>
INREF<A>
I/O<A>
IOCTRL<B>
I/O<B>
VCC
I/O<C>
U6
I/O<F>
VCC
I/O<C>
U7
I/O<B>
VCCIO<F>
IOCTRL<F>
I/O<F>
GND
K2
TCK
I/O<C>
U8
I/O<A>
I/O<B>
GND
K3
I/O<G>
I/O<G>
GND
I/O<C>
U9
VCCIO<A>
CLK<0>
I/O<B>
I/O<D>
VCCIO<D>
INREF<D>
K4
I/O<H>
U10
U11
U12
PLLOUT<1>
I/O<F>
K5
R2
I/O<H>
VCCIO<B>
I/O<B>
VCCIO<F>
K15
GND
R3
VCCIO<H>
•
•
•
•
•
•
QL7100 QuickDSPTM Data Sheet Rev A
17
QL7100 QuickDSP Data Sheet
9.0 484 PBGA Pinout Diagram
Top
QuickDSP
QL7100-4PS484C
Bottom
Pin A1
Corner
20 19 18 17 16 15 14 13 12 11 10
9
8
7
6
5
4
3
2
1
22 21
A
B
C
D
E
F
G
H
J
K
L
M
N
P
R
T
U
V
W
Y
AA
AB
•
•
•
•
•
•
18
www.quicklogic.com
© 2001 QuickLogic Corporation
QL7100 QuickDSP Data Sheet
10.0 484 PBGA Pinout Table
Table 18: 484 PBGA Pinout Table
484 PBGA Function 484 PBGA Function 484 PBGA Function 484 PBGA
Function
I/O<A>
I/O<A>
I/O<A>
VCC
484 PBGA
L21
L22
M1
Function
NC
484 PBGA Function
A1
A2
NC
PLLRST<3>
I/O<A>
I/O<A>
I/O<A>
NC
C17
C18
C19
C20
C21
C22
D1
NC
I/O<G>
I/O<F>
GNDPLL<0>
I/O<F>
I/O<F>
I/O<A>
I/O<A>
I/O<A>
I/O<A>
I/O<A>
I/O<H>
NC
F11
F12
F13
F14
F15
F16
F17
F18
F19
F20
F21
F22
G1
VCCIO<H>
VCCIO<G>
I/O<G>
VCCIO<G>
NC
J5
J6
P15
P16
P17
P18
P19
P20
P21
P22
R1
VCC
I/O<E>
NC
I/O<F>
I/O<B>
I/O<B>
I/O<B>
CLK<3>/PLLIN<1>
NC
A3
J7
A4
J8
M2
I/O<E>
NC
A5
J9
GND
M3
A6
VCCIO<G>
NC
J10
J11
J12
J13
J14
J15
J16
J17
J18
J19
J20
J21
J22
K1
VCC
M4
I/O<E>
I/O<E>
I/O<E>
I/O<B>
INREF<B>
I/O<B>
I/O<B>
I/O<B>
NC
A7
I/O<H>
IOCTRL<H>
I/O<H>
NC
VCC
M5
A8
D2
I/O<F>
I/O<F>
IOCTRL<F>
I/O<F>
IOCTRL<F>
NC
GND
M6
VCCIO<B>
CLK<1>
VCC
A9
D3
VCC
M7
A10
A11
A12
A13
A14
A15
A16
A17
A18
A19
A20
A21
A22
B1
D4
GND
M8
R2
NC
D5
VCC
M9
VCC
R3
TCK
D6
I/O<F>
VCCIO<F>
I/O<F>
I/O<F>
I/O<F>
I/O<F>
I/O<F>
TDI
M10
M11
M12
M13
M14
M15
M16
M17
M18
M19
M20
M21
M22
N1
GND
R4
I/O<G>
I/O<G>
I/O<G>
NC
D7
GND
R5
D8
I/O<H>
NC
G2
NC
GND
R6
D9
G3
I/O<A>
I/O<A>
I/O<A>
I/O<A>
GND
GND
R7
I/O<B>
GND
D10
D11
D12
D13
D14
D15
D16
D17
D18
D19
D20
D21
D22
E1
I/O<H>
I/O<H>
I/O<G>
I/O<G>
I/O<G>
IOCTRL<G>
I/O<G>
I/O<G>
I/O<F>
VCCPLL<0>
I/O<F>
I/O<F>
I/O<F>
IOCTRL<A>
I/O<A>
I/O<A>
I/O<A>
NC
G4
GND
R8
I/O<G>
I/O<G>
I/O<F>
GND
G5
GND
R9
VCC
G6
GND
R10
R11
R12
R13
R14
R15
R16
R17
R18
R19
R20
R21
R22
T1
VCC
G7
I/O<E>
I/O<E>
I/O<E>
CLK<7>
CLK<5>/PLLIN<3>
TMS
GND
G8
I/O<H>
I/O<H>
NC
K2
I/O<A>
I/O<A>
I/O<A>
I/O<A>
VCCIO<A>
NC
VCC
PLLOUT<3>
I/O<F>
I/O<A>
GND
G9
K3
VCC
G10
G11
G12
G13
G14
G15
G16
G17
G18
G19
G20
G21
G22
H1
K4
VCC
I/O<G>
GND
K5
GND
B2
K6
I/O<D>
VCCIO<E>
I/O<E>
I/O<E>
I/O<E>
I/O<E>
I/O<E>
I/O<B>
I/O<B>
I/O<B>
I/O<B>
I/O<B>
VCCIO<B>
GND
B3
GNDPLL<3>
GND
NC
K7
NC
B4
NC
K8
VCC
N2
I/O<B>
I/O<B>
NC
B5
I/O<A>
I/O<H>
I/O<H>
INREF<H>
I/O<H>
I/O<H>
I/O<H>
NC
I/O<G>
GND
K9
VCC
N3
B6
K10
K11
K12
K13
K14
K15
K16
K17
K18
K19
K20
K21
K22
GND
N4
B7
VCCIO<F>
I/O<F>
I/O<F>
I/O<F>
INREF<F>
I/O<F>
I/O<A>
I/O<A>
I/O<A>
I/O<A>
IOCTRL<A>
VCCIO<A>
GND
N5
I/O<B>
NC
B8
E2
GND
N6
B9
E3
GND
N7
NC
B10
B11
B12
B13
B14
B15
B16
B17
B18
E4
VCC
N8
VCC
T2
E5
VCC
N9
VCC
T3
E6
I/O<H>
NC
NC
N10
N11
N12
N13
N14
N15
N16
GND
T4
NC
E7
I/O<F>
I/O<F>
NC
GND
T5
NC
E8
I/O<H>
I/O<H>
I/O<H>
VCC
H2
GND
T6
NC
E9
H3
GND
T7
I/O<G>
I/O<G>
I/O<G>
E10
E11
E12
H4
I/O<F>
I/O<F>
NC
VCC
T8
I/O<C>
NC
H5
VCC
T9
I/O<G>
H6
I/O<E>
T10
TRSTB
CLK<4>
DEDCLK/PLLIN<0>
B19
PLLRST<0>
E13
I/O<G>
H7
I/O<H>
L1
N17
VCCIO<E>
T11
GND
B20
B21
B22
C1
I/O<F>
I/O<F>
I/O<F>
NC
E14
E15
E16
E17
E18
E19
E20
E21
E22
F1
NC
IOCTRL<G>
I/O<G>
INREF<G>
NC
H8
H9
GND
VCC
L2
L3
CLK<0>
CLK<2>/PLLIN<2>
I/O<A>
I/O<A>
I/O<A>
GND
N18
N19
N20
N21
N22
P1
I/O<E>
I/O<E>
I/O<E>
I/O<E>
I/O<E>
NC
T12
T13
T14
T15
T16
T17
T18
T19
T20
T21
T22
U1
NC
I/O<D>
NC
H10
H11
H12
H13
H14
H15
H16
H17
H18
H19
H20
H21
H22
J1
VCC
L4
VCC
L5
I/O<D>
GND
C2
I/O<A>
VCCPLL<3>
PLLOUT<2>
I/O<A>
NC
GND
L6
C3
I/O<F>
VCC
L7
I/O<E>
I/O<E>
NC
C4
I/O<F>
VCC
L8
GND
P2
I/O<B>
I/O<B>
I/O<B>
I/O<B>
VCCIO<B>
I/O<B>
VCC
C5
NC
GND
L9
GND
P3
C6
I/O<F>
I/O<F>
I/O<F>
NC
L10
L11
L12
L13
L14
L15
L16
L17
L18
L19
L20
GND
P4
NC
C7
I/O<H>
NC
I/O<A>
GND
P5
IOCTRL<E>
I/O<E>
IOCTRL<B>
I/O<B>
IOCTRL<B>
I/O<B>
I/O<B>
I/O<C>
VCCIO<C>
NC
C8
F2
INREF<A>
NC
GND
P6
C9
IOCTRL<H>
NC
F3
I/O<F>
I/O<F>
I/O<F>
NC
GND
P7
C10
C11
C12
C13
C14
C15
C16
F4
I/O<A>
VCC
P8
U2
I/O<H>
NC
F5
I/O<A>
VCC
P9
GND
U3
F6
VCCIO<A>
VCCIO<H>
I/O<H>
VCCIO<H>
I/O<H>
CLK<6>
VCCIO<F>
I/O<F>
CLK<8>
I/O<F>
P10
P11
P12
P13
P14
VCC
U4
I/O<G>
NC
F7
I/O<A>
I/O<A>
I/O<A>
I/O<A>
GND
U5
F8
J2
VCC
U6
I/O<G>
I/O<G>
F9
J3
VCC
U7
F10
J4
GND
U8
•
•
•
•
•
•
QL7100 QuickDSPTM Data Sheet Rev A
19
QL7100 QuickDSP Data Sheet
Table 18: 484 PBGA Pinout Table (Continued)
484 PBGA Function 484 PBGA Function 484 PBGA Function 484 PBGA
Function
I/O<C>
484 PBGA
AA5
Function
I/O<C>
I/O<C>
NC
484 PBGA Function
U9
U10
U11
U12
U13
U14
U15
U16
U17
U18
U19
U20
U21
U22
V1
VCCIO<C>
I/O<C>
V8
I/O<C>
NC
W7
W8
NC
NC
Y6
Y7
AB4
AB5
I/O<B>
I/O<B>
I/O<C>
I/O<C>
IOCTRL<C>
I/O<C>
I/O<C>
NC
V9
I/O<C>
AA6
VCCIO<C>
VCCIO<D>
I/O<D>
V10
V11
V12
V13
V14
V15
V16
V17
V18
V19
V20
V21
V22
W1
I/O<C>
NC
W9
NC
Y8
IOCTRL<C>
I/O<C>
AA7
AB6
W10
W11
W12
W13
W14
W15
W16
W17
W18
W19
W20
W21
W22
Y1
NC
Y9
AA8
INREF<C>
NC
AB7
VCC
I/O<C>
NC
Y10
Y11
Y12
Y13
Y14
Y15
Y16
Y17
Y18
Y19
Y20
Y21
Y22
AA1
AA2
AA3
AA4
I/O<C>
AA9
AB8
VCCIO<D>
NC
NC
I/O<D>
AA10
AA11
AA12
AA13
AA14
AA15
AA16
AA17
AA18
AA19
AA20
AA21
AA22
AB1
I/O<C>
I/O<C>
I/O<D>
I/O<D>
I/O<D>
I/O<D>
NC
AB9
I/O<D>
I/O<D>
INREF<D>
I/O<D>
I/O<E>
I/O<E>
I/O<E>
I/O<E>
I/O<E>
I/O<B>
I/O<B>
I/O<B>
I/O<B>
I/O<B>
I/O<C>
I/O<D>
NC
NC
AB10
AB11
AB12
AB13
AB14
AB15
AB16
AB17
AB18
AB19
AB20
AB21
AB22
VCCIO<D>
VCCIO<E>
I/O<E>
NC
I/O<D>
NC
I/O<D>
I/O<D>
I/O<D>
NC
IOCTRL<D>
I/O<D>
I/O<E>
NC
IOCTRL<E>
NC
I/O<E>
NC
I/O<D>
I/O<D>
IOCTRL<D>
I/O<D>
I/O<D>
I/O<E>
GND
I/O<E>
NC
INREF<E>
I/O<B>
I/O<E>
NC
PLLOUT<0>
PLLRST<1>
I/O<E>
I/O<D>
I/O<E>
GNDPLL<1>
I/O<E>
I/O<E>
I/O<B>
GNDPLL<2>
PLLRST<2>
V2
I/O<B>
I/O<E>
I/O<B>
I/O<B>
VCCPLL<2>
I/O<C>
I/O<C>
V3
I/O<B>
W2
I/O<E>
V4
I/O<B>
W3
Y2
TDO
VCCPLL<1>
I/O<E>
V5
I/O<B>
W4
Y3
PLLOUT<1>
GND
V6
NC
W5
Y4
AB2
V7
I/O<C>
W6
Y5
I/O<B>
AB3
•
•
•
•
•
•
20
www.quicklogic.com
© 2001 QuickLogic Corporation
QL7100 QuickDSP Data Sheet
11.0 516 PBGA Pinout Diagram
Top
QuickDSP
QL7100-4PB516C
Bottom
PIN A1
CORNER
•
•
•
•
•
•
QL7100 QuickDSPTM Data Sheet Rev A
21
QL7100 QuickDSP Data Sheet
12.0 516 PBGA Pinout Table
Table 19: 516 PBGA Pinout Table
516 PBGA
A1
Function
GND
516 PBGA
C10
C11
C12
C13
C14
C15
C16
C17
C18
C19
C20
C21
C22
C23
C24
C25
C26
D1
Function
NC
516 PBGA Function 516 PBGA Function 516 PBGA Function 516 PBGA
Function
GND
E19
E20
E21
E22
E23
E24
E25
E26
F1
NC
IO(E)
J4
J5
NC
IO(G)
VCCIO(G)
VCCIO(D)
IO(D)
IO(D)
NC
N5
N6
IO(G)
GND
GND
GND
GND
GND
GND
GND
GND
IO(D)
IO(D)
NC
T16
T21
T22
T23
T24
T25
T26
U1
A2
IO(F)
IO(F)
NC
VCC
A3
IO(F)
NC
J6
N11
N12
N13
N14
N15
N16
N21
N22
N23
N24
N25
N26
P1
VCC
A4
IO(F)
CLK(7)
IO(E)
IO(E)
IO(E)
NC
NC
J21
J22
J23
J24
J25
J26
K1
NC
A5
NC
GNDPLL(1)
IO(E)
IO(C)
NC
A6
IO(F)
A7
IOCTRL(F)
IO(F)
IO(D)
IO(C)
IO(H)
IO(H)
NC
A8
IO(D)
IO(D)
IO(D)
NC
A9
IO(F)
IO(E)
IO(E)
IO(E)
IO(E)
IO(E)
IO(E)
IO(E)
IO(E)
IO(E)
IO(G)
IO(G)
IO(F)
NC
IOCTRL(G)
NC
U2
A10
A11
A12
A13
A14
A15
A16
A17
A18
A19
A20
A21
A22
A23
A24
A25
A26
B1
IO(F)
F2
U3
NC
F3
NC
K2
IO(G)
IO(G)
IO(G)
NC
U4
IO(H)
IO(H)
GND
IO(F)
F4
NC
K3
U5
IO(E)
F5
IO(F)
K4
IO(D)
IO(D)
NC
U6
NC
F6
GND
K5
U21
U22
U23
U24
U25
U26
V1
GND
IO(E)
F7
VCCIO(F)
VCC
K6
GND
GND
IO(D)
IO(D)
NC
NC
IO(E)
F8
K21
K22
K23
K24
K25
K26
L1
P2
IO(H)
IO(H)
VCC
IO(H)
VCCIO(H)
GND
GND
GND
GND
GND
GND
VCCIO(C)
IO(C)
VCC
NC
NC
IO(E)
F9
VCCIO(F)
GND
P3
NC
IOCTRL(E)
IOCTRL(E)
NC
F10
F11
F12
F13
F14
F15
F16
F17
F18
F19
F20
F21
F22
F23
F24
F25
F26
G1
P4
IO(C)
IO(C)
IO(H)
IOCTRL(H)
IOCTRL(H)
IO(H)
NC
D2
VCC
P5
D3
VCCIO(F)
GND
NC
P6
IO(E)
D4
NC
P11
P12
P13
P14
P15
P16
P21
P22
P23
P24
P25
P26
R1
V2
NC
D5
GNDPLL(0)
IO(F)
IO(F)
NC
VCCIO(E)
VCC
IO(G)
NC
V3
IO(E)
D6
L2
V4
IO(E)
D7
VCC
L3
IO(G)
IO(G)
VCC
VCC
GND
GND
GND
GND
GND
GND
VCC
IO(D)
IO(D)
NC
V5
PLLRST(1)
GND
D8
GND
L4
V6
VCCIO(H)
VCCIO(C)
IO(C)
NC
D9
IO(F)
IO(F)
IO(F)
NC
VCCIO(E)
VCC
L5
V21
V22
V23
V24
V25
V26
W1
W2
W3
W4
W5
W6
W21
W22
W23
W24
W25
W26
Y1
IO(F)
D10
D11
D12
D13
D14
D15
D16
D17
D18
D19
D20
D21
D22
D23
D24
D25
D26
E1
L6
B2
PLLRST(0)
IO(F)
VCCIO(E)
GND
L11
L12
L13
L14
L15
L16
L21
L22
L23
L24
L25
L26
M1
B3
IOCTRL(C)
IO(C)
IO(C)
INREF(H)
IO(H)
NC
B4
IO(F)
TMS
NC
B5
IO(F)
IO(E)
IO(E)
NC
NC
NC
B6
IO(F)
IO(D)
TRSTB
NC
B7
IOCTRL(F)
IO(F)
NC
B8
IO(E)
IO(F)
CLK(8)
IO(E)
IO(E)
NC
IO(D)
R2
IO(H)
NC
B9
IO(F)
NC
R3
NC
B10
B11
B12
B13
B14
B15
B16
B17
B18
B19
B20
B21
B22
B23
B24
B25
B26
C1
IO(F)
G2
INREF(G)
IO(G)
IO(G)
IO(G)
VCCIO(G)
VCCIO(D)
IO(D)
R4
IO(H)
VCC
VCC
GND
GND
GND
GND
GND
GND
VCC
IO(C)
NC
VCC
IO(F)
G3
R5
VCC
IO(F)
G4
IO(D)
IO(D)
NC
R6
VCCIO(C)
NC
CLK(5),PLLIN(3)
IO(E)
G5
R11
R12
R13
R14
R15
R16
R21
R22
R23
R24
R25
R26
T1
VCCPLL(1)
IO(E)
IO(E)
NC
G6
IO(C)
IO(C)
INREF(C)
IO(C)
IO(H)
IO(H)
NC
IO(E)
G21
G22
G23
G24
G25
G26
H1
M2
NC
IO(E)
M3
NC
IO(E)
IO(D)
M4
NC
INREF(E)
IO(E)
IO(G)
IO(G)
NC
NC
M5
IO(G)
VCCIO(G)
GND
GND
GND
GND
GND
GND
VCCIO(D)
VCC
NC
E2
NC
M6
Y2
NC
E3
INREF(D)
NC
M11
M12
M13
M14
M15
M16
M21
M22
M23
M24
M25
M26
N1
Y3
IO(E)
E4
VCCPLL(0)
IO(F)
IO(F)
IO(F)
VCC
Y4
IO(H)
IO(H)
VCCIO(H)
VCCIO(C)
NC
IO(E)
E5
H2
IO(G)
IOCTRL(G)
IO(G)
IO(G)
VCC
NC
Y5
IO(E)
E6
H3
NC
Y6
IO(E)
E7
H4
IO(C)
NC
Y21
Y22
Y23
Y24
Y25
Y26
AA1
AA2
AA3
AA4
AA5
AA6
IO(E)
E8
H5
PLLOUT(0)
IO(F)
E9
NC
H6
T2
IO(H)
IO(H)
IO(H)
NC
IO(C)
IO(C)
NC
E10
E11
E12
E13
E14
E15
E16
E17
E18
IO(F)
IO(F)
VCC
H21
H22
H23
H24
H25
H26
J1
VCC
T3
C2
NC
VCC
T4
C3
IO(F)
IO(D)
NC
T5
IOCTRL(C)
IO(H)
IO(H)
NC
C4
PLLOUT(3)
IO(F)
IO(F)
IO(F)
IO(E)
VCC
IOCTRL(D)
IOCTRL(D)
IO(D)
IO(D)
NC
T6
VCC
GND
GND
GND
GND
GND
C5
T11
T12
T13
T14
T15
C6
IO(F)
TCK
C7
IO(F)
NC
N2
NC
IO(A)
IO(A
C8
INREF(F)
IO(F)
CLK(6)
IO(E)
J2
IO(G)
IO(G)
N3
IO(G)
IO(G)
C9
J3
N4
GND
•
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22
www.quicklogic.com
© 2001 QuickLogic Corporation
QL7100 QuickDSP Data Sheet
Table 19: 516 PBGA Pinout Table (Continued)
516 PBGA
AA7
Function
VCCIO(A)
VCC
516 PBGA
AB6
Function
NC
516 PBGA Function 516 PBGA Function 516 PBGA Function 516 PBGA
Function
IO(A)
AC5
AC6
IO(A)
IO(A)
IO(A)
IO(A)
IO(A)
NC
AD4
AD5
NC
IO(A)
IO(A)
IO(A)
IOCTRL(A)
NC
AE3
AE4
AE5
AE6
AE7
AE8
AE9
AE10
AE11
IO(A)
IO(A)
IO(A)
IO(A)
INREF(A)
NC
AF2
AF3
AF4
AF5
AF6
AF7
AF8
AF9
AF10
AA8
AB7
NC
NC
AA9
VCCIO(A)
GND
AB8
IO(A)
AC7
AD6
IO(A)
AA10
AA11
AA12
AA13
AA14
AA15
AB9
IO(A)
AC8
AD7
IO(A)
VCC
AB10
AB11
AB12
AB13
AB14
IO(A)
AC9
AD8
IOCTRL(A)
IO(A)
VCCIO(A)
GND
VCC
AC10
AC11
AC12
AC13
AD9
IO(A)
IO(A)
IO(A)
NC
AD10
AD11
AD12
IO(A)
IO(A)
TDI
IO(A)
IO(A)
IO(A)
IO(A)
VCCIO(B)
VCC
IO(A)
NC
CLK(3),PLLIN(1)
IO(A)
CLK(4),
DEDCLK,
PLLIN(0)
AA16
VCC
AB15
VCC
AC14
CLK(1)
AD13
AE12
CLK(0)
AF11
IO(A)
AA17
AA18
AA19
AA20
AA21
AA22
AA23
AA24
AA25
AA26
AB1
GND
VCCIO(B)
VCC
AB16
AB17
AB18
AB19
AB20
AB21
AB22
AB23
AB24
AB25
AB26
AC1
IO(B)
NC
AC15
AC16
AC17
AC18
AC19
AC20
AC21
AC22
AC23
AC24
AC25
AC26
AD1
NC
NC
AD14
AD15
AD16
AD17
AD18
AD19
AD20
AD21
AD22
AD23
AD24
AD25
AD26
AE1
IO(A)
NC
AE13
AE14
AE15
AE16
AE17
AE18
AE19
AE20
AE21
AE22
AE23
AE24
AE25
AE26
AF1
IO(B)
IO(B)
NC
AF12
AF13
AF14
AF15
AF16
AF17
AF18
AF19
AF20
AF21
AF22
AF23
AF24
AF25
AF26
CLK(2),PLLIN(2)
NC
IO(B)
VCC
IO(B)
IO(B)
NC
IO(B)
VCCIO(B)
GND
IO(B)
IO(B)
IO(B)
IO(B)
IO(B)
IO(B)
IO(B)
IO(B)
IO(B)
IO(B)
PLLRST(2)
IO(B)
IO(A)
IO(B)
NC
IO(B)
INREF(B)
IO(B)
IO(B)
IO(B)
IO(B)
IO(B)
GND
IO(B)
IO(B)
GND
GND
IO(B)
VCCPLL(2)
IO(C)
IO(B)
GNDPLL(2)
IO(B)
IO(C)
IO(C)
IO(C)
NC
IO(B)
IO(B)
IO(B)
IO(B)
IO(C)
TDO
IOCTRL(B)
IOCTRL(B)
NC
IO(C)
PLLOUT(1)
IO(B)
NC
IO(H)
NC
IO(B)
AB2
NC
IO(C)
IO(B)
AB3
IO(A)
AC2
IO(A)
IO(A)
IO(A)
IO(A)
IO(B)
AB4
GNDPLL(3)
VCCPLL(3)
AC3
AD2
PLLOUT(2)
PLLRST(3)
IO(B)
AB5
AC4
AD3
AE2
IO(B)
•
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•
•
•
QL7100 QuickDSPTM Data Sheet Rev A
23
QL7100 QuickDSP Data Sheet
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24
www.quicklogic.com
© 2001 QuickLogic Corporation
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