RDC-19222 [ETC]
Resolver and Synchro To Digital Converters ; 解析器和同步数字转换器\n
| 型号： | RDC-19222 |
| 厂家： | 
ETC |
| 描述： | Resolver and Synchro To Digital Converters
|
| 文件： | 总24页 (文件大小：255K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
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®
RDC-19220 SERIES
16-BIT MONOLITHIC TRACKING RESOLVER
(LVDT)-TO-DIGITAL CONVERTERS
FEATURES
• +5 Volt Only Option
• Only Five External Passive
Components
• Programmable:
- Resolution: 10-, 12-, 14-, or 16-Bit
- Bandwidth: to 1200 Hz
- Tracking: to 2300 RPS
• Differential Resolver and LVDT
Input Modes
• Velocity Output Eliminates
Tachometer
• Built-In-Test (BIT) Output,
No 180° Hangup
• Small Size: 40-Pin DDIP or
44-Pin J-Lead Package
DESCRIPTION
The RDC-19220 Series of converters are low-cost, versatile, 16-bit
monolithic, state-of-the-art Resolver(/LVDT)-to-Digital Converters.
These single-chip converters are available in small 40-pin DDIP, or 44-
pin J-Lead packages and offer programmable features such as reso-
lution, bandwidth and velocity output scaling.
• -55° to +125°C Operating
Temperature Available
Resolution programming allows selection of 10-, 12-, 14-, or 16-bit,
with accuracies to 2.3 min. This feature combines the high tracking
rate of a 10-bit converter with the precision and low-speed velocity
resolution of a 16-bit converter in one package.
The velocity output (VEL) from the RDC-19220 Series, which can be
used to replace a tachometer, is a 4 V signal (3.5 V with the +5 V only
option) referenced to ground with a linearity of 0.75% of output volt-
age. The full scale value of VEL is set by the user with a single resis-
tor.
RDC-19220 Series converters are available with operating tempera-
ture ranges of 0° to +70°C, -40° to +85°C and -55° to +125°C. Military
processing is available (consult factory).
APPLICATIONS
With its low cost, small size, high accuracy and versatile performance,
the RDC-19220 Series converter is ideal for use in modern high-per-
formance industrial and military control systems. Typical applications
include motor control, radar antenna positioning, machine tool con-
trol, robotics, and process control.
FOR MORE INFORMATION CONTACT:
Technical Support:
1-800-DDC-5757 ext. 7382
Data Device Corporation
105 Wilbur Place
Bohemia, New York 11716
631-567-5600 Fax: 631-567-7358
www.ddc-web.com
©
1999 Data Device Corporation
+REF -REF
BIT
-VSUM
VEL
SIN
-S
C
R
BW
-
C
10
BW
+
+S
COS
-C
B
R1
CONTROL
TRANSFORMER
GAIN
A
DEMODULATOR
-
INTEGRATOR
+
+C
R
V
HYSTERESIS
B
+5C
+CAP
-CAP
-5C
-VCO
16 BIT
UP/DOWN
COUNTER
VCO
&
TIMING
-5 V
INVERTER
R
R
S
C
E
A GND
+5 V
DATA
LATCH
GND
-5 V
INH
BIT 1
THRU
BIT 16
A
B
CB
EM
EL
FIGURE 1. RDC-19220 SERIES BLOCK DIAGRAM
TABLE 1. RDC-19220 SPECIFICATIONS
These specifications apply over the rated power supply, temperature
and reference frequency ranges, and 10% signal amplitude variation
and harmonic distortion.
TABLE 1. RDC-19220 SPECIFICATIONS (CONTD)
PARAMETER
DYNAMIC
UNIT
VALUE
(at maximum bandwidth)
CHARACTERISTICS
Resolution
Tracking Rate (max)(note 4)
Bandwidth(Closed Loop)
(max) (note 4)
Ka
PARAMETER
RESOLUTION
UNIT
VALUE
bits
rps
Hz
10
1152
1200 1200
12
288
14
72
600
16
18
300
Bits 10, 12, 14, or 16
Min 4 or 2 + 1 LSB (note 3)
LSB 1 max
ACCURACY
REPEATABILITY
2
1/sec
1/sec
5.7M 5.7M
19.5 19.5
1.4M 360k
4.9 1.2
295k 295k
A1
DIFFERENTIAL LINEARITY LSB 1 max in the 16th bit
A2
A
B
1/sec 295k 295k
1/sec 2400 2400
REFERENCE
Type
Voltage:
(+REF, -REF)
Differential
1200
600
30k
20
600
300
2k
1/sec 1200 1200
2
Acceleration (1 LSB lag)
Settling Time(179° step)
deg/s
msec
2M 500k
differential
single ended
overload
Frequency
Input Impedance
VP-P ±10 max
2
8
50
VP
V
Hz
±5 max
±25 continuous, 100 transient
DC to 40,000 (note 4)
VELOCITY
CHARACTERISTICS
Polarity
Voltage Range(Full Scale)
Scale Factor Error
Scale Factor TC
Reversal Error
Linearity
Positive for increasing angle
±4 (at nominal ps)
Ohm 10M min // 20 pf
(+S, -S, SIN, +C, -C, COS)
Resolver, differential, groundbased
Vrms 2 ±15%
±25 continuous
Ohm 10M min//10 pf.
V
SIGNAL INPUT
Type
Voltage: operating
overload
%
10 typ
20 max
PPM/C 100 typ
200 max
%
%
0.75 typ 1.3 max
0.25 typ 0.50 max
V
Input impedance
Zero Offset
Zero Offset TC
Load
mv
5 typ
10 max
DIGITAL INPUT/OUTPUT
Logic Type
Inputs
µV/C 15 typ
kΩ
(Vp/V)% 1 typ
30max
8 max
.125 min 2 max
TTL/CMOS compatible
Logic 0 = 0.8 V max.
Logic 1 = 2.0 V min.
Loading =10 µA max P.U. current
source to +5 V //5 pF max.
CMOS transient protected
Logic 0 inhibits; Data stable
within 0.3 µs
Noise
POWER SUPPLIES
Nominal Voltage
Voltage Range
Max Volt. w/o Damage
Current
(note 5)
V
%
V
+5
± 5 +5, -20 (-4 V to -5.25 V)
+7 -7
-5
Inhibit (INH)
mA 14 typ, 22 max (each)
Enable Bits 1 to 8 (EM)
Enable Bits 9 to 16 (EL)
Logic 0 enables; Data stable
within 150 ns
TEMPERATURE RANGE
Operating
Logic 1 = High Impedance
Data High Z within 100 nS
-30X
-20X
-10X
°C
°C
°C
0 to +70
-40 to +85
-55 to +125
Resolution and Mode
Control (A & B)
(see notes 1 and 2.)
Mode
resolver
B
0
0
1
1
A
0
1
0
1
0
-5 V
-5 V
Resolution
10 bits
12 bits
14 bits
16 bits
8 bits
Storage
plastic package
ceramic package
°C
°C
-65 to +150
-65 to +150
"
"
"
THERMAL RESISTANCE
Junction-to-Case (θjc)
40-pin DDIP (plastic)
40-pin DDIP (ceramic)
44-pin J-Lead (plastic)
44-pin J-Lead (ceramic)
LVDT -5 V
°C/W 92.4
°C/W 4.6
°C/W 72.6
°C/W 2.4
"
"
"
0
1
10 bits
12 bits
14 bits
-5 V -5 V
Outputs
Parallel Data (1-16)
PHYSICAL
10, 12, 14, or 16 parallel lines;
natural binary angle positive
logic (see TABLE 2)
0.25 to 0.75 µs positive pulse
leading edge initiates counter
update.
CHARACTERISTICS
Size: 40-pin DDIP
44-pin J-Lead
in(mm) 2.0 x 0.6 x 0.2 (50.8 x 15.24 x 5.08)
in(mm) 0.690 square (17.526)
Converter Busy (CB)
Weight:
40-pin DDIP
44-pin J-Lead
Plastic
oz(g) 0.21 (5.95)
oz(g) 0.08 (2.27)
Ceramic
0.24 (6.80)
0.065 (1.84)
Zero Index
Logic 1 at all 0s (ENL to -5 V);
LSBs are enabled
(Zl)
Built-in-Test (BIT)
Logic 0 for BIT condition.
±100 LSBs of error typ. with a
filter of 500 µS, or total Loss-of-
Signal (LOS)
50 pF +
Logic 0; 1 TTL load, 1.6 mA at
0.4 V max
Notes: 1. Unused data bits are set to logic “0.”
2. In LVDT mode, bit 16 is LSB for 14-bit resolution
or bit 12 is LSB for 10-bit resolution.
3. Accuracy in LVDT mode is 0.15% + 1 LSB of full scale.
4. See text, General Setup Considerations and Higher
Tracking Rates.
Drive Capability
5. See text: General Setup Considerations for RDC19222.
Logic 1; 10 TTL loads, -0.4 mA
at 2.8 V min
Logic 0; 100 mV max driving CMOS
Logic 1; +5 V supply minus 100mV
min driving CMOS, High Z;
10 uA//5 pF max
Data Device Corporation
www.ddc-web.com
RDC-19220 SERIES
L-11/02-300
3
THEORY OF OPERATION
er with the velocity integrator forms a type II servo feedback loop.
A lead in the frequency response is introduced to stabilize the
loop and another lag at higher frequency is introduced to reduce
the gain and ripple at the carrier frequency and above. The set-
tings of the various error processor gains and break frequencies
are done with external resistors and capacitors so that the con-
verter loop dynamics can be easily controlled by the user.
The RDC-19220 Series of converters are single CMOS custom
monolithic chips. They are implemented using the latest IC tech-
nology which merges precision analog circuitry with digital logic
to form a complete, high-performance tracking resolver-to-digital
converter. For user flexibility and convenience, the converter
bandwidth, dynamics and velocity scaling are externally set with
passive components.
TABLE 2. DIGITAL ANGLE OUTPUTS
FIGURE 1 is the functional block diagram of the RDC-19220
Series. The converter operates with ±5 Vdc power supplies.
Analog signals are referenced to analog ground, which is at
ground potential.The converter is made up of two main sections;
a converter and a digital interface. The converter front-end con-
sists of sine and cosine differential input amplifiers. These inputs
are protected to ±25 V with 2 kΩ resistors and diode clamps to
the ±5 Vdc supplies. These amplifiers feed the high accuracy
Control Transformer (CT). Its other input is the 16-bit digital angle
φ. Its output is an analog error angle, or difference angle,
between the two inputs. The CT performs the ratiometric trigono-
metric computation of SINθCOSφ - COSθSINφ = SIN(θ-φ) using
amplifiers, switches, logic and capacitors in precision ratios.
BIT
DEG/BIT
MIN/BIT
1(MSB)
180
90
45
10800
5400
2700
1350
675
337.5
168.75
84.38
42.19
21.09
10.55
5.27
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
22.5
11.25
5.625
2.813
1.405
0.7031
0.3516
0.1758
0.0879
0.0439
0.0220
0.0110
0.0055
2.64
1.32
0.66
0.33
Note: The transfer function of the CT is normally trigonometric,
but in LDVT mode the transfer function is triangular (linear)
and could thereby convert any linear transducer output.
Note: EM enables the MSBs and EL enables the LSBs.
TRANSFER FUNCTION AND BODE PLOT
The converter accuracy is limited by the precision of the com-
puting elements in the CT. In these converters, ratioed capacitors
are used in the CT instead of the more conventional precision
ratioed resistors. Capacitors, used as computing elements with
op-amps, need to be sampled to eliminate voltage drifting.
Therefore, the circuits are sampled at a high rate (67 kHz) to
eliminate this drifting and at the same time to cancel out the op-
amp offsets.
The dynamic performance of the converter can be determined from
its Transfer Function Block Diagrams and its Bode Plots (open and
closed loop). These are shown in FIGURES 2, 3, and 4.
The open loop transfer function is as follows:
S
A2
S2
+1
(B )
Open Loop Transfer Function =
S
+1
(10B )
The error processing is performed using the industry standard
technique for type II tracking R/D converters.The dc error is inte-
grated yielding a velocity voltage which in turn drives a voltage
controlled oscillator (VCO). This VCO is an incremental integra-
tor (constant voltage input to position rate output) which togeth-
where A is the gain coefficient and A2= A1A2
and B is the frequency of lead compensation.
C
R
BW
B
VEL
C
/10
R
BW
V
R
S
-VSUM
VEL
-VCO
50 pf
C
VCO
CT
R
1
16 BIT
UP/DOWN
COUNTER
RESOLVER
INPUT
(θ)
+
VCO
GAIN
DEMOD
1
±1.25 V
THRESHOLD
-
C
F
S
S
11 mV/LSB
DIGITAL
OUTPUT
(φ)
H = 1
FIGURE 2. TRANSFER FUNCTION BLOCK DIAGRAM #1
Data Device Corporation
www.ddc-web.com
RDC-19220 SERIES
L-11/02-300
4
The components of gain coefficient are error gradient, integrator
gain and VCO gain. These can be broken down as follows:
4) The BIT output which is active low is activated by an error
of approximately 100 LSBs. During normal operation for step
inputs or on power up, a large error can exist.
- Error Gradient = 0.011 volts per LSB (CT + Error Amp + Demod
with 2 Vrms input)
5) This device has several high impedance amplifier inputs
(+C, -C, +S, -S, -VCO and -VSUM). These nodes are sensi-
tive to noise and coupling components should be connected
as close as possible.
Cs Fs
1.1 CBW
- Integrator Gain =
volts per second per volt
1
- VCO Gain =
LSBs per second per volt
1.25 RV CVCO
6) Setup of bandwidth and velocity scaling for the optimized
critically damped case should proceed as follows:
where: Cs = 10 pF
Fs = 67 kHz when Rs = 30 kΩ
Fs = 100 kHz when Rs = 20 kΩ
Fs = 134 kHz when Rs = 15 kΩ
CVCO = 50 pF
- Select the desired f BW (closed loop) based on overall
system dynamics.
RV, RB, and CBW are selected by the user to set velocity scaling
and bandwidth.
- Select f
≥ 3.5f BW
carrier
For the converter’s max tracking rate value,
see the row indicated in TABLE 4.
Application max. rate
{
}
GENERAL SETUP CONSIDERATIONS
- Compute Rv = 55 kΩ x
DDC has external component selection software which consid-
ers all the criteria below, and in a simple fashion, asks the key
parameters (carrier frequency, resolution, bandwidth, and track-
ing rate) to derive the external component value.
3.2 x Fs (Hz) x 108
Rv x (f BW)2
- Compute CBW (pF) =
- Where Fs = 67 kHz for R CLK = 30 KΩ
100 kHz for R CLK = 20 KΩ
The following recommendations should be considered when
installing the RDC-19220 Series R/D converters:
134 kHz for R CLK = 15 KΩ
1) In setting the bandwidth (BW) and Tracking Rate (TR)
(selecting five external components), the system require-
ments need to be considered. For greatest noise immunity,
select the minimum BW and TR the system will allow.
0.9
CBW x f BW
- Compute RB =
CBW
- Compute
10
2) Power supplies are ±5 V dc. For lowest noise performance
it is recommended that a 0.1 µF or larger cap be connected
from each supply to ground near the converter package.
Note: DDC has software available to perform the previous calcu-
lations. Contact DDC to request software or visit our web-
site at www.ddc-web.com to download software.
3) Resolver inputs and velocity output are referenced to A
GND. This pin should be connected to GND near the con-
verter package. Digital currents flowing through ground will
not disturb the analog signals.
(CRITICALLY DAMPED)
VELOCITY
OUT
GAIN = 4
2A
ERROR PROCESSOR
ω (rad/sec)
10B
OPEN LOOP
VCO
CT
S
B
B
A
A
S
+ 1
1
A
S
DIGITAL
POSITION
OUT (φ)
+
2
RESOLVER
INPUT
(θ)
e
(B = A/2)
S
10B
+ 1
-
GAIN = 0.4
H = 1
2 A
fBW = BW (Hz) =
2 A
π
2A
2
ω (rad/sec)
CLOSED LOOP
FIGURE 3. TRANSFER FUNCTION
BLOCK DIAGRAM #2
FIGURE 4. BODE PLOTS
Data Device Corporation
www.ddc-web.com
RDC-19220 SERIES
L-11/02-300
5
7) Selecting a fBW that is too low relative to the maximum appli-
cation tracking rate can create a spin-around condition in
which the converter never settles. The relationship to insure
against spin-around is as follows (TABLE 3):
For a 12-bit converter there are 212 or 4096 counts per rotation.
1,333,333/4096 = 325 rotations per second or 333,333 counts
per second per volt.
1
Rv =
= 48 kΩ
(333,333 x 50 pF x 1.25)
TABLE 3. TRACKING/BW RELATIONSHIP
RPS (MAX)/BW
RESOLUTION
1
10
12
14
16
The maximum rate capability of the RDC-19220 is set by Rs.
When Rs = 30 kΩ it is nominally 1,333,333 counts/sec, which
equates to 325 rps (rotations per second). This is the absolute
maximum rate; it is recommended to only run at <90% of this rate
0.45
0.25
0.125
(as seen in TABLE 3), therefore the minimum R will be limited
v
8) For RDC-19222:
to 55 kΩ. The converter maximum tracking rate can be increased
50% in the 16- and 14-bit modes and 100% in the 12- and 10-bit
modes by increasing the supply current from 12 to 15 mA (by
using an Rc = 23 kΩ), and by increasing the sampling rate by
changing Rs to 20 kΩ for 16- and 14-bit resolution or to 15 kΩ for
12- and 10-bit resolution (see TABLE 4).
This version is capable of +5V only operation. It accomplishes
this with a charge pump technique that inverts the +5V supply
for use as -5V, hence the +5V supply current doubles. The
built-in -5 V inverter can be used by connecting pin 2 to 26, pin
17 to 22, a 10 µF/10 Vdc capacitor from pin 23 (negative ter-
minal) to pin 25 (positive terminal), and a 47 µF/10 Vdc capac-
itor from -5 V to GND. The current drain from the +5 V supply
doubles. No external -5 V supply is needed.
The maximum carrier frequency can, in the same way, increase
from: 5 to 10 kHz in the 16-bit mode, 7 to 14 kHz in the 14-bit
mode,11 to 32 kHz in the 12-bit mode, and 20 to 40 kHz in the
10-bit mode (see TABLE 5).
When using the -5 V inverter, the max. tracking rate should be
scaled for a velocity output of 3.5 V max. Use the following equa-
tion to determine tracking rate used in the formula on page 4:
The maximum tracking rate and carrier frequency for full perfor-
mance are set by the power supply current control resistor (Rc)
per the following tables:
TR (required) x (4.0) = Tracking rate used in calculation
(3.5)
TABLE 4. MAX TRACKING RATE
(MIN) IN RPS
Depending on the res-
olution, select one of
the values from this
row, for use in convert-
er max tracking rate
formula. (See previous
page for formula.)
R
R
RESOLUTION
10 12 14 16
30k** or open 30k 1152 288 72 18
Note:When using the highest BW and Tracking Rates, using
the -5 V inverter is not recommended.
C
S
(Ω)
(Ω)
HIGHER TRACKING RATES AND CARRIER FREQUENCIES
Tracking rate (nominally 4 V) is limited by two factors: velocity
voltage saturation and maximum internal clock rate (nominally
1,333,333 Hz). An understanding of their interaction is essential
to extending performance.
23k
23k
20k 1728 432 108 27
15k 2304 576
*
*
* Not recommended.
** The use of a high quality thin-film resistor will provide better temperature
stability than leaving open.
TABLE 5. CARRIER FREQUENCY
(MAX) IN KHZ
The General Setup Considerations section makes note of the
selection of Rv for the desired velocity scaling. Rv is the input resis-
tor to an inverting integrator with a 50 pF nominal feedback capac-
itor. When it integrates to -1.25 V, the converter counts up 1 LSB
and when it integrates to +1.25 V, the converter counts down 1
LSB. When a count is taken, a charge is dumped on the capacitor;
such that, the voltage on it changes 1.25 V in a direction to bring
it to 0 V. The output counts per second per volt input is therefore:
R
R
RESOLUTION
C
S
(Ω)
30k** or open
23k
(Ω)
30k
30k
20k
15k
10
20
24
34
40
12
11
12
24
32
14
7
16
5
11
14
*
7
23k
10
*
23k
* Not recommended.
** The use of a high quality thin-film resistor will provide better temperature
stability than leaving open.
1
(R x 50 pF x 1.25)
v
The carrier frequency should be 1/10, or less, of the sampling fre-
quency in order to have many samples per carrier cycle. The con-
verter will work with reduced quadrature rejection at a carrier fre-
quency up to 1/4 the sampling frequency. Carrier frequency should
be at least 3.5 times the BW in order to eliminate the chance of jitter.
As an example:
Calculate Rv for the maximum counting rate, at a VEL voltage
of 4 V.
Data Device Corporation
www.ddc-web.com
RDC-19220 SERIES
L-11/02-300
6
TABLE 6. TRANSFORMERS
ANGLE
ACCURACY***
FIGURE
NUMBER
P/N
TYPE
FREQUENCY (HZ)* IN (VRMS)* OUT (VRMS)**
LENGTH (IN) WIDTH (IN) HEIGHT (IN)
52034
52035
52036
52037
52038
B-426
52039
24133
S - R
S - R
400
400
400
400
400
400
60
11.8
90
2
1
1
0.81
0.81
0.81
0.81
0.81
0.81
1.1
0.61
0.61
0.61
0.61
0.61
0.61
1.14
1.125
0.3
0.3
0.3
0.3
0.3
0.32
.42
.42
5A
5A
5B
5B
5B
5C
5D
5D
2
R - R
11.8
26
2
1
R - R
2
1
R - R
90
2
3.4
1
Reference
Synchro
Reference
115
90
N/A
1
2
60
115
3/6 ****
N/A
1.125
*
±10% Frequency (Hz) and Line-to-Line input voltage (Vrms) tolerances
** 2 Vrms Output Magnitudes are -2 Vrms ±0.5% full scale
*** Angle Accuracy (Max Minutes)
**** 3 Vrms to ground or 6 Vrms differential (±3% full scale)
Dimensions are for each individual main and teaser
60 Hz Synchro transformers are active (requires ±15 Vdc power supplies)
400 Hz transformer temperature range: -55°C to +125°C
60 Hz transformer temperature ranges: -55°C to +125°C, 0 to +70°C
0.61 MAX
(15.49)
0.61 MAX
(15.49)
0.15 MAX
(3.81)
0.09 MAX
(2.29)
0.30 MAX
(7.62)
0.09 MAX
(2.29)
0.15 MAX
(3.81)
1
3
T1A
8
4
7
5
6
11 12
14 15
0.81 MAX
(20.57)
T1B
0.600
(15.24)
10
9
20 19 18 17 16
0.115 MAX
(2.92)
SIDE VIEW
0.100 (2.54) TYP
TOL NON CUM
BOTTOM VIEW
BOTTOM VIEW
TERMINALS
0.025 ±0.001 (6.35 ±0.03) DIAM
0.125 (3.18) MIN LENGTH
SOLDER PLATED BRASS
PIN NUMBERS FOR REF. ONLY
Dimensions are shown in inches (mm).
T1A
1
6
-SIN
S1
S3
5
3
10
+SIN
SYNCHRO
INPUT
RESOLVER
OUTPUT
T1B
11
15
16
20
-COS
S2
+COS
FIGURE 5A. TRANSFORMER LAYOUT AND SCHEMATIC (SYNCHRO INPUT - 52034/52035)
0.61 MAX
(15.49)
0.61 MAX
(15.49)
0.15 MAX
(3.81)
0.09 MAX
(2.29)
0.30 MAX
(7.62)
0.09 MAX
(2.29)
0.15 MAX
(3.81)
1
3
T1A
8
4
5
6
11 12
14 15
0.81 MAX
(20.57)
T1B
0.600
(15.24)
10
9
7
20 19 18 17 16
0.115 MAX
(2.92)
SIDE VIEW
0.100 (2.54) TYP
TOL NON CUM
BOTTOM VIEW
BOTTOM VIEW
TERMINALS
0.025 ±0.001 (6.35 ±0.03) DIAM
0.125 (3.18) MIN LENGTH
SOLDER PLATED BRASS
PIN NUMBERS FOR REF. ONLY
Dimensions are shown in inches (mm).
T1A
1
3
6
-SIN
S1
S3
10
+SIN
RESOLVER
INPUT
RESOLVER
OUTPUT
T1B
11
15
16
20
-COS
S4
S2
+COS
FIGURE 5B. TRANSFORMER LAYOUT AND SCHEMATIC (RESOLVER INPUT - 52036/52037/52038)
Data Device Corporation
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RDC-19220 SERIES
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CASE IS BLACK AND
NON-CONDUCTIVE
0.25
(6.35)
MIN.
1.14 MAX
(28.96)
+
•
•
•
•
+S
S3
S1
+15 V
*
*
(+15 V) (-R)
*
*
0.61 MAX
(15.49)
0.32 MAX
(8.13)
1.14 MAX
(28.96)
0.85 ±0.010
(21.59 ±0.25)
52039
or
24133
0.125 MIN
(3.17)
0.09 MAX
(2.29)
0.15 MAX
(3.81)
(RH)
S2
•
(RL)
(V)
V
•
(+R)
+C
•
(-Vs)
-Vs
•
*
1
2
9
3
T1A
8
5
6
+
(BOTTOM VIEW)
0.42
(10.67)
MAX.
0.600
(15.24)
0.81 MAX
(20.57)
0.13 ±0.03
(3.30 ±0.76)
0.21 ±0.3
10
7
(5.33 ±0.76)
0.175 ±0.010 (4.45 ±0.25)
NONCUMULATIVE
TOLERANCE
0.105 (2.66)
0.040 ±0.002 DIA. PIN.
SOLDER PLATED BRASS
SIDE VIEW
0.100 (2.54) TYP
TOL NON CUM
BOTTOM VIEW
TERMINALS
0.025 ±0.001 (6.35 ±0.03) DIAM
0.125 (3.18) MIN LENGTH
SOLDER-PLATED BRASS
+15 V
+15 V
Input
RH
Input
S1
Output
+R (RH)
Output
+S
Dimensions are shown in inches (mm).
24133
52039
S2
-R (RL)
+C
RL
S3
V
-Vs
(-15 V)
V
-Vs
(-15 V)
(Analog
Gnd)
(Analog
Gnd)
1
6
INPUT
OUTPUT
The mechanical outline is the same for the synchro input trans-
former (52039) and the reference input transformer (24133),
except for the pins. Pins for the reference transformer are shown
in parenthesis ( ) below. An asterisk * indicates that the pin is
omitted.
5
10
FIGURE 5D. 60 HZ SYNCHRO AND REFERENCE
TRANSFORMER DIAGRAMS
(SYNCHRO INPUT - 52039 / REFERENCE INPUT - 24133)
FIGURE 5C. TRANSFORMER LAYOUT AND
SCHEMATIC (REFERENCE INPUT - B-426)
EXTERNAL
REFERENCE
LO
HI
6
CBW
RB
1
5
B-426
10
CBW/10
RV
+R
-VSUM
-S SIN
+S
-R
VEL
-VCO
S1
S3
RH
RL
1
3
10
6
TIA
TIB
DIGITAL
OUTPUT
+C
-C
RDC-19220
16
S4
11
15
20
CB
BIT
COS
S2
16
AGND
52036(11.8V)
OR
INH
EM
EL
52037(26V)
OR
GND
Rc
Rs
52038(90V)
A
B
+5V
-5V
SYNCHRO INPUT
RESOLUTION
CONTROL
S1
+S
+C
1
RH
RL
10
S3
3
TIA
6
5
20
11
TIB
S2
AGND
GND
15
16
52034(11.8V)
OR
52035(90V)
FIGURE 6. TYPICAL TRANSFORMER CONNECTIONS
Data Device Corporation
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RDC-19220 SERIES
L-11/02-300
8
TYPICAL INPUT CONNECTIONS
FIGURES 7 through 9 illustrate typical input configurations
EXTERNAL
REF
LO
HI
R
R
R
1
2
4
R
3
10k Ω (1%)
-R
+R
S3
+S
-S
SIN
Note: The five external BW components as
shown in FIGURE 1 and 2 are necessary
for the R/D to function.
COS
-C
S1
+C
10k Ω (1%)
S2
S4
A GND
RESOLVER
GND
Notes:
1) Resistors selected to limit Vref peak to between 1 V and 4 V.
2) External reference LO is grounded, then R3 and R4 are not
needed, and -R is connected to GND.
FIGURE 7A. TYPICAL CONNECTIONS, 2 V RESOLVER, DIRECT INPUT
R
1
-S
SIN
S3
S1
+S
R
R
2
Note: The five external BW components as
shown in FIGURE 1 and 2 are necessary for
the R/D to function.
R
1
S2
S4
+C
2
A GND
-C
COS
R2
2
=
R1 + R2 X Volt
R1 + R2 should not load the Resolver too much; it is recommended to use a R2 = 10k.
R1 + R2 Ratio Errors will result in Angular Errors,
2 cycle, 0.1% Ratio Error = 0.029° Peak Error.
FIGURE 7B. TYPICAL CONNECTIONS, X- VOLT RESOLVER, DIRECT INPUT
Data Device Corporation
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RDC-19220 SERIES
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9
SIN
R
f
R
R
i
i
-S
-
S1
S3
+S
+
Note: The five external BW components as
shown in FIGURE 1 and 2 are necessary
for the R/D to function.
R
R
f
f
A GND
RESOLVER
INPUT
COS
R
R
i
i
-C
-
S4
S2
+C
+
R
f
Ri
Rf
x 2 Vrms = Resolver L-L rms voltage
CONVERTER
Rf ≥ 6 kΩ
S1 and S3, S2 and S4, and RH and RL should be ideally twisted shielded, with the shield tied to GND at the converter.
FIGURE 8A. DIFFERENTIAL RESOLVER INPUT
SIN
3
R
f
R
i
-S
1
6
-
S1
S3
2
5
R
i
+S
+
Note: The five external BW components as
shown in FIGURE 1 and 2 are necessary
for the R/D to function.
R
f
f
4
RESOLVER
INPUT
A GND
COS
13
R
R
R
i
i
-C
15
16
7
-
S4
S2
+C
+
8 10
R
f
12
CONVERTER
S1 and S3, S2 and S4, and RH and RL should be ideally twisted shielded, with the shield tied to GND at the converter.
For DDC-49530 or DDC-57470: Ri = 70.8 kΩ, 11.8 V input, synchro or resolver.
For DDC-49590: Ri = 270 kΩ, 90 V input, synchro or resolver.
Maximum addition error is 1 minute.
FIGURE 8B. DIFFERENTIAL RESOLVER INPUT, USING DDC-49530 (11.8 V) OR DDC-49590 (90 V)
Data Device Corporation
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RDC-19220 SERIES
L-11/02-300
10
SIN
R
R
f
f
R
R
i
i
-S
-
S1
S3
+S
+
Note: The five external BW components as
shown in FIGURE 1 and 2 are necessary
for the R/D to function.
A GND
COS
R
i
R /
f
3
R
i
-C
-
R /2
i
+C
3
+
S2
R /
f
CONVERTER
Ri
Rf
x 2 Vrms = Synchro L-L rms voltage
Rf ≥ 6 kΩ
S1, S2, and S3 should be triple twisted shielded; RH and RL should be twisted shielded, In both cases the shield should be tied to GND at the
converter.
FIGURE 9A. SYNCHRO INPUT
SIN
3
R
f
R
i
-S
1
6
-
S1
S3
2
5
R
i
+S
+
Note: The five external BW components as
shown in FIGURE 1 and 2 are necessary
for the R/D to function.
R
f
4
A GND
COS
14
R
i
16
7
R / 3
f
R
i
8
-C
-
15
15
R /2
i
+C
10
9
+
S2
R / 3
f
11
CONVERTER
S1, S2, and S3 should be triple twisted shielded; RH and RL should be twisted shielded, In both cases the shield should be tied to GND at the converter.
90 V input = DDC-49590: Ri = 270 kΩ, 90 V input, synchro or resolver.
11.8 V input = DDC-49530 or DDC-57470: Ri = 70.8 kΩ, 11.8 V input, synchro or resolver.
Maximum addition error is 1 minute.
FIGURE 9B. SYNCHRO INPUT, USING DDC-49530/DDC-57470 (11.8 V) OR DDC-49590 (90 V)
Data Device Corporation
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RDC-19220 SERIES
L-11/02-300
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REDUCED POWER SUPPLY CURRENTS
When Rs = 30 kΩ (tracking rate is not being pushed), nominal power
supply current can be cut from 14 to 9 mA by setting Rc = 53 kΩ.
INCREASED TRACKING/DECREASED SETTLING
(GEAR SHIFTING)
Connecting the BIT output to the resolution control lines (A and
B) will change the resolution of the converter down (“gear shift”)
and make the converter settle faster and track at higher rates.
The converter bandwidth is independent of the resolution.
TRANSFORMER ISOLATION
System requirements often include electrical isolation. There are
transformers available for reference and synchro/resolver signal
isolation. TABLE 6 includes a listing of the most common trans-
formers.The synchro/resolver transformers reduce the voltage to
2 Vrms for a direct connection to the converter. See FIGURES
5A, 5B, 5C and 5D for transformer layouts and schematics, and
FIGURE 6 for typical connections.
ADDITIONAL ERROR SOURCES
Quadrature voltages in a resolver or synchro are by definition the
resulting 90° fundamental signal in the nulled out error voltage (e)
in the converter. This voltage is due to capacitive or inductive cou-
pling in the synchro or resolver signals. A digital position error will
result due to the interaction of this quadrature voltage and a refer-
ence phase shift between the converter signal and reference
inputs. The magnitude of this error is given in the following formula:
DC INPUTS
As noted in TABLE 1 the RDC-19220 will accept dc inputs. It is
necessary to set the REF input to dc by tying +REF to +5 V and
-REF to GND or -5 \/. (With dc inputs, the converter will function
from 0 to 180° and BIT will remain at logic 0.)
Magnitude of Error = (Quadrature Voltage/F.S.signal) • tan α
Where:
VELOCITY TRIMMING
RDC-19220 Series specifications for velocity scaling, reversal
error and offset are contained in TABLE 1. Velocity scaling and
offset are externally trimmable for applications requiring tighter
specifications than those available from the standard unit. FIG-
URE 10 shows the setup for trimming these parameters with
external pots. It should also be noted that when the resolution is
changed, VEL scaling is also changed. Since the VEL output is
from an integrator with capacitor feedback, the VEL voltage can-
not change instantaneously. Therefore, when changing resolu-
tion while moving there will be a transient with a magnitude pro-
portional to the velocity and a duration determined by the con-
verter bandwidth.
Magnitude of Error is in radians
Quadrature Voltage is in volts
LAG
R
+ REF
- REF
+ REF
- REF
C
LEAD
R
C
RDC-19220
+ REF
- REF
+ REF
- REF
+5 V
100 R
V
8
100 kΩ
(OFFSET)
Xc
R
tan ϕ =
-5 V
0.8 R
-VCO
VEL
V
Where ϕ = desired phase-shift
0.4 R (SCALING)
1
Xc =
V
10
2πfc
Where f = carrier frequency
Where c = capacitance
FIGURE 10. VELOCITY TRIMMING
FIGURE 11. PHASE-SHIFT COMPENSATION
Data Device Corporation
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RDC-19220 SERIES
L-11/02-300
12
Full Scale signal is in volts
LVDT MODE
α = signal to REF phase shift
As shown in TABLE 1 the RDC-19220 Series units can be made
to operate as LVDT-to-digital converters by connecting
Resolution Control inputs A and B to “0,” “1,” or the -5 volt supply.
In this mode the RDC-19220 Series functions as a ratiometric
tracking linear converter. When linear ac inputs are applied from
a LVDT the converter operates over one quarter of its range.This
results in two less bits of resolution for LVDT mode than are pro-
vided in resolver mode.
An example of the magnitude of error is as follows:
Let: Quadrature Voltage = 11.8 mV
Let: F.S. signal = 11.8 V
Let: α = 6°
Then: Magnitude of Error = 0.36 min @ 1 LSB in the 16th bit.
FIGURE 12B shows a direct LVDT 2 Vrms full scale input. Some
LDVT output signals will need to be scaled to be compatible with
the converter input. FIGURE 12C is a schematic of an input scal-
ing circuit applicable to 3-wire LVDTs. The value of the scaling
Note: Quadrature is composed of static quadrature which is
specified by the synchro or resolver supplier plus the speed
voltage which is determined by the following formula:
Speed Voltage = (rotational speed/carrier frequency) • F.S. signal
Where:
TABLE 7. LVDT OUTPUT CODE (14-BIT R/D OR
12-BIT LVDT)
LVDT OUTPUT
MSB
LSB
+ over full travel
+ full travel -1 LSB
+0.5 travel
+1 LSB
null
- 1 LSB
-0.5 travel
- full travel
- over full travel
01
00
00
00
00
00
00
00
11
xxxx
1111
1100
1000
1000
0111
0100
0000
xxxx
xxxx
1111
0000
0000
0000
1111
0000
0000
xxxx
xxxx
1111
0000
0001
0000
1111
0000
0000
xxxx
Speed Voltage is the quadrature due to rotation.
Rotation speed is the rps (rotations per second) of the synchro
or resolver.
Carrier frequency is the REF in Hz.
A circuit to LEAD or LAG the reference into the converter that will
compensate for phase-shift between the signal and the refer-
ence to reduce the effects of the quadrature is illustrated in FIG-
URE 11.
Note: TABLE 7 refers to FIGURE 12C.
C1
SIN
aR
-S
2 WIRE LVDT
R
-
R
+S
REF IN
R
+
FS = 2 V
aR
C2
COS
bR
R
R
2R
-C
R
R
-
2R
+C
+
2 V
R
bR
+REF
-REF
C
= C , set for phase lag = phase lead through the LVDT.
2
1
FIGURE 12A. 2-WIRE LVDT DIRECT INPUT
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RDC-19220 SERIES
L-11/02-300
13
-S
SIN
+S
A GND
-REF
+REF
+C
RDC-19220
-C
COS
FIGURE 12B. 3-WIRE LVDT DIRECT INPUT
aR
SIN
-S
R
V
B
-
R'
R'
+S
R
+
R'
aR
bR
R
2R'
COS
-C
R
-
V
A
R'
R/2
2R'
+
+C
+REF
-REF
bR
Notes:
1. R' ≥ 10 kΩ
2. Consideration for the value of R is LVDT loading.
1
1
=
b =
a =
VAnull
VBnull
RDC-19220
INPUT
LVDT
OUTPUT
2
(VA - VB )max.
2V
SIN
V
A
1V
a
SIN = 1 + (VA - VB )
2
V
B
COS
+FS
+FS
NULL
-FS
-FS
NULL
a
COS = 1 - (VA - VB )
2
FIGURE 12C. 3-WIRE LVDT SCALING CIRCUIT
Data Device Corporation
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RDC-19220 SERIES
L-11/02-300
14
constant “a” is selected to provide an input of 2 Vrms at full stroke
of the LVDT. The value of scaling constant “b” is selected to pro-
vide an input of 1 Vrms at null of the LVDT. Suggested compo-
nents for implementing the input scaling circuit are a quad op-
amp, such as a 4741 type, and precision film resistors of 0.1%
tolerance. FIGURE 12A illustrates a 2-wire LVDT configuration.
Output angle data is enabled onto the tri-state data bus in two
bytes. Enable MSBs (EM) is used for the most significant 8 bits
and Enable LSBs (EL) is used for the least significant 8 bits. As
shown in FIGURE 14, output data is valid 150 ns maximum after
the application of a negative enable pulse. The tri-state data bus
returns to the high impedance state 100 ns maximum after the
rising edge of the enable signal.
Data output of the RDC-19220 Series is Binary Coded in LVDT
mode. The most negative stroke of the LVDT is represented by
all zeros and the most positive stroke of the LVDT is represent-
ed by all ones.The most significant 2 bits (2 MSBs) may be used
as overrange indicators. Positive overrange is indicated by code
“01” and negative overrange is indicated by code “11” (see
TABLE 7).
The Converter Busy (CB) signal indicates that the tracking con-
verter output angle is changing 1 LSB. As shown in FIGURE 15,
output data is valid 50 ns maximum after the middle of the CB
pulse. CB pulse width is 1/40 Fs, which is nominally 375 ns.
BUILT-IN-TEST (BIT)
The Built-ln-Test output (BIT) monitors the level of error from the
demodulator. This signal is the difference in the input and output
angles and ideally should be zero. However, if it exceeds approx-
imately 100 LSBs (of the selected resolution) the logic level at
BIT will change from a logic 1 to a logic 0.
INHIBIT, ENABLE, AND CB TIMING
The Inhibit (INH) signal is used to freeze the digital output angle
in the transparent output data latch while data is being trans-
ferred. Application of an Inhibit signal does not interfere with the
continuous tracking of the converter. As shown in FIGURE 13,
angular output data is valid 300 ns maximum after the applica-
tion of the negative inhibit pulse.
This condition will occur during a large step and reset after the
converter settles out. BIT will also change to logic 0 for an over-
velocity condition, because the converter loop cannot maintain
input/output or if the converter malfunctions where it cannot
maintain the loop at a null. BIT will also be set low for a detected
total Loss-of-Signal (LOS). The BIT signal may pulse during cer-
tain error conditions (i.e., converter spin around or signal ampli-
tude on threshold of LOS).
INHIBIT
300 ns max
LOS will be detected if both sin and cos input voltages are less
than 800 mV peak.
DATA
DATA
VALID
FIGURE 13. INHIBIT TIMING
1/40 F
S
(375 nsec nominal)
ENABLE
CB
150 ns MAX
50 ns
100 ns MAX
DATA
VALID
DATA
VALID
DATA
VALID
DATA
HIGH Z
HIGH Z
DATA
FIGURE 14. ENABLE TIMING
FIGURE 15. CONVERTER BUSY TIMING
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RDC-19220 SERIES
L-11/02-300
15
ENCODER EMULATION
signals as illustrated in FIGURE 16A. Also, the LSB byte is
always enabled.
The RDC-19220 can be made to emulate incremental optical
encoder output signals, where such an interface is desired. This
is accomplished by tying EL to -5 V, whereby CB becomes Zero
Index (Zl) Logic 1 at all 0s, the LSB+1 becomes A, and the exclu-
sive-or of the LSB and LSB+1 becomes B emulating A QUAD B
FIGURE 16B illustrates a more detailed circuit with delays and
filtering to eliminate potential glitch due to data skew and rise/fall
differences caused by logic loading.
CB (ZI)
LSB +1
(ZI)
A
B
LSB
EL
-5 V
FIGURE 16A. INCREMENTAL ENCODER EMULATION
U2D
74AC86
R2
2k
13
11
C2
A
B
RDC-19220
220 pF
12
U2A
74AC86
R1
2k
U2B
2
1
LSB +1
74AC86
3
4
5
6
8
C1
220 pF
LSB
U2C
74AC86
R3
2k
9
CB/NRP
C3
120 pF
NRP
10
EL
D1
1N4148
-5 V
NOTE: CMOS LOGIC IS RECOMMENDED. TTL AND TTL
COMPATABLE LOGIC WILL SKEW THE DELAYS.
FIGURE 16B. FILTERED/BUFFERED ENCODER EMULATOR CIRCUIT
Data Device Corporation
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RDC-19220 SERIES
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16
TYPICAL-5 VOLT CIRCUITS
PINOUT FUNCTION TABLES BY MODEL NUMBER
The TABLES 8 and 9 detail pinout functions by the DDC model
number.
Since the 40-pin DDIP RDC-19220 does not have a pinout for
the -5 V inverter, it may be necessary to create a -5 V from other
supplies on the board. FIGURE 17 illustrates several possibili-
ties.
The RDC-19220 has differential inputs but requires both ±5 V
power supplies.
The RDC-19222 has differential inputs and can be used with the
+5 V only option.
-15
79LO5
-5
3 TERMINAL
NEGATIVE REGULATOR
TABLE 9. RDC-19222 PINOUTS (44-PIN, +5 V ONLY)
#
1
NAME
#
NAME
Bit 16 (LSB)
EL
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
-5
-5
-15
-12
2
+5 V
A
Bit 8
10.2 V
3
Bit 15
Bit 7
ZENER
4
B
5.1 V
ZENER
5
INH
+REF
-REF
-VCO
-VSUM
VEL
+C
Bit 14
Bit 6
6
-5
-15
7
Bit 13
Bit 5
6.8 V
ZENER
8
9
Bit 12
Bit 4
FIGURE 17. TYPICAL -5 VOLT CIRCUITS
10
11
12
13
14
15
16
17
18
19
20
21
22
NOTES:
Bit 11
Bit 3
COS
-C
TABLE 8. RDC-19220 PINOUTS (40-PIN)
Bit 10
Bit 2
#
1
NAME
DESCRIPTION
#
NAME
DESCRIPTION
+S
A
Resolution Control 40 +5 V
Power Supply
SIN
-S
Bit 9
Bit 1 (MSB)
Enable LSBs (see
note)
2
B
Resolution Control 39 EL
-5 V
RS
CB
3
4
5
6
7
8
9
INH
Inhibit
38 Bit 16
37 Bit 8
36 Bit 15
35 Bit 7
34 Bit 14
33 Bit 6
32 Bit 13
31 Bit 5
30 Bit 12
29 Bit 4
28 Bit 11
27 Bit 3
26 Bit 10
25 Bit 2
24 Bit 9
23 Bit 1
22 CB
LSB
BIT
+REF
-REF
-VCO
+Reference Input
-Reference Input
Neg VCO Input
RC
+5C (+5 V)
+CAP
GND
EM
A GND
-VSUM Vel Sum Point
-5C (-5 V)
-CAP
VEL
+C
Velocity Output
Signal Input
Signal Output
Signal Input
Signal Input
Signal Output
Signal Input
Power Supply
Sampling Set
Current Set
1. When -5 V is applied to pin 1 (EL), Converter Busy (CB) becomes
Zero index (ZI).
10 COS
11 -C
2. When using the built-in -5 V inverter: connect pin 2 to 26, pin 17 to
22, and a 10 µF/10 Vdc capacitor from pin 23 (negative terminal) to
pin 25 (positive terminal). Connect a 47 µF/10 Vdc capacitor from -5
V to GND. The current drain from the +5 V supply doubles. No exter-
nal -5 V supply is needed.
12 +S
13 +SIN
14 -S
15 -5 V
R
R
16
17
S
C
18 EM
Enable MSBs
MSB
19 A GND Analog Ground
20 GND Ground
Converter Busy
Built-In-Test
21 BIT
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RDC-19220 SERIES
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17
2.035 - 2.065 (40 PIN)
(51.65 - 52.45)
DIMENSIONS SHOWN ARE IN INCHES (MM).
0.590 ±0.010
(14.99 ±0.25)
0.150 - 0.160
(3.81 - 4.06)
0.008 - 0.015
(0.20 - 0.38)
0.010 - 0.020
(0.25 - 0.51)
0.012 - 0.025
(0.31 - 0.64)
0.120 - 0.160
(3.05 - 4.06)
0.580 - 0.695
(14.73 - 17.65)
0.090 - 0.110
(2.29 - 2.79
0.030 - 0.070
(0.76 - 1.78)
FIGURE 18. RDC-19220 (40-PIN DDIP) PLASTIC
PACKAGE MECHANICAL OUTLINE
PIN NUMBERS
FOR REF ONLY
0.125 ±0.020
(3.18 ±0.508)
0.085 ±0.010
0.590 ±0.010
(14.99 ±0.25)
0.050 ±0.010
(1.27 ±0.25)
(2.16 ±0.25)
1
40
0.100 ±0.010 TYP
(2.54 ±0.25)
0.018 ±0.006 TYP
(0.46 ±0.15)
2.000 ±0.020
(50.8 ±0.51)
0.050 ±0.020 TYP
(1.27 ±0.51)
20
21
0.012 ±0.004 TYP
(0.31 ±0.10)
DIMENSIONS SHOWN ARE IN INCHES (MM).
+0.050
0.095 ±0.010
(2.41 ±0.25)
0.600
- 0.020
+1.27
- 0.51
(15.25
)
FIGURE 19. RDC-19220 (40-PIN DDIP) CERAMIC PACKAGE MECHANICAL OUTLINE
Data Device Corporation
www.ddc-web.com
RDC-19220 SERIES
L-11/02-300
18
PIN 1 IDENTIFIER
PIN #'S SHOWN
FOR REFERENCE ONLY
ALTERNATE PIN 1 IDENTIFIER
6
40
.155 MAX
(3.94)
.020 MIN
0.690 SQ. ±.005
(17.53)
.620 SQ
± .010
(15.75)
0.650 SQ. NOM
(16.51)
.016 ± .005 (.41)
DIMENSIONS SHOWN ARE IN INCHES (MM) TOLERANCE IN INCHES
0.010 x 45˚ CHFR (3)
(0.25)
.050 ± .002
(1.27)
FIGURE 20. RDC-19222 (44-PIN PLASTIC J-LEAD) MECHANICAL OUTLINE
0.075 ±0.010
(1.91 ±0.25)
0.040 x 45˚
CHAMFER
0.500 ±0.010
(12.70 ±0.25)
(1.02)
(3 PLACES)
0.020 x 45˚
(0.51)
CHAMFER
(ORIENTATION
MARK)
0.113 (REF)
(2.87)
0.050 TYP
(1.27)
0.065 ±0.007
(1.65 ±0.18)
6
1
40
7
39
0.630 ±0.020 TYP
(16.00 ±0.51)
0.500 ±0.010
(12.70 ±0.25)
0.017 TYP
(0.43)
17
29
PIN NUMBERS
FOR REF ONLY
18
28
0.075 ±0.010
(1.91 ±0.25)
0.650 SQ ±0.010
(16.51 ±0.25)
DIMENSIONS SHOWN ARE IN INCHES (MM)
0.690 ±0.010 TYP
(17.53 ±0.25)
FIGURE 21. RDC-19222 (44-PIN CERAMIC J-LEAD) MECHANICAL OUTLINE
Data Device Corporation
www.ddc-web.com
RDC-19220 SERIES
L-11/02-300
19
16
15
14
13
12
11
10
9
TABLE 10. FRONT-END THIN-FILM RESISTOR
NETWORKS (SEE FIGURE 23)
DDC-49530, DDC-57470 RESISTOR VALUES (11.8 V INPUTS)
SYMBOL
ABS
VALUE (Ω) (%)
70.8 k 0.1
TOL REL TO
REL
VALUE (Ω) (%)
TOL TCR(PPM)
R1
R2
R1
R2
R3
R4
R5
R6
R7
R8
R9
R10
R11
25
2
2
2
2
2
2
2
2
2
2
1
2
3
4
5
6
7
8
R1
R4
12 k
12 k
0.02
0.02
0.02
0.02
0.02
FIGURE 22. (DDC-55688-1) LAYOUT AND RESISTOR
R1
70.8 k
70.8 k
35.4 k
Ω
VALUES (R1 AND R2 = 10 K , 1.0% TOL.,
R1
ABSOLUTE Tc = ±100 PPM MAX.)
R1
R6
6.9282 k 0.02
5.0718 k 0.02
5.0718 k 0.02
6.9282 k 0.02
R6
16
R11
15
R10
14
R9
13
12
R8
11
R7
10
R6
9
R11
R11
R1
70.8 k
0.02
DDC-49590 RESISTOR VALUES (90 V INPUTS)
270 k 0.1
R1
R2
R3
R4
R5
R1
R2
R3
R4
R5
R6
R7
R8
R9
R10
R11
25
2
2
2
2
2
2
2
2
2
2
R1
R4
6 k
0.02
0.02
0.02
0.02
0.02
6 k
1
2
3
4
5
6
7
8
R1
270 k
270 k
135 k
FIGURE 23. (DDC-49530, DDC-57470, DDC-49590)
LAYOUT AND RESISTOR VALUES (SEE TABLE 10)
R1
R1
R6
3.4641 k 0.02
2.5359 k 0.02
2.5359 k 0.02
3.4641 k 0.02
R6
0.870 MAX
(22.10)
R11
R11
R1
0.250 ±0.005
(6.35 ±0.13)
270 k
0.02
0.320 - 0.300
(8.13 - 7.62)
0.13 ±0.005
(3.30 ±0.13)
0.810 MAX
0.015 ±0.009
(0.38 ±0.23)
0.020 MIN
(0.51)
0.125 MIN
(3.18)
XXX-XXX
0.075 ±0.015
(1.91 ±0.38)
0.018 ±0.003
(0.46 ±0.08)
0.305 MAX
0.200 MAX
0.300 ±0.10
+0.025
0.325
DATECODE
Pin #1
-0.015
0.100 TYP
(2.54)
+0.64
-0.38
(8.26
)
DIMENSIONS SHOWN ARE IN INCHES (MM).
0.125 MIN
FIGURE 24. 16-PIN THIN-FILM RESISTOR
NETWORK MECHANICAL OUTLINE
(DDC-49530, DDC-49590*, DDC-55688)
0.100 TYP
0.820 MAX
*Note: DDC-49590 - alternate ceramic package may be substituted for plastic
package depending upon availability (See Figure 26).
XXX-XXX
0.260 ±0.010
0.200 MAX
.405
DATECODE
Pin #1
0.325 ±0.010
7˚
45˚
0.299
(7.6)
0.406
(10.3)
0.101
(2.6)
0.014
(.36)
0.125 MIN
0.342
(8.7)
0.087 MAX
0.010 TYP
0.009
(0.23)
0.100 TYP
0.092
(2.3)
DIMENSIONS SHOWN ARE IN INCHES
DIMENSIONS SHOWN ARE IN INCHES (MM).
FIGURE 26. 16-PIN THIN-FILM RESISTOR
NETWORK MECHANICAL OUTLINE
(ALTERNATE CERAMIC PACKAGE FOR DDC-49590)
FIGURE 25. 16-PIN SURFACE MOUNT THIN-FILM
RESISTOR NETWORK MECHANICAL OUTLINE
(DDC-57470)
Data Device Corporation
www.ddc-web.com
RDC-19220 SERIES
L-11/02-300
20
ORDERING INFORMATION
RDC-1922X-XXXX
Supplemental Process Requirements:
T = Tape and Reel
S = Pre-Cap Source Inspection
L = Pull Test
Q = Pre-Cap Source and Pull Test
K = One Lot Date Code
W = One Lot Date Code and Pre-Cap Source Inspection
Y = One Lot Date Code and 100% Pull Test
Z = One Lot Date Code, Pre-Cap Source Inspection and 100% Pull Test
Accuracy:
2 = 4 minutes + 1 LSB
3 = 2 minutes + 1 LSB
Process Requirements:
0 = Standard DDC Processing, no Burn-In
2 = 168 Hour Burn-In at +125°C (-55 to +125°C devices only) **
7 = 168 Hour Burn-In at +125°C (-55 to +125°C devices only) plus solder dip **
Temperature Grade:
1 = -55 to +125°C
2 = -40 to +85°C
3 = 0 to +70°C
4 = -55 to +125°C with Variables Test Data
Package:
0 = 40-Pin DDIP*
2 = 44-Pin J-Lead* with +5 Volt-Only Option
9 = Screened to Class K, 44-Pin J-Lead ceramic package,
only available in the following options: **
Temperature Grade: #1 or 4
Process Requirements: #2 or 7
*Plastic for -20X and -3XX, ceramic for -1XX and -4XX.
** For RDC-19229 Process Requirement Burn-In will be 320 hours.
Notes:
1) DDC reserves the right to supply ceramic packages in place of plastic packages.
2) Consult factory for External Component Selection Software.
THIN-FILM RESISTOR NETWORKS: (Operating temperature range: -55 to +125°C)
DDC-49530 = 11.8 V input, DIP
DDC-57470 = 11.8 V input, surface mount
DDC-49590 = 90 V input, DIP
DDC-55688-1 = 2 V direct, DIP
Data Device Corporation
www.ddc-web.com
RDC-19220 SERIES
L-11/02-300
21
NOTES:
Data Device Corporation
www.ddc-web.com
RDC-19220 SERIES
L-11/02-300
22
NOTES:
Data Device Corporation
www.ddc-web.com
RDC-19220 SERIES
L-11/02-300
23
The information in this data sheet is believed to be accurate; however, no responsibility is
assumed by Data Device Corporation for its use, and no license or rights are
granted by implication or otherwise in connection therewith.
Specifications are subject to change without notice.
105 Wilbur Place, Bohemia, New York, U.S.A. 11716-2482
For Technical Support - 1-800-DDC-5757 ext. 7382
Headquarters, N.Y., U.S.A. - Tel: (631) 567-5600, Fax: (631) 567-7358
Southeast, U.S.A. - Tel: (703) 450-7900, Fax: (703) 450-6610
West Coast, U.S.A. - Tel: (714) 895-9777, Fax: (714) 895-4988
United Kingdom - Tel: +44-(0)1635-811140, Fax: +44-(0)1635-32264
Ireland - Tel: +353-21-341065, Fax: +353-21-341568
France - Tel: +33-(0)1-41-16-3424, Fax: +33-(0)1-41-16-3425
Germany - Tel: +49-(0)8141-349-087, Fax: +49-(0)8141-349-089
Japan - Tel: +81-(0)3-3814-7688, Fax: +81-(0)3-3814-7689
World Wide Web - http://www.ddc-web.com
U
®
DATA DEVICE CORPORATION
REGISTERED TO ISO 9001
FILE NO. A5976
L-11/02-300
24
PRINTED IN THE U.S.A.
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