RF1K4922496 [ETC]
TRANSISTOR | MOSFET | PAIR | COMPLEMENTARY | 30V V(BR)DSS | 3.5A I(D) | SO ; 晶体管| MOSFET | PAIR |辅食| 30V V（ BR ） DSS | 3.5AI （ D） | SO\n
| 型号： | RF1K4922496 |
| 厂家： | 
ETC |
| 描述： | TRANSISTOR | MOSFET | PAIR | COMPLEMENTARY | 30V V(BR)DSS | 3.5A I(D) | SO
|
| 文件： | 总15页 (文件大小：444K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
RF1K49224
Data Sheet
January 2002
3.5A/2.5A, 30V, 0.060/0.150 Ohms,
Complementary LittleFET™ Power
MOSFET
Features
• 3.5A, 30V (N-Channel)
2.5A, 30V (P-Channel)
The RF1K49224 complementary power MOSFET is
manufactured using an advanced MegaFET process. This
process, which uses feature sizes approaching those of LSI
integrated circuits, gives optimum utilization of silicon,
resulting in outstanding performance. It is designed for use
in applications such as switching regulators, switching
converters, motor drivers, relay drivers, and low voltage bus
switches. This device can be operated directly from
intergrated circuits.
• r
r
= 0.060Ω (N-Channel)
= 0.150Ω (P-Channel)
DS(ON)
DS(ON)
®
• Temperature Compensating PSPICE Model
• Thermal Impedance PSPICE Model
• Peak Current vs Pulse Width Curve
• UIS Rating Curve
• Related Literature
- TB334 “Guidelines for Soldering Surface Mount
Components to PC Boards”
Formerly developmental type TA49224.
Ordering Information
Symbol
PART NUMBER
PACKAGE
BRAND
RF1K49224
D1(8)
D1(7)
RF1K49224
MS-012AA
NOTE: When ordering, use the entire part number. For ordering in
tape and reel, add the suffix 96 to the part number, i.e. RF1K4922496.
S1(1)
G1(2)
D2(6)
D2(5)
S2(3)
G2(4)
Packaging
JEDEC MS-012AA
BRANDING DASH
5
1
2
3
4
©2002 Fairchild Semiconductor Corporation
RF1K49224 Rev. B
RF1K49224
o
Absolute Maximum Ratings
T = 25 C Unless Otherwise Specified
A
N-CHANNEL
P-CHANNEL
UNITS
Drain to Source Voltage . . . . . . . . . . . . . . . . . . . . . . . . . V
30
30
-30
-30
±20
V
V
V
DSS
DGR
Drain to Gate Voltage (R = 20kΩ ) . . . . . . . . . . . . . . .V
GS
Gate to Source Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . V
±20
GS
Drain Current
Continuous (Pulse Width = 5s). . . . . . . . . . . . . . . . . . . . . I
3.5
2.5
A
D
Pulsed . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . I
Refer to Peak Current Curve
Refer to Peak Current Curve
DM
Pulsed Avalanche Rating. . . . . . . . . . . . . . . . . . . . . . . . . E
Refer to UIS Curve
Refer to UIS Curve
AS
Power Dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . P
2
2
W
D
o
o
Derate Above 25 C . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
0.016
0.016
W/ C
o
Operating and Storage Temperature . . . . . . . . . . . . T , T
-55 to 150
-55 to 150
C
J
STG
Maximum Temperature for Soldering
Leads at 0.063in (1.6mm) from Case for 10s. . . . . . . . . T
Package Body for 10s, See Techbrief 334 . . . . . . . . . .T
o
300
260
300
260
C
C
L
o
pkg
CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the
device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
NOTE:
o
o
1. T = 25 C to 125 C.
J
o
N-Channel Electrical Specifications T = 25 C, Unless Otherwise Specified
A
PARAMETER
SYMBOL
BV
TEST CONDITIONS
= 250µA, V = 0V
MIN
TYP
MAX
UNITS
V
Drain to Source Breakdown Voltage
Gate to Source Threshold Voltage
Zero Gate Voltage Drain Current
I
30
1
-
-
-
-
-
-
-
-
DSS
D
GS
V
V
= V , I = 250µA
3
V
GS(TH)
GS
DS D
o
I
V
V
= 30V,
= 0V
T
T
= 25 C
1
µA
µA
nA
Ω
DSS
DS
GS
A
A
o
= 150 C
-
50
Gate to Source Leakage Current
Drain to Source On Resistance
I
V
= ±20V
-
100
GSS
GS
r
I
= 3.5A
V
V
= 10V
-
0.060
DS(ON)
D
GS
GS
= 4.5V
0.132
Ω
Turn-On Time
t
V
R
R
= 15V, I
D
3.5A,
= 10V,
-
-
-
-
-
-
-
-
-
-
-
-
-
-
50
ns
ON
DD
= 4.29Ω, V
L
GS
Turn-On Delay Time
Rise Time
t
10
30
60
45
-
-
ns
d(ON)
= 25Ω
GS
t
-
-
ns
r
Turn-Off Delay Time
Fall Time
t
ns
d(OFF)
t
-
ns
f
Turn-Off Time
t
130
45
17
2.9
-
ns
OFF
Total Gate Charge
Gate Charge at 10V
Threshold Gate Charge
Input Capacitance
Output Capacitance
Reverse Transfer Capacitance
Thermal Resistance Junction to Ambient
Q
V
V
V
V
= 0V to 20V
= 0V to 10V
= 0V to 2V
V
DD
= 24V,
3.5A,
= 6.86Ω
35
13
2.3
575
275
100
-
nC
nC
nC
pF
pF
pF
g(TOT)
GS
GS
GS
DS
I
D
Q
g(10)
R
L
I
= 1.0mA
Q
g(REF)
g(TH)
C
= 25V, V
GS
= 0V,
ISS
OSS
RSS
f = 1MHz
C
C
-
-
o
R
Pulse width = 1s
Device mounted on FR-4 material
62.5
C/W
JA
θ
N-Channel Source to Drain Diode Specifications
PARAMETER
Source to Drain Diode Voltage
Reverse Recovery Time
SYMBOL
TEST CONDITIONS
= 3.5A
MIN
TYP
MAX
1.25
45
UNITS
V
V
I
I
-
-
-
-
SD
SD
t
= 3.5A, dI /dt = 100A/µs
SD
ns
rr
SD
©2002 Fairchild Semiconductor Corporation
RF1K49224 Rev. B
RF1K49224
o
P-Channel Electrical Specifications T = 25 C, Unless Otherwise Specified
A
PARAMETER
SYMBOL
BV
TEST CONDITIONS
= 250µA, V = 0V
MIN
TYP
MAX
UNITS
V
Drain to Source Breakdown Voltage
Gate to Source Threshold Voltage
Zero Gate Voltage Drain Current
I
-30
-
-
-
-
-
-
-
-3
DSS
D
GS
V
V
= V , I = 250µA
-1
-
V
GS(TH)
GS
DS D
o
I
V
V
= -30V,
= 0V
T
T
= 25 C
-1
µA
µA
nA
Ω
DSS
DS
GS
A
A
o
= 150 C
-
-50
100
0.150
0.360
40
-
Gate to Source Leakage Current
Drain to Source On Resistance
I
V
= ±20V
-
GSS
GS
r
I
= 2.5A
V
= -10V
= -4.5v
-
DS(ON)
D
GS
GS
V
Ω
Turn-On Time
t
V
R
R
= -15V, I
2.5A,
= -10V,
-
-
-
-
-
-
-
-
-
-
-
-
-
-
9
ns
ns
ns
ns
ns
ns
nC
nC
nC
pF
pF
pF
ON
DD
D
= 6Ω, V
L
GS
Turn-On Delay Time
Rise Time
t
d(ON)
= 25Ω
GS
t
19
60
34
-
-
r
Turn-Off Delay Time
Fall Time
t
-
d(OFF)
t
-
f
Turn-Off Time
t
140
35
19
1.9
-
OFF
Total Gate Charge
Gate Charge at -10V
Threshold Gate Charge
Input Capacitance
Output Capacitance
Reverse Transfer Capacitance
Thermal Resistance Junction to Ambient
Q
V
= 0V to -20V
= 0V to -10V
= 0V to -2V
V
DD = -24V,
28
15
1.5
580
260
38
-
g(TOT)
GS
GS
GS
DS
I
2.5A,
D
Q
V
V
V
g(-10)
g(TH)
R
= 9.6Ω
L
I
= -1.0mA
Q
g(REF)
C
= -25V, V
GS
= 0V,
ISS
OSS
RSS
f = 1MHz
C
-
C
-
o
R
Pulse width = 1s
Device mounted on FR-4 material
62.5
C/W
θJA
P-Channel Source to Drain Diode Specifications
PARAMETER
Source to Drain Diode Voltage
Reverse Recovery Time
SYMBOL
TEST CONDITIONS
= -2.5A
MIN
TYP
MAX
-1.25
49
UNITS
V
V
I
I
-
-
-
-
SD
SD
SD
t
= -2.5A, dI /dt = -100A/µs
ns
rr
SD
Typical Performance Curves (N-Channel)
1.2
1.0
0.8
4.0
3.5
3.0
2.5
2.0
1.5
1.0
0.6
0.4
0.2
0
0.5
0
75
100
125
150
0
25
50
75
100
125
150
25
50
o
o
T , AMBIENT TEMPERATURE ( C)
T , AMBIENT TEMPERATURE ( C)
A
A
FIGURE 1. NORMALIZED POWER DISSIPATION vs AMBIENT
TEMPERATURE
FIGURE 2. MAXIMUM CONTINUOUS DRAIN CURRENT vs
AMBIENT TEMPERATURE
©2002 Fairchild Semiconductor Corporation
RF1K49224 Rev. B
RF1K49224
Typical Performance Curves (N-Channel) (Continued)
10
DUTY CYCLE - DESCENDING ORDER
0.5
0.2
0.1
0.05
1
0.02
0.01
P
DM
0.1
t
1
t
2
0.01
NOTES:
DUTY FACTOR: D = t /t
1
2
PEAK T = P
J
x Z
x R
+ T
JA A
DM
JA
θ
θ
SINGLE PULSE
0.001
-4
10
-5
10
-3
10
-2
-1
10
0
1
2
3
10
10
10
10
10
t, RECTANGULAR PULSE DURATION (s)
FIGURE 3. NORMALIZED MAXIMUM TRANSIENT THERMAL IMPEDANCE
100
10
200
o
= 25 C
T
= MAX RATED
FOR TEMPERATURES
ABOVE 25 C DERATE PEAK
CURRENT AS FOLLOWS:
T
J
A
o
o
T
= 25 C
A
100
10
1
150 - T
A
I = I
25
V
= 10V
GS
125
5ms
10ms
1
0.1
TRANSCONDUCTANCE
MAY LIMIT CURRENT
IN THIS REGION
100ms
OPERATION IN THIS
AREA MAY BE
1s
LIMITED BY r
DS(ON)
DC
V
= 30V
10
DSS(MAX)
0.01
-5
-4
-3
-2
-1
10
0
1
0.1
1
100
10
10
10
10
10
10
V
, DRAIN TO SOURCE VOLTAGE (V)
t, PULSE WIDTH (s)
DS
FIGURE 4. FORWARD BIAS SAFE OPERATING AREA
FIGURE 5. PEAK CURRENT CAPABILITY
20
If R = 0
= (L)(I )/(1.3*RATED BV
25
20
15
10
5
t
- V
)
DD
AV
If R ≠ 0
= (L/R)ln[(I *R)/(1.3*RATED BV
AS
DSS
V
= 5V
GS
t
AV
- V ) +1]
DD
AS DSS
V
= 20V
= 10V
GS
10
V
GS
V
= 4.5V
= 4V
GS
o
V
GS
STARTING T = 25 C
J
PULSE DURATION = 80µs
DUTY CYCLE = 0.5% MAX
o
T
= 25 C
A
o
V
= 3V
STARTING T = 150 C
J
GS
0
1
0.1
0
1
2
3
4
5
1
10
100
t
, TIME IN AVALANCHE (ms)
AV
V
, DRAIN TO SOURCE VOLTAGE (V)
DS
NOTE: Refer to Fairchild Application Notes AN9321 and AN9322.
FIGURE 6. UNCLAMPED INDUCTIVE SWITCHING CAPABILITY
FIGURE 7. SATURATION CHARACTERISTICS
©2002 Fairchild Semiconductor Corporation
RF1K49224 Rev. B
RF1K49224
Typical Performance Curves (N-Channel) (Continued)
25
250
200
150
100
50
PULSE DURATION = 80µs
DUTY CYCLE = 0.5% MAX
PULSE DURATION = 80µs
DUTY CYCLE = 0.5% MAX
V
= 15V
o
DD
25 C
V = 15V
I
I
I
= 7.0A
= 3.5A
= 1.75A
DD
D
D
20
15
10
5
o
-55 C
D
o
150 C
I
= 0.5A
D
0
0
3
4
5
6
7
8
9
10
0
1.5
3.0
4.5
6.0
7.5
V
, GATE TO SOURCE VOLTAGE (V)
V
, GATE TO SOURCE VOLTAGE (V)
GS
GS
FIGURE 8. TRANSFER CHARACTERISTICS
FIGURE 9. DRAIN TO SOURCE ON RESISTANCE vs GATE
VOLTAGE AND DRAIN CURRENT
2.0
1.5
1.0
0.5
0
2.0
V
= V , I = 250µA
DS
PULSE DURATION = 80µs
DUTY CYCLE = 0.5% MAX
GS
D
V
= 10V, I = 3.5A
GS
D
1.5
1.0
0.5
0
-80
-80
-40
0
40
80
120
160
-40
0
40
80
120
160
o
o
T , JUNCTION TEMPERATURE ( C)
T , JUNCTION TEMPERATURE ( C)
J
J
FIGURE 10. NORMALIZED DRAIN TO SOURCE ON
RESISTANCE vs JUNCTION TEMPERATURE
FIGURE 11. NORMALIZED GATE THRESHOLD VOLTAGE vs
JUNCTION TEMPERATURE
2.0
1000
V
= 0V, f = 1MHz
GS
ISS
I
= 250µA
C
C
C
= C
+ C
D
GS
GD
= C
= C
RSS
OSS
GD
DS
+ C
GD
750
1.5
1.0
0.5
0
C
ISS
500
250
0
C
OSS
C
RSS
-80
-40
0
40
80
120
160
0
5
10
15
20
25
o
T , JUNCTION TEMPERATURE ( C)
V
, DRAIN TO SOURCE VOLTAGE (V)
DS
J
FIGURE 12. NORMALIZED DRAIN TO SOURCE BREAKDOWN
VOLTAGE vs JUNCTION TEMPERATURE
FIGURE 13. CAPACITANCE vs DRAIN TO SOURCE VOLTAGE
©2002 Fairchild Semiconductor Corporation
RF1K49224 Rev. B
RF1K49224
Typical Performance Curves (N-Channel) (Continued)
30
10.0
7.5
V
= BV
V = BV
DD DSS
DD
DSS
22.5
15
R
= 8.57Ω
L
I
= 0.75mA
g(REF)
5.0
V
= 10V
GS
PLATEAU VOLTAGES IN
DESCENDING ORDER:
V
V
V
V
= BV
2.5
0
7.5
0
DD
DD
DD
DD
DSS
= 0.75 BV
= 0.50 BV
= 0.25 BV
DSS
DSS
DSS
I
I
g(REF)
g(REF)
t, TIME (ms)
20-----------------------
80-----------------------
I
I
g(ACT)
g(ACT)
NOTE: Refer to Fairchild Application Notes AN7254 and AN7260.
FIGURE 14. NORMALIZED SWITCHING WAVEFORMS FOR CONSTANT GATE CURRENT
Test Circuits and Waveforms (N-Channel)
V
DS
BV
DSS
L
t
P
V
DS
I
VARY t TO OBTAIN
P
AS
+
-
V
DD
R
REQUIRED PEAK I
G
AS
V
DD
V
GS
DUT
t
P
I
AS
0V
0
0.01Ω
t
AV
FIGURE 15. UNCLAMPED ENERGY TEST CIRCUIT
FIGURE 16. UNCLAMPED ENERGY WAVEFORMS
t
t
ON
OFF
t
d(OFF)
t
d(ON)
t
t
f
r
R
L
V
DS
90%
90%
V
DS
V
GS
+
V
DD
10%
10%
0
0
-
DUT
90%
50%
R
GS
V
GS
50%
PULSE WIDTH
10%
V
GS
FIGURE 17. SWITCHING TIME TEST CIRCUIT
FIGURE 18. RESISTIVE SWITCHING WAVEFORMS
©2002 Fairchild Semiconductor Corporation
RF1K49224 Rev. B
RF1K49224
Test Circuits and Waveforms (N-Channel) (Continued)
V
DS
V
DD
Q
g(TOT)
R
L
V
DS
V
= 20V
GS
Q
g(10)
V
GS
+
-
V
= 10V
V
V
GS
DD
GS
V
= 2V
GS
DUT
0
I
g(REF)
Q
g(TH)
I
g(REF)
0
FIGURE 19. GATE CHARGE TEST CIRCUIT
FIGURE 20. GATE CHARGE WAVEFORM
Typical Performance Curves (P-Channel)
1.2
1.0
0.8
-3.0
-2.5
-2.0
-1.5
-1.0
0.6
0.4
0.2
0
-0.5
0
75
100
125
150
0
25
50
75
100
125
150
25
50
o
o
T , AMBIENT TEMPERATURE ( C)
T , AMBIENT TEMPERATURE ( C)
A
A
FIGURE 21. NORMALIZED POWER DISSIPATION vs AMBIENT
TEMPERATURE
FIGURE 22. MAXIMUM CONTINUOUS DRAIN CURRENT vs
AMBIENT TEMPERATURE
10
DUTY CYCLE - DESCENDING ORDER
0.5
0.2
0.1
0.05
1
0.02
0.01
P
DM
0.1
t
1
t
2
0.01
NOTES:
DUTY FACTOR: D = t /t
1
2
PEAK T = P
J
x Z
x R
+ T
JA A
DM
JA
θ
θ
SINGLE PULSE
0.001
-4
10
-5
-3
-2
-1
0
1
2
3
10
10
10
10
10
10
10
10
t, RECTANGULAR PULSE DURATION (s)
FIGURE 23. NORMALIZED MAXIMUM TRANSIENT THERMAL IMPEDANCE
©2002 Fairchild Semiconductor Corporation
RF1K49224 Rev. B
RF1K49224
Typical Performance Curves (P-Channel) (Continued)
-50
-10
-100
o
T
= MAX RATED
V
= -20V
= -10V
FOR TEMPERATURES
ABOVE 25 C DERATE PEAK
CURRENT AS FOLLOWS:
J
T
= 25 C
GS
A
o
o
T
= 25 C
A
150 - T
I = I
A
25
V
GS
125
5ms
-1
-0.1
10ms
-10
TRANSCONDUCTANCE
MAY LIMIT CURRENT
IN THIS REGION
100ms
1s
OPERATION IN THIS
AREA MAY BE
DC
V
= -30V
-10
LIMITED BY r
DSS(MAX)
DS(ON)
-0.01
-1
-5
10
-4
-3
10
-2
10
-1
0
1
-0.1
-1
-100
10
10
t, PULSE WIDTH (s)
10
10
V
, DRAIN TO SOURCE VOLTAGE (V)
DS
FIGURE 24. FORWARD BIAS SAFE OPERATING AREA
FIGURE 25. PEAK CURRENT CAPABILITY
-15
-10
-20
If R = 0
= (L)(I )/(1.3*RATED BV
V
= -20V
= -10V
= -8V
PULSE DURATION = 80µs
GS
t
- V
)
DD
AV
If R ≠ 0
AS
DSS
DUTY CYCLE = 0.5% MAX
V
GS
o
T
= 25 C
A
V
= -7V
t
AV
= (L/R)ln[(I *R)/(1.3*RATED BV
AS
- V ) +1]
DD
-16
-12
-8
DSS
GS
V
GS
V
= -6V
GS
o
STARTING T = 25 C
J
V
= -5V
GS
o
STARTING T = 150 C
J
V
= -4.5V
GS
-4
0
-1
0.1
0
-1.5
-3.0
-4.5
-6.0
-7.5
1
10
100
t
, TIME IN AVALANCHE (ms)
AV
V
, DRAIN TO SOURCE VOLTAGE (V)
DS
NOTE: Refer to Fairchild Application Notes AN9321 and AN9322.
FIGURE 26. UNCLAMPED INDUCTIVE SWITCHING CAPABILITY
FIGURE 27. SATURATION CHARACTERISTICS
-20
500
PULSE DURATION = 80µs
DUTY CYCLE = 0.5% MAX
PULSE DURATION = 80µs
DUTY CYCLE = 0.5% MAX
o
V
= -15V
V
= -15V
150 C
DD
DD
400
300
200
100
0
-16
-12
-8
I
I
= -5.0A
= -2.5A
o
D
-55 C
o
D
D
25 C
I
= -1.25A
I
= -0.625A
D
-4
0
-4
-6
-8
-10
-2
0
-2
-4
-6
-8
-10
V
, GATE TO SOURCEVOLTAGE (V)
V
GS
, GATE TO SOURCE VOLTAGE (V)
GS
FIGURE 28. TRANSFER CHARACTERISTICS
FIGURE 29. DRAIN TO SOURCE ON RESISTANCE vs GATE
VOLTAGE AND DRAIN CURRENT
©2002 Fairchild Semiconductor Corporation
RF1K49224 Rev. B
RF1K49224
Typical Performance Curves (P-Channel) (Continued)
2.0
1.2
1.0
0.8
0.6
0.4
V
= V , I = -250µA
DS
GS
D
PULSE DURATION = 80µs
DUTY CYCLE = 0.5% MAX
V
= -10V, I = -2.5A
GS
D
1.5
1.0
0.5
0
-80
-40
0
40
80
120
160
-80
-40
0
40
80
120
160
o
o
T , JUNCTION TEMPERATURE ( C)
T , JUNCTION TEMPERATURE ( C)
J
J
FIGURE 30. NORMALIZED DRAIN TO SOURCE ON
RESISTANCE vs JUNCTION TEMPERATURE
FIGURE 31. NORMALIZED GATE THRESHOLD VOLTAGE vs
JUNCTION TEMPERATURE
1.2
750
I
= -250µA
D
C
ISS
600
450
300
1.1
1.0
0.9
0.8
V
= 0V, f = 1MHz
GS
ISS
C
C
C
= C
+ C
GS
GD
= C
= C
RSS
OSS
GD
DS GD
+ C
C
C
OSS
150
0
RSS
0
-5
-10
, DRAIN TO SOURCE VOLTAGE (V)
DS
-15
-20
-25
-80
-40
0
40
80
120
160
o
T , JUNCTION TEMPERATURE ( C)
V
J
FIGURE 32. NORMALIZED DRAIN TO SOURCE BREAKDOWN
VOLTAGE vs JUNCTION TEMPERATURE
FIGURE 33. CAPACITANCE vs DRAIN TO SOURCE VOLTAGE
-10.0
-30.0
V
= BV
DD
DSS
V
= BV
DSS
DD
-22.5
-15.0
-7.5
0
-7.5
-5.0
R
I
= 12Ω
g(REF)
L
= -0.26mA
V
= -10V
GS
PLATEAU VOLTAGES IN
DESCENDING ORDER:
-2.5
0
V
V
V
V
= BV
DD
DD
DD
DD
DSS
= 0.75 BV
= 0.50 BV
= 0.25 BV
DSS
DSS
DSS
I
I
g(REF)
g(REF)
t, TIME (µs)
20-----------------------
80--------------------
I
I
g(ACT)
g(ACT)
NOTE: Refer to Fairchild Application Notes AN7254 and AN7260.
FIGURE 34. NORMALIZED SWITCHING WAVEFORMS FOR CONSTANT GATE CURRENT
©2002 Fairchild Semiconductor Corporation
RF1K49224 Rev. B
RF1K49224
Test Circuits and Waveforms (P-Channel)
V
DS
t
AV
L
0
VARY t TO OBTAIN
P
-
R
REQUIRED PEAK I
G
AS
V
DD
+
DUT
0V
V
DD
t
P
I
AS
V
GS
V
DS
I
AS
t
P
0.01Ω
BV
DSS
FIGURE 35. UNCLAMPED ENERGY TEST CIRCUIT
FIGURE 36. UNCLAMPED ENERGY WAVEFORMS
t
t
ON
OFF
t
t
d(OFF)
d(ON)
t
t
f
r
0
10%
10%
R
L
V
DS
V
GS
-
V
DS
90%
90%
V
DD
+
V
0
GS
V
GS
10%
50%
DUT
R
GS
50%
90%
PULSE WIDTH
FIGURE 37. SWITCHING TIME TEST CIRCUIT
FIGURE 38. RESISTIVE SWITCHING WAVEFORMS
V
DS
V
DS
Q
R
g(TH)
L
0
V
= -2V
-V
GS
V
GS
-
V
= -10V
GS
GS
V
DD
Q
+
g(-10)
V
= -20V
GS
DUT
V
DD
I
g(REF)
Q
g(TOT)
0
I
g(REF)
FIGURE 39. GATE CHARGE TEST CIRCUIT
FIGURE 40. GATE CHARGE WAVEFORMS
©2002 Fairchild Semiconductor Corporation
RF1K49224 Rev. B
RF1K49224
Soldering Precautions
o
The soldering process creates a considerable thermal stress
on any semiconductor component. The melting temperature
of solder is higher than the maximum rated temperature of
the device. The amount of time the device is heated to a high
temperature should be minimized to assure device reliability.
Therefore, the following precautions should always be
observed in order to minimize the thermal stress to which the
devices are subjected.
3. Themaximumtemperaturegradientshouldbelessthan5 C
per second when changing from preheating to soldering.
4. The peak temperature in the soldering process should be
o
at least 30 C higher than the melting point of the solder
chosen.
5. The maximum soldering temperature and time must not
o
exceed 260 C for 10 seconds on the leads and case of
the device.
6. After soldering is complete, the device should be allowed
to cool naturally for at least three minutes, as forced cool-
ing will increase the temperature gradient and may result
in latent failure due to mechanical stress.
1. Always preheat the device.
2. The deltatemperature between the preheatandsoldering
o
should always be less than 100 C. Failure to preheat the
device can result in excessive thermal stress which can
damage the device.
7. During cooling, mechanical stress or shock should be
avoided.
©2002 Fairchild Semiconductor Corporation
RF1K49224 Rev. B
RF1K49224
PSPICE Electrical Model (N-Channel)
SUBCKT RF1K49224 2 1 3 ;N-Channel Model rev 12/15/94
CA 12 8 1.75e-9
CB 15 14 1.80e-9
CIN 6 8 1.20e-9
DPLCAP
5
DRAIN
2
DBODY 7 5 DBDMOD
10
LDRAIN
DBREAK 5 11 DBKMOD
DPLCAP 10 5 DPLCAPMOD
DBREAK
EBREAK 11 7 17 18 33.29
EDS 14 8 5 8 1
RDRAIN
EGS 13 8 6 8 1
ESG 6 10 6 8 1
EVTO 20 6 18 8 1
11
+
DBODY
6
8
EBREAK
MOS2
ESG
17
18
16
+
VTO
+
IT 8 17 1
EVTO
GATE
21
9
20
+
6
18
8
LDRAIN 2 5 1e-9
LGATE 1 9 1.233e-9
LSOURCE 3 7 0.452e-9
1
MOS1
RGATE
LGATE
CIN
RIN
LSOURCE
RSOURCE
8
7
MOS1 16 6 8 8 MOSMOD M = 0.99
MOS2 16 21 8 8 MOSMOD M = 0.01
3
SOURCE
S1A
S2A
RBREAK 17 18 RBKMOD 1
RDRAIN 5 16 RDSMOD 1e-4
RGATE 9 20 1.83
RIN 6 8 1e9
RSOURCE 8 7 RDSMOD 13.5e-3
RVTO 18 19 RVTOMOD 1
RBREAK
12
15
13
8
14
13
17
18
S1B
CA
S2B
13
RVTO
19
CB
IT
14
+
+
VBAT
+
6
8
5
8
EDS
EGS
S1A 6 12 13 8 S1AMOD
S1B 13 12 13 8 S1BMOD
S2A 6 15 14 13 S2AMOD
S2B 13 15 14 13 S2BMOD
VBAT 8 19 DC 1
VTO 21 6 0.1
.MODEL DBDMOD D (IS = 2.50e-13 RS = 1.35e-2 TRS1 = 4.31e-5 TRS2 = 2.15e-5 CJO = 9.33e-10 TT = 2.08e-8)
.MODEL DBKMOD D (RS = 1.14 TRS1 = 2.23e-3 TRS2 = -8.91e-6)
.MODEL DPLCAPMOD D (CJO = 7.99e-10 IS = 1e-30 N = 10)
.MODEL MOSMOD NMOS (VTO = 2.1 5KP = 6.2 5IS = 1e-3 0N = 1 0TOX = 1L = 1 uW = 1u)
.MODEL RBKMOD RES (TC1 = 7.74e- 4TC2 = 1.13e-6)
.MODEL RDSMOD RES (TC1 = 4.5e-3 TC2 = -7.45e-7)
.MODEL RVTOMOD RES (TC1 = -4.16e- 3TC2 = 2.16e-6)
.MODEL S1AMOD VSWITCH (RON = 1e-5 ROFF = 0.1 VON = -7.15 VOFF= -5.15)
.MODEL S1BMOD VSWITCH (RON = 1e-5 ROFF = 0.1 VON = -5.15 VOFF= -7.15)
.MODEL S2AMOD VSWITCH (RON = 1e-5 ROFF = 0.1 VON = -2.6 VOFF= 2.4)
.MODEL S2BMOD VSWITCH (RON = 1e-5 ROFF = 0.1 VON = 2.4 VOFF= -2.6)
.ENDS
NOTE: For further discussion of the PSPICE model, consult A New PSPICE Sub-Circuit for the Power MOSFET Featuring Global
Temperature Options; IEEE Power Electronics Specialist Conference Records, 1991.
©2002 Fairchild Semiconductor Corporation
RF1K49224 Rev. B
RF1K49224
PSPICE Electrical Model (P-Channel)
SUBCKT RF1K49224 2 1 3 ;P-Channel Model rev 4/7/97
CA 12 8 7.29e-10
CB 15 14 5.01e-10
CIN 6 8 5.55e-10
LDRAIN
ESG
DRAIN
2
5
-
+
8
6
10
DBODY 5 7 DBODYMOD
DBREAK 7 11 DBREAKMOD
DPLCAP 10 6 DPLCAPMOD
RLDRAIN
RSLC1
51
+
+
RSLC2
17
18
5
51
EBREAK
ESLC
EBREAK 5 11 17 18 -35.46
EDS 14 8 5 8 1
EGS 13 8 6 8 1
ESG 5 10 8 6 1
EVTHRES 6 21 19 8 1
-
50
-
DPLCAP
RDRAIN
DBODY
EVTHRES
+
EVTEMP 6 20 18 22 1
16
21
-
19
8
MWEAK
LGATE
EVTEMP
11
RGATE
GATE
1
6
IT 8 17 1
-
+
18
22
MMED
9
20
DBREAK
LDRAIN 2 5 1e-9
LGATE 1 9 1.27e-9
LSOURCE 3 7 4.20e-10
MSTRO
8
RLGATE
LSOURCE
CIN
SOURCE
3
7
MMED 16 6 8 8 MMEDMOD
MSTRO 16 6 8 8 MSTROMOD
MWEAK 16 21 8 8 MWEAKMOD
RSOURCE
RLSOURCE
S1A
S2A
RBREAK
12
15
13
14
13
RBREAK 17 18 RBREAKMOD 1
RDRAIN 50 16 RDRAINMOD 19.3e-3
RGATE 9 20 7.44
RLDRAIN 2 5 10
RLGATE 1 9 12.7
RLSOURCE 3 7 4.2
RSLC1 5 51 RSLCMOD 1e-6
RSLC2 5 50 1e3
17
18
8
RVTEMP
19
S1B
S2B
13
CB
CA
IT
14
-
+
+
VBAT
6
8
5
8
EGS
EDS
+
-
-
RSOURCE 8 7 RSOURCEMOD 65.37e-3
RVTHRES 22 8 RVTHRESMOD 1
RVTEMP 18 19 RVTEMPMOD 1
8
22
RVTHRES
S1A 6 12 13 8 S1AMOD
S1B 13 12 13 8 S1BMOD
S2A 6 15 14 13 S2AMOD
S2B 13 15 14 13 S2BMOD
VBAT 22 19 DC 1
ESLC 51 50 VALUE={(V(5,51)/ABS(V(5,51)))*(PWR(V(5,51)/(1e-6*48),2.5))}
.MODEL DBODYMOD D (IS = 3.30e-13 RS = 4.56e-2 TRS1 =6.98e-4 TRS2 =8.08e-7 CJO = 8.21e-10 TT = 3.51e-8 M=0.4)
.MODEL DBREAKMOD D (RS = 8.18e- 1TRS1 =5.28e- 3TRS2 = -7.18e-5
.MODEL DPLCAPMOD D (CJO = 2.52e-1 0IS = 1e-3 0N = 10 M=0.6)
.MODEL MMEDMOD PMOS (VTO= -1.95 KP=0.75 IS=1e-30 N=10 TOX=1 L=1u W=1u RG=7.44)
.MODEL MSTROMOD PMOS (VTO= -2.44 KP= 7.25 IS=1e-30 N=10 TOX=1 L=1u W=1u)
.MODEL MWEAKMOD PMOS (VTO= -1.68 KP=0.045 IS=1e-30 N=10 TOX=1 L=1u W=1u RG=74.4 RS=0.1)
.MODEL RBREAKMOD RES (TC1 = 9.45e- 4TC2 = -1.01e-7)
.MODEL RDRAINMOD RES (TC1 = 3.69e-3 TC2 = 5.90e-6)
.MODEL RSLCMOD RES (TC1=3.46e-3 TC2= 1.26e-6)
.MODEL RSOURCEMOD RES (TC1=3.69e-3 TC2=5.90e-6)
.MODEL RVTHRESMOD RES (TC=-5.19e-4 TC2= 5.02e-6)
.MODEL RVTEMPMOD RES (TC1 = -3.54e- 3TC2 = -6.53e-7)
.MODEL S1AMOD VSWITCH (RON = 1e-5 ROFF = 0.1 VON = 6.94 VOFF= 3.94)
.MODEL S1BMOD VSWITCH (RON = 1e-5 ROFF = 0.1 VON = 3.94 VOFF= 6.94)
.MODEL S2AMOD VSWITCH (RON = 1e-5 ROFF = 0.1 VON = 0.40 VOFF= -2.60)
.MODEL S2AMOD VSWITCH (RON = 1e-5 ROFF = 0.1 VON = -2.60 VOFF= 0.40)
.ENDS
NOTE:For further discussion of the PSPICE model, consult A New PSPICE Sub-Circuit for the Power MOSFET Featuring Global
Temperature Options;IEEE Power Electronics Specialist Conference Records, 1991, written by William J. Hepp and C. Frank Wheatley.
©2002 Fairchild Semiconductor Corporation
RF1K49224 Rev. B
RF1K49224
PSpice Thermal Model
JUNCTION
7
REV 28 Feb 97
RF1K49224
RTHERM1
CTHERM1
CTHERM1 7 6 1.00e-7
CTHERM2 6 5 9.00e-4
CTHERM3 5 4 3.00e-3
CTHERM4 4 3 4.00e-2
CTHERM5 3 2 5.20e-3
CTHERM6 2 1 1.90e-2
6
RTHERM2
RTHERM3
RTHERM4
RTHERM5
RTHERM6
CTHERM2
CTHERM3
CTHERM4
CTHERM5
CTHERM6
RTHERM1 7 6 7.10e-2
RTHERM2 6 5 1.90e-1
RTHERM3 5 4 5.95e-1
RTHERM4 4 3 4.27
RTHERM5 3 2 1.2e1
RTHERM6 2 1 1.04e2
5
4
3
2
1
CASE
©2002 Fairchild Semiconductor Corporation
RF1K49224 Rev. B
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not intended to be an exhaustive list of all such trademarks.
â
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STAR*POWER™
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ACEx™
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OPTOLOGIC™
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PACMAN™
FASTr™
FRFET™
SuperSOT™-3
SuperSOT™-6
SuperSOT™-8
SyncFET™
GlobalOptoisolator™
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HiSeC™
ISOPLANAR™
LittleFET™
MicroFET™
MicroPak™
MICROWIRE™
CROSSVOLT™
DenseTrench™
DOME™
POP™
Power247™
PowerTrenchâ
QFET™
EcoSPARK™
E2CMOSTM
TinyLogic™
QS™
EnSignaTM
TruTranslation™
UHC™
QT Optoelectronics™
Quiet Series™
SILENTSWITCHERâ
FACT™
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UltraFETâ
STAR*POWER is used under license
DISCLAIMER
FAIRCHILD SEMICONDUCTOR RESERVES THE RIGHT TO MAKE CHANGES WITHOUT FURTHER
NOTICE TO ANY PRODUCTS HEREIN TO IMPROVE RELIABILITY, FUNCTION OR DESIGN. FAIRCHILD
DOES NOT ASSUME ANY LIABILITYARISING OUT OF THE APPLICATION OR USE OFANY PRODUCT
OR CIRCUIT DESCRIBED HEREIN; NEITHER DOES IT CONVEY ANY LICENSE UNDER ITS PATENT
RIGHTS, NOR THE RIGHTS OF OTHERS.
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FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT
DEVICESORSYSTEMSWITHOUTTHEEXPRESSWRITTENAPPROVALOFFAIRCHILDSEMICONDUCTORCORPORATION.
As used herein:
1. Life support devices or systems are devices or
systems which, (a) are intended for surgical implant into
the body, or (b) support or sustain life, or (c) whose
failure to perform when properly used in accordance
with instructions for use provided in the labeling, can be
reasonably expected to result in significant injury to the
user.
2. A critical component is any component of a life
support device or system whose failure to perform can
be reasonably expected to cause the failure of the life
support device or system, or to affect its safety or
effectiveness.
PRODUCT STATUS DEFINITIONS
Definition of Terms
Datasheet Identification
Product Status
Definition
Advance Information
Formative or
In Design
This datasheet contains the design specifications for
product development. Specifications may change in
any manner without notice.
Preliminary
First Production
This datasheet contains preliminary data, and
supplementary data will be published at a later date.
Fairchild Semiconductor reserves the right to make
changes at any time without notice in order to improve
design.
No Identification Needed
Obsolete
Full Production
This datasheet contains final specifications. Fairchild
Semiconductor reserves the right to make changes at
any time without notice in order to improve design.
Not In Production
This datasheet contains specifications on a product
that has been discontinued by Fairchild semiconductor.
The datasheet is printed for reference information only.
Rev. H4
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