RH80532NC021256 [ETC]
Microprocessor ; 微处理器\n
| 型号： | RH80532NC021256 |
| 厂家： | 
ETC |
| 描述： | Microprocessor
|
| 文件： | 总93页 (文件大小：1955K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Mobile Intel Celeron Processor
on .13 Micron Process and in
Micro-FCPGA Package
Datasheet
September 2002
Order Number: 251308-002
Information in this document is provided solely to enable use of Intel products. Intel assumes no liability whatsoever, including infringement of any
patent or copyright, for sale and use of Intel products except as provided in Intel's Terms and Conditions of Sale for such products. Information
contained herein supersedes previously published specifications on these devices from Intel.
Actual system-level properties, such as skin temperature, are a function of various factors, including component placement, component power
characteristics, system power and thermal management techniques, software application usage and general system design. Intel is not responsible
for its customers' system designs, nor is Intel responsible for ensuring that its customers' products comply with all applicable laws and regulations.
Intel provides this and other thermal design information for informational purposes only. System design is the sole responsibility of Intel's customers,
and Intel's customers should not rely on any Intel-provided information as either an endorsement or recommendation of any particular system design
characteristics.
Information in this document is provided in connection with Intel products. No license, express or implied, by estoppel or otherwise, to any intellectual
property rights is granted by this document. Except as provided in Intel’s Terms and Conditions of Sale for such products, Intel assumes no liability
whatsoever, and Intel disclaims any express or implied warranty, relating to sale and/or use of Intel products including liability or warranties relating to
fitness for a particular purpose, merchantability, or infringement of any patent, copyright or other intellectual property right. Intel products are not
intended for use in medical, life saving, or life sustaining applications.
Intel may make changes to specifications and product descriptions at any time, without notice.
Designers must not rely on the absence or characteristics of any features or instructions marked “reserved” or “undefined.” Intel reserves these for
future definition and shall have no responsibility whatsoever for conflicts or incompatibilities arising from future changes to them.
The Mobile Intel Celeron Processor may contain design defects or errors known as errata which may cause the product to deviate from published
specifications. Current characterized errata are available on request.
Contact your local Intel sales office or your distributor to obtain the latest specifications and before placing your product order.
Copies of documents which have an ordering number and are referenced in this document, or other Intel literature, may be obtained by calling 1-800-
548-4725 or by visiting Intel’s website at http://www.intel.com
Copyright © 2002 Intel Corporation.
Intel, Celeron, and Intel NetBurst are registered trademarks or trademarks of Intel Corporation and its subsidiares in the United States and other
countries.
* Other brands and names may be claimed as property of others.
2
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Datasheet
Contents
Contents
1
Introduction......................................................................................................................................9
1.1
Terminology........................................................................................................................10
1.1.1 Terminology ...........................................................................................................10
References .........................................................................................................................11
1.2
2
Electrical Specifications.................................................................................................................13
2.1
2.2
2.3
System Bus and GTLREF ..................................................................................................13
Power and Ground Pins......................................................................................................13
Decoupling Guidelines........................................................................................................13
2.3.1 VCC Decoupling ....................................................................................................14
2.3.2 System Bus AGTL+ Decoupling ............................................................................14
2.3.3 System Bus Clock (BCLK[1:0]) and Processor Clocking.......................................14
Voltage Identification and Power Sequencing ....................................................................15
2.4.1 Phase Lock Loop (PLL) Power and Filter ..............................................................16
2.4.2 Catastrophic Thermal Protection ...........................................................................18
Signal Terminations, Unused Pins, and TESTHI[11:0].......................................................18
System Bus Signal Groups.................................................................................................19
Asynchronous GTL+ Signals ..............................................................................................21
Test Access Port (TAP) Connection...................................................................................21
System Bus Frequency Select Signals (BSEL[1:0]) ...........................................................21
2.4
2.5
2.6
2.7
2.8
2.9
2.10 Maximum Ratings...............................................................................................................22
2.11 Processor DC Specifications ..............................................................................................22
2.12 AGTL+ System Bus Specifications.....................................................................................31
2.13 System Bus AC Specifications ...........................................................................................32
2.14 Processor AC Timing Waveforms.......................................................................................37
3
System Bus Signal Quality Specifications.....................................................................................47
3.1
3.2
3.3
System Bus Clock (BCLK) Signal Quality Specifications and Measurement Guidelines ...47
System Bus Signal Quality Specifications and Measurement Guidelines ..........................48
System Bus Signal Quality Specifications and Measurement Guidelines ..........................51
3.3.1 Overshoot/Undershoot Guidelines.........................................................................51
3.3.2 Overshoot/Undershoot Magnitude.........................................................................51
3.3.3 Overshoot/Undershoot Pulse Duration ..................................................................51
3.3.4 Activity Factor ........................................................................................................52
3.3.5 Reading Overshoot/Undershoot Specification Tables ...........................................52
3.3.6 Conformance Determination to Overshoot/Undershoot Specifications..................53
4
5
Package Mechanical Specifications ..............................................................................................57
4.1 Processor Pin-Out ..............................................................................................................60
Pin Listing and Signal Definitions ..................................................................................................63
5.1
5.2
Mobile Intel Celeron Processor Pin Assignments...............................................................63
Alphabetical Signals Reference..........................................................................................77
6
Thermal Specifications and Design Considerations......................................................................85
6.1
Thermal Specifications .......................................................................................................86
6.1.1 Thermal Diode .......................................................................................................86
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6.1.2 Thermal Monitor.....................................................................................................87
Configuration and Low Power Features ........................................................................................89
7
7.1
7.2
Power-On Configuration Options........................................................................................89
Clock Control and Low Power States .................................................................................89
7.2.1 Normal State..........................................................................................................89
7.2.2 AutoHALT Powerdown State.................................................................................90
7.2.3 Stop-Grant State....................................................................................................90
7.2.4 HALT/Grant Snoop State.......................................................................................91
7.2.5 Sleep State ............................................................................................................91
7.2.6 Deep Sleep State...................................................................................................92
8
Debug Tools Specifications...........................................................................................................93
8.1
Logic Analyzer Interface (LAI) ............................................................................................93
8.1.1 Mechanical Considerations....................................................................................93
8.1.2 Electrical Considerations .......................................................................................93
4
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Figures
1
2
3
4
5
6
7
8
9
VCCVID Pin Voltage and Current Requirements .......................................................................15
Typical VCCIOPLL, VCCA and VSSA Power Distribution..........................................................17
Phase Lock Loop (PLL) Filter Requirements.............................................................................17
Illustration of VCC Static and Transient Tolerances (VID = 1.30 V)...........................................25
Illustration of Deep Sleep VCC Static and Transient Tolerances (VID Setting = 1.30 V)...........26
ITPCLKOUT[1:0] Output Buffer Diagram....................................................................................31
AC Test Circuit............................................................................................................................38
TCK Clock Waveform .................................................................................................................38
Differential Clock Waveform .......................................................................................................39
10 Differential Clock Crosspoint Specification.................................................................................40
11 System Bus Common Clock Valid Delay Timings ......................................................................40
12 System Bus Reset and Configuration Timings ...........................................................................41
13 Source Synchronous 2X (Address) Timings...............................................................................41
14 Source Synchronous 4X Timings ...............................................................................................42
15 Power Up Sequence..................................................................................................................43
16 Power Down Sequence ..............................................................................................................43
17 Test Reset Timings.....................................................................................................................44
18 THERMTRIP# to Vcc Timing......................................................................................................44
19 FERR#/PBE# Valid Delay Timing...............................................................................................44
20 TAP Valid Delay Timing..............................................................................................................45
21 ITPCLKOUT Valid Delay Timing.................................................................................................45
22 Stop Grant/Sleep/Deep Sleep Timing.........................................................................................46
23 BCLK Signal Integrity Waveform ................................................................................................48
24 Low-to-High System Bus Receiver Ringback Tolerance............................................................49
25 High-to-Low System Bus Receiver Ringback Tolerance............................................................49
26 Low-to-High System Bus Receiver Ringback Tolerance for PWRGOOD and TAP Buffers.......50
27 High-to-Low System Bus Receiver Ringback Tolerance for PWRGOOD and TAP Buffers.......50
28 Maximum Acceptable Overshoot/Undershoot Waveform...........................................................56
29 Micro-FCPGA Package Top and Bottom Isometric Views..........................................................57
30 Micro-FCPGA Package - Top and Side Views ...........................................................................58
31 Micro-FCPGA Package - Bottom View.......................................................................................60
32 The Coordinates of the Processor Pins as Viewed From the Top of the Package.....................61
33 Clock Control States...................................................................................................................90
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Datasheet
Contents
Tables
1
2
3
4
5
6
7
8
9
References .................................................................................................................................11
Core Frequency to System Bus Multipliers ................................................................................14
Voltage Identification Definition ..................................................................................................15
System Bus Pin Groups .............................................................................................................20
BSEL[1:0] Frequency Table for BCLK[1:0].................................................................................21
Processor DC Absolute Maximum Ratings ................................................................................22
Voltage and Current Specifications ............................................................................................23
IMVP-III Voltage Regulator Tolerances for VID = 1.30 V Operating Mode.................................24
IMVP-III Deep Sleep State Voltage Regulator Tolerances (VID = 1.30 V, VID Offset = 4.62%) 25
10 System Bus Differential BCLK Specifications.............................................................................27
11 AGTL+ Signal Group DC Specifications.....................................................................................28
12 Asynchronous GTL+ Signal Group DC Specifications ...............................................................29
13 PWRGOOD and TAP Signal Group DC Specifications..............................................................30
14 ITPCLKOUT[1:0] DC Specifications...........................................................................................30
15 BSEL [1:0] and VID[4:0] DC Specifications................................................................................31
16 AGTL+ Bus Voltage Definitions..................................................................................................32
17 System Bus Differential Clock Specifications.............................................................................33
18 System Bus Common Clock AC Specifications..........................................................................33
19 System Bus Source Synch AC Specifications AGTL+ Signal Group .........................................34
20 Miscellaneous Signals AC Specifications...................................................................................35
21 System Bus AC Specifications (Reset Conditions) ....................................................................35
22 TAP Signals AC Specifications...................................................................................................36
23 ITPCLKOUT[1:0] AC Specifications ...........................................................................................36
24 Stop Grant/Sleep/Deep Sleep AC Specifications.......................................................................37
25 BCLK Signal Quality Specifications............................................................................................47
26 Ringback Specifications for AGTL+ and Asynchronous GTL+ Signal Groups...........................48
27 Ringback Specifications for PWRGOOD Input and TAP Signal Groups....................................49
28 Source Synchronous (400 MHz) AGTL+ Signal Group Overshoot/Undershoot Tolerance........53
29 Source Synchronous (200 MHz) AGTL+ Signal Group Overshoot/Undershoot Tolerance........54
30 Common Clock (100 MHz) AGTL+ Signal Group Overshoot/Undershoot Tolerance.................54
31 Asynchronous GTL+, PWRGOOD Input, and TAP Signal Groups Overshoot/Undershoot
Tolerance....................................................................................................................................56
32 Micro-FCPGA Package Dimensions ..........................................................................................59
33 Pin Listing by Pin Name .............................................................................................................64
34 Pin Listing by Pin Number ..........................................................................................................70
35 Signal Description.......................................................................................................................77
36 Power Specifications for the Mobile Intel Celeron Processor.....................................................85
37 Thermal Diode Interface.............................................................................................................86
38 Thermal Diode Specifications.....................................................................................................86
39 Power-On Configuration Option Pins .........................................................................................89
6
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Datasheet
Contents
Revision History
Date
Revision
Description
June 2002
1.0
Initial release of the datasheet
Updates include:
•
•
•
Added specifications for 1.6 GHz, 1.7 GHz, and 1.8 GHz
September 2002 2.0
Current and power specifications updated in Table 7 and Table 38
Corrected STPCLK#/SLP# timing relationship in Section 7.2.3 to match
parameter T75.
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Introduction
1 Introduction
The Mobile Intel Celeron Processor on .13 Micron Process and in Micro-FCPGA Package
utilizes a 478-pin, Micro Flip-Chip Pin Grid Array (Micro-FCPGA) package, and plugs into a
surface-mount, Zero Insertion Force (ZIF) socket. The Mobile Intel Celeron Processor on .13
micron process maintains the tradition of compatibility with IA-32 software. In this document the
Mobile Intel Celeron Processor on .13 Micron Process and in Micro-FCPGA Package will be
referred to as the “Mobile Intel Celeron Processor” or simply “the processor”.
The Mobile Intel Celeron Processor is designed for uni-processor based Value PC mobile systems.
Features of the processor include hyper pipelined technology, a 400-MHz system bus, and an
execution trace cache. The 400-MHz system bus is a quad-pumped bus running off a 100-MHz
system clock making 3.2 GB/sec data transfer rates possible. The execution trace cache is a first
level cache that stores approximately 12-k decoded micro-operations, which removes the decoder
from the main execution path.
Additional features include advanced dynamic execution, advanced transfer cache, enhanced
floating point and multi-media unit, and Streaming SIMD Extensions 2 (SSE2). The advanced
dynamic execution improves speculative execution and branch prediction internal to the processor.
The advanced transfer cache is a 256 KB, on-die level 2 (L2) cache. The floating point and multi
media units have 128-bit wide registers with a separate register for data movement. Finally, SSE2
support includes instructions for double-precision floating point, SIMD integer, and memory
management. Power management capabilities such as AutoHALT, Stop-Grant, Sleep, and Deep
Sleep have been incorporated. The processor includes an address bus power down capability which
removes power from the address and data pins when the system bus is not in use. This feature is
always enabled on the processor.
The Mobile Intel Celeron Processor’s 400-MHz system bus utilizes a split-transaction, deferred
reply protocol. This system bus is not compatible with the P6 processor family bus. The 400-MHz
system bus uses Source-Synchronous Transfer (SST) of address and data to improve throughput by
transferring data four times per bus clock (4X data transfer rate, as in AGP 4X). Along with the 4X
data bus, the address bus can deliver addresses two times per bus clock and is referred to as a
“double-clocked” or 2X address bus. Working together, the 4X data bus and 2X address bus
provide a data bus bandwidth of up to 3.2 Gbytes/second.
The processor system bus uses a variant of GTL+ signalling technology called Assisted Gunning
Transceiver Logic (AGTL+) signal technology. The Mobile Intel Celeron Processor is available at
the following core frequencies:
• 1.8 GHz (at 1.30 V)
• 1.7 GHz (at 1.30 V)
• 1.6 GHz (at 1.30 V)
• 1.5 GHz (at 1.30 V)
• 1.4 GHz (at 1.30 V)
251308-002
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Datasheet
Introduction
1.1
Terminology
A “#” symbol after a signal name refers to an active low signal, indicating a signal is in the active
state when driven to a low level. For example, when RESET# is low, a reset has been requested.
Conversely, when NMI is high, a nonmaskable interrupt has occurred. In the case of signals where
the name does not imply an active state but describes part of a binary sequence (such as address or
data), the “#” symbol implies that the signal is inverted. For example, D[3:0] = “HLHL” refers to a
hex ‘A’, and D[3:0]# = “LHLH” also refers to a hex “A” (H= High logic level, L= Low logic level).
“System Bus” refers to the interface between the processor and system core logic (also known as
the chipset components). The system bus is a multiprocessing interface to processors, memory, and
I/O.
1.1.1
Terminology
Commonly used terms are explained here for clarification:
• Processor — For this document, the term processor shall mean the Mobile Intel Celeron
Processor in the 478-pin package.
• Keep out zone — The area on or near the processor that system design can not utilize.
• Intel 845MP/845MZ chipsets — Mobile chipsets that will support the Mobile Intel
Celeron Processor.
• Processor core — Mobile Intel Celeron Processor core die with integrated L2 cache.
• Micro-FCPGA package — Micro Flip-Chip Pin Grid Array package with 50-mil pin pitch.
10
251308-002
Datasheet
Introduction
1.2
References
Material and concepts available in the following documents may be beneficial when reading this
document.
Table 1. References
Document
Order Number
250688-002
Mobile Intel Pentium 4 Processor-M and Intel 845MP/845MZ Chipset
Platform Design Guide
Intel Architecture Software Developer's Manual
Volume I: Basic Architecture
245470
245471
245472
Volume II: Instruction Set Reference
Volume III: System Programming Guide
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Introduction
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Electrical Specifications
2 Electrical Specifications
2.1
System Bus and GTLREF
Most Mobile Intel Celeron Processor system bus signals use Assisted Gunning Transceiver Logic
(AGTL+) signalling technology. As with the Intel P6 family of microprocessors, this signalling
technology provides improved noise margins and reduced ringing through low-voltage swings and
controlled edge rates. The termination voltage level for the Mobile Intel Celeron Processor AGTL+
signals is VCC, which is the operating voltage of the processor core. Previous generations of Intel
mobile processors utilize a fixed termination voltage known as VCCT. The use of a termination
voltage that is determined by the processor core allows better voltage scaling on the system bus for
Mobile Intel Celeron Processor. Because of the speed improvements to data and address bus, signal
integrity and platform design methods have become more critical than with previous processor
families. Design guidelines for the Mobile Intel Celeron Processor system bus will be detailed in
the Mobile Intel Pentium 4 Processor-M and Intel 845MP/845MZ Chipset Platform Design
Guide.
The AGTL+ inputs require a reference voltage (GTLREF) which is used by the receivers to
determine if a signal is a logical 0 or a logical 1. GTLREF must be generated on the system board.
Termination resistors are provided on the processor silicon and are terminated to its core voltage
(VCC). Intel’s 845MP/845MZ chipsets will also provide on-die termination, thus eliminating the
need to terminate the bus on the system board for most AGTL+ signals. However, some AGTL+
signals do not include on-die termination and must be terminated on the system board. For more
information, refer to the Mobile Intel Pentium 4 Processor-M and Intel 845MP/845MZ
Chipset Platform Design Guide.
The AGTL+ bus depends on incident wave switching. Therefore, timing calculations for AGTL+
signals are based on flight time as opposed to capacitive deratings. Analog signal simulation of the
system bus, including trace lengths, is highly recommended when designing a system.
2.2
2.3
Power and Ground Pins
For clean on-chip power distribution, the Mobile Intel Celeron Processor have 85 VCC (power) and
181 VSS (ground) inputs. All power pins must be connected to VCC, while all VSS pins must be
connected to a system ground plane.The processor VCC pins must be supplied with the voltage
determined by the VID (Voltage ID) pins and the loadline specifications (see Figure 4 to Figure 5).
Decoupling Guidelines
Due to its large number of transistors and high internal clock speeds, the processor is capable of
generating large average current swings between low and full power states. This may cause
voltages on power planes to sag below their minimum values if bulk decoupling is not adequate.
Care must be taken in the board design to ensure that the voltage provided to the processor remains
within the specifications listed in Table 7. Failure to do so can result in timing violations and affect
251308-002
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Datasheet
Electrical Specifications
the long term reliability of the processor. For further information and design guidelines, refer to the
Mobile Intel Pentium 4 Processor-M and Intel 845MP/845MZ Chipset Platform Design
Guide.
2.3.1
V
Decoupling
CC
Regulator solutions need to provide bulk capacitance with a low Effective Series Resistance (ESR)
and keep a low interconnect resistance from the regulator to the socket. Bulk decoupling for the
large current swings when the part is powering on, or entering/exiting low-power states, must be
provided by the voltage regulator solution. For more details on decoupling recommendations,
please refer to the Mobile Intel Pentium 4 Processor-M and Intel 845MP/845MZ Chipset
Platform Design Guide.
2.3.2
2.3.3
System Bus AGTL+ Decoupling
The Mobile Intel Celeron Processor integrates signal termination on the die and incorporates high
frequency decoupling capacitance on the processor package. Decoupling must also be provided by
the system motherboard for proper AGTL+ bus operation. For more information, refer to the
Mobile Intel Pentium 4 Processor-M and Intel 845MP/845MZ Chipset Platform Design
Guide.
System Bus Clock (BCLK[1:0]) and Processor Clocking
BCLK[1:0] directly controls the system bus interface speed as well as the core frequency of the
processor. As in previous generation processors, the Mobile Intel Celeron Processor core frequency
is a multiple of the BCLK[1:0] frequency. Refer to Table 2 for the Mobile Intel Celeron Processor
supported ratios.
Table 2. Core Frequency to System Bus Multipliers
Multiplication of System Core
Frequency to System Bus Frequency
2
Core Frequency
Notes
800 MHz
1.20 GHz
1.40 GHz
1.50 GHz
1.60 GHz
1.70 GHz
1.80 GHz
1/8
1
1/12
1/14
1/15
1/16
1/17
1/18
NOTES:
1. Ratio is used for debug purposes only.
2. Listed frequencies are not necessarily committed production frequencies.
The Mobile Intel Celeron Processor uses a differential clocking implementation.
251308-002
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Datasheet
Electrical Specifications
2.4
Voltage Identification and Power Sequencing
The voltage set by the VID pins is the nominal/typical voltage setting for the processor. A
minimum voltage is provided in Table 7 and changes with frequency. This allows processors
running at a higher frequency to have a relaxed minimum voltage specification. The specifications
have been set such that one voltage regulator can work with all supported frequencies.
The Mobile Intel Celeron Processor uses five voltage identification pins, VID[4:0], to support
automatic selection of power supply voltages. The VID pins for the Mobile Intel Celeron Processor
are open drain outputs driven by the processor VID circuitry. Table 3 specifies the voltage level
corresponding to the state of VID[4:0]. A “1” in this table refers to a high-voltage level and a “0”
refers to low-voltage level.
Power source characteristics must be stable whenever the supply to the voltage regulator is stable.
Refer to Figure 15 for timing details of the power up sequence. Also refer to Mobile Intel
Pentium 4 Processor-M and Intel 845MP/845MZ Chipset Platform Design Guide for
implementation details.
Mobile Intel Celeron Processor’s Voltage Identification circuit requires an independent 1.2 V
supply. This voltage must be routed to the processor VCCVID pin. Figure 1 shows the voltage and
current requirements of the VCCVID pin.
Figure 1. VCCVID Pin Voltage and Current Requirements
1.2V+10%
1.2V-5%
1V
150mA to 300mA
80mA
30mA
1mA
70nS
5nS
Table 3. Voltage Identification Definition (Sheet 1 of 2)
Processor Pins
VID4
VID3
VID2
VID1
VID0
VCC_
1
1
1
1
1
0.600
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Datasheet
Electrical Specifications
Table 3. Voltage Identification Definition (Sheet 2 of 2)
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
0.625
0.650
0.675
0.700
0.725
0.750
0.775
0.800
0.825
0.850
0.875
0.900
0.925
0.950
0.975
1.000
1.050
1.100
1.150
1.200
1.250
1.300
1.350
1.400
1.450
1.500
1.550
1.600
1.650
1.700
1.750
2.4.1
Phase Lock Loop (PLL) Power and Filter
VCCA and VCCIOPLL are power sources required by the PLL clock generators on the Mobile Intel
Celeron Processor silicon. Since these PLLs are analog in nature, they require quiet power supplies
for minimum jitter. Jitter is detrimental to the system: it degrades external I/O timings as well as
internal core timings (i.e. maximum frequency). To prevent this degradation, these supplies must
be low pass filtered from VCCVID. A typical filter topology is shown in Figure 2.
The AC low-pass requirements, with input at VCCVID and output measured across the capacitor
(CA or CIO in Figure 2), is as follows:
• < 0.2 dB gain in pass band
• < 0.5 dB attenuation in pass band < 1 Hz
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Datasheet
Electrical Specifications
• > 34 dB attenuation from 1 MHz to 66 MHz
• > 28 dB attenuation from 66 MHz to core frequency
The filter requirements are illustrated in Figure 3. For recommendations on implementing the filter
refer to the Mobile Intel Pentium 4 Processor-M and Intel 845MP/845MZ Chipset Platform
Design Guide.
Figure 2. Typical VCCIOPLL, VCCA and VSSA Power Distribution
VCCVID
L
VCCA
CA
PLL
Processor
Core
VSSA
CIO
VCCIOPLL
L
.
Figure 3. Phase Lock Loop (PLL) Filter Requirements
0.2 dB
0 dB
-0.5 dB
forbidden
zone
-28 dB
forbidden
zone
-34 dB
DC
passband
1 Hz
fpeak
1 MHz
66 MHz
fcore
high frequency
band
NOTES:
1. Diagram not to scale.
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Datasheet
Electrical Specifications
1. No specification for frequencies beyond fcore (core frequency).
1. fpeak, if existent, should be less than 0.05 MHz.
2.4.2
Catastrophic Thermal Protection
The Mobile Intel Celeron Processor supports the THERMTRIP# signal for catastrophic thermal
protection. Alternatively, an external thermal sensor can be used to protect the processor and the
system against excessive temperatures. Even with the activation of THERMTRIP#, which halts all
processor internal clocks and activity, leakage current can be high enough such that the processor
cannot be protected in all conditions without the removal of power to the processor. If the external
thermal sensor detects a catastrophic processor temperature of 135°C (maximum), or if the
THERMTRIP# signal is asserted, the VCC supply to the processor must be turned off within
500 ms to prevent permanent silicon damage due to thermal runaway of the processor. Refer to
Section 5.2 for more details on THERMTRIP#.
2.5
Signal Terminations, Unused Pins and TESTHI[11:0]
All NC pins must remain unconnected. Connection of these pins to VCC, VSS, or to any other signal
(including each other) can result in component malfunction or incompatibility with future Mobile
Intel Celeron Processors. See Section 5.2 for a processor pin listing and the location of all NC pins.
For reliable operation, always connect unused inputs or bidirectional signals that are not terminated
on the die to an appropriate signal level. Note that on-die termination has been included on the
Mobile Intel Celeron Processor to allow signals to be terminated within the processor silicon.
Unused active low AGTL+ inputs may be left as no connects if AGTL+ termination is provided on
the processor silicon. Table 4 lists details on AGTL+ signals that do not include on-die termination.
Unused active high inputs should be connected through a resistor to ground (VSS). Refer to the
Mobile Intel Pentium 4 Processor-M and Intel 845MP/845MZ Chipset Platform Design Guide
for the appropriate resistor values.
Unused outputs can be left unconnected, however, this may interfere with some TAP functions,
complicate debug probing, and prevent boundary scan testing. A resistor must be used when tying
bidirectional signals to power or ground. When tying any signal to power or ground, a resistor will
also allow for system testability. For unused AGTL+ input or I/O signals that don’t have on-die
termination, use pull-up resistors of the same value in place of the on-die termination resistors
(RTT). See Table 16.
The TAP, Asynchronous GTL+ inputs, and Asynchronous GTL+ outputs do not include on-die
termination. Inputs and used outputs must be terminated on the system board. Unused outputs may
be terminated on the system board or left unconnected. Note that leaving unused outputs
unterminated may interfere with some TAP functions, complicate debug probing, and prevent
boundary scan testing. Signal termination for these signal types is discussed in the Mobile Intel
Pentium 4 Processor-M and Intel 845MP/845MZ Chipset Platform Design Guide.
The TESTHI pins should be tied to the processor VCC using a matched resistor, where a matched
resistor has a resistance value within + 20% of the impedance of the board transmission line traces.
For example, if the trace impedance is 50 Ω, then a value between 40 Ω and 60 Ω is required.
The TESTHI pins may use individual pull-up resistors or be grouped together as detailed below. A
matched resistor should be used for each group:
1.TESTHI[1:0]
2.TESTHI[5:2]
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3.TESTHI[10:8]
4.TESTHI[11]
Additionally, if the ITPCLKOUT[1:0] pins are not used then they may be connected individually to
VCC using matched resistors or grouped with TESTHI[5:2] with a single matched resistor. If they
are being used, individual termination with 1-kΩ resistors is required. Tying ITPCLKOUT[1:0]
directly to VCC or sharing a pull-up resistor to VCC will prevent use of debug interposers. This
implementation is strongly discouraged for system boards that do not implement an onboard debug
port.
As an alternative, group 2 (TESTHI[5:2]), and the ITPCLKOUT[1:0] pins may be tied directly to
the processor VCC. This has no impact on system functionality. TESTHI[0] may also be tied
directly to processor VCC if resistor termination is a problem, but matched resistor termination is
recommended. In the case of the ITPCLKOUT[1:0] pins, direct tie to VCC is strongly discouraged
for system boards that do not implement an onboard debug port.
Tying any of the TESTHI pins together will prevent the ability to perform boundary scan testing.
Pullup/down resistor requirements for the VID[4:0] and BSEL[1:0] signals are included in the
signal descriptions in Section 5.
2.6
System Bus Signal Groups
In order to simplify the following discussion, the system bus signals have been combined into
groups by buffer type. AGTL+ input signals have differential input buffers, which use GTLREF as
a reference level. In this document, the term "AGTL+ Input" refers to the AGTL+ input group as
well as the AGTL+ I/O group when receiving. Similarly, "AGTL+ Output" refers to the AGTL+
output group as well as the AGTL+ I/O group when driving.
With the implementation of a source synchronous data bus comes the need to specify two sets of
timing parameters. One set is for common clock signals which are dependant upon the rising edge
of BCLK0 (ADS#, HIT#, HITM#, etc.) and the second set is for the source synchronous signals
which are relative to their respective strobe lines (data and address) as well as the rising edge of
BCLK0. Asychronous signals are still present (A20M#, IGNNE#, etc.) and can become active at
any time during the clock cycle. Table 4 identifies which signals are common clock, source
synchronous, and asynchronous.
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Table 4. System Bus Pin Groups
1
Signal Group
Type
Signals
Common
clock
2
AGTL+ Common Clock Input
AGTL+ Common Clock I/O
BPRI#, DEFER#, RESET# , RS[2:0]#, RSP#, TRDY#
2
2
AP[1:0]#, ADS#, BINIT#, BNR#, BPM[5:0]# , BR0# ,
DBSY#, DP[3:0]#, DRDY#, HIT#, HITM#, LOCK#,
MCERR#
Synchronous
Signals
Associated Strobe
5
REQ[4:0]#, A[16:3]#
ADSTB0#
5
A[35:17]#
ADSTB1#
AGTL+ Source Synchronous
I/O
Source
Synchronous
D[15:0]#, DBI0#
D[31:16]#, DBI1#
D[47:32]#, DBI2#
D[63:48]#, DBI3#
DSTBP0#, DSTBN0#
DSTBP1#, DSTBN1#
DSTBP2#, DSTBN2#
DSTBP3#, DSTBN3#
Common
Clock
AGTL+ Strobes
ADSTB[1:0]#, DSTBP[3:0]#, DSTBN[3:0]#
5
A20M#, DPSLP#, IGNNE#, INIT# , LINT0/INTR, LINT1/
NMI, SMI# , SLP#, STPCLK#
4,5
Asynchronous GTL+ Input
Asynchronous
5
4
2
Asynchronous GTL+ Output
Asynchronous FERR#/PBE#, IERR# , THERMTRIP#, PROCHOT#
Synchronous
4
TAP Input
TCK, TDI, TMS, TRST#
to TCK
Synchronous
TDO
4
TAP Output
to TCK
3
System Bus Clock
Power/Other
N/A
BCLK[1:0], ITP_CLK[1:0]
VCC, VCCA, VCCIOPLL, VCCVID, VID[4:0], VSS, VSSA
GTLREF[3:0], COMP[1:0], NC, TESTHI[5:0],
TESTHI[10:8], TESTHI[11], ITPCLKOUT[1:0],
,
N/A
PWRGOOD, THERMDA, THERMDC, SKTOCC#,
3
V
, V
BSEL[1:0], DBR#
CC_SENSE
SS_SENSE,
NOTES:
1. Refer to Section 5.2 for signal descriptions.
2. These AGTL+ signals do not have on-die termination. Refer to Section 2.5 for termination requirements.
3. In processor systems where there is no debug port implemented on the system board, these signals are used
to support a debug port interposer. In systems with the debug port implemented on the system board, these
signals are no connects.
4. These signal groups are not terminated by the processor. Signals not driven by the ICH3-M component must
be terminated on the system board. Refer to Section 2.5 and the Mobile Intel Pentium 4 Processor-M and
Intel 845MP/845MZ Chipset Platform Design Guide for termination requirements and further details.
5. The value of these pins during the active-to-inactive edge of RESET# defines the processor configuration
options. See Section 7.1 for details.
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2.7
Asynchronous GTL+ Signals
Mobile Intel Celeron Processor does not utilize CMOS voltage levels on any signals that connect to
the processor. As a result, legacy input signals such as A20M#, IGNNE#, INIT#, LINT0/INTR,
LINT1/NMI, SMI#, SLP#, and STPCLK# use GTL+ input buffers. Legacy output FERR#/PBE#
and other non-AGTL+ signals (THERMTRIP# and PROCHOT#) use GTL+ output buffers. All of
these signals follow the same DC requirements as AGTL+ signals, however the outputs are not
actively driven high (during a logical 0 to 1 transition) by the processor (the major difference
between GTL+ and AGTL+). These signals do not have setup or hold time specifications in relation
to BCLK[1:0]. However, all of the Asynchronous GTL+ signals are required to be asserted for at
least two BCLKs in order for the processor to recognize them. See Section 2.11 and Section 2.13
for the DC and AC specifications for the Asynchronous GTL+ signal groups.
2.8
2.9
Test Access Port (TAP) Connection
Due to the voltage levels supported by other components in the Test Access Port (TAP) logic, it is
recommended that the Mobile Intel Celeron Processor be first in the TAP chain and followed by
any other components within the system. A translation buffer should be used to connect to the rest
of the chain unless one of the other components is capable of accepting an input of the appropriate
voltage level. Similar considerations must be made for TCK, TMS, and TRST#. Two copies of
each signal may be required, with each driving a different voltage level.
System Bus Frequency Select Signals (BSEL[1:0])
The BSEL[1:0] are output signals used to select the frequency of the processor input clock
(BCLK[1:0]). Table 5 defines the possible combinations of the signals and the frequency
associated with each combination. The required frequency is determined by the processor, chipset,
and clock synthesizer. All agents must operate at the same frequency.
The Mobile Intel Celeron Processor currently operates at a 400-MHz system bus frequency
(selected by a 100-MHz BCLK[1:0] frequency). Individual processors will only operate at their
specified system bus frequency.
For more information about these pins refer to Section 5.2 and the appropriate platform design
guidelines.
Table 5. BSEL[1:0] Frequency Table for BCLK[1:0]
BSEL1
BSEL0
Function
L
L
L
H
L
100 MHz
RESERVED
RESERVED
RESERVED
H
H
H
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2.10
Maximum Ratings
Table 6 lists the processor’s maximum environmental stress ratings. The processor should not
receive a clock while subjected to these conditions. Functional operating parameters are listed in
the AC and DC tables. Extended exposure to the maximum ratings may affect device reliability.
Furthermore, although the processor contains protective circuitry to resist damage from Electro
Static Discharge (ESD), one should always take precautions to avoid high static voltages or electric
fields.
Table 6. Processor DC Absolute Maximum Ratings
Symbol
Parameter
Min
Max
Unit
Notes
TSTORAGE
Processor storage temperature
–40
85
°C
2
Any processor supply voltage with respect to
V
V
V
-0.3
-0.1
-0.1
1.75
1.75
V
V
1
CC
V
SS
AGTL+ buffer DC input voltage with respect to
VSS
inAGTL+
inAsynch_GTL+
Asynch GTL+ buffer DC input voltage with
respect to VSS
1.75
5
V
IVID
Max VID pin current
mA
NOTES:
1. This rating applies to any processor pin.
2. Contact Intel for storage requirements in excess of one year.
2.11
Processor DC Specifications
The processor DC specifications in this section are defined at the processor core (pads) unless
noted otherwise. See Section 5 for the pin signal definitions and signal pin assignments. Most of
the signals on the processor system bus are in the AGTL+ signal group. The DC specifications for
these signals are listed in Table 11.
Previously, legacy signals and Test Access Port (TAP) signals to the processor used low-voltage
CMOS buffer types. However, these interfaces now follow DC specifications similar to GTL+. The
DC specifications for these signal groups are listed in Table 12 and Table 13.
Table 7 through Table 15 list the DC specifications for the Mobile Intel Celeron Processor and are
valid only while meeting specifications for junction temperature, clock frequency, and input
voltages. Unless specified otherwise, all specifications for the Mobile Intel Celeron Processor are
at TJ = 100°C. Care should be taken to read all notes associated with each parameter.
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Table 7. Voltage and Current Specifications
1
Symbol
Parameter
for core logic
Min
Typ
Max
Unit
Notes
V
V
CC
CC
V
V
2, 3, 4, 5, 7, 8,11
2, 12
1.30
1.20
VCCVID
VID supply voltage
-5%
+10%
Current for V at core frequency
CC
1.80 GHz & 1.30 V
1.70 GHz & 1.30 V
1.60 GHz & 1.30 V
1.50 GHz & 1.30 V
1.40 GHz & 1.30 V
31.0
29.9
28.7
27.5
26.3
A
4, 5, 8, 9
I
CC
I
I
Current for VID supply
300
mA
A
VCCVID
I
Stop-Grant and I Sleep at
CC
CC
SGNT, I
SLP
1.30 V
Deep Sleep at
10.1
9.0
6, 9
I
CC
I
DSLP
1.30 V
A
A
9
I
I
I
I
TCC active
for PLL pins
I
CC
8
TCC
CC
CC
60
mA
10
CC PLL
NOTES:
1. Unless otherwise noted, all specifications in this table are based on latest post-silicon measurements
available at the time of publication.
2. These voltages are targets only. A variable voltage source should exist on systems in the event that a
different voltage is required. See Section 2.4 and Table 3 for more information. The VID bits will set the
typical V with the minimum being defined according to current consumption at that voltage.
CC
3. The voltage specification requirements are measured at the system board socket ball with a 100-MHz
bandwidth oscilloscope, 1.5-pF maximum probe capacitance, and 1-MΩ minimum impedance. The maximum
length of ground wire on the probe should be less than 5 mm. Ensure external noise from the system is not
coupled in the scope probe.
4. Refer to Table 8 to Table 9 and Figure 4 to Figure 5 for the minimum, typical, and maximum V (measured
CC
at the system board socket ball) allowed for a given current. The processor should not be subjected to any
V
and I combination wherein V exceeds V
for a given current. Failure to adhere to this
CC
CC
CC
CC_MAX
specification can affect the long term reliability of the processor.
5. V is defined at I
.
CC_MAX
CC_MIN
6. The current specified is also for AutoHALT State.
7. Typical V indicates the VID encoded voltage. Voltage supplied must conform to the load line specification
CC
shown in Table 8 to Table 9.
8. The maximum instantaneous current the processor will draw while the thermal control circuit is active as
indicated by the assertion of PROCHOT# is the same as the maximum I for the processor.
CC
9. Maximum specifications for I Core, I Stop-Grant, I Sleep, and I Deep Sleep are specified at V
CC
CC
CC
CC
CC
Static Max. derived from the tolerances in Table 8 through Table 9, T Max., and under maximum signal
J
loading conditions.
10.The specification is defined per PLL pin.
11.The voltage response to a processor current load step (transient) must stay within the Transient Voltage
Tolerance Window. The voltage surge or droop response measured in this window is typically on the order of
several hundred nanoseconds to several microseconds. The Transient Voltage Tolerance Window is defined
as follows:
Case a) Load Current Step Up: e.g., from Icc = I_leakage to Icc = Icc_max. Allowable Vcc_min is defined as
minimum transient voltage at Icc = Icc_max for a period of time lasting several hundred nanoseconds to
several microseconds after the transient event.
Case b) Load Current Step Down: e.g., form Icc = Icc_max to Icc = I_leakage. Allowable Vcc_max is defined
as the maximum transient voltage at Icc = I_leakage for a period of time lasting several hundred
nanoseconds to several microseconds after the transient event.
12.This specification applies to both static and transient components. The rising edge of VCCVID must be
monotonic from 0 to 1.1 V. See Figure 1 for current requirements. In this case, monotonic is defined as
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Electrical Specifications
continuously increasing with less than 50 mV of peak to peak noise for any width greater than 2 nS
superimposed on the rising edge.
Table 8. IMVP-III Voltage Regulator Tolerances for VID = 1.30 V Operating Mode
V
Nominal
(V)
V
Static Min
(V)
V
Static Max
(V)
V
Transient
Min (V)
V
Transient
Max (V)
CC
CC
CC
CC
CC
I
(A)
CC
0.0
1.300
1.298
1.296
1.294
1.292
1.290
1.288
1.286
1.284
1.282
1.280
1.278
1.276
1.274
1.272
1.270
1.268
1.266
1.264
1.262
1.260
1.258
1.256
1.254
1.252
1.250
1.248
1.246
1.244
1.242
1.240
1.238
1.236
1.234
1.232
1.275
1.273
1.271
1.269
1.267
1.265
1.263
1.261
1.259
1.257
1.255
1.253
1.251
1.249
1.247
1.245
1.243
1.241
1.239
1.237
1.235
1.233
1.231
1.229
1.227
1.225
1.223
1.221
1.219
1.217
1.215
1.213
1.211
1.209
1.207
1.325
1.323
1.321
1.319
1.317
1.315
1.313
1.311
1.309
1.307
1.305
1.303
1.301
1.299
1.297
1.295
1.293
1.291
1.289
1.287
1.285
1.283
1.281
1.279
1.277
1.275
1.273
1.271
1.269
1.267
1.265
1.263
1.261
1.259
1.257
1.255
1.253
1.251
1.249
1.247
1.245
1.243
1.241
1.239
1.237
1.235
1.233
1.231
1.229
1.227
1.225
1.223
1.221
1.219
1.217
1.215
1.213
1.211
1.209
1.207
1.205
1.203
1.201
1.199
1.197
1.195
1.193
1.191
1.189
1.187
1.345
1.343
1.341
1.339
1.337
1.335
1.333
1.331
1.329
1.327
1.325
1.323
1.321
1.319
1.317
1.315
1.313
1.311
1.309
1.307
1.305
1.303
1.301
1.299
1.297
1.295
1.293
1.291
1.289
1.287
1.285
1.283
1.281
1.279
1.277
1.0
2.0
3.0
4.0
5.0
6.0
7.0
8.0
9.0
10.0
11.0
12.0
13.0
14.0
15.0
16.0
17.0
18.0
19.0
20.0
21.0
22.0
23.0
24.0
25.0
26.0
27.0
28.0
29.0
30.0
31.0
32.0
33.0
34.0
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Table 8. IMVP-III Voltage Regulator Tolerances for VID = 1.30 V Operating Mode
V
Nominal
(V)
V
Static Min
(V)
V
Static Max
(V)
V
Transient
Min (V)
V
Transient
Max (V)
CC
CC
CC
CC
CC
I
(A)
CC
35.0
36.0
37.0
38.0
39.0
40.0
1.230
1.228
1.226
1.224
1.222
1.220
1.205
1.203
1.201
1.199
1.197
1.195
1.255
1.253
1.251
1.249
1.247
1.245
1.185
1.183
1.181
1.179
1.177
1.175
1.275
1.273
1.271
1.269
1.267
1.265
Figure 4. Illustration of VCC Static and Transient Tolerances (VID = 1.30 V)
1.400
Vcc Transient Maximum
Vcc Static Maximum
1.350
1.300
1.250
1.200
1.150
1.100
1.050
Vcc Nominal
Vcc Static Minimum
Vcc Transient Minimum
0
2
4
6
8
10 12 14 16 18 20 22 24 26 28 30 32 34 36 38 40
Icc Maximum (A)
Table 9. IMVP-III Deep Sleep State Voltage Regulator Tolerances (VID = 1.30 V, VID Offset =
4.62%)
V
Nominal
(V)
V
Static Min
(V)
V
Static Max
(V)
V
Transient
Min (V)
V
Transient
Max (V)
CC
CC
CC
CC
CC
I
(A)
CC
0.0
1.240
1.238
1.236
1.234
1.232
1.230
1.228
1.226
1.215
1.213
1.211
1.209
1.207
1.205
1.203
1.201
1.265
1.263
1.261
1.259
1.257
1.255
1.253
1.251
1.195
1.193
1.191
1.189
1.187
1.185
1.183
1.181
1.285
1.283
1.281
1.279
1.277
1.275
1.273
1.271
1.0
2.0
3.0
4.0
5.0
6.0
7.0
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Table 9. IMVP-III Deep Sleep State Voltage Regulator Tolerances (VID = 1.30 V, VID Offset =
4.62%)
V
Nominal
(V)
V
Static Min
(V)
V
Static Max
(V)
V
Transient
Min (V)
V
Transient
Max (V)
CC
CC
CC
CC
CC
I
(A)
CC
8.0
1.224
1.222
1.220
1.199
1.197
1.195
1.249
1.247
1.245
1.179
1.177
1.175
1.269
1.267
1.265
9.0
10.0
Figure 5. Illustration of Deep Sleep VCC Static and Transient Tolerances (VID Setting = 1.30 V)
1.300
Vcc Transient Maximum
1.280
Vcc Static Maximum
1.260
1.240
1.220
1.200
1.180
1.160
1.140
1.120
Vcc Nominal
Vcc Static Minimum
Vcc Transient Minimum
0
1
2
3
4
5
6
7
8
9
10
11
Isb Maximum (A)
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Table 10. System Bus Differential BCLK Specifications
1
Symbol
Parameter
Min
Typ
Max
Unit Figure Notes
Input Low
Voltage
V
-0.150
0.000
N/A
V
V
V
9
9
L
Input High
Voltage
V
0.660
0.710
N/A
0.850
H
Absolute
Crossing Point
V
0.250
0.550
9, 10
2,3,8
2,3,8,9
2,10
CROSS(abs)
0.250 +
0.550 +
Relative
Crossing Point
V
N/A
N/A
V
V
9, 10
9, 10
CROSS(rel)
0.5(V
- 0.710)
0.5(V
- 0.710)
Havg
Havg
Range of
Crossing Points
∆V
N/A
0.140
CROSS
V
Overshoot
N/A
N/A
N/A
V
+ 0.3
H
V
V
9
9
4
5
OV
US
V
Undershoot
-0.300
N/A
N/A
+ 0.100
Ringback
Margin
V
0.200
N/A
N/A
V
V
9
9
6
7
RBM
Threshold
Margin
VTM
V
- 0.100
V
CROSS
CROSS
NOTES:
1. Unless otherwise noted, all specifications in this table apply to all processor frequencies.
2. Crossing voltage is defined as the instantaneous voltage value when the rising edge of BCLK0 equals the
falling edge of BCLK1.
3. V
is the statistical average of the V measured by the oscilloscope.
Havg
H
4. Overshoot is defined as the absolute value of the maximum voltage.
5. Undershoot is defined as the absolute value of the minimum voltage.
6. Ringback Margin is defined as the absolute voltage difference between the maximum Rising Edge Ringback
and the maximum Falling Edge Ringback.
7. Threshold Region is defined as a region entered around the crossing point voltage in which the differential
receiver switches. It includes input threshold hysteresis.
8. The crossing point must meet the absolute and relative crossing point specifications simultaneously.
9. V
can be measured directly using "Vtop" on Agilent* scopes and "High" on Tektronix* scopes.
Havg
10.∆V
is defined as the total variation of all crossing voltages as defined in note 2.
CROSS
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Table 11. AGTL+ Signal Group DC Specifications
1
Symbol
Parameter
Min
Max
Unit Notes
GTLREF
VIH
Reference Voltage
Input High Voltage
Input Low Voltage
Output High Voltage
Output Low Current
Pin Leakage High
Pin Leakage Low
2/3 Vcc - 2%
2/3 Vcc + 2%
V
1.10*GTLREF
VCC
V
V
2,6
VIL
0.0
N/A
N/A
N/A
N/A
7
0.9*GTLREF
3,4,6
VOH
IOL
Vcc
50
V
7
6
8
9
5
mA
µA
µA
Ω
IHI
100
500
11
ILO
RON
Buffer On Resistance
NOTES:
1. Unless otherwise noted, all specifications in this table apply to all processor frequencies.
2. VIL is defined as the maximum voltage level at a receiving agent that will be interpreted as a logical low value.
3. VIH is defined as the minimum voltage level at a receiving agent that will be interpreted as a logical high
value.
4. VIH and VOH may experience excursions above V . However, input signal drivers must comply with the
CC
signal quality specifications in Section 3.
5. Refer to processor I/O Buffer Models for I/V characteristics.
6. The V referred to in these specifications is the instantaneous V
.
CC
CC
7. Vol max of 0.450 Volts is guaranteed when driving into a test load of 50 Ω as indicated in Figure 7.
8. Leakage to V with pin held at V
.
CC
SS
9. Leakage to V with pin held at 300 mV.
CC
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Table 12. Asynchronous GTL+ Signal Group DC Specifications
1
Symbol
Parameter
Min
Max
Unit Notes
Input High Voltage
Asynch GTL+
1.10*GTLREF
VCC
VIH
V
V
3, 4, 5
5
Input Low Voltage
Asynch. GTL+
VIL
0
0.9*GTLREF
VOH
IOL
Output High Voltage
Output Low Current
Pin Leakage High
Pin Leakage Low
N/A
N/A
N/A
N/A
VCC
50
V
2, 3, 4
6, 8
9
mA
µA
µA
I
100
500
HI
I
10
LO
Buffer On Resistance
Asynch GTL+
Ron
7
11
Ω
5, 7
NOTES:
1. Unless otherwise noted, all specifications in this table apply to all processor frequencies.
2. All outputs are open-drain.
3. V and V
may experience excursions above V . However, input signal drivers must comply with the
IH
OH
CC
signal quality specifications in Chapter 3.0.
4. The V referred to in these specifications refers to instantaneous V
.
CC
CC
5. This specification applies to the asynchronous GTL+ signal group.
6. The maximum output current is based on maximum current handling capability of the buffer and is not
specified into the test load shown in Figure 7.
7. Refer to the processor I/O Buffer Models for I/V characteristics.
8. Vol max of 0.270 Volts is guaranteed when driving into a test load of 50 Ω as indicated in Figure 7 for the
Asynchronous GTL+ signals.
9. Leakage to V with pin held at V
.
SS
CC
10. Leakage to V with pin held at 300 mV.
CC
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Table 13. PWRGOOD and TAP Signal Group DC Specifications
1
Symbol
Parameter
Min
Max
Unit Notes
VHYS
Input Hysteresis
200
300
mV
V
8
5
Input Low to High
Threshold Voltage
VT+
VT-
1/2*(Vcc+VHYS_MIN)
1/2*(Vcc-VHYS_MAX)
1/2*(Vcc+VHYS_MAX)
Input High to Low
Threshold Voltage
1/2*(Vcc-VHYS_MIN)
V
5
VOH
IOL
Output High Voltage
Output Low Current
Pin Leakage High
Pin Leakage Low
N/A
N/A
N/A
N/A
8.75
VCC
40
V
mA
µA
µA
Ω
2,3,5
6,7
9
I
100
500
13.75
HI
I
10
4
LO
Ron
Buffer On Resistance
NOTES:
1. Unless otherwise noted, all specifications in this table apply to all processor frequencies.
2. All outputs are open-drain.
3. TAP signal group must comply with the signal quality specifications in Section 3.
4. Refer to I/O Buffer Models for I/V characteristics.
5. The V referred to in these specifications refers to instantaneous V
.
CC
CC
6. The maximum output current is based on maximum current handling capability of the buffer and is not
specified into the test load shown if Figure 7.
7. Vol max of 0.320 Volts is guaranteed when driving into a test load of 50 Ohms as indicated in Figure 7 for the
TAP Signals.
8. VHYS represents the amount of hysteresis, nominally centered about 1/2 Vcc for all TAP inputs.
9. Leakage to V with pin held at V
.
SS
CC
10.Leakage to V with pin held at 300 mV.
CC
Table 14. ITPCLKOUT[1:0] DC Specifications
1
Symbol
Parameter
Min
Max
Unit
Notes
Ron
Buffer On Resistance
27
46
Ω
2,3
NOTES:
1. Unless otherwise noted, all specifications in this table apply to all processor frequencies.
2. These parameters are not tested and are based on design simulations.
3. See Figure 6 for ITPCLKOUT[1:0] output buffer diagram.
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Figure 6. ITPCLKOUT[1:0] Output Buffer Diagram
Vcc
Ron
To Debug Port
Processor Package
Rext
NOTES:
1. See Table 14 for range of Ron.
2. The Vcc referred to in this figure is the instantaneous Vcc.
3. Refer to the appropriate platform design guidelines for the value of Rext.
Table 15. BSEL [1:0] and VID[4:0] DC Specifications
1
Symbol
Parameter
Min
Max
Unit
Notes
Ron
(BSEL)
Buffer On Resistance
9.2
14.3
Ω
2
Ron
(VID)
Buffer On Resistance
Pin Leakage Hi
7.8
12.8
100
Ω
2
3
I
N/A
µA
HI
NOTES:
1. Unless otherwise noted, all specifications in this table apply to all processor frequencies.
2. These parameters are not tested and are based on design simulations.
3. Leakage to Vss with pin held at 2.50 V.
2.12
AGTL+ System Bus Specifications
Routing topology recommendations may be found in the Mobile Intel Pentium 4 Processor-M
and Intel 845MP/845MZ Chipset Platform Design Guide. Termination resistors are not required
for most AGTL+ signals, as these are integrated into the processor silicon.
Valid high and low levels are determined by the input buffers that compare a signal’s voltage with a
reference voltage called GTLREF (known as VREF in previous documentation).
Table 16 lists the GTLREF specifications. The AGTL+ reference voltage (GTLREF) should be
generated on the system board using high precision voltage divider circuits. It is important that the
system board impedance is held to the specified tolerance, and that the intrinsic trace capacitance
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Electrical Specifications
for the AGTL+ signal group traces is known and well-controlled. For more details on platform
design see the Mobile Intel Pentium 4 Processor-M and Intel 845MP/845MZ Chipset Platform
Design Guide.
Table 16. AGTL+ Bus Voltage Definitions
1
Symbol
Parameter
Min
Typ
Max
Units
Notes
Bus Reference
Voltage
GTLREF
2/3 V -2%
2/3 V
2/3 V +2%
V
2, 3, 6
CC
CC
CC
Termination
Resistance
RTT
45
50
55
Ω
Ω
4
5
COMP
Resistance
COMP[1:0]
50.49
51
51.51
NOTES:
1. Unless otherwise noted, all specifications in this table apply to all processor frequencies.
1. The tolerances for this specification have been stated generically to enable the system designer to calculate
the minimum and maximum values across the range of V
.
CC
1. GTLREF should be generated from V by a voltage divider of 1% tolerance resistors or 1% tolerance
CC
matched resistors. Refer to the Mobile Intel Pentium 4 Processor-M and Intel 845MP/845MZ Chipset
Platform Design Guide for implementation details.
1. R is the on-die termination resistance measured at V of the AGTL+ output driver. Refer to processor I/O
TT
OL
buffer models for I/V characteristics.
1. COMP resistance must be provided on the system board with 1% tolerance resistors. See the Mobile Intel
Pentium 4 Processor-M and Intel 845MP/845MZ Chipset Platform Design Guide for implementation
details.
1. The V referred to in these specifications is the instantaneous V
.
CC
CC
2.13
System Bus AC Specifications
The processor system bus timings specified in this section are defined at the processor core
(pads). See Section 5.2 for the Mobile Intel Celeron Processor pin signal definitions.
Table 17 through Table 24 list the AC specifications associated with the processor system bus.
All AGTL+ timings are referenced to GTLREF for both “0” and “1” logic levels unless otherwise
specified.
The timings specified in this section should be used in conjunction with the I/O buffer models
provided by Intel. These I/O buffer models, which include package information, are available for
the Mobile Intel Celeron Processor in IBIS format. AGTL+ layout guidelines are also available in
the Mobile IntelPentium4 Processor-M and Intel845MP/845MZ Chipset Platform Design
Guide.
Unless specified otherwise, all Mobile Intel Celeron Processor AC specifications are at TJ =
100°C. Care should be taken to read all notes associated with a particular timing parameter.
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Table 17. System Bus Differential Clock Specifications
1
T# Parameter
System Bus Frequency
Min
Nom
Max
Unit
Figure
Notes
100
10.2
200
6.12
6.12
700
700
MHz
ns
T1: BCLK[1:0] Period
10.0
9
2
T2: BCLK[1:0] Period Stability
T3: BCLK[1:0] High Time
T4: BCLK[1:0] Low Time
T5: BCLK[1:0] Rise Time
T6: BCLK[1:0] Fall Time
ps
3
3.94
3.94
175
175
5
5
ns
9
9
9
9
ns
ps
4
4
ps
NOTES:
1. Unless otherwise noted, all specifications in this table apply to all processor frequencies.
1. The period specified here is the average period. A given period may vary from this specification as governed
by the period stability specification (T2).
1. In this context, period stability is defined as the worst case timing difference between successive crossover
voltages. In other words, the largest absolute difference between adjacent clock periods must be less than
the period stability.
1. Slew rate is measured between the 35% and 65% points of the clock swing (V to V ).
L
H
.
Table 18. System Bus Common Clock AC Specifications
1,2,3
T# Parameter
Min
Max
Unit
Figure
Notes
T10: Common Clock Output Valid Delay
T11: Common Clock Input Setup Time
T12: Common Clock Input Hold Time
T13: RESET# Pulse Width
0.12
0.65
0.40
1
1.55
ns
ns
11
11
11
12
4
5
ns
5
10
ms
6, 7, 8
NOTES:
1. Unless otherwise noted, all specifications in this table apply to all processor frequencies.
1. Not 100% tested. Specified by design characterization.
1. All common clock AC timings for AGTL+ signals are referenced to the Crossing Voltage (V
) of the
CROSS
BCLK[1:0] at rising edge of BCLK0. All common clock AGTL+ signal timings are referenced at GTLREF at the
processor core.
1. Valid delay timings for these signals are specified into the test circuit described in Figure 7 and with GTLREF
at 2/3 V ± 2%.
CC
1. Specification is for a minimum swing defined between AGTL+ V
of 0.4 V/ns to 4.0 V/ns.
to V
. This assumes an edge rate
IH_MIN
IL_MAX
1. RESET# can be asserted asynchronously, but must be deasserted synchronously.
1. This should be measured after V and BCLK[1:0] become stable.
CC
1. Maximum specification applies only while PWRGOOD is asserted.
.
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Table 19. System Bus Source Synch AC Specifications AGTL+ Signal Group
1,2,3,4
T# Parameter
Min
Typ
Max
Unit
Figure Notes
T20: Source Synchronous Data Output
Valid Delay (first data/address only)
0.20
1.20
ns
13, 14
14
5
T21: T
: Source Synchronous Data
VBD
0.85
0.85
1.88
1.88
0.21
0.21
0.65
ns
ns
5, 8
5, 9
5, 8
5, 9
6
Output Valid Before Strobe
T22: T : Source Synchronous Data
VAD
14
Output Valid After Strobe
T23: T : Source Synchronous
VBA
ns
13
Address Output Valid Before Strobe
T24: T : Source Synchronous
VAA
ns
13
Address Output Valid After Strobe
T25: T : Source Synchronous Input
SUSS
ns
13, 14
13, 14
13, 14
13
Setup Time to Strobe
T26: T : Source Synchronous Input
HSS
ns
6
Hold Time to Strobe
T27: T : Source Synchronous Input
SUCC
ns
7
Setup Time to BCLK[1:0]
T28: T : First Address Strobe to
FASS
1/2
n/4
BCLK
BCLK
ns
10
Second Address Strobe
T29: T : First Data Strobe to
FDSS
14
11, 12
13
Subsequent Strobes
T30: Data Strobe ‘n’ (DSTBN#) Output
valid Delay
8.80
2.27
10.20
4.23
14
T31: Address Strobe Output Valid
Delay
ns
13
NOTES:
1. Unless otherwise noted, all specifications in this table apply to all processor frequencies and cache sizes.
2. Not 100% tested. Specified by design characterization.
3. All source synchronous AC timings are referenced to their associated strobe at GTLREF. Source
synchronous data signals are referenced to the falling edge of their associated data strobe. Source
synchronous address signals are referenced to the rising and falling edge of their associated address strobe.
All source synchronous AGTL+ signal timings are referenced to GTLREF at the processor core.
4. Unless otherwise noted these specifications apply to both data and address timings.
5. Valid delay timings for these signals are specified into the test circuit described in Figure 7 and with GTLREF
at 2/3 V ± 2%.
CC
6. Specification is for a minimum swing defined between AGTL+ V
of 0.3 V/ns to 4.0V /ns.
to V
. This assumes an edge rate
IH_MIN
IL_MAX
7. All source synchronous signals must meet the specified setup time to BCLK as well as the setup time to each
respective strobe.
8. This specification represents the minimum time the data or address will be valid before its strobe. Refer to the
Mobile Intel Pentium 4 Processor-M and Intel 845MP/845MZ Chipset Platform Design Guide for more
information on the definitions and use of these specifications.
9. This specification represents the minimum time the data or address will be valid after its strobe. Refer to the
Mobile Intel Pentium 4 Processor-M and Intel 845MP/845MZ Chipset Platform Design Guide for more
information on the definitions and use of these specifications.
10.The rising edge of ADSTB# must come approximately 1/2 BCLK period (5 ns) after the falling edge of
ADSTB#.
11.For this timing parameter, n = 1, 2, and 3 for the second, third, and last data strobes respectively.
12.The second data strobe (falling edge of DSTBn#) must come approximately 1/4 BCLK period (2.5 ns) after
the first falling edge of DSTBp#. The third data strobe (falling edge of DSTBp#) must come approximately 2/4
BCLK period (5 ns) after the first falling edge of DSTBp#. The last data strobe (falling edge of DSTBn#) must
come approximately 3/4 BCLK period (7.5 ns) after the first falling edge of DSTBp#.
13.This specification applies only to DSTBN[3:0]# and is measured to the second falling edge of the strobe.
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Table 20. Miscellaneous Signals AC Specifications
1,2,3,6
T# Parameter
Min
Max
Unit
Figure
Notes
T35: Asynch GTL+ Input Pulse Width
2
1
BCLKs
T36: PWRGOOD to RESET# de-assertion
time
10
ms
15
T37: PWRGOOD Inactive Pulse Width
T38: PROCHOT# pulse width
10
BCLKs
15
17
18
4
500
us
s
5
T39: THERMTRIP# to Vcc Removal
0.5
5
T40: FERR# Valid Delay from STPCLK#
deassertion
0
BCLKs
19
NOTES:
1. Unless otherwise noted, all specifications in this table apply to all processor frequencies.
2. All AC timings for the Asynch GTL+ signals are referenced to the BCLK0 rising edge at Crossing Voltage. All
Asynch GTL+ signal timings are referenced at GTLREF. PWRGOOD is referenced to the BCLK0 rising edge
at 0.5*V
CC
3. These signals may be driven asynchronously.
4. Refer to the PWRGOOD definition for more details regarding the behavior of this signal.
5. Length of assertion for PROCHOT# does not equal internal clock modulation time. Time is allocated after the
assertion and before the deassertion of PROCHOT# for the processor to complete current instruction
execution.
6. See Section 7.2 for additional timing requirements for entering and leaving the low power states.
Table 21. System Bus AC Specifications (Reset Conditions)
T# Parameter
Min
Max
Unit
Figure
Notes
T45: Reset Configuration Signals (A[31:3]#,
BR0#, INIT#, SMI#) Setup Time
4
BCLKs
12
1
2
T46: Reset Configuration Signals (A[31:3]#,
BR0#, INIT#, SMI#) Hold Time
2
20
BCLKs
12
NOTES:
1. Before the deassertion of RESET#.
2. After clock that deasserts RESET#.
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Table 22. TAP Signals AC Specifications
1,2,3
Parameter
Min
Max
Unit
Figure
Notes
T55: TCK Period
60.0
ns
ns
8
8
T56: TCK Rise Time
T57: TCK Fall Time
10.0
10.0
8.5
4
4
ns
8
T58: TMS Rise Time
T59: TMS Fall Time
T61: TDI Setup Time
T62: TDI Hold Time
ns
8
4
8.5
ns
8
4, 9
5, 7
5, 7
6
0
3
ns
20
20
20
17
ns
T63: TDO Clock to Output Delay
T64: TRST# Assert Time
3.5
ns
2
TCK
8, 9
NOTES:
1. Unless otherwise noted, all specifications in this table apply to all processor frequencies.
2. Not 100% tested. Specified by design characterization.
3. All AC timings for the TAP signals are referenced to the TCK signal at 0.5*V at the processor pins. All TAP
CC
signal timings (TMS, TDI, etc) are referenced at 0.5*V at the processor pins.
CC
4. Rise and fall times are measured from the 20% to 80% points of the signal swing.
5. Referenced to the rising edge of TCK.
6. Referenced to the falling edge of TCK.
7. Specifications for a minimum swing defined between TAP V to V . This assumes a minimum edge rate of
T-
T+
0.5 V/ns
8. TRST# must be held asserted for 2 TCK periods to be guaranteed that it is recognized by the processor.
9. It is recommended that TMS be asserted while TRST# is being deasserted.
Table 23. ITPCLKOUT[1:0] AC Specifications
1,2
Parameter
Min
Typ
Max
Unit
Figure
Notes
T65: ITPCLKOUT Delay
T66: Slew Rate
400
2
560
8
ps
21
3
V/ns
T67: ITPCLKOUT[1:0] High
Time
3.89
3.89
5
5
6.17
6.17
ns
ns
T68: ITPCLKOUT[1:0] Low
Time
NOTES:
1. Unless otherwise noted, all specifications in this table apply to all processor frequencies.
2. These parameters are not tested and are based on design simulations.
3. This delay is from rising edge of BCLK0 to the falling edge of ITPCLK0.
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.
Table 24. Stop Grant/Sleep/Deep Sleep AC Specifications
T# Parameter
Min
Max
Unit
Figure
Notes
T70: SLP# Signal Hold Time from Stop Grant
Cycle Completion
100
BCLKs
22
T71: Input Signals Stable to SLP# Assertion
T72: SLP# to DPSLP# Assertion
10
10
0
BCLKs
BCLKs
µs
22
22
22
22
1
2
T73: Deep Sleep PLL Lock Latency
T74: SLP# Hold Time from PLL Lock
30
0
ns
T75: STPCLK# Hold Time from SLP#
Deassertion
10
10
BCLKs
BCLKs
22
22
T76: Input Signal Hold Time from SLP#
Deassertion
NOTES:
1. Input signals other than RESET# must be held constant in the Sleep state.
1. The BCLK can be stopped after DPSLP# is asserted. The BCLK must be turned on and within specification
before DPSLP# is deasserted.
2.14
Processor AC Timing Waveforms
The following figures are used in conjunction with the AC timing tables, Table 17 through
Table 24.
Note: For Figure 8 through Figure 22, the following apply:
5.All common clock AC timings for AGTL+ signals are referenced to the Crossing Voltage
(VCROSS) of the BCLK[1:0] at rising edge of BCLK0. All common clock AGTL+ signal timings
are referenced at GTLREF at the processor core.
6.All source synchronous AC timings for AGTL+ signals are referenced to their associated strobe
(address or data) at GTLREF. Source synchronous data signals are referenced to the falling edge
of their associated data strobe. Source synchronous address signals are referenced to the rising
and falling edge of their associated address strobe. All source synchronous AGTL+ signal
timings are referenced at GTLREF at the processor core silicon.
7.All AC timings for AGTL+ strobe signals are referenced to BCLK[1:0] at VCROSS. All AGTL+
strobe signal timings are referenced at GTLREF at the processor core silicon.
8.All AC timings for the TAP signals are referenced to the TCK signal at 0.5*VCC at the processor
pins. All TAP signal timings (TMS, TDI, etc) are referenced at 0.5*VCC at the processor pins.
The circuit used to test the AC specifications is shown in.
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Electrical Specifications
Figure 7. AC Test Circuit
VCC
VCC
Rload= 50 ohms
2.4nH
1.2pF
420 mils, 50 ohms, 169 ps/in
AC Timings test measurements made here.
Figure 8. TCK Clock Waveform
V2
V3
V1
tr = T56, T58 (Rise Time)
tf = T57, T59 (Fall Time)
tp = T55 (TCK Period)
V1,V2: For rise and fall times, TCK is measured
between 20% to 80% points on the waveform
V3: TCK is referenced to 0.5*Vcc
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.
Figure 9. Differential Clock Waveform
Tph
Overshoot
VH
BCLK1
Rising Edge
Ringback
Crossing
Voltage
Crossing
Voltage
Ringback
Margin
Threshold
Region
Falling Edge
Ringback,
BCLK0
VL
Undershoot
Tpl
Tp
Tp = T1 (BCLK[1:0] period)
T2 = BCLK[1:0] Period stability (not shown)
Tph =T3 (BCLK[1:0] pulse high time)
Tpl = T4 (BCLK[1:0] pulse low time)
T5 = BCLK[1:0] rise time through the threshold region
T6 = BCLK[1:0] fall time through the threshold region
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Figure 10. Differential Clock Crosspoint Specification
Crosspoint Specification
650
600
550
500
450
400
350
300
250
200
550 mV
550 + 0.5 (VHavg - 710)
250 + 0.5 (VHavg - 710)
250 mV
660 670 680 690 700 710 720 730 740 750 760 770 780 790 800 810 820 830 840 850
Vhavg (mV)
Figure 11. System Bus Common Clock Valid Delay Timings
T0
T1
T2
BCLK1
BCLK0
TP
Common Clock
Signal (@ driver)
valid
valid
TQ
TR
Common Clock
Signal (@ receiver)
valid
TP = T10: TCO (Data Valid Output Delay)
Q = T11: TSU (Common Clock Setup)
T
TR = T12: TH (Common Clock Hold Time)
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Figure 12. System Bus Reset and Configuration Timings
BCLK
Tt
Reset
Tv
Tx
Tw
Configuration
A[31:3], SMI#,
INIT#, BR[3:0]#
Valid
Tv = T13 (RESET# Pulse Width)
Tw = T45 (Reset Configuration Signals Setup TIme)
Tx = T46 (Reset Configuration Signals Hold TIme)
Figure 13. Source Synchronous 2X (Address) Timings
T1
T2
2.5 ns 5.0 ns 7.5 ns
BCLK1
BCLK0
TP
ADSTB# (@ driver)
A# (@ driver)
TR
TH
TJ
TH
TJ
valid
valid
TS
ADSTB# (@ receiver)
A# (@ receiver)
TK
valid
valid
TN
TM
TH = T23: Source Sync. Address Output Valid Before Address Strobe
TJ = T24: Source Sync. Address Output Valid After Address Strobe
TK = T27: Source Sync. Input Setup to BCLK
TM = T26: Source Sync. Input Hold Time
TN = T25: Source Sync. Input Setup Time
TP = T28: First Address Strobe to Second Address Strobe
TS = T20: Source Sync. Output Valid Delay
TR = T31: Address Strobe Output Valid Delay
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Figure 14. Source Synchronous 4X Timings
T0
T1
T2
2.5 ns 5.0 ns 7.5 ns
BCLK1
BCLK0
DSTBp# (@ driver)
DSTBn# (@ driver)
TH
TD
TA TB TA
D# (@ driver)
TJ
DSTBp# (@ receiver)
DSTBn# (@ receiver)
D# (@ receiver)
TC
TE TG TE TG
TA = T21: Source Sync. Data Output Valid Delay Before Data Strobe
TB = T22: Source Sync. Data Output Valid Delay After Data Strobe
T
C = T27: Source Sync. Setup Time to BCLK
TD = T30: Source Sync. Data Strobe 'N' (DSTBN#) Output Valid Delay
TE = T25: Source Sync. Input Setup Time
T
T
G = T26: Source Sync. Input Hold Time
H = T29: First Data Strobe to Subsequent Strobes
TJ = T20: Source Sync. Data Output Valid Delay
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Figure 15. Power Up Sequence
BCLK
Vcc
PWRGOOD
RESET#
VCCVID
Tc
Td
Ta
Tb
VID_GOOD
VID[4:0],
BSEL[1:0]
Ta= 1us minimum (VCCVID > 1V to VID_GOOD high)
Tb= 50ms maximum (VID_GOOD to Vcc valid maximum time)
Tc= T37 (PWRGOOD inactive pulse width)
Td= T36 (PWRGOOD to RESET# de-assertion time)
Note: VID_GOOD is not a processor signal. This signal is routed to the
output enable pin of the voltage regluator control silicon. For more
information on implementation refer to the Intel Mobile Northwood
Processor and Intel 845MP Platform RDDP.
Figure 16. Power Down Sequence
Vcc
PWRGOOD
VCCVID
VID_GOOD
VID[4:0]
Note: VID_GOOD is not a processor signal. This signal is routed to the
output enable pin of the voltage regluator control silicon. For more
information on implementation refer to the Intel Mobile Northwood
Processor and Intel 845MP Platform RDDP.
1. This timing diagram is not intended to show specific times. Instead a
general ordering of events with respect to time should be observed.
2. When VCCVID is less than 1V, VID_GOOD must be low.
3. Vcc must be disabled before VID[4:0] becomes invalid.
4. VCCVID and Vcc regulator can be disabled simultaneously
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Datasheet
Electrical Specifications
Figure 17. Test Reset Timings
V
TRST#
T
q
Tq = T64 (TRST# Pulse Width), V=0.5*Vcc
T38 (PROCHOT# Pulse Width), V=GTLREF
Figure 18. THERMTRIP# to Vcc Timing
T39
THERMTRIP#
Vcc
T39 < 0.5 seconds
Note: THERMTRIP# is undefined when RESET# is active
Figure 19. FERR#/PBE# Valid Delay Timing
BCLK
system bus
STPCLK#
SG
Ack
Ta
FERR#/
PBE#
FERR# undefined
PBE#
undefined FERR#
Ta = T40 (FERR# Valid Delay from STPCLK# Deassertion)
Note: FERR#/PBE# is undefined from STPCLK# assertion until the stop grant acknowledge is driven on the processor system
bus. FERR#/PBE# is also undefined for a period of Ta from STPCLK# deassertion. Inside these undefined regions the PBE#
signal is driven. FERR# is driven at all other times.
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Datasheet
Electrical Specifications
Figure 20. TAP Valid Delay Timing
V
TCK
Tx
Ts
Th
Signal
V Valid
Tx = T63 (Valid Time)
Ts = T61 (Setup Time)
Th = T62 (Hold Time)
V = 0.5 * Vcc
Figure 21. ITPCLKOUT Valid Delay Timing
Tx
BCLK
ITPCLKOUT
T65 = Tx = BCLK input to ITPCLKOUT output delay
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Datasheet
Electrical Specifications
Figure 22. Stop Grant/Sleep/Deep Sleep Timing
Stop
Grant
Stop
Grant
Normal
Sleep
Deep Sleep
Sleep
Normal
BCLK[1:0]
DPSLP#
Tv
STPCLK#
Ty
CPU bus
SLP#
stpgnt
Tw
Tx
Tt
Tu
Changing
Tz
Compatibility
Signals
Changing
Frozen
V0011-02
Tt = T70 (Stop Grant Acknowledge Bus Cycle Completion to SLP# Assertion Delay)
Tu = T71 (Input Signals Stable to SLP# assertion requirement)
Tv = T72 (SLP# to DPSLP# assertion)
Tw = T73 (Deep Sleep PLL lock latency)
Tx = T74 (SLP# Hold Time)
Ty = T75 (STPCLK# Hold Time)
Tz = T76 (Input Signal Hold Time)
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Datasheet
System Bus Signal Quality Specifications
3 System Bus Signal Quality
Specifications
Source synchronous data transfer requires the clean reception of data signals and their associated
strobes. Ringing below receiver thresholds, non-monotonic signal edges, and excessive voltage
swing will adversely affect system timings. Ringback and signal non-monotinicity cannot be
tolerated since these phenomena may inadvertently advance receiver state machines. Excessive
signal swings (overshoot and undershoot) are detrimental to silicon gate oxide integrity, and can
cause device failure if absolute voltage limits are exceeded. Additionally, overshoot and
undershoot can cause timing degradation due to the build up of inter-symbol interference (ISI)
effects. For these reasons, it is important that the designer work to achieve a solution that provides
acceptable signal quality across all systematic variations encountered in volume manufacturing.
This section documents signal quality metrics used to derive topology and routing guidelines
through simulation and for interpreting results for signal quality measurements of actual designs.
The Mobile Intel Celeron Processor IBIS models should be used while performing signal integrity
simulations.
3.1
System Bus Clock (BCLK) Signal Quality
Specifications and Measurement Guidelines
Table 25 describes the signal quality specifications at the processor pads for the processor system
bus clock (BCLK) signals. Figure 23 describes the signal quality waveform for the system bus
clock at the processor pads.
Table 25. BCLK Signal Quality Specifications
1
Parameter
Min
Max
Unit
Figure
Notes
BCLK[1:0] Overshoot
N/A
N/A
0.20
N/A
0.30
0.30
N/A
V
V
V
V
23
23
23
23
BCLK[1:0] Undershoot
BCLK[1:0] Ringback Margin
BCLK[1:0] Threshold Region
2
0.10
NOTES:
1. Unless otherwise noted, all specifications in this table apply to all Mobile Intel Celeron Processor frequencies.
1. The rising and falling edge ringback voltage specified is the minimum (rising) or maximum (falling) absolute
voltage the BCLK signal can dip back to after passing the VIH (rising) or VIL (falling) voltage limits. This
specification is an absolute value.
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Datasheet
System Bus Signal Quality Specifications
Figure 23. BCLK Signal Integrity Waveform
Overshoot
VH
BCLK1
Rising Edge
Ringback
Crossing
Voltage
Crossing
Voltage
Ringback
Margin
Threshold
Region
Falling Edge
Ringback,
BCLK0
VL
Undershoot
3.2
System Bus Signal Quality Specifications and
Measurement Guidelines
Various scenarios have been simulated to generate a set of AGTL+ layout guidelines which are
available in the Mobile Intel Pentium 4 Processor-M and Intel 845MP/845MZ Chipset
Platform Design Guide.
Table 26 and Table 27 provides the signal quality specifications for all processor signals for use in
simulating signal quality at the processor core silicon (pads).
Mobile Intel Celeron Processor maximum allowable overshoot and undershoot specifications for a
given duration of time are detailed in Table 28 through Table 31. Figure 24 shows the system bus
ringback tolerance for low-to-high transitions and Figure 25 shows ringback tolerance for high-to-
low transitions.
Table 26. Ringback Specifications for AGTL+ and Asynchronous GTL+ Signal Groups
Maximum Ringback
(with Input Diodes Present)
Notes
Signal Group
All Signals
Transition
Unit
Figure
0 →
1 →
1
0
GTLREF + 10%
GTLREF - 10%
V
V
24
25
1,2,3,4,5,6,7
1,2,3,4,5,6,7
All Signals
NOTES:
1. All signal integrity specifications are measured at the processor silicon (pads).
1. Unless otherwise noted, all specifications in this table apply to all Mobile Intel Celeron Processor frequencies.
1. Specifications are for the edge rate of 0.3 - 4.0 V/ns.
1. All values specified by design characterization.
1. Please see Section 3.3 for maximum allowable overshoot.
1. Ringback between GTLREF + 10% and GTLREF - 10% is not supported.
1. Intel recommends simulations not exceed a ringback value of GTLREF ± 200 mV to allow margin for other
sources of system noise.
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Datasheet
System Bus Signal Quality Specifications
Table 27. Ringback Specifications for PWRGOOD Input and TAP Signal Groups
Maximum Ringback
(with Input Diodes Present)
Notes
Signal Group
Transition
Unit
Figure
TAP and PWRGOOD
TAP and PWRGOOD
0 → 1
1 → 0
Vt+(max) TO Vt-(max)
Vt-(min) TO Vt+(min)
V
V
26
27
1,2,3,4
1,2,3,4
NOTES:
1. All signal integrity specifications are measured at the processor silicon.
2. Unless otherwise noted, all specifications in this table apply to all Mobile Intel Celeron Processor frequencies.
3. Please see Section 3.3 for maximum allowable overshoot.
4. Please see Section 2.11 for the DC specifications.
Figure 24. Low-to-High System Bus Receiver Ringback Tolerance
VCC
Noise
Margin
+10% GTLREF
GTLREF
-10% GTLREF
VSS
Figure 25. High-to-Low System Bus Receiver Ringback Tolerance
VCC
+10% GTLREF
GTLREF
-10% GTLREF
Noise
Margin
VSS
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System Bus Signal Quality Specifications
Figure 26. Low-to-High System Bus Receiver Ringback Tolerance for PWRGOOD and TAP
Buffers
Vcc
Threshold Region to switch
receiver to a logic 1.
Vt+ (max)
Vt+ (min)
0.5 * Vcc
Vt- (max)
Allowable Ringback
Vss
Figure 27. High-to-Low System Bus Receiver Ringback Tolerance for PWRGOOD and TAP
Buffers
Vcc
Allowable Ringback
Vt+ (min)
0.5 * Vcc
Vt- (max)
Vt- (min)
Threshold Region to switch
receiver to a logic 0.
Vss
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Datasheet
System Bus Signal Quality Specifications
3.3
System Bus Signal Quality Specifications and
Measurement Guidelines
3.3.1
Overshoot/Undershoot Guidelines
Overshoot (or undershoot) is the absolute value of the maximum voltage above the nominal high
voltage (or below VSS) as shown in Figure 28. The overshoot guideline limits transitions beyond
VCC or VSS due to the fast signal edge rates. The processor can be damaged by repeated overshoot
or undershoot events on any input, output, or I/O buffer if the charge is large enough (i.e., if the
over/undershoot is great enough). Determining the impact of an overshoot/undershoot condition
requires knowledge of the magnitude, the pulse direction, and the activity factor (AF). Permanent
damage to the processor is the likely result of excessive overshoot/undershoot.
When performing simulations to determine impact of overshoot and undershoot, ESD diodes must
be properly characterized. ESD protection diodes do not act as voltage clamps and will not provide
overshoot or undershoot protection. ESD diodes modelled within Intel I/O buffer models do not
clamp undershoot or overshoot and will yield correct simulation results. If other I/O buffer models
are being used to characterize the Mobile Intel Celeron Processor system bus, care must be taken to
ensure that ESD models do not clamp extreme voltage levels. Intel I/O buffer models also contain
I/O capacitance characterization. Therefore, removing the ESD diodes from an I/O buffer model
will impact results and may yield excessive overshoot/undershoot.
3.3.2
Overshoot/Undershoot Magnitude
Magnitude describes the maximum potential difference between a signal and its voltage reference
level. For the Mobile Intel Celeron Processor both are referenced to VSS. It is important to note that
overshoot and undershoot conditions are separate and their impact must be determined
independently.
Overshoot/undershoot magnitude levels must observe the absolute maximum specifications listed
in Table 28 through Table 31. These specifications must not be violated at any time regardless of
bus activity or system state. Within these specifications are threshold levels that define different
allowed pulse durations. Provided that the magnitude of the overshoot/undershoot is within the
absolute maximum specifications, the pulse magnitude, duration and activity factor must all be
used to determine if the overshoot/undershoot pulse is within specifications.
3.3.3
Overshoot/Undershoot Pulse Duration
Pulse duration describes the total time an overshoot/undershoot event exceeds the overshoot/
undershoot reference voltage (maximum overshoot = 1.700 V, maximum undershoot = -0.400 V).
The total time could encompass several oscillations above the reference voltage. Multiple
overshoot/undershoot pulses within a single overshoot/undershoot event may need to be measured
to determine the total pulse duration.
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Datasheet
System Bus Signal Quality Specifications
Note: Oscillations below the reference voltage can not be subtracted from the total overshoot/undershoot
pulse duration.
3.3.4
Activity Factor
Activity Factor (AF) describes the frequency of overshoot (or undershoot) occurrence relative to a
clock. Since the highest frequency of assertion of any signal is every other clock, an AF = 1
indicates that the specific overshoot (or undershoot) waveform occurs EVERY OTHER clock
cycle. Thus, an AF = 0.01 indicates that the specific overshoot (or undershoot) waveform occurs
one time in every 200 clock cycles.
For source synchronous signals (address, data, and associated strobes), the activity factor is in
reference to the strobe edge, since the highest frequency of assertion of any source synchronous
signal is every active edge of its associated strobe. An AF = 1 indicates that the specific overshoot
(undershoot) waveform occurs every strobe cycle.
The specifications provided in Table 28 through Table 31 show the maximum pulse duration
allowed for a given overshoot/undershoot magnitude at a specific activity factor. Each table entry is
independent of all others, meaning that the pulse duration reflects the existence of overshoot/
undershoot events of that magnitude ONLY. A platform with an overshoot/undershoot that just
meets the pulse duration for a specific magnitude where the AF < 1, means that there can be no
other overshoot/undershoot events, even of lesser magnitude (note that if AF = 1, then the event
occurs at all times and no other events can occur).
Note: 1: Activity factor for AGTL+ signals is referenced to BCLK[1:0] frequency.
Note: 2: Activity factor for source synchronous (2x) signals is referenced to ADSTB[1:0]#.
Note: 3: Activity factor for source synchronous (4x) signals is referenced to DSTBP[3:0]# and
DSTBN[3:0]#.
3.3.5
Reading Overshoot/Undershoot Specification Tables
The overshoot/undershoot specification for the Mobile Intel Celeron Processor is not a simple
single value. Instead, many factors are needed to determine what the over/undershoot specification
is. In addition to the magnitude of the overshoot, the following parameters must also be known: the
width of the overshoot (as measured above VCC) and the activity factor (AF). To determine the
allowed overshoot for a particular overshoot event, the following must be done:
1. Determine the signal group a particular signal falls into. If the signal is an AGTL+ signal
operating in the common clock domain, use Table 30. For AGTL+ signals operating in the 2x
source synchronous domain, use Table 29. For AGTL+ signals operating in the 4x source
synchronous domain, use Table 28. Finally, all other signals reside in the 100MHz domain
(asynchronous GTL+, TAP, etc.) and are referenced in Table 31.
2. Determine the magnitude of the overshoot (relative to VSS)
3. Determine the activity factor (how often does this overshoot occur?)
4. Next, from the appropriate specification table, determine the maximum pulse duration (in
nanoseconds) allowed.
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System Bus Signal Quality Specifications
5. Compare the specified maximum pulse duration to the signal being measured. If the pulse
duration measured is less than the pulse duration shown in the table, then the signal meets the
specifications.
The above procedure is similar for undershoot after the undershoot waveform has been converted
to look like an overshoot. Undershoot events must be analyzed separately from overshoot events as
they are mutually exclusive.
3.3.6
Conformance Determination to Overshoot/Undershoot
Specifications
The overshoot/undershoot specifications listed in the following tables specify the allowable
overshoot/undershoot for a single overshoot/undershoot event. However, most systems will have
multiple overshoot and/or undershoot events that each have their own set of parameters (duration,
AF and magnitude). While each overshoot on its own may meet the overshoot specification, when
you add the total impact of all overshoot events, the system may fail. A guideline to ensure a
system passes the overshoot and undershoot specifications is shown below.
1. Ensure no signal ever exceeds VCC or -0.25 V OR
2. If only one overshoot/undershoot event magnitude occurs, ensure it meets the over/undershoot
specifications in the following tables OR
3. If multiple overshoots and/or multiple undershoots occur, measure the worst case pulse
duration for each magnitude and compare the results against the AF = 1 specifications. If all of
these worst case overshoot or undershoot events meet the specifications (measured time <
specifications) in the table (where AF=1), then the system passes.
The following notes apply to Table 28 through Table 31.
NOTES:
1. Absolute Maximum Overshoot magnitude of 1.70 V must never be exceeded.
2. Absolute Maximum Overshoot is measured relative to VSS, Pulse Duration of overshoot is measured relative
to VCC
.
3. Absolute Maximum Undershoot and Pulse Duration of undershoot is measured relative to VSS
4. Ringback below VCC can not be subtracted from overshoots/undershoots.
5. Lesser undershoot does not allocate longer or larger overshoot.
6. OEM's are strongly encouraged to follow Intel provided layout guidelines.
7. All values specified by design characterization.
.
Table 28. Source Synchronous (400 MHz) AGTL+ Signal Group Overshoot/Undershoot
Tolerance
Absolute
Maximum
Overshoot
(V)
Absolute
Maximum
Undershoot
(V)
Pulse
Pulse
Pulse
1,2
Duration (ns) Duration (ns) Duration (ns)
Notes
AF = 1
AF = 0.1
AF = 0.01
1.700
1.650
1.600
1.550
1.500
-0.400
-0.350
-0.300
-0.250
-0.200
0.11
0.24
0.53
1.19
5.00
1.05
2.40
5.00
5.00
5.00
5.00
5.00
5.00
5.00
5.00
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System Bus Signal Quality Specifications
Table 28. Source Synchronous (400 MHz) AGTL+ Signal Group Overshoot/Undershoot
Tolerance
Absolute
Maximum
Overshoot
(V)
Absolute
Maximum
Undershoot
(V)
Pulse
Pulse
Pulse
1,2
Duration (ns) Duration (ns) Duration (ns)
Notes
AF = 1
AF = 0.1
AF = 0.01
1.450
1.400
1.350
-0.150
-0.100
-0.050
5.00
5.00
5.00
5.00
5.00
5.00
5.00
5.00
5.00
NOTES:
1. These specifications are measured at the processor core silicon.
2. BCLK period is 10 ns.
Table 29. Source Synchronous (200 MHz) AGTL+ Signal Group Overshoot/Undershoot
Tolerance
Absolute
Maximum
Overshoot
(V)
Absolute
Maximum
Undershoot
(V)
Pulse
Pulse
Pulse
1,2
Duration (ns) Duration (ns) Duration (ns)
Notes
AF = 1
AF = 0.1
AF = 0.01
1.700
1.650
1.600
1.550
1.500
1.450
1.400
1.350
-0.400
-0.350
-0.300
-0.250
-0.200
-0.150
-0.100
-0.050
0.21
0.48
2.10
4.80
10.00
10.00
10.00
10.00
10.00
10.00
10.00
10.00
1.05
10.00
10.00
10.00
10.00
10.00
10.00
2.38
10.00
10.00
10.00
10.00
NOTES:
1. These specifications are measured at the processor core silicon.
2. BCLK period is 10 ns.
Table 30. Common Clock (100 MHz) AGTL+ Signal Group Overshoot/Undershoot Tolerance
Absolute
Maximum
Overshoot
(V)
Absolute
Maximum
Undershoot
(V)
Pulse
Pulse
Pulse
1,2
Duration (ns) Duration (ns) Duration (ns)
Notes
AF = 1
AF = 0.1
AF = 0.01
1.700
1.650
1.600
1.550
1.500
1.450
1.400
1.350
-0.400
-0.350
-0.300
-0.250
-0.200
-0.150
-0.100
-0.050
0.42
0.96
4.20
9.60
20.00
20.00
20.00
20.00
20.00
20.00
20.00
20.00
2.10
20.00
20.00
20.00
20.00
20.00
20.00
4.76
20.00
20.00
20.00
20.00
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System Bus Signal Quality Specifications
NOTES:
1. These specifications are measured at the processor core silicon.
2. BCLK period is 10 ns.
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System Bus Signal Quality Specifications
Table 31. Asynchronous GTL+, PWRGOOD Input, and TAP Signal Groups Overshoot/
Undershoot Tolerance
Absolute
Maximum
Overshoot
(V)
Absolute
Maximum
Undershoot
(V)
Pulse
Pulse
Pulse
1,2
Duration (ns) Duration (ns) Duration (ns)
Notes
AF = 1
AF = 0.1
AF = 0.01
1.700
1.650
1.600
1.550
1.500
1.450
1.400
1.350
-0.400
-0.350
-0.300
-0.250
-0.200
-0.150
-0.100
-0.050
1.26
2.88
12.6
28.8
60.00
60.00
60.00
60.00
60.00
60.00
60.00
60.00
6.30
60.00
60.00
60.00
60.00
60.00
60.00
14.28
60.00
60.00
60.00
60.00
NOTES:
1. These specifications are measured at the processor core silicon.
2. BCLK period is 10 ns.
Figure 28. Maximum Acceptable Overshoot/Undershoot Waveform
Maximum
Absolute
Overshoot
Time-dependent
Overshoot
VMAX
VCC
GTLREF
VOL
VSS
VMIN
Time-dependent
Undershoot
Maximum
Absolute
Undershoot
000588
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Datasheet
Package Mechanical Specifications
4 Package Mechanical
Specifications
The Mobile Intel Celeron Processor is packaged in a 478 pin Micro-FCPGA package. Different
views of the package are shown in Figure 29 through Figure 31. Package dimensions are shown in
Table 32.
Figure 29. Micro-FCPGA Package Top and Bottom Isometric Views
PACKAGE KEEPOUT
CAPACITOR AREA
DIE
LABEL
TOP VIEW
BOTTOM VIEW
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Datasheet
Package Mechanical Specifications
Figure 30. Micro-FCPGA Package - Top and Side Views
0.286
A
SUBSTRATE KEEPOUT ZONE
DO NOT CONTACT PACKAGE
INSIDE THIS LINE
7 (K1)
8 places
5 (K)
4 places
1.25 MAX
(A3)
D1
35 (D)
Ø 0.32 (B)
478 places
A2
E1
2.03 ± 0.08
35 (E)
(A1)
PIN A1 CORNER
NOTE: All dimensions in millimeters. Values shown are for reference only.
58
251308-002
Datasheet
Package Mechanical Specifications
Table 32. Micro-FCPGA Package Dimensions
Symbol Parameter
Min
Max
Unit
A
-
Overall height, top of die to package seating plane
1.81
4.69
1.95
2.03
5.15
2.11
mm
mm
mm
mm
mm
mm
mm
mm
Overall height, top of die to PCB surface, including socket(1)
A1
A2
A3
B
Pin length
Die height
0.854
Pin-side capacitor height
Pin diameter
-
1.25
0.36
35.1
35.1
0.28
34.9
34.9
D
Package substrate length
Package substrate width
E
D1
Die length
11.62 (B0 Step)
mm
E1
e
Die width
11.34 (B0 Step)
mm
mm
mm
mm
mm
mm
each
kPa
g
Pin pitch
1.27
K
Package edge keep-out
Package corner keep-out
Pin-side capacitor boundary
Pin tip radial true position
Pin count
5
7
K1
K3
-
14
<=0.254
478
N
Pdie Allowable pressure on the die for thermal solution
-
689
W
Package weight
4.5
Package Surface Flatness
0.286
mm
NOTES:
1. All Dimensions are Preliminary and subject to change. Values shown are for reference only.
1. Overall height with socket is based on design dimensions of the Micro-FCPGA package and socket with no
thermal solution attached. Values were based on design specifications and tolerances. This dimension is
subject to change based on socket design, OEM motherboard design, or OEM SMT process.
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Datasheet
Package Mechanical Specifications
Figure 31. Micro-FCPGA Package - Bottom View
14 (K3)
AF
AE
AD
AC
AB
AA
Y
W
V
U
T
R
P
14 (K3)
N
M
L
K
J
H
G
F
E
D
C
B
A
1
3
5
7
9
11 13 15 17 19 21 23 25
25X 1.27
(e)
2
4
6
8
10 12 14 16 18 20 22 24 26
25X 1.27
(e)
NOTE: All dimensions in millimeters. Values shown are for reference only.
4.1
Processor Pin-Out
Figure 32 shows the top view pinout of the Mobile Intel Celeron Processor.
60
251308-002
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Package Mechanical Specifications
Figure 32.
The Coordinates of the Processor Pins as Viewed From the Top of the Package.
1
2
3
4
5
6
7
8
9
10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26
A
A
B
VSSSE VCCSE TESTHI
VSS
NC
VCC
VSS
VCC
VSS
VCC
VSS
VSS
VCC
VSS
VCC
VSS
VCC
VCC
VSS
VCC
VSS
VCC
VSS
VSS
VCC
VSS
VCC
VSS
VCC
VCC
VSS
VCC
VSS
VCC
VSS
VSS
VCC
VSS
VCC
VSS
VCC
VCC
VSS
VCC
VSS
VCC
VSS
VSS
VCC
VSS
VCC
VSS
VCC
VCC
VSS
VCC
VSS
VCC
VSS
VSS
VCC
VSS
VCC
VSS
VCC
VCC
VSS
VCC
VSS
VCC
VSS
VSS
VCC
VSS
VCC
VSS
VCC
VSS
VCC
VSS
VSS
NC
D#[2]
VSS
VSS
D#[3]
VSS
VSS
THERMTRIP#
IGNNE#
NSE
NSE
11
B
C
THRMD
A
FERR#/
PBE#
VSS
SMI#
VCC
D#[0] D#[1]
D#[6] D#[9]
C
VSS PROCHOT#
TDI
THRMDC VSS A20M# VSS
D#[4]
VSS
VSS
D#[7] D#[8]
VSS D#[12]
D
D
LINT0 BPRI# VSS
TCK
VSS
TDO
VSS
VCC
D#[5] D#[13] VSS D#[15] D#[23]
DSTBN#
E
E
VSS DEFER#
HITM#
LINT1 TRST# VSS
VCC DBI#[0]
DSTBP#
VSS D#[17] D#[21] VSS
[0]
F
F
RS#[0] VSS
ADS# BNR#
HIT# RS#[2] VSS GTLREF TMS
VSS LOCK# RS#[1] VSS
VCC GTLREF
VSS D#[19] D#[20] VSS D#[22]
[0]
G
G
VSS D#[10] D#[18] VSS DBI#[1] D#[25]
H
H
VSS DRDY# REQ#[4] VSS DBSY# BR0#
REQ#[0] VSS REQ#[3]REQ#[2] VSS TRDY#
D#[11] D#[16] VSS D#[26] D#[31] VSS
DSTBP#
J
J
D#[14] VSS
D#[29] VSS DP#[0]
[1]
K
K
DSTBN#
D#[30] VSS DP#[1] DP#[2]
A#[6] A#[3]
VSS
A#[4] REQ#[1] VSS
VSS
[1]
L
L
VSS ADSTB#[0]
A#[5]
VSS
A#[9] A#[7]
D#[24] D#[28] VSS COMP[0] DP#[3] VSS
D#[27] VSS D#[32] D#[35] VSS D#[37]
M
N
M
N
VSS A#[10] A#[11] VSS
A#[8]
A#[13]
A#[12] A#[14] VSS A#[15] A#[16] VSS
COMP[1] VSS A#[19] A#[20] VSS A#[24]
VSS D#[33] D#[36] VSS D#[39] D#[38]
DSTBP#
TOP VIEW
P
P
D#[34] VSS
D#[41] VSS DBI#[2]
[2]
R
R
DSTBN#
D#[40]
A#[28]
VSS A#[18] A#[21] VSS ADSTB#[1]
VSS D#[43] D#[42] VSS
[2]
T
T
A#[17] A#[22] VSS A#[26] A#[30] VSS
VSS D#[46] D#[47] VSS D#[45] D#[44]
D#[52] VSS D#[50] D#[49] VSS D#[48]
U
U
TESTHI
A#[23] VSS A#[25] A#[31] VSS
8
V
V
VSS A#[27] A#[32] VSS AP#[1] MCERR#
DBI#[3] D#[53] VSS D#[54] D#[51] VSS
DSTBP#
VSS D#[57] D#[55]
W
Y
W
Y
TESTHI
9
VSS
A#[29] A#[33] VSS
INIT#
VSS
DSTBN#[3]
[3]
TESTHI
A#[34] VSS
10
VSS BPM#[3]
D#[60] VSS D#[58] D#[59] VSS D#[56]
STPCLK#
AA
AB
AC
AD
AE
AF
AA
AB
AC
AD
AE
AF
ITPCLKOUT
[0]
VSS TESTHI1 BINIT# VSS BPM#[4] GTLREF VSS
VCC
VSS
VCC
VSS
VCC
VSS
VSS
VCC
VSS
VCC
VSS
VCC
VCC
VSS
VCC
VSS
VCC
VSS
VSS
VCC
VSS
VCC
VSS
VCC
VCC
VSS
VCC
VSS
VCC
VSS
VCC
VSS
VCC
VSS
VCC
VCC
VSS
VCC
VSS
VCC
VSS
VSS
VCC
VSS
VCC
VSS
VCC
VCC
VSS
VCC
VSS
VSS
VCC
VSS
VCC
VSS
VCC
VCC
VSS
VCC
VSS
VCC
VSS
VSS
VCC
GTLREF
VSS D#[63] D#[61] VSS
D#[62]
ITPCLKOU
PWRGOODVSS RESET# SLP#
A#[35] RSP#
VSS
VSS
VCC
VSS VSS
BPM#[1]
BPM#[5]
T[1]
AP#[0] VSS IERR# BPM#[2] VSS BPM#[0] VSS
VSS TESTHI3 TESTHI2 VSS TESTHI5 TESTHI4 VSS ITP_CLK0
TESTHI
0
ITP_CL
K1
VSS
VID4
VSS
NC
NC
VID2
NC
VSS
VID1
BSEL0 VCC
VCC VCCA
VSS
NC
VSSA
VSS
VSS
DPSLP#
DBR#
NC
BSEL1
VID0
VCCIO_
PLL
VID3
VCC
VCC
VSS
VSS
VCC
VSS
VCC
VCC
VSS
VSS
VSS
VCC
VSS
SKTOC
C#
VCCVID VCC
VCC BCLK[0] BCLK[1] NC
VSS
1
2
3
4
5
6
7
8
9
10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26
VSS
VCC
Other
251308-002
61
Datasheet
Package Mechanical Specifications
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62
251308-002
Datasheet
Pin Listing and Signal Definitions
5 Pin Listing and Signal Definitions
5.1
Mobile Intel Celeron Processor Pin Assignments
Section 5.1 contains the preliminary pin list for the Mobile Intel Celeron Processor in Table 33 and
Table 34. Table 33 is a listing of all processor pins ordered alphabetically by pin name. Table 34 is
also a listing of all processor pins but ordered by pin number.
251308-002
63
Datasheet
Pin Listing and Signal Definitions
Table 33.
Pin Listing by Pin Name
Pin
Number
Signal Buffer
Type
Table 33.
Pin Listing by Pin Name
Pin Name
Direction
Pin
Number
Signal Buffer
Type
AP#[0]
AP#[1]
BCLK[0]
BCLK[1]
BINIT#
BNR#
AC1
V5
Common Clock Input/Output
Common Clock Input/Output
Pin Name
Direction
A#[03]
A#[04]
A#[05]
A#[06]
A#[07]
A#[08]
A#[09]
A#[10]
A#[11]
A#[12]
A#[13]
A#[14]
A#[15]
A#[16]
A#[17]
A#[18]
A#[19]
A#[20]
A#[21]
A#[22]
A#[23]
A#[24]
A#[25]
A#[26]
A#[27]
A#[28]
A#[29]
A#[30]
A#[31]
A#[32]
A#[33]
A#[34]
A#[35]
A20M#
ADS#
K2
K4
L6
Source Synch
Source Synch
Source Synch
Source Synch
Source Synch
Source Synch
Source Synch
Source Synch
Source Synch
Source Synch
Source Synch
Source Synch
Source Synch
Source Synch
Source Synch
Source Synch
Source Synch
Source Synch
Source Synch
Source Synch
Source Synch
Source Synch
Source Synch
Source Synch
Source Synch
Source Synch
Source Synch
Source Synch
Source Synch
Source Synch
Source Synch
Source Synch
Source Synch
Asynch GTL+
Input/Output
Input/Output
Input/Output
Input/Output
Input/Output
Input/Output
Input/Output
Input/Output
Input/Output
Input/Output
Input/Output
Input/Output
Input/Output
Input/Output
Input/Output
Input/Output
Input/Output
Input/Output
Input/Output
Input/Output
Input/Output
Input/Output
Input/Output
Input/Output
Input/Output
Input/Output
Input/Output
Input/Output
Input/Output
Input/Output
Input/Output
Input/Output
Input/Output
Input
AF22
AF23
AA3
G2
Bus Clock
Bus Clock
Input
Input
Common Clock Input/Output
Common Clock Input/Output
Common Clock Input/Output
Common Clock Input/Output
Common Clock Input/Output
Common Clock Input/Output
Common Clock Input/Output
Common Clock Input/Output
Common Clock Input
K1
L3
BPM#[0]
BPM#[1]
BPM#[2]
BPM#[3]
BPM#[4]
BPM#[5]
BPRI#
BR0#
AC6
AB5
AC4
Y6
M6
L2
M3
M4
N1
M1
N2
N4
N5
T1
R2
P3
P4
R3
T2
U1
P6
U3
T4
V2
R6
W1
T5
U4
V3
W2
Y1
AB1
C6
G1
L5
AA5
AB4
D2
H6
Common Clock Input/Output
BSEL0
BSEL1
COMP[0]
COMP[1]
D#[0]
AD6
AD5
L24
P1
Power/Other
Power/Other
Power/Other
Power/Other
Source Synch
Source Synch
Source Synch
Source Synch
Source Synch
Source Synch
Source Synch
Source Synch
Source Synch
Source Synch
Source Synch
Source Synch
Source Synch
Source Synch
Source Synch
Source Synch
Source Synch
Source Synch
Source Synch
Source Synch
Source Synch
Output
Output
Input/Output
Input/Output
Input/Output
Input/Output
Input/Output
Input/Output
Input/Output
Input/Output
Input/Output
Input/Output
Input/Output
Input/Output
Input/Output
Input/Output
Input/Output
Input/Output
Input/Output
Input/Output
Input/Output
Input/Output
Input/Output
Input/Output
Input/Output
B21
B22
A23
A25
C21
D22
B24
C23
C24
B25
G22
H21
C26
D23
J21
D25
H22
E24
G23
F23
F24
D#[01]
D#[02]
D#[03]
D#[04]
D#[05]
D#[06]
D#[07]
D#[08]
D#[09]
D#[10]
D#[11]
D#[12]
D#[13]
D#[14]
D#[15]
D#[16]
D#[17]
D#[18]
D#[19]
D#[20]
Common Clock Input/Output
ADSTB#[0]
ADSTB#[1]
Source Synch
Source Synch
Input/Output
Input/Output
R5
64
251308-002
Datasheet
Pin Listing and Signal Definitions
Table 33.
Pin Listing by Pin Name
Table 33.
Pin Listing by Pin Name
Pin
Number
Signal Buffer
Type
Pin
Number
Signal Buffer
Type
Pin Name
Direction
Pin Name
Direction
D#[21]
D#[22]
D#[23]
D#[24]
D#[25]
D#[26]
D#[27]
D#[28]
D#[29]
D#[30]
D#[31]
D#[32]
D#[33]
D#[34]
D#[35]
D#[36]
D#[37]
D#[38]
D#[39]
D#[40]
D#[41]
D#[42]
D#[43]
D#[44]
D#[45]
D#[46]
D#[47]
D#[48]
D#[49]
D#[50]
D#[51]
D#[52]
D#[53]
D#[54]
D#[55]
D#[56]
D#[57]
D#[58]
D#[59]
E25
F26
D26
L21
G26
H24
M21
L22
J24
Source Synch
Source Synch
Source Synch
Source Synch
Source Synch
Source Synch
Source Synch
Source Synch
Source Synch
Source Synch
Source Synch
Source Synch
Source Synch
Source Synch
Source Synch
Source Synch
Source Synch
Source Synch
Source Synch
Source Synch
Source Synch
Source Synch
Source Synch
Source Synch
Source Synch
Source Synch
Source Synch
Source Synch
Source Synch
Source Synch
Source Synch
Source Synch
Source Synch
Source Synch
Source Synch
Source Synch
Source Synch
Source Synch
Source Synch
Input/Output
Input/Output
Input/Output
Input/Output
Input/Output
Input/Output
Input/Output
Input/Output
Input/Output
Input/Output
Input/Output
Input/Output
Input/Output
Input/Output
Input/Output
Input/Output
Input/Output
Input/Output
Input/Output
Input/Output
Input/Output
Input/Output
Input/Output
Input/Output
Input/Output
Input/Output
Input/Output
Input/Output
Input/Output
Input/Output
Input/Output
Input/Output
Input/Output
Input/Output
Input/Output
Input/Output
Input/Output
Input/Output
Input/Output
D#[60]
Y21
AA25
AA22
AA24
E21
G25
P26
V21
AE25
H5
Source Synch
Source Synch
Source Synch
Source Synch
Source Synch
Source Synch
Source Synch
Source Synch
Power/Other
Input/Output
Input/Output
Input/Output
Input/Output
Input/Output
Input/Output
Input/Output
Input/Output
Output
D#[61]
D#[62]
D#[63]
DBI#[0]
DBI#[1]
DBI#[2]
DBI#[3]
DBR#
K23
H25
M23
N22
P21
M24
N23
M26
N26
N25
R21
P24
R25
R24
T26
T25
T22
T23
U26
U24
U23
V25
U21
V22
V24
W26
Y26
W25
Y23
Y24
DBSY#
Common Clock Input/Output
Common Clock Input
DEFER#
DP#[0]
E2
J26
K25
K26
L25
AD25
H2
Common Clock Input/Output
Common Clock Input/Output
Common Clock Input/Output
Common Clock Input/Output
DP#[1]
DP#[2]
DP#[3]
DPSLP#
DRDY#
DSTBN#[0]
DSTBN#[1]
DSTBN#[2]
DSTBN#[3]
DSTBP#[0]
DSTBP#[1]
DSTBP#[2]
DSTBP#[3]
FERR#/PBE#
GTLREF
GTLREF
GTLREF
GTLREF
HIT#
Asynch GTL+
Input
Common Clock Input/Output
E22
K22
R22
W22
F21
J23
P23
W23
B6
Source Synch
Source Synch
Source Synch
Source Synch
Source Synch
Source Synch
Source Synch
Source Synch
Asynch AGL+
Power/Other
Power/Other
Power/Other
Power/Other
Input/Output
Input/Output
Input/Output
Input/Output
Input/Output
Input/Output
Input/Output
Input/Output
Output
AA21
AA6
F20
F6
Input
Input
Input
Input
F3
Common Clock Input/Output
Common Clock Input/Output
Common Clock Output
HITM#
E3
IERR#
AC3
B2
IGNNE#
INIT#
Asynch GTL+
Asynch GTL+
Power/Other
Power/Other
TAP
Input
W5
Input
ITPCLKOUT[0] AA20
ITPCLKOUT[1] AB22
Output
Output
input
ITP_CLK0
ITP_CLK1
AC26
AD26
TAP
input
251308-002
65
Datasheet
Pin Listing and Signal Definitions
Table 33.
Pin Listing by Pin Name
Table 33.
Pin Listing by Pin Name
Pin
Number
Signal Buffer
Type
Pin
Number
Signal Buffer
Type
Pin Name
Direction
Pin Name
Direction
LINT0
D1
Asynch GTL+
Asynch GTL+
Input
Input
TESTHI10
TESTHI11
THERMDA
THERMDC
THERMTRIP#
TMS
Y3
Power/Other
Power/Other
Power/Other
Power/Other
Asynch GTL+
TAP
Input
LINT1
E5
A6
Input
LOCK#
MCERR#
NC
G4
Common Clock Input/Output
Common Clock Input/Output
B3
V6
C4
A22
A7
A2
Output
Input
NC
F7
NC
AD2
AD3
AE21
AF3
AF24
AF25
C3
TRDY#
TRST#
VCC
J6
Common Clock Input
NC
E6
TAP
Input
NC
A10
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
NC
VCC
A12
NC
VCC
A14
NC
VCC
A16
PROCHOT#
PWRGOOD
REQ#[0]
REQ#[1]
REQ#[2]
REQ#[3]
REQ#[4]
RESET#
RS#[0]
RS#[1]
RS#[2]
RSP#
Asynch GTL+
Power/Other
Source Synch
Source Synch
Source Synch
Source Synch
Source Synch
Output
VCC
A18
AB23
J1
Input
VCC
A20
Input/Output
Input/Output
Input/Output
Input/Output
Input/Output
VCC
A8
K5
VCC
AA10
AA12
AA14
AA16
AA18
AA8
AB11
AB13
AB15
AB17
AB19
AB7
AB9
AC10
AC12
AC14
AC16
AC18
AC8
AD11
AD13
AD15
AD17
AD19
J4
VCC
J3
VCC
H3
VCC
AB25
F1
Common Clock Input
Common Clock Input
Common Clock Input
Common Clock Input
Common Clock Input
VCC
VCC
G5
VCC
F4
VCC
AB2
AF26
AB26
B5
VCC
SKTOCC#
SLP#
Power/Other
Asynch GTL+
Asynch GTL+
Asynch GTL+
TAP
Output
VCC
Input
Input
Input
Input
Input
Output
Input
Input
Input
Input
Input
Input
Input
Input
VCC
SMI#
VCC
STPCLK#
TCK
Y4
VCC
D4
VCC
TDI
C1
TAP
VCC
TDO
D5
TAP
VCC
TESTHI0
TESTHI1
TESTHI2
TESTHI3
TESTHI4
TESTHI5
TESTHI8
TESTHI9
AD24
AA2
AC21
AC20
AC24
AC23
U6
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
VCC
VCC
VCC
VCC
VCC
VCC
VCC
W4
VCC
66
251308-002
Datasheet
Pin Listing and Signal Definitions
Table 33.
Pin Listing by Pin Name
Table 33.
Pin Listing by Pin Name
Pin
Number
Signal Buffer
Type
Pin
Number
Signal Buffer
Type
Pin Name
Direction
Pin Name
Direction
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
AD7
AD9
AE10
AE12
AE14
AE16
AE18
AE20
AE6
AE8
AF11
AF13
AF15
AF17
AF19
AF2
AF21
AF5
AF7
AF9
B11
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCCA
VCCIOPLL
VCCSENSE
VCCVID
VID0
VID1
VID2
VID3
VID4
VSS
D7
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
D9
E10
E12
E14
E16
E18
E20
E8
F11
F13
F15
F17
F19
F9
AD20
AE23
A5
Output
AF4
AE5
AE4
AE3
AE2
AE1
A11
A13
A15
A17
A19
A21
A24
A26
A3
Input
Output
Output
Output
Output
Output
B13
B15
B17
B19
B7
VSS
B9
VSS
C10
C12
C14
C16
C18
C20
C8
VSS
VSS
VSS
VSS
VSS
VSS
VSS
A9
D11
VSS
AA1
AA11
AA13
AA15
AA17
D13
D15
D17
D19
VSS
VSS
VSS
VSS
251308-002
67
Datasheet
Pin Listing and Signal Definitions
Table 33.
Pin Listing by Pin Name
Table 33.
Pin Listing by Pin Name
Pin
Number
Signal Buffer
Type
Pin
Number
Signal Buffer
Type
Pin Name
Direction
Pin Name
Direction
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
AA19
AA23
AA26
AA4
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
AE13
AE15
AE17
AE19
AE22
AE24
AE26
AE7
AE9
AF1
AF10
AF12
AF14
AF16
AF18
AF20
AF6
AF8
B10
B12
B14
B16
B18
B20
B23
B26
B4
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
AA7
AA9
AB10
AB12
AB14
AB16
AB18
AB20
AB21
AB24
AB3
AB6
AB8
AC11
AC13
AC15
AC17
AC19
AC2
AC22
AC25
AC5
AC7
AC9
B8
AD1
C11
C13
C15
C17
C19
C2
AD10
AD12
AD14
AD16
AD18
AD21
AD23
AD4
C22
C25
C5
AD8
C7
AE11
C9
68
251308-002
Datasheet
Pin Listing and Signal Definitions
Table 33.
Pin Listing by Pin Name
Table 33.
Pin Listing by Pin Name
Pin
Number
Signal Buffer
Type
Pin
Number
Signal Buffer
Type
Pin Name
Direction
Pin Name
Direction
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
D10
D12
D14
D16
D18
D20
D21
D24
D3
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
H4
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
J2
J22
J25
J5
K21
K24
K3
K6
D6
L1
D8
L23
L26
L4
E1
E11
E13
E15
E17
E19
E23
E26
E4
M2
M22
M25
M5
N21
N24
N3
E7
N6
E9
P2
F10
F12
F14
F16
F18
F2
P22
P25
P5
R1
R23
R26
R4
F22
F25
F5
T21
T24
T3
F8
G21
G24
G3
T6
U2
U22
U25
U5
G6
H1
H23
H26
V1
V23
251308-002
69
Datasheet
Pin Listing and Signal Definitions
Table 33.
Pin Listing by Pin Name
Table 34. Pin Listing by Pin Number
Pin
Number
Signal Buffer
Type
Pin
Number
Signal Buffer
Type
Pin Name
Direction
Pin Name
Direction
VSS
V26
V4
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
A25
D#[03]
Source Synch
Power/Other
Power/Other
Power/Other
Input/Output
VSS
A26
VSS
VSS
W21
W24
W3
AA1
VSS
VSS
AA2
TESTHI1
BINIT#
VSS
Input
VSS
AA3
Common Clock Input/Output
Power/Other
VSS
W6
AA4
VSS
Y2
AA5
BPM#[4]
GTLREF
VSS
Common Clock Input/Output
VSS
Y22
Y25
Y5
AA6
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Input
VSS
AA7
VSS
AA8
VCC
VSSA
VSSSENSE
AD22
A4
AA9
VSS
Output
AA10
AA11
AA12
AA13
AA14
AA15
AA16
AA17
AA18
AA19
VCC
VSS
Table 34. Pin Listing by Pin Number
VCC
Pin
Number
Signal Buffer
Type
VSS
Pin Name
Direction
Output
VCC
A2
THERMTRIP# Asynch GTL+
VSS
A3
VSS
Power/Other
Power/Other
Power/Other
Power/Other
VCC
A4
VSSSENSE
VCCSENSE
TESTHI11
NC
Output
Output
Input
VSS
A5
VCC
A6
VSS
A7
ITPCLKOUT
[0]
AA20
Power/Other
Output
A8
VCC
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
AA21
AA22
AA23
AA24
AA25
AA26
AB1
GTLREF
D#[62]
VSS
Power/Other
Source Synch
Power/Other
Source Synch
Source Synch
Power/Other
Source Synch
Input
A9
VSS
Input/Output
A10
A11
A12
A13
A14
A15
A16
A17
A18
A19
A20
A21
A22
A23
A24
VCC
VSS
D#[63]
D#[61]
VSS
Input/Output
Input/Output
VCC
VSS
VCC
A#[35]
RSP#
VSS
Input/Output
VSS
AB2
Common Clock Input
Power/Other
VCC
AB3
VSS
AB4
BPM#[5]
BPM#[1]
VSS
Common Clock Input/Output
Common Clock Input/Output
Power/Other
VCC
AB5
VSS
AB6
VCC
AB7
VCC
Power/Other
VSS
AB8
VSS
Power/Other
NC
AB9
VCC
Power/Other
D#[02]
VSS
Source Synch
Power/Other
Input/Output
AB10
VSS
Power/Other
70
251308-002
Datasheet
Pin Listing and Signal Definitions
Table 34. Pin Listing by Pin Number
Table 34. Pin Listing by Pin Number
Pin
Number
Signal Buffer
Type
Pin
Number
Signal Buffer
Type
Pin Name
Direction
Pin Name
Direction
AB11
AB12
AB13
AB14
AB15
AB16
AB17
AB18
AB19
AB20
AB21
VCC
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
AC23
AC24
AC25
AC26
AD1
TESTHI5
Power/Other
Power/Other
Power/Other
TAP
Input
VSS
VCC
VSS
VCC
VSS
VCC
VSS
VCC
VSS
VSS
TESTHI4
VSS
Input
input
ITP_CLK0
VSS
Power/Other
AD2
NC
AD3
NC
AD4
VSS
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Asynch GTL+
TAP
AD5
BSEL1
BSEL0
VCC
Output
Output
AD6
AD7
ITPCLKOUT
[1]
AD8
VSS
AB22
Power/Other
Output
Input
AD9
VCC
AB23
AB24
AB25
AB26
AC1
PWRGOOD
VSS
Power/Other
Power/Other
AD10
AD11
AD12
AD13
AD14
AD15
AD16
AD17
AD18
AD19
AD20
AD21
AD22
AD23
AD24
AD25
AD26
AE1
VSS
VCC
RESET#
SLP#
AP#[0]
VSS
Common Clock Input
Asynch GTL+ Input
VSS
VCC
Common Clock Input/Output
Power/Other
VSS
AC2
VCC
AC3
IERR#
BPM#[2]
VSS
Common Clock Output
Common Clock Input/Output
Power/Other
VSS
AC4
VCC
AC5
VSS
AC6
BPM#[0]
VSS
Common Clock Input/Output
Power/Other
VCC
AC7
VCCA
VSS
AC8
VCC
Power/Other
AC9
VSS
Power/Other
VSSA
VSS
AC10
AC11
AC12
AC13
AC14
AC15
AC16
AC17
AC18
AC19
AC20
AC21
AC22
VCC
Power/Other
VSS
Power/Other
TESTHI0
DPSLP#
ITP_CLK1
VID4
VID3
VID2
VID1
VID0
VCC
Input
VCC
Power/Other
Input
VSS
Power/Other
input
VCC
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Output
Output
Output
Output
Output
VSS
Power/Other
AE2
VCC
Power/Other
AE3
VSS
Power/Other
AE4
VCC
Power/Other
AE5
VSS
Power/Other
AE6
TESTHI3
TESTHI2
VSS
Power/Other
Power/Other
Power/Other
Input
Input
AE7
VSS
AE8
VCC
AE9
VSS
251308-002
71
Datasheet
Pin Listing and Signal Definitions
Table 34. Pin Listing by Pin Number
Table 34. Pin Listing by Pin Number
Pin
Number
Signal Buffer
Type
Pin
Number
Signal Buffer
Type
Pin Name
Direction
Pin Name
Direction
Input
AE10
AE11
AE12
AE13
AE14
AE15
AE16
AE17
AE18
AE19
AE20
AE21
AE22
AE23
AE24
AE25
AE26
AF1
VCC
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
AF23
AF24
AF25
AF26
B2
BCLK[1]
Bus Clock
VSS
NC
VCC
VSS
NC
SKTOCC#
IGNNE#
THERMDA
VSS
Power/Other
Asynch GTL+
Power/Other
Power/Other
Asynch GTL+
Asynch AGL+
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Source Synch
Source Synch
Power/Other
Source Synch
Source Synch
Power/Other
TAP
Output
Input
VCC
VSS
B3
VCC
VSS
B4
B5
SMI#
Input
VCC
VSS
B6
FERR#/PBE#
VCC
Output
B7
VCC
NC
B8
VSS
B9
VCC
VSS
Power/Other
Power/Other
Power/Other
Asynch GTL+
Power/Other
Power/Other
Power/Other
B10
B11
B12
B13
B14
B15
B16
B17
B18
B19
B20
B21
B22
B23
B24
B25
B26
C1
VSS
VCCIOPLL
VSS
VCC
VSS
DBR#
VSS
Output
VCC
VSS
VSS
VCC
AF2
VCC
NC
VSS
AF3
VCC
AF4
VCCVID
VCC
VSS
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Bus Clock
Input
VSS
AF5
VCC
AF6
VSS
AF7
VCC
VSS
D#[0]
D#[01]
VSS
Input/Output
Input/Output
AF8
AF9
VCC
VSS
AF10
AF11
AF12
AF13
AF14
AF15
AF16
AF17
AF18
AF19
AF20
AF21
AF22
D#[06]
D#[09]
VSS
Input/Output
Input/Output
VCC
VSS
VCC
VSS
TDI
Input
C2
VSS
Power/Other
Asynch GTL+
Power/Other
Power/Other
Asynch GTL+
Power/Other
Power/Other
Power/Other
Power/Other
VCC
VSS
C3
PROCHOT#
THERMDC
VSS
Output
C4
VCC
VSS
C5
C6
A20M#
VSS
Input
VCC
VSS
C7
C8
VCC
VCC
BCLK[0]
C9
VSS
Input
C10
VCC
72
251308-002
Datasheet
Pin Listing and Signal Definitions
Table 34. Pin Listing by Pin Number
Table 34. Pin Listing by Pin Number
Pin
Number
Signal Buffer
Type
Pin
Number
Signal Buffer
Type
Pin Name
Direction
Pin Name
Direction
C11
C12
C13
C14
C15
C16
C17
C18
C19
C20
C21
C22
C23
C24
C25
C26
D1
VSS
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Source Synch
Power/Other
Source Synch
Source Synch
Power/Other
Source Synch
Asynch GTL+
D24
D25
D26
E1
VSS
Power/Other
Source Synch
Source Synch
Power/Other
VCC
VSS
D#[15]
D#[23]
VSS
Input/Output
Input/Output
VCC
VSS
E2
DEFER#
HITM#
VSS
Common Clock Input
Common Clock Input/Output
Power/Other
VCC
VSS
E3
E4
VCC
VSS
E5
LINT1
TRST#
VSS
Asynch GTL+
TAP
Input
Input
E6
VCC
D#[04]
VSS
E7
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Source Synch
Source Synch
Power/Other
Source Synch
Source Synch
Power/Other
Input/Output
E8
VCC
E9
VSS
D#[07]
D#[08]
VSS
Input/Output
Input/Output
E10
E11
E12
E13
E14
E15
E16
E17
E18
E19
E20
E21
E22
E23
E24
E25
E26
F1
VCC
VSS
VCC
D#[12]
LINT0
BPRI#
VSS
Input/Output
Input
VSS
VCC
D2
Common Clock Input
Power/Other
VSS
D3
VCC
D4
TCK
TAP
Input
VSS
D5
TDO
VSS
TAP
Output
VCC
D6
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Source Synch
Source Synch
VSS
D7
VCC
VSS
VCC
D8
DBI#[0]
DSTBN#[0]
VSS
Input/Output
Input/Output
D9
VCC
VSS
D10
D11
D12
D13
D14
D15
D16
D17
D18
D19
D20
D21
D22
D23
VCC
VSS
D#[17]
D#[21]
VSS
Input/Output
Input/Output
VCC
VSS
RS#[0]
VSS
Common Clock Input
Power/Other
VCC
VSS
F2
F3
HIT#
Common Clock Input/Output
Common Clock Input
Power/Other
VCC
VSS
F4
RS#[2]
VSS
F5
VCC
VSS
F6
GTLREF
TMS
Power/Other
TAP
Input
Input
F7
VSS
F8
VSS
Power/Other
Power/Other
Power/Other
D#[05]
D#[13]
Input/Output
Input/Output
F9
VCC
F10
VSS
251308-002
73
Datasheet
Pin Listing and Signal Definitions
Table 34. Pin Listing by Pin Number
Table 34. Pin Listing by Pin Number
Pin
Number
Signal Buffer
Type
Pin
Number
Signal Buffer
Type
Pin Name
Direction
Pin Name
Direction
F11
F12
F13
F14
F15
F16
F17
F18
F19
F20
F21
F22
F23
F24
F25
F26
G1
VCC
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Source Synch
Power/Other
Source Synch
Source Synch
Power/Other
Source Synch
H26
J1
VSS
Power/Other
Source Synch
Power/Other
Source Synch
Source Synch
Power/Other
VSS
REQ#[0]
VSS
Input/Output
VCC
J2
VSS
J3
REQ#[3]
REQ#[2]
VSS
Input/Output
Input/Output
VCC
J4
VSS
J5
VCC
J6
TRDY#
D#[14]
VSS
Common Clock Input
VSS
J21
J22
J23
J24
J25
J26
K1
Source Synch
Power/Other
Source Synch
Source Synch
Power/Other
Input/Output
VCC
GTLREF
DSTBP#[0]
VSS
Input
DSTBP#[1]
D#[29]
VSS
Input/Output
Input/Output
Input/Output
D#[19]
D#[20]
VSS
Input/Output
Input/Output
DP#[0]
A#[06]
A#[03]
VSS
Common Clock Input/Output
Source Synch
Source Synch
Power/Other
Source Synch
Source Synch
Power/Other
Power/Other
Source Synch
Source Synch
Power/Other
Input/Output
Input/Output
K2
D#[22]
ADS#
BNR#
VSS
Input/Output
K3
Common Clock Input/Output
Common Clock Input/Output
Power/Other
K4
A#[04]
REQ#[1]
VSS
Input/Output
Input/Output
G2
K5
G3
K6
G4
LOCK#
RS#[1]
VSS
Common Clock Input/Output
Common Clock Input
Power/Other
K21
K22
K23
K24
K25
K26
L1
VSS
G5
DSTBN#[1]
D#[30]
VSS
Input/Output
Input/Output
G6
G21
G22
G23
G24
G25
G26
H1
VSS
Power/Other
D#[10]
D#[18]
VSS
Source Synch
Source Synch
Power/Other
Source Synch
Source Synch
Power/Other
Input/Output
Input/Output
DP#[1]
DP#[2]
VSS
Common Clock Input/Output
Common Clock Input/Output
Power/Other
DBI#[1]
D#[25]
VSS
Input/Output
Input/Output
L2
A#[09]
A#[07]
VSS
Source Synch
Source Synch
Power/Other
Source Synch
Source Synch
Source Synch
Source Synch
Power/Other
Power/Other
Input/Output
Input/Output
L3
L4
H2
DRDY#
REQ#[4]
VSS
Common Clock Input/Output
L5
ADSTB#[0]
A#[05]
D#[24]
D#[28]
VSS
Input/Output
Input/Output
Input/Output
Input/Output
H3
Source Synch
Power/Other
Input/Output
L6
H4
L21
L22
L23
L24
L25
L26
M1
M2
H5
DBSY#
BR0#
D#[11]
D#[16]
VSS
Common Clock Input/Output
Common Clock Input/Output
H6
H21
H22
H23
H24
H25
Source Synch
Source Synch
Power/Other
Source Synch
Source Synch
Input/Output
Input/Output
COMP[0]
DP#[3]
VSS
Input/Output
Common Clock Input/Output
Power/Other
D#[26]
D#[31]
Input/Output
Input/Output
A#[13]
VSS
Source Synch
Power/Other
Input/Output
74
251308-002
Datasheet
Pin Listing and Signal Definitions
Table 34. Pin Listing by Pin Number
Table 34. Pin Listing by Pin Number
Pin
Number
Signal Buffer
Type
Pin
Number
Signal Buffer
Type
Pin Name
Direction
Pin Name
Direction
M3
A#[10]
Source Synch
Source Synch
Power/Other
Source Synch
Source Synch
Power/Other
Source Synch
Source Synch
Power/Other
Source Synch
Source Synch
Source Synch
Power/Other
Source Synch
Source Synch
Power/Other
Power/Other
Source Synch
Source Synch
Power/Other
Source Synch
Source Synch
Power/Other
Power/Other
Source Synch
Source Synch
Power/Other
Source Synch
Source Synch
Power/Other
Source Synch
Source Synch
Power/Other
Source Synch
Power/Other
Source Synch
Source Synch
Power/Other
Source Synch
Input/Output
Input/Output
R6
A#[28]
Source Synch
Source Synch
Source Synch
Power/Other
Source Synch
Source Synch
Power/Other
Source Synch
Source Synch
Power/Other
Source Synch
Source Synch
Power/Other
Power/Other
Source Synch
Source Synch
Power/Other
Source Synch
Source Synch
Source Synch
Power/Other
Source Synch
Source Synch
Power/Other
Power/Other
Source Synch
Power/Other
Source Synch
Source Synch
Power/Other
Source Synch
Power/Other
Source Synch
Source Synch
Power/Other
Input/Output
Input/Output
Input/Output
M4
A#[11]
VSS
R21
R22
R23
R24
R25
R26
T1
D#[40]
DSTBN#[2]
VSS
M5
M6
A#[08]
D#[27]
VSS
Input/Output
Input/Output
M21
M22
M23
M24
M25
M26
N1
D#[43]
D#[42]
VSS
Input/Output
Input/Output
D#[32]
D#[35]
VSS
Input/Output
Input/Output
A#[17]
A#[22]
VSS
Input/Output
Input/Output
T2
D#[37]
A#[12]
A#[14]
VSS
Input/Output
Input/Output
Input/Output
T3
T4
A#[26]
A#[30]
VSS
Input/Output
Input/Output
N2
T5
N3
T6
N4
A#[15]
A#[16]
VSS
Input/Output
Input/Output
T21
T22
T23
T24
T25
T26
U1
VSS
N5
D#[46]
D#[47]
VSS
Input/Output
Input/Output
N6
N21
N22
N23
N24
N25
N26
P1
VSS
D#[33]
D#[36]
VSS
Input/Output
Input/Output
D#[45]
D#[44]
A#[23]
VSS
Input/Output
Input/Output
Input/Output
D#[39]
D#[38]
COMP[1]
VSS
Input/Output
Input/Output
Input/Output
U2
U3
A#[25]
A#[31]
VSS
Input/Output
Input/Output
U4
P2
U5
P3
A#[19]
A#[20]
VSS
Input/Output
Input/Output
U6
TESTHI8
D#[52]
VSS
Input
P4
U21
U22
U23
U24
U25
U26
V1
Input/Output
P5
P6
A#[24]
D#[34]
VSS
Input/Output
Input/Output
D#[50]
D#[49]
VSS
Input/Output
Input/Output
P21
P22
P23
P24
P25
P26
R1
DSTBP#[2]
D#[41]
VSS
Input/Output
Input/Output
D#[48]
VSS
Input/Output
V2
A#[27]
A#[32]
VSS
Input/Output
Input/Output
DBI#[2]
VSS
Input/Output
V3
V4
R2
A#[18]
A#[21]
VSS
Input/Output
Input/Output
V5
AP#[1]
MCERR#
DBI#[3]
D#[53]
Common Clock Input/Output
Common Clock Input/Output
R3
V6
R4
V21
V22
Source Synch
Source Synch
Input/Output
Input/Output
R5
ADSTB#[1]
Input/Output
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Pin Listing and Signal Definitions
Table 34. Pin Listing by Pin Number
Pin
Number
Signal Buffer
Type
Pin Name
Direction
V23
V24
V25
V26
W1
VSS
Power/Other
Source Synch
Source Synch
Power/Other
Source Synch
Source Synch
Power/Other
Power/Other
Asynch GTL+
Power/Other
Power/Other
Source Synch
Source Synch
Power/Other
Source Synch
Source Synch
Source Synch
Power/Other
Power/Other
Asynch GTL+
Power/Other
D#[54]
D#[51]
VSS
Input/Output
Input/Output
A#[29]
A#[33]
VSS
Input/Output
Input/Output
W2
W3
W4
TESTHI9
INIT#
Input
Input
W5
W6
VSS
W21
W22
W23
W24
W25
W26
Y1
VSS
DSTBN#[3]
DSTBP#[3]
VSS
Input/Output
Input/Output
D#[57]
D#[55]
A#[34]
VSS
Input/Output
Input/Output
Input/Output
Y2
Y3
TESTHI10
STPCLK#
VSS
Input
Input
Y4
Y5
Y6
BPM#[3]
D#[60]
VSS
Common Clock Input/Output
Y21
Y22
Y23
Y24
Y25
Y26
Source Synch
Power/Other
Source Synch
Source Synch
Power/Other
Source Synch
Input/Output
D#[58]
D#[59]
VSS
Input/Output
Input/Output
D#[56]
Input/Output
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Pin Listing and Signal Definitions
5.2
Alphabetical Signals Reference
Table 35. Signal Description (Sheet 1 of 8)
Name
Type
Description
A[35:3]# (Address) define a 236-byte physical memory address space. In sub-
phase 1 of the address phase, these pins transmit the address of a transaction. In
sub-phase 2, these pins transmit transaction type information. These signals must
connect the appropriate pins of all agents on the Mobile Intel Pentium 4
Processor-M system bus. A[35:3]# are protected by parity signals AP[1:0]#.
A[35:3]# are source synchronous signals and are latched into the receiving buffers
by ADSTB[1:0]#.
Input/
Output
A[35:3]#
On the active-to-inactive transition of RESET#, the processor samples a subset of
the A[35:3]# pins to determine power-on configuration. See Section 7.1 for more
details.
If A20M# (Address-20 Mask) is asserted, the processor masks physical address bit
20 (A20#) before looking up a line in any internal cache and before driving a read/
write transaction on the bus. Asserting A20M# emulates the 8086 processor's
address wrap-around at the 1-Mbyte boundary. Assertion of A20M# is only
supported in real mode.
A20M#
ADS#
Input
A20M# is an asynchronous signal. However, to ensure recognition of this signal
following an Input/Output write instruction, it must be valid along with the TRDY#
assertion of the corresponding Input/Output Write bus transaction.
ADS# (Address Strobe) is asserted to indicate the validity of the transaction
Input/ address on the A[35:3]# and REQ[4:0]# pins. All bus agents observe the ADS#
Output activation to begin parity checking, protocol checking, address decode, internal
snoop, or deferred reply ID match operations associated with the new transaction.
Address strobes are used to latch A[35:3]# and REQ[4:0]# on their rising and falling
edges. Strobes are associated with signals as shown below.
Input/
Output
Signals
Associated Strobe
ADSTB[1:0]#
REQ[4:0]#, A[16:3]#
A[35:17]#
ADSTB0#
ADSTB1#
AP[1:0]# (Address Parity) are driven by the request initiator along with ADS#,
A[35:3]#, and the transaction type on the REQ[4:0]#. A correct parity signal is high if
an even number of covered signals are low and low if an odd number of covered
signals are low. This allows parity to be high when all the covered signals are high.
AP[1:0]# should connect the appropriate pins of all Mobile Intel Celeron Processor
system bus agents. The following table defines the coverage model of these
signals.
Input/
Output
AP[1:0]#
Request Signals
A[35:24]#
subphase 1
AP0#
subphase 2
AP1#
A[23:3]#
AP1#
AP0#
REQ[4:0]#
AP1#
AP0#
The differential pair BCLK (Bus Clock) determines the system bus frequency. All
processor system bus agents must receive these signals to drive their outputs and
latch their inputs.
BCLK[1:0]
Input
All external timing parameters are specified with respect to the rising edge of
BCLK0 crossing VCROSS
.
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Table 35. Signal Description (Sheet 2 of 8)
Name
Type
Description
BINIT# (Bus Initialization) may be observed and driven by all processor system bus
agents and if used, must connect the appropriate pins of all such agents. If the
BINIT# driver is enabled during power-on configuration, BINIT# is asserted to
signal any bus condition that prevents reliable future operation.
If BINIT# observation is enabled during power-on configuration, and BINIT# is
sampled asserted, symmetric agents reset their bus LOCK# activity and bus
request arbitration state machines. The bus agents do not reset their IOQ and
transaction tracking state machines upon observation of BINIT# activation. Once
the BINIT# assertion has been observed, the bus agents will re-arbitrate for the
system bus and attempt completion of their bus queue and IOQ entries.
Input/
Output
BINIT#
If BINIT# observation is disabled during power-on configuration, a central agent
may handle an assertion of BINIT# as appropriate to the error handling architecture
of the system.
BNR# (Block Next Request) is used to assert a bus stall by any bus agent who is
unable to accept new bus transactions. During a bus stall, the current bus owner
cannot issue any new transactions.
Input/
Output
BNR#
BPM[5:0]# (Breakpoint Monitor) are breakpoint and performance monitor signals.
They are outputs from the processor which indicate the status of breakpoints and
programmable counters used for monitoring processor performance. BPM[5:0]#
should connect the appropriate pins of all Mobile Intel Celeron Processor system
bus agents.
BPM4# provides PRDY# (Probe Ready) functionality for the TAP port. PRDY# is a
processor output used by debug tools to determine processor debug readiness.
Input/
Output
BPM[5:0]#
BPM5# provides PREQ# (Probe Request) functionality for the TAP port. PREQ# is
used by debug tools to request debug operation of the processor.
Please refer to the Mobile Intel Pentium 4 Processor-M and Intel 845MP/
845MZ Chipset Platform Design Guide for more detailed information.
These signals do not have on-die termination and must be terminated on the
system board.
BPRI# (Bus Priority Request) is used to arbitrate for ownership of the processor
system bus. It must connect the appropriate pins of all processor system bus
agents. Observing BPRI# active (as asserted by the priority agent) causes all other
agents to stop issuing new requests, unless such requests are part of an ongoing
locked operation. The priority agent keeps BPRI# asserted until all of its requests
are completed, then releases the bus by deasserting BPRI#.
BPRI#
BR0#
Input
BR0# drives the BREQ0# signal in the system and is used by the processor to
request the bus. During power-on configuration this pin is sampled to determine the
agent ID = 0.
Input/
Output
This signal does not have on-die termination and must be terminated.
BSEL[1:0] (Bus Select) are used to select the processor input clock frequency.
Table 5 defines the possible combinations of the signals and the frequency
associated with each combination. The required frequency is determined by the
processor, chipset and clock synthesizer. All agents must operate at the same
frequency. The Mobile Intel Celeron Processor operates at a 400-MHz system bus
frequency (100-MHz BCLK[1:0] frequency). For more information about these pins,
including termination recommendations refer to Section 2.9 and the appropriate
platform design guidelines.
BSEL[1:0]
Output
COMP[1:0] must be terminated on the system board using precision resistors.
COMP[1:0]
Analog Refer to the Mobile Intel Pentium 4 Processor-M and Intel 845MP/845MZ
Chipset Platform Design Guide for details on implementation.
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Pin Listing and Signal Definitions
Table 35. Signal Description (Sheet 3 of 8)
Name
Type
Description
D[63:0]# (Data) are the data signals. These signals provide a 64-bit data path
between the processor system bus agents, and must connect the appropriate pins
on all such agents. The data driver asserts DRDY# to indicate a valid data transfer.
D[63:0]# are quad-pumped signals and will thus be driven four times in a common
clock period. D[63:0]# are latched off the falling edge of both DSTBP[3:0]# and
DSTBN[3:0]#. Each group of 16 data signals correspond to a pair of one DSTBP#
and one DSTBN#. The following table shows the grouping of data signals to data
strobes and DBI#.
Quad-Pumped Signal Groups
DSTBN#/
Input/
Output
D[63:0]#
Data Group
DBI#
DSTBP#
D[15:0]#
D[31:16]#
D[47:32]#
D[63:48]#
0
1
2
3
0
1
2
3
Furthermore, the DBI# pins determine the polarity of the data signals. Each group
of 16 data signals corresponds to one DBI# signal. When the DBI# signal is active,
the corresponding data group is inverted and therefore sampled active high.
DBI[3:0]# (Data Bus Inversion) are source synchronous and indicate the polarity of
the D[63:0]# signals. The DBI[3:0]# signals are activated when the data on the data
bus is inverted. The bus agent will invert the data bus signals if more than half the
bits, within the covered group, would change level in the next cycle.
DBI[3:0] Assignment To Data Bus
Input/
Output
Bus Signal
Data Bus Signals
DBI[3:0]#
DBI3#
DBI2#
DBI1#
DBI0#
D[63:48]#
D[47:32]#
D[31:16]#
D[15:0]#
DBR# (Data Bus Reset) is used only in processor systems where no debug port is
implemented on the system board. DBR# is used by a debug port interposer so that
an in-target probe can drive system reset. If a debug port is implemented in the
system, DBR# is a no connect in the system. DBR# is not a processor signal.
DBR#
Output
DBSY# (Data Bus Busy) is asserted by the agent responsible for driving data on the
Input/ processor system bus to indicate that the data bus is in use. The data bus is
Output released after DBSY# is deasserted. This signal must connect the appropriate pins
on all processor system bus agents.
DBSY#
DEFER#
DEFER# is asserted by an agent to indicate that a transaction cannot be
guaranteed in-order completion. Assertion of DEFER# is normally the responsibility
of the addressed memory or Input/Output agent. This signal must connect the
Input
appropriate pins of all processor system bus agents.
DP[3:0]# (Data parity) provide parity protection for the D[63:0]# signals. They are
driven by the agent responsible for driving D[63:0]#, and must connect the
appropriate pins of all Mobile Intel Celeron Processor system bus agents.
Input/
Output
DP[3:0]#
DPSLP#
DPSLP# when asserted on the platform causes the processor to transition from the
Sleep State to the Deep Sleep state. In order to return to the Sleep State, DPSLP#
must be deasserted and BCLK[1:0] must be running.
Input
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Table 35. Signal Description (Sheet 4 of 8)
Name
Type
Description
DRDY# (Data Ready) is asserted by the data driver on each data transfer,
Input/ indicating valid data on the data bus. In a multi-common clock data transfer, DRDY#
Output may be deasserted to insert idle clocks. This signal must connect the appropriate
pins of all processor system bus agents.
DRDY#
Data strobe used to latch in D[63:0]#.
Signals
Associated Strobe
D[15:0]#, DBI0#
D[31:16]#, DBI1#
D[47:32]#, DBI2#
D[63:48]#, DBI3#
DSTBN0#
DSTBN1#
DSTBN2#
DSTBN3#
Input/
Output
DSTBN[3:0]#
Data strobe used to latch in D[63:0]#.
Signals
Associated Strobe
D[15:0]#, DBI0#
D[31:16]#, DBI1#
D[47:32]#, DBI2#
D[63:48]#, DBI3#
DSTBP0#
DSTBP1#
DSTBP2#
DSTBP3#
Input/
Output
DSTBP[3:0]#
FERR#/PBE# (floating point error/pending break event) is a multiplexed signal and
its meaning is qualified by STPCLK#. When STPCLK# is not asserted, FERR#/
PBE# indicates a floating-point error and will be asserted when the processor
detects an unmasked floating-point error. When STPCLK# is not asserted, FERR#/
PBE# is similar to the ERROR# signal on the INTEL 387 coprocessor, and is
included for compatibility with systems using MS-DOS*-type floating-point error
reporting. When STPCLK# is asserted, an assertion of FERR#/PBE# indicates that
FERR#/PBE# Output the processor has a pending break event waiting for service. The assertion of
FERR#/PBE# indicates that the processor should be returned to the Normal state.
When FERR#/PBE# is asserted, indicating a break event, it will remain asserted
until STPCLK# is deasserted. For additional information on the pending break
event functionality, including the identification of support of the feature and enable/
disable information, refer to volume 3 of the Intel Architecture Software Developer's
Manual and the Intel Processor Identification and the CPUID Instruction application
note.
GTLREF determines the signal reference level for AGTL+ input pins. GTLREF
should be set at 2/3 VCC. GTLREF is used by the AGTL+ receivers to determine if a
GTLREF
Input
signal is a logical 0 or logical 1. Refer to the Mobile Intel Pentium 4 Processor-M
and Intel 845MP/845MZ Chipset Platform Design Guide for more information.
Input/
Output
HIT# (Snoop Hit) and HITM# (Hit Modified) convey transaction snoop operation
results. Any system bus agent may assert both HIT# and HITM# together to
indicate that it requires a snoop stall, which can be continued by reasserting HIT#
and HITM# together.
HIT#
HITM#
Input/
Output
IERR# (Internal Error) is asserted by a processor as the result of an internal error.
Assertion of IERR# is usually accompanied by a SHUTDOWN transaction on the
processor system bus. This transaction may optionally be converted to an external
error signal (e.g., NMI) by system core logic. The processor will keep IERR#
asserted until the assertion of RESET#.
IERR#
Output
This signal does not have on-die termination and must be terminated on the
system board.
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Table 35. Signal Description (Sheet 5 of 8)
Name
Type
Description
IGNNE# (Ignore Numeric Error) is asserted to force the processor to ignore a
numeric error and continue to execute noncontrol floating-point instructions. If
IGNNE# is deasserted, the processor generates an exception on a noncontrol
floating-point instruction if a previous floating-point instruction caused an error.
IGNNE# has no effect when the NE bit in control register 0 (CR0) is set.
IGNNE#
Input
IGNNE# is an asynchronous signal. However, to ensure recognition of this signal
following an Input/Output write instruction, it must be valid along with the TRDY#
assertion of the corresponding Input/Output Write bus transaction.
INIT# (Initialization), when asserted, resets integer registers inside the processor
without affecting its internal caches or floating-point registers. The processor then
begins execution at the power-on Reset vector configured during power-on
configuration. The processor continues to handle snoop requests during INIT#
assertion. INIT# is an asynchronous signal and must connect the appropriate pins
of all processor system bus agents.
INIT#
Input
If INIT# is sampled active on the active to inactive transition of RESET#, then the
processor executes its Built-in Self-Test (BIST).
ITPCLKOUT[1:0] is an uncompensated differential clock output that is a delayed
copy of the BCLK[1:0], which is an input to the processor. This clock output can be
Output used as the differential clock into the ITP port that is designed onto the
motherboard. If ITPCLKOUT[1:0] outputs are not used, they must be terminated
properly. Refer to Section 2.5 for additional details and termination requirements.
ITPCLKOUT
[1:0]
ITP_CLK[1:0] are copies of BCLK that are used only in processor systems where
no debug port is implemented on the system board. ITP_CLK[1:0] are used as
ITP_CLK[1:0]
Input
BCLK[1:0] references for a debug port implemented on an interposer. If a debug
port is implemented in the system, ITP_CLK[1:0] are no connects in the system.
These are not processor signals.
LINT[1:0] (Local APIC Interrupt) must connect the appropriate pins of all APIC Bus
agents. When the APIC is disabled, the LINT0 signal becomes INTR, a maskable
interrupt request signal, and LINT1 becomes NMI, a nonmaskable interrupt. INTR
and NMI are backward compatible with the signals of those names on the Pentium
processor. Both signals are asynchronous.
LINT[1:0]
Input
Both of these signals must be software configured via BIOS programming of the
APIC register space to be used either as NMI/INTR or LINT[1:0]. Because the APIC
is enabled by default after Reset, operation of these pins as LINT[1:0] is the default
configuration.
LOCK# indicates to the system that a transaction must occur atomically. This signal
must connect the appropriate pins of all processor system bus agents. For a locked
sequence of transactions, LOCK# is asserted from the beginning of the first
transaction to the end of the last transaction.
Input/
Output
LOCK#
When the priority agent asserts BPRI# to arbitrate for ownership of the processor
system bus, it will wait until it observes LOCK# deasserted. This enables symmetric
agents to retain ownership of the processor system bus throughout the bus locked
operation and ensure the atomicity of lock.
MCERR# (Machine Check Error) is asserted to indicate an unrecoverable error
without a bus protocol violation. It may be driven by all processor system bus
agents.
MCERR# assertion conditions are configurable at a system level. Assertion options
are defined by the following options:
Enabled or disabled.
Input/
Output
MCERR#
Asserted, if configured, for internal errors along with IERR#.
Asserted, if configured, by the request initiator of a bus transaction after it
observes an error.
Asserted by any bus agent when it observes an error in a bus transaction.
For more details regarding machine check architecture, please refer to the IA-32
Software Developer’s Manual, Volume 3: System Programming Guide.
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Table 35. Signal Description (Sheet 6 of 8)
Name
Type
Description
The assertion of PROCHOT# (Processor Hot) indicates that the processor die
temperature has reached its thermal limit. See Section 6 for more details.
PROCHOT#
Output
PWRGOOD (Power Good) is a processor input. The processor requires this signal
to be a clean indication that the clocks and power supplies are stable and within
their specifications. ‘Clean’ implies that the signal will remain low (capable of
sinking leakage current), without glitches, from the time that the power supplies are
turned on until they come within specification. The signal must then transition
monotonically to a high state. Figure 15 illustrates the relationship of PWRGOOD to
the RESET# signal. PWRGOOD can be driven inactive at any time, but clocks and
power must again be stable before a subsequent rising edge of PWRGOOD. It
must also meet the minimum pulse width specification in Table 20, and be followed
by a 1 to 10 ms RESET# pulse.
PWRGOOD
Input
The PWRGOOD signal must be supplied to the processor; it is used to protect
internal circuits against voltage sequencing issues. It should be driven high
throughout boundary scan operation.
REQ[4:0]# (Request Command) must connect the appropriate pins of all processor
system bus agents. They are asserted by the current bus owner to define the
currently active transaction type. These signals are source synchronous to
ADSTB0#. Refer to the AP[1:0]# signal description for details on parity checking of
these signals.
Input/
Output
REQ[4:0]#
Asserting the RESET# signal resets the processor to a known state and invalidates
its internal caches without writing back any of their contents. For a power-on Reset,
RESET# must stay active for at least one millisecond after VCC and BCLK have
reached their proper specifications. On observing active RESET#, all system bus
agents will deassert their outputs within two clocks. RESET# must not be kept
asserted for more than 10 ms while PWRGOOD is asserted.
RESET#
RS[2:0]#
Input
Input
A number of bus signals are sampled at the active-to-inactive transition of RESET#
for power-on configuration. These configuration options are described in the
Section 7.1.
This signal does not have on-die termination and must be terminated on the
system board.
RS[2:0]# (Response Status) are driven by the response agent (the agent
responsible for completion of the current transaction), and must connect the
appropriate pins of all processor system bus agents.
RSP# (Response Parity) is driven by the response agent (the agent responsible for
completion of the current transaction) during assertion of RS[2:0]#, the signals for
which RSP# provides parity protection. It must connect to the appropriate pins of all
processor system bus agents.
RSP#
Input
A correct parity signal is high if an even number of covered signals are low and low
if an odd number of covered signals are low. While RS[2:0]# = 000, RSP# is also
high, since this indicates it is not being driven by any agent guaranteeing correct
parity.
SKTOCC# (Socket Occupied) will be pulled to ground by the processor. System
board designers may use this pin to determine if the processor is present.
SKTOCC#
Output
SLP# (Sleep), when asserted in Stop-Grant state, causes the processor to enter the
Sleep state. During Sleep state, the processor stops providing internal clock signals
to all units, leaving only the Phase-Locked Loop (PLL) still operating. Processors in
this state will not recognize snoops or interrupts. The processor will only recognize
the assertion of the RESET# signal, deassertion of SLP#, and assertion of DPSLP#
input while in Sleep state. If SLP# is deasserted, the processor exits Sleep state
and returns to Stop-Grant state, restarting its internal clock signals to the bus and
processor core units. If the BCLK input is stopped or if DPSLP# is asserted while in
the Sleep state, the processor will exit the Sleep state and transition to the Deep
Sleep state.
SLP#
Input
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Table 35. Signal Description (Sheet 7 of 8)
Name
Type
Description
SMI# (System Management Interrupt) is asserted asynchronously by system logic.
On accepting a System Management Interrupt, the processor saves the current
state and enter System Management Mode (SMM). An SMI Acknowledge
transaction is issued, and the processor begins program execution from the SMM
handler.
SMI#
Input
If SMI# is asserted during the deassertion of RESET# the processor will tristate its
outputs.
Assertion of STPCLK# (Stop Clock) causes the processor to enter a low power
Stop-Grant state. The processor issues a Stop-Grant Acknowledge transaction, and
stops providing internal clock signals to all processor core units except the system
bus and APIC units. The processor continues to snoop bus transactions and
service interrupts while in Stop-Grant state. When STPCLK# is deasserted, the
processor restarts its internal clock to all units and resumes execution. The
assertion of STPCLK# has no effect on the bus clock; STPCLK# is an
asynchronous input.
STPCLK#
Input
TCK (Test Clock) provides the clock input for the processor Test Bus (also known
as the Test Access Port).
TCK
TDI
Input
Input
TDI (Test Data In) transfers serial test data into the processor. TDI provides the
serial input needed for JTAG specification support.
TDO (Test Data Out) transfers serial test data out of the processor. TDO provides
the serial output needed for JTAG specification support.
TDO
Output
TESTHI[11]
TESTHI[10:8]
TESTHI[11], TESTHI[10:8], and TESTHI[5:0] must be connected to a VCC power
source through a resistor for proper processor operation. See Section 2.5 for more
details.
Input
TESTHI[5:0]
THERMDA
THERMDC
Other Thermal Diode Anode. See Section 6
Other Thermal Diode Cathode. See Section 6
Assertion of THERMTRIP# (Thermal Trip) indicates the processor junction
temperature has reached a level beyond which permanent silicon damage may
occur. Measurement of the temperature is accomplished through an internal
thermal sensor which is configured to trip at approximately 135°C. Upon assertion
of THERMTRIP#, the processor will shut off its internal clocks (thus halting program
execution) in an attempt to reduce the processor junction temperature. To protect
the processor, its core voltage (Vcc) must be removed following the assertion of
THERMTRIP#. See Figure 18 and Table 20 for the appropriate power down
sequence and timing requirements. Once activated, THERMTRIP# remains latched
until RESET# is asserted. While the assertion of the RESET# signal will deassert
THERMTRIP#, if the processor’s junction temperature remains at or above the trip
level, THERMTRIP# will again be asserted.
THERMTRIP# Output
TMS (Test Mode Select) is a JTAG specification support signal used by debug
tools.
TMS
Input
Input
Input
Input
TRDY# (Target Ready) is asserted by the target to indicate that it is ready to receive
a write or implicit writeback data transfer. TRDY# must connect the appropriate pins
of all system bus agents.
TRDY#
TRST#
VCCA
TRST# (Test Reset) resets the Test Access Port (TAP) logic. TRST# must be driven
low during power on Reset. This can be done with a 680 ohm pull-down resistor.
VCCA provides isolated power for the internal processor core PLL’s. Refer to the
Mobile Intel Pentium 4 Processor-M and Intel 845MP/845MZ Chipset Platform
Design Guide for complete implementation details.
V
CCIOPLL provides isolated power for internal processor system bus PLL’s. Follow the
guidelines for VCCA, and refer to the Mobile Intel Pentium 4 Processor-M and
Intel 845MP/845MZ Chipset Platform Design Guide for complete implementation
VCCIOPLL
Input
details.
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Table 35. Signal Description (Sheet 8 of 8)
Name
VCCSENSE
Type
Description
VCCSENSE is an isolated low impedance connection to processor core power (VCC). It
can be used to sense or measure power near the silicon with little noise.
Output
Independent 1.2-V supply must be routed to VCCVID pin for the Mobile Intel
Celeron Processor’s Voltage Identification circuit.
VCCVID
Input
VID[4:0] (Voltage ID) pins are used to support automatic selection of power supply
voltages (Vcc). Unlike some previous generations of processors, these are open
drain signals that are driven by the Mobile Intel Celeron Processor and must be
pulled up to 3.3 V (max.) with 1-Kohm resistors. The voltage supply for these pins
VID[4:0]
Output must be valid before the VR can supply Vcc to the processor. Conversely, the VR
output must be disabled until the voltage supply for the VID pins becomes valid.
The VID pins are needed to support the processor voltage specification variations.
See Table 3 for definitions of these pins. The VR must supply the voltage that is
requested by the pins, or disable itself.
VSSA
Input
VSSA is the isolated ground for internal PLLs.
SSSENSE is an isolated low impedance connection to processor core VSS. It can be
V
VSSSENSE
Output
used to sense or measure ground near the silicon with little noise.
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Thermal Specifications and Design Considerations
6 Thermal Specifications and
Design Considerations
In order to achieve proper cooling of the processor, a thermal solution (e.g., heat spreader, heat
pipe, or other heat transfer system) must make firm contact to the exposed processor die. The
processor die must be clean before the thermal solution is attached or the processor may be
damaged.
Table 36 provides the Thermal Design Power (TDP) dissipation and the minimum and maximum
TJ temperatures for the Mobile Intel Celeron Processor. A thermal solution should be designed to
ensure the junction temperature never exceeds the 100°C TJ specification while operating at the
Thermal Design Power. Additionally, a secondary failsafe mechanism in hardware would be
provided to shutdown the processor under catastrophic thermal conditions, as described in
Section 2.4.2. TDP is a thermal design power specification based on the worst case power
dissipation of the processor while executing publicly available software under normal operating
conditions at nominal voltages. Contact your Intel Field Sales Representative for further
information.
Table 36. Power Specifications for the Mobile Intel Celeron Processor
Symbol
Parameter
Min
Typ
Max
Unit
Notes
Thermal Design Power at
1.80 GHz & 1.30 V
1.70 GHz & 1.30 V
1.60 GHz & 1.30 V
1.50 GHz & 1.30 V
1.40 GHz & 1.30 V
W
At 100°C, Note 1
30.0
30.0
30.0
30.0
30.0
TDP
Auto Halt/Stop Grant/Sleep
Power at
PAH
PSGNT
PSLP
1.30 V
7.5
W
At 50°C, Note 2
Deep Sleep Power at
1.30 V
PDSLP
TJ
5.0
W
At 35°C, Note 2
Note 3
Junction Temperature
0
100
°C
NOTES:
1. TDP is defined as the worst case power dissipated by the processor while executing publicly available
software under normal operating conditions at nominal voltages that meet the load line specifications. The
TDP number shown is a specification based on ICC (maximum) at nominal voltages and indirectly tested by
this ICC (maximum) testing. TDP definition is synonymous with the Thermal Design Power (typical)
specification referred to in the previous EMTS. The Intel TDP specification is a recommended design point
and is not representative of the absolute maximum power the processor may dissipate under worst case
conditions.
1. Not 100% tested. These power specifications are determined by characterization of the processor currents at
higher temperatures and extrapolating the values for the temperature indicated.
1. The maximum junction temperature (TJ) is specified as the hottest location on the die. The Thermal Monitor’s
automatic mode is used to indicate that the maximum TJ has been reached. Refer to Section 6.1.1 for TJ
measurement guidelines (refer to Section 6.1.2 for Thermal Monitor details).
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Thermal Specifications and Design Considerations
6.1
Thermal Specifications
6.1.1
Thermal Diode
The Mobile Intel Celeron Processor incorporates two methods of monitoring die temperature, the
Thermal Monitor and the thermal diode. The Thermal Monitor (detailed in Section 6.1.2) must be
used to determine when the maximum specified processor junction temperature has been reached.
The second method, the thermal diode, can be read by an off-die analog/digital converter (a thermal
sensor) located on the motherboard, or a stand-alone measurement kit. The thermal diode may be
used to monitor the die temperature of the processor for thermal management or instrumentation
purposes but cannot be used to indicate that the maximum TJ of the processor has been reached.
Table 37 and Table 38 provide the diode interface and specifications.
Note: The reading of the thermal sensor connected to the thermal diode does not reflect the temperature
of the hottest location on the die (TJ). This is due to inaccuracies in the thermal diode, on-die
temperature gradients between the location of the thermal diode and the hottest location on the die,
and time based variations in the die temperature. Time based variations can occur since the
sampling rate of the sensor is much slower than the die level temperature changes.
The offset between the thermal diode based temperature reading and the hottest location of the die
(Thermal Monitor) may be characterized using the Thermal Monitor’s Automatic mode activation
of thermal control circuit. This temperature offset must be taken into account when using the
processor thermal diode to implement power management events.
Table 37. Thermal Diode Interface
Signal Name
Pin/Ball Number
Signal Description
THERMDA
THERMDC
B3
C4
Thermal diode anode
Thermal diode cathode
Table 38. Thermal Diode Specifications
Symbol
Parameter
Min
Typ
Max
Unit
Notes
IFW
n
Forward Bias Current
Diode Ideality Factor
Series Resistance
5
300
µA
1
1.0012
1.0021
3.86
1.0030
2, 3, 4
2, 3, 5
RT
ohms
NOTES:
1. Intel does not support or recommend operation of the thermal diode under reverse bias.
2. Characterized at 100°C.
3. Not 100% tested. Specified by design characterization.
4. The ideality factor, n, represents the deviation from ideal diode behavior as exemplified by the diode
equation:
I
FW=Is *(e(qVD/nkT) -1)
Where IS = saturation current, q = electronic charge, VD = voltage across the diode, k = Boltzmann Constant,
and T = absolute temperature (Kelvin).
5. The series resistance, RT, is provided to allow for a more accurate measurement of the diode junction
temperature. RT as defined includes the pins of the processor but does not include any socket resistance or
board trace resistance between the socket and the external remote diode thermal sensor. RT can be used by
remote diode thermal sensors with automatic series resistance cancellation to calibrate out this error term.
Another application is that a temperature offset can be manually calculated and programmed into an offset
register in the remote diode thermal sensors as exemplified by the equation:
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Thermal Specifications and Design Considerations
Terror = [RT*(N-1)*IFWmin]/[(nk/q)*ln N]
Where Terror = sensor temperature error, N = sensor current ration, k = Boltzmann Constant, q = electronic
charge.
6.1.2
Thermal Monitor
The Thermal Monitor feature found in the Mobile Intel Celeron Processor allows system designers
to design lower cost thermal solutions without compromising system integrity or reliability. By
using a factory-tuned, precision on-die thermal sensor, and a fast acting thermal control circuit
(TCC), the processor, without the aid of any additional software or hardware, can keep the
processor’s die temperature within factory specifications under nearly all conditions. Thus, the
Thermal Monitor allows the processor and system thermal solutions to be designed much closer to
the power envelopes of real applications instead of being designed to the much higher maximum
processor power envelopes.
Thermal Monitor controls the processor temperature by modulating (starting and stopping) the
processor core clocks. The processor clocks are modulated when the thermal control circuit (TCC)
is activated. Thermal Monitor uses two modes to activate the TCC: Automatic mode and On-
Demand mode. Automatic mode is required for the processor to operate within specifications
and must first be enabled via BIOS. Once automatic mode is enabled, the TCC will activate only
when the internal die temperature is very near the temperature limits of the processor. When TCC
is enabled, and a high temperature situation exists (i.e. TCC is active), the clocks will be modulated
by alternately turning the clocks off and on at a duty cycle specific to the processor (typically
30-50%). Cycle times are processor speed dependent and will decrease linearly as processor core
frequencies increase. Once the temperature has returned to a non-critical level, modulation ceases
and TCC goes inactive. A small amount of hysteresis has been included to prevent rapid active/
inactive transitions of the TCC when the processor temperature is near the trip point. Processor
performance will be decreased by approximately the same amount as the duty cycle when the TCC
is active, however, with a properly designed and characterized thermal solution, the TCC will only
be activated briefly when running the most power intensive applications in a high ambient
temperature environment.
For automatic mode, the duty cycle is factory configured and cannot be modified. Also, automatic
mode does not require any additional hardware, software drivers, or interrupt handling routines.
The TCC may also be activated via On-Demand mode. If bit 4 of the ACPI Thermal Monitor
Control Register is written to a "1", the TCC will be activated immediately, independent of the
processor temperature. When using On-Demand mode to activate the TCC, the duty cycle of the
clock modulation is programmable via bits 3:1 of the same ACPI Thermal Monitor Control
Register. In automatic mode, the duty cycle is fixed, however in On-Demand mode, the duty cycle
can be programmed from 12.5% on/ 87.5% off, to 87.5% on/12.5% off in 12.5% increments. On-
Demand mode may be used at the same time Automatic mode is enabled, however, if the system
tries to enable the TCC via On-Demand mode at the same time automatic mode is enabled AND a
high temperature condition exists, the duty cycle of the automatic mode will override the duty
cycle selected by the On-Demand mode.
An external signal, PROCHOT# (processor hot) is asserted when the processor die temperature has
reached its thermal limit. If the TCC is enabled (note that the TCC must be enabled for the
processor to be operating within spec), TCC will be active when the PROCHOT# signal is active.
The temperature at which the thermal control circuit activates is not user configurable and is not
software visible. Bus snooping and interrupt latching are active while the TCC is active.
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Besides the thermal sensor and TCC, the Thermal Monitor feature also includes one ACPI register,
performance monitoring logic, bits in three model specific registers (MSR), and one I/O pin
(PROCHOT#). All are available to monitor and control the state of the Thermal Monitor feature.
Thermal Monitor can be configured to generate an interrupt upon the assertion or de-assertion of
PROCHOT#.
If automatic mode is disabled, the processor will be operating out of specification. Regardless of
enabling of the automatic or On-Demand modes, in the event of a catastrophic cooling failure, the
processor will automatically shut down when the silicon has reached a temperature of
approximately 135 °C. At this point the system bus signal THERMTRIP# will go active and stay
active until RESET# has been initiated. THERMTRIP# activation is independent of processor
activity and does not generate any bus cycles. If THERMTRIP# is asserted, processor core voltage
(VCC) must be removed within the timeframe defined in Table 20.
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Configuration and Low Power Features
7 Configuration and Low Power
Features
7.1
Power-On Configuration Options
Several configuration options can be configured by hardware. The Mobile Intel Celeron Processor
samples its hardware configuration at reset, on the active-to-inactive transition of RESET#. For
specifications on these options, please refer to Table 39.
Frequency determination functionality will exist on engineering sample processors which means
that samples can run at varied frequencies. Production material will have the bus to core ratio
locked during manufacturing and can only be operated at the rated frequency.
The sampled information configures the processor for subsequent operation. These configuration
options cannot be changed except by another reset. All resets reconfigure the processor.
Table 39. Power-On Configuration Option Pins
Configuration Option
Pin1
Output tristate
SMI#
INIT#
A7#
Execute BIST
In Order Queue pipelining (set IOQ depth to 1)
Disable MCERR# observation
Disable BINIT# observation
APIC Cluster ID (0-3)
A9#
A10#
A[12:11]#
A15#
Disable bus parking
Symmetric agent arbitration ID
BR0#
NOTE: Asserting this signal during RESET# will select the corresponding option.
7.2
Clock Control and Low Power States
The use of AutoHALT, Stop-Grant, Sleep, and Deep Sleep states is allowed in Mobile Intel Celeron
Processor based systems to reduce power consumption by stopping the clock to internal sections of
the processor, depending on each particular state. See Figure 33 for a visual representation of the
processor low-power states.
7.2.1
Normal State
This is the normal operating state for the processor.
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7.2.2
AutoHALT Powerdown State
AutoHALT is a low-power state entered when the processor executes the HALT instruction. The
processor will transition to the Normal state upon the occurrence of SMI#, BINIT#, INIT#,
LINT[1:0] (NMI, INTR), or PSB interrupt message. RESET# will cause the processor to
immediately initialize itself.
The return from a System Management Interrupt (SMI) handler can be to either Normal Mode or
the AutoHALT Powerdown state. See the Intel Architecture Software Developer's Manual, Volume
III: System Programmer's Guide for more information.
The system can generate a STPCLK# while the processor is in the AutoHALT Powerdown state.
When the system deasserts the STPCLK# interrupt, the processor will return execution to the
HALT state.
While in AutoHALT Powerdown state, the processor will process bus snoops.
Figure 33. Clock Control States
SLP# asserted
STPCLK# asserted
Stop
Grant
Normal
Sleep
STPCLK# de-asserted
SLP# de-asserted
STPCLK#
asserted
halt
break
DPSLP#
de-asserted
DPSLP#
asserted
snoop
serviced
HLT
snoop
occurs
STPCLK#
de-asserted
instruction
snoop
occurs
HALT/
Grant
Snoop
Deep
Sleep
Auto Halt
snoop
serviced
V0001-04
Halt break - A20M#, BINIT#, INIT#, INTR, NMI, PREQ#, RESET#, SMI#, or APIC interrupt
7.2.3
Stop-Grant State
When the STPCLK# pin is asserted, the Stop-Grant state of the processor is entered 20 bus clocks
after the response phase of the processor-issued Stop Grant Acknowledge special bus cycle.
Since the AGTL+ signal pins receive power from the system bus, these pins should not be driven
(allowing the level to return to VCC) for minimum power drawn by the termination resistors in this
state. In addition, all other input pins on the system bus should be driven to the inactive state.
BINIT# will not be serviced while the processor is in Stop-Grant state. The event will be latched
and can be serviced by software upon exit from the Stop-Grant state.
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RESET# will cause the processor to immediately initialize itself, but the processor will stay in
Stop-Grant state. A transition back to the Normal state will occur with the deassertion of the
STPCLK# signal. When re-entering the Stop-Grant state from the Sleep state, STPCLK# should
only be deasserted ten or more bus clocks after the deassertion of SLP#.
A transition to the HALT/Grant Snoop state will occur when the processor detects a snoop on the
system bus (see Section 7.2.4). A transition to the Sleep state (see Section 7.2.5) will occur with the
assertion of the SLP# signal.
While in the Stop-Grant State, SMI#, INIT#, BINIT# and LINT[1:0] will be latched by the
processor, and only serviced when the processor returns to the Normal State. Only one occurrence
of each event will be recognized upon return to the Normal state.
While in Stop-Grant state, the processor will process a system bus snoop.
7.2.4
7.2.5
HALT/Grant Snoop State
The processor will respond to snoop transactions on the system bus while in Stop-Grant state or in
AutoHALT Power Down state. During a snoop transaction, the processor enters the HALT/Grant
Snoop state. The processor will stay in this state until the snoop on the system bus has been
serviced (whether by the processor or another agent on the system bus). After the snoop is serviced,
the processor will return to the Stop-Grant state or AutoHALT Power Down state, as appropriate.
Sleep State
The Sleep state is a low power state in which the processor maintains its context, maintains the
phase-locked loop (PLL), and has stopped all internal clocks. The Sleep state can only be entered
from Stop-Grant state. Once in the Stop-Grant state, the processor will enter the Sleep state upon
the assertion of the SLP# signal. The SLP# pin should only be asserted when the processor is in the
Stop Grant state. SLP# assertions while the processor is not in the Stop-Grant state is out of
specification and may result in unapproved operation.
Snoop events that occur while in Sleep State or during a transition into or out of Sleep state will
cause unpredictable behaviour.
In the Sleep state, the processor is incapable of responding to snoop transactions or latching
interrupt signals. No transitions or assertions of signals (with the exception of SLP#, DPSLP# or
RESET#) are allowed on the system bus while the processor is in Sleep state. Any transition on an
input signal before the processor has returned to Stop-Grant state will result in unpredictable
behaviour.
If RESET# is driven active while the processor is in the Sleep state, and held active as specified in
the RESET# pin specification, then the processor will reset itself, ignoring the transition through
Stop-Grant State. If RESET# is driven active while the processor is in the Sleep State, the SLP#
and STPCLK# signals should be deasserted immediately after RESET# is asserted to ensure the
processor correctly executes the Reset sequence.
While in the Sleep state, the processor is capable of entering an even lower power state, the Deep
Sleep state, by asserting the DPSLP# pin. (See Section 7.2.6.) Once in the Sleep or Deep Sleep
states, the SLP# pin must be de-asserted if another asynchronous system bus event needs to occur.
The SLP# pin has a minimum assertion of one BCLK period.
When the processor is in Sleep state, it will not respond to interrupts or snoop transactions.
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7.2.6
Deep Sleep State
Deep Sleep state is a very low power state the processor can enter while maintaining context. Deep
Sleep state is entered by asserting the DPSLP# pin. The DPSLP# pin must be de-asserted to re-
enter the Sleep state. A period of 30 microseconds (to allow for PLL stabilization) must occur
before the processor can be considered to be in the Sleep State. Once in the Sleep state, the SLP#
pin can be deasserted to re-enter the Stop-Grant state.
The clock may be stopped when the processor is in the Deep Sleep state in order to support the
ACPI S1 state. The clock may only be stopped after DPSLP# is asserted and must be restarted
before DPSLP# is deasserted. To provide maximum power conservation when stopping the clock
during Deep Sleep, hold the BLCK0 input at VOL and the BCLK1 input at VOH
.
While in Deep Sleep state, the processor is incapable of responding to snoop transactions or
latching interrupt signals. No transitions of signals are allowed on the system bus while the
processor is in Deep Sleep state. Any transition on an input signal before the processor has returned
to Stop-Grant state will result in unpredictable behaviour.
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Debug Tools Specifications
8 Debug Tools Specifications
Please refer to the Mobile Intel Pentium 4 Processor-M and Intel 845MP/845MZ Chipset
Platform Design Guide for information regarding debug tools specifications.
8.1
Logic Analyzer Interface (LAI)
Intel is working with two logic analyzer vendors to provide logic analyzer interfaces (LAIs) for use
in debugging Mobile Intel Celeron Processor systems. Tektronix* and Agilent* should be
contacted to get specific information about their logic analyzer interfaces. The following
information is general in nature. Specific information must be obtained from the logic analyzer
vendor.
Due to the complexity of Mobile Intel Celeron Processor systems, the LAI is critical in providing
the ability to probe and capture system bus signals. There are two sets of considerations to keep in
mind when designing a Mobile Intel Celeron Processor system that can make use of an LAI:
mechanical and electrical.
8.1.1
8.1.2
Mechanical Considerations
The LAI is installed between the processor socket and the Mobile Intel Celeron Processor. The LAI
pins plug into the socket, while the Mobile Intel Celeron Processor pins plug into a socket on the
LAI. Cabling that is part of the LAI egresses the system to allow an electrical connection between
the Mobile Intel Celeron Processor and a logic analyzer. The maximum volume occupied by the
LAI, known as the keepout volume, as well as the cable egress restrictions, should be obtained
from the logic analyzer vendor. System designers must make sure that the keepout volume remains
unobstructed inside the system.
Electrical Considerations
The LAI will also affect the electrical performance of the system bus; therefore, it is critical to
obtain electrical load models from each of the logic analyzer vendors to be able to run system level
simulations to prove that their tool will work in the system. Contact the logic analyzer vendor for
electrical specifications and load models for the LAI solution they provide.
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