RT3070_技术文档

RT3070

Datasheet

Preliminary

Revision September 25, 2008

Application

•IEEE802.11 b/g/n Wireless Local Area Networks

•USB 2.0 Wi‐Fi Dongle

standards, delivers reliable, cost‐effective,

Features

throughput from an extended distance. Optimized RF

architecture and baseband

• CMOS Technology with RF, Baseband, and MAC

Integrated.

• 1T1R Mode with 150Mbps PHY Rate for Both

Transmit and Receiving.

• Legacy and High Throughput Modes

• 20MHz/40MHz Bandwidth

• Reverse Direction Grant Data Flow and Frame

Aggregation

• WEP 64/128, WPA, WPA2,TKIP, AES

• QoS‐WMM, WMM‐PS

• WPS,PIN,PBC

algorithms provide superb performance and low

power consumption. Intelligent MAC design.

deploys a high efficient USB engine and

hardware data processing accelerators without

overloading the host processor. The RT3070 is designed to

support standard based features in the areas of security,

quality of service and international regulation, giving end

users the greatest performance anytime in any

circumstance.

• Multiple BSSID Support

• USB 2.0

• International Regulation ‐ 802.11d + h

• Cisco CCX Support

Order Information

• Bluetooth Co‐existence

Part Number

RT3070L

Temp Range

Package

• Low Power with Advanced Power Management

• Operating Systems ‐ Windows XP 32/64, 2000,

Vista 32/64 , Linux, Macintosh

‐10~85℃

Green/RoHS

Compliant 76LD

QFN (9mmx9mm)

Ralink Technology, Corp. (Taiwan)

5th F. No. 36,Taiyuan St, Jhubei City, Hsin‐Chu,

Taiwan, R.O.C.

Tel: 886‐3‐567‐8868 Fax: 886‐3‐567‐8818

Product Description

The RT3070 is a highly integrated MAC/BBP and 2.4

GHz RF single chip with 150Mbps PHY rate supporting.

It fully complies with IEEE 802.11n draft 3.0 and IEEE

802.11 b/g feature rich wireless connectivity at high

Ralink Technology, Corp. (USA) Cupertino, CA9501420833

Stevens Creek Blvd. Ste 200

Tel: (408) 725‐8070Fax:(408)725‐8069

http://www.ralinktech.com

Block Diagram

RF_RF2G_INP/

RF

USB bus

ADC

USB

MAC/

Packet

Buffer/

RF_RF2G_INN

receiver

Baseband

EEPROM/

GPIO/LED

Encrption

Engine

System

Control

RF

transmitter

RF_RF2G_OUTP

DAC

digital controlled

RF

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RT3070

Datasheet

Preliminary

Revision September 25, 2008

1. Pin Layout

RF_RF2G_INP

RF_RF2G_INN

RF_RF_V12A

RF_RF2G_OUTP

RF_IO_V33A

RF_PA_PE

1

2

3

4

5

6

7

8

9

10

11

12

13

14

15

16

17

18

19

57

56

55

54

53

52

51

50

49

48

47

46

45

44

43

42

41

40

39

ADC_VCC12D

ADC_VREF025P

ADC_VREF025N

ADC_VREF

ADC_V33A

BASE_2_V12A

BASE_TRX_IP

BASE_TRX_IN

BASE_TRX_QP

BASE_TRX_QN

PLLDVDD

PLLAVDD

VCCIO

VDD

SPISO

SPISI

SPISCK

SPICSN

RF_TSSI_IN

BASE_1_V12A

LDO_CORE_VO12

LDO_CORE_VI15

RST_N

LDO_FUSE_VO25

LDO_FUSE_VI33

VDD

TR_SW0

TR_SWN0

EXT_PM_MODE

CPU_PFL_CSN

LED_ACT_N

RT3070

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Datasheet

Preliminary

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2. Pin Description

Name

Type*

Description

RF TX/RX: 3 pins

Rx RF input

1

2

4

RF_RF2G_INP

RF_RF2G_INN

RF_RF2G_OUTP

I

Transmit RF output (2.4GHz)

O

RF Power: 16 pins

1.2V power supply for RF circuits

3.3V power supply for RF IO

3

5

RF_RF_V12A

P

RF_IO_V33A

BASE_1_V12A

BASE_2_V12A

ADC_V33A

1.2V power supply for baseband circuits

3.3V analog power supply for ADC

8

51

52

1.2V digital power supply for ADC and DAC

1.2V analog power supply for ADC and DAC

3.3V power supply for bandgap reference

1.2V power supply for digital CMOS divider of PLL

1.2V power supply for prescaler of PLL

1.2V power supply for LO buffers

56,57

ADC_VCC12D

58,59,62 ADC_VCC12A

68

BG_V33A

71

PLL_DIV_V12A

PLL_PRE_V12A

VCO_LO_V12A

VCO_VCO_V12A

RF_LO_V12A

72

74

1.2V power supply for internal VCO

75

1.2V power supply for LO buffers

76

RF LDO: 3 pins

63

1.2V output of LDO1 (supply up to 100mA)

LDO_OUT1_V12A

LDO_IN12_VX

O

P

1.5/1.8V power supply for LDO1 and LDO2 (consuming up to

120mA)

64

1.2V output of LDO2 (supply up to 20mA)

65

RF PLL: 2 pins

69

LDO_OUT2_V12A

O

Crystal inputs

PLL_X2

PLL_X1

I

Crystal inputs or external crystal oscillator input (PLL_X1

only)

70

RF REF: 8 pins

Main ADC reference voltage

53

54

55

60

61

66

67

73

ADC_VREF

IO

Auxiliary ADC reference voltages

Bandgap voltage

ADC_VREF025N

ADC_VREF025P

ADC_VREFN

ADC_VREFP

BG_VBG

12K ohm precision resistor for reference current

Control voltage of internal VCO

BG_RES_12K

PLL_VC_CAP

RF Misc.: 5 pins

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Datasheet

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Transmit signal strength indicator input from power

amplifier

7

RF_TSSI_IN

I

Baseband Q differential input/output

47

48

49

50

BASE_TRX_QN

BASE_TRX_QP

BASE_TRX_IN

BASE_TRX_IP

IO

Baseband Q differential input/output

Baseband I differential input/output

Digital LDO: 4 pins

1.2V LDO power output.

9

LDO_CORE_VO12

O

P

1.5V power supply for internal LDO

2.5V LDO power output

10

12

13

LDO_CORE_VI15

LDO_FUSE_VO25

LDO_FUSE_VI33

O

P

3.3V power supply for internal LDO

RF Control: 4 pins

Enable control output to external power amplifier

Positive signal of RX and TX switching control

Negative signal of RX and TX switching control

Enable control output to external LNA

6

RF_PA_PE

O

15

TR_SW0

TR_SWN0

LNA_PE

16

25

LED: 2 pins

For driving the LED when the wireless device is transmitting

For driving the LED when the wireless device is active

19

LED_ACT_N

O

20

LED_RDYG_N

GPIO: 4 pins

26

GPIO3

GPIO2

GPIO1

GPIO0

IO

GPIO

27

28

29

USB: 5 pins

Connect to external 8.2K resistor

(the 8.2K resistor connects one end to VRES and the other

end to PCB ground)

34

VRES

IO

3.3V USB power

35

36

37

38

VDDA

PADM

PADP

VDDL

P

IO

P

D‐ line of USB 2.0

D+ line of USB 2.0

1.2V USB power

EEPROM: 4 pins

39

40

41

42

SPICSN

O

I

EEPROM chip select

EEPROM clock

SPISCK

SPISI

serial data to EEPROM

serial data from EEPROM

SPISO

PLL Power: 2 pins

45

46

PLLAVDD

PLLDVDD

P

1.2V PLL power

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Datasheet

Preliminary

Revision September 25, 2008

Core Power: 4 pins

14,21,33,43 VDD

IO Power: 2 pins

P

1.2V core power

3.3V IO power

22,44

VCCIO

Misc.: 8 pins

0: reset the whole chip

1: normal function active

1: enable test mode. For normal function, tie to GND.

11

23

24

RST_N

I

TESTEN

1: use internal e‐fuse

SEL_EFUSE

0: use external EEPROM

1: use external program memory

0: use internal ROM

17

18

30

EXT_PM_MODE

CPU_PFL_CSN

USB_SUSPM

I

Parallel flash chip select

O

0: USB is in suspended state

1: USB is in active state

1: use 12MHz external clock for USB PHY

0: use internal clock. For normal function, tie to GND

External clock input. Enable by setting SEL_EXT_CLK = 1.

For normal function, tie to GND.

31

32

SEL_EXT_CLK

CLK_EXT

I

GND: exposed pad

*Notation of Type:

I

O

: input

: output

IO : bi‐direction

: power

P

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Datasheet

Preliminary

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3. Maximum Ratings, Operation Conditions and Electrical Characteristics

3.1. Absolute Maximum Ratings

Core Supply Voltage.…………………………………………………………………………………………………………………………….1.26V

I/O Supply Voltage …………………………………………………………………………………………………………………………….…3.46V

Input, Output or I/O Voltage .………………………………………………..………………………………… GND –0.3V to Vcc+0.3V

3.2. Thermal Information

Thermal ResistanceꢀθJA (℃/W) in free air for QFN (9mmx9mm) package…….……………….…….……26 °C /W

Thermal ResistanceꢀθJC (℃/W) in free air for QFN (9mmx9mm) package…….………………………….…6 °C /W

Max case temperature………………………………………………………………………………………………………………………. 115°C

Maximum Junction Temperature (Plactic Package) …………………………………………………………….……………….125°C

Peak package body temperature ………………………………..………………………………………….……………………………250°C

3.3. Operating Conditions

Ambient Temperature Range …………………………………………………………….…….………………………………..‐10 to 85°C

Core Supply Voltage …………………………………….…………………….……………..…………………………………………1.2V +/‐ 5%

I/O Supply Voltage ……………………………………….………………….…………………………………………………………..3.3V +/‐ 5%

3.4. Storage Condition

Calculated shelf life in sealed bag: 12 months among 0~40^oC and < 90% relative humidity (RH) storage

condition.

After bag is opened, devices that subjected to solder reflow or other high temperature process must follow

below constrains:

a) Mounted within 168‐hours of factory conditions < 30 ^oC/60%RH

b) Humidity for storage needs to control at < 10% RH

c) Baking is necessary if customer expose the component to air over 168 hrs, baking condition: 125°C / 8hrs

3.5. Maximum Lead Temperature (Soldering 10s)…………………….....…………………………………….....……….. 260°C

3.6. DC Electrical Characteristics

Parameters

3.3V Supply Voltage

1.2V Supply Voltage

Receiving

Symbo

Vcc33

Vcc12

Conditions

Min

3.14

1.14

Typ

3.3

1.2

Max

3.46

1.26

Unit

V

HT40 MCS7

3.3V Current Consumption

1.2V Current Consumption

Transmission

Icc33rx

Icc12rx

37

mA

HT40 MCS7

243

HT40 MCS7

3.3V Current Consumption

1.2V Current Consumption

Icc33tx

Icc12tx

31

mA

124

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Datasheet

Preliminary

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3.7. AC Electrical Characteristics

3.7.1. RF Receiver

f_RF= 2437MHz, f_baseband= 5MHz, unless otherwise specified.

Parameters

Conditions

Min

2400

92

Typ

90

Max

2500

100

Unit

RF Frequency Range

MHz

lna_gain<1:0> = 11

lna_gain<1:0> = 10

lna_gain<1:0> = 01

Conversion Voltage Gain

(agc<5:1> = 11111)

74

61

dB

Gain Variation over RF

Frequency

lna_gain<1:0> = 11

1

lna_gain<1:0> = 11

lna_gain<1:0> = 10

lna_gain<1:0> = 01

lna_gain<1:0> = 11, agc<5:1> = 11111

lna_gain<1:0> = 11

lna_gain<1:0> = 10

lna_gain<1:0> = 01

RF to Baseband Filter Input

RF Input

316

50

Baseband Output Amplitude

(Pin = ‐90 dBm, AGC code =

11111)

mV

dB

11.2

5

Double‐Sideband Noise Figure

‐30

‐16

0

Input P1dB

dBm

LNA Gain Switching Time

LO Leakage

0.1

μs

dBm

3.7.2. 2.2 RF Transmitter

f_RF= 2437MHz, f_LO= 3256MHz, f_baseband= 5MHz, unless otherwise specified.

Parameters

Conditions

Min

2400

Typ

Max

2500

Unit

MHz

dBm

RF Frequency Range

Output Power (OFDM)

Output Power (CCK)

Vin(rms)=45mV, ALC Code = 11000

Vin(rms)=90mV, ALC Code = 11000

‐6

0

Output Power Variation over

RF Frequency

dB

1

dBm

Output P1dB

3

‐48

‐141

30

dBc

ACPR (OFDM)

Pout=‐6dBm, OFDM, 10MHz offset

Pout=‐6dBm, ALC Code = 10010

Pout=‐6dBm

‐45

dBm/Hz

dBc

Output Noise Floor

LO Suppression

dBc

Carrier Suppression

Single‐Sideband Suppression

Tx ALC Gain Control Step

30

dBc

2f_LO‐ f_RF

35

40

dB/step

5‐bit control = 32 levels

0.5

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4. Register map

0000 h

USB controller (200h)

SCH/DMA register (200h)

SYS/PBF/FCE/MISC register (400h)

Reserved (800h)

0200 h

0400 h

0800 h

1000 h

1800 h

2000 h

4000 h

distributed

register

MAC register (800h)

SRAM (2KB)

SRAM (8KB)

MAC search table(800h)

Program memory (2000h)

MAC key table (2600h)

FCE table (1000h)

SRAM

(16KB)

CIS (100h)

NULL frame (100h)

Beacon frame (800h)

8000 h

Packet buffer

(8000 h)

SRAM

(32KB)

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4.1.SCH registers

WMM_AIFSN_CFG (offset:0x0214,default :0x00000000)

Bits

Type Name

Description

Init Value

31:16

Reserved

15:12 RW

11:8 RW

AIFSN3

AIFSN2

AIFSN1

AIFSN0

WMM parameter AIFSN3

WMM parameter AIFSN2

WMM parameter AIFSN1

WMM parameter AIFSN0

4’h0

7:4

3:0

RW

WMM_CWMIN_CFG (offset:0x0218,default :0x00000000)

Bits

Type Name

Description

Init Value

31:16

Reserved

15:12 RW

11:8 RW

CW_MIN3

CW_MIN2

CW_MIN1

CW_MIN0

WMM parameter Cw_min3

WMM parameter Cw_min2

WMM parameter Cw_min1

WMM parameter Cw_min0

4’h0

7:4

3:0

RW

WMM_CWMAX_CFG (offset:0x021C,default :0x00000000)

Bits

Type Name

Description

Init Value

31:16

Reserved

15:12 RW

11:8 RW

CW_MAX3

CW_MAX2

CW_MAX1

CW_MAX0

WMM parameter Cw_max3

WMM parameter Cw_max2

WMM parameter Cw_max1

WMM parameter Cw_max0

4’h0

7:4

3:0

RW

WMM_TXOP0_CFG (offset:0x0220,default :0x00000000)

Bits

31:16 RW

15:0 RW

Type Name

Description

WMM parameter TXOP1

WMM parameter TXOP0

Init Value

16’h0

TXOP1

TXOP0

WMM_TXOP1_CFG (offset:0x0224,default :0x00000000)

Bits

31:16 RW

15:0 RW

Type Name

Description

WMM parameter TXOP3

WMM parameter TXOP2

Init Value

16’h0

TXOP3

TXOP2

GPIO_CTRL (offset:0x0228,default :0x0000FF00)

Bits

31:16

15:8 RW

Type Name

Description

Reserved

GPIO direction

0: Output

1: Input

Init Value

8’hFF

GPIO_D

7:0

RW

GPIO_O

GPIO data

8’h00

USB_DMA_CFG (offset:0x02A0,default :0x00000000)

Bits

31

30

Type Name

Description

USB DMA TX FSM busy

USB DMA RX FSM busy

Init Value

0

R

TX_BUSY

RX_BUSY

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29:24

23

22

21

20

R

EPOUT_VLD

OUT endpoint data valid

USB DMA TX enable

USB DMA RX enable

RX bulk aggregation enable

Halt TXOP count down when TX buffer is full.

0: disable

0

R/W UDMA_TX_EN

R/W UDMA_RX_EN

R/W RX_AGG_EN

R/W TXOP_HALT

1: enable

19

18:17

16

15:8 RW

7:0 RW

R/W TX_CLEAR

Clear USB DMA TX path

Reserved

USB PHY watch‐dog enable

RX bulk aggregation limit. Unit is 1024 bytes

0

R/W PHY_WD_EN

0

00

RX_AGG_LMT

RX_AGG_TO

RX bulk aggregation time‐out count. Unit is 1μs

US_CYC_CNT (offset:0x02A4,default :0x00F00021)

Bits Type Name

31:25

Description

Reserved

Init Value

R/W TEST_EN

R/W TEST_SEL

0

24

Test mode enable

Test mode selection

Reserved

8’hf0

23:16

15:9

8

R/W BT_MODE_EN

RW US_CYC_CNT

0

Blue‐tooth mode enable

7:0

Clock cycle count in 1μs. It’s dependent on the interface 8’h21

clock rate. For PCI 33, set 8’h21. For PCI express, set

8’h7D. For USB, set 8’h1E.

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4.2. PBF registers

SYS_CTRL (offset: 0x0400,default :0x00002000)

Bits

31:18

17

Type Name

Description

Reserved

Init Value

0

R/W PBF_MSEL

Packet buffer memory access selection.

0: address 0x8000 – 0xFFFF mapping to lower 32kB of packet

buffer.

1: address 0x8000 – 0xBFFF mapping to higher 16kB of

packet buffer.

16

R/W HST_PM_SEL

R/W CAP_MODE

Host program ram write selection. This bit is only for

PCI/PCIe mode.

Reserved

Packet buffer capture mode.

0: packet buffer in normal mode.

1: packet buffer in BBP capture mode.

PCI and PCIE mode: PCI PME OEN

USB mode: 1: force TR_PE=0, RF_PE = 0. 0: normal function.

MAC/PBF clock source selection.

0: from PLL

0

15

14

13

12

R/W PME_OEN

R/W CLKSELECT

1

0

1: from 40MHz clock input

11

10

9

R/W PBF_CLKEN

R/W MAC_CLK_EN

R/W DMA_CLK_EN

PBF clock enable.

MAC clock enable.

DMA clock enable.

0

8

Reserved

7

R/W MCU_READY

MCU ready. 8051 writes ‘1’ to this bit to inform the host

internal MCU is ready.

0

6:5

4

Reserved

R/W ASY_RESET

R/W PBF_RESET

R/W MAC_RESET

R/W DMA_RESET

W1C MCU_RESET

ASYNC interface reset. Writing ‘1’ to this bit will put ASYNC

into reset state.

PBF hardware reset. Writing ‘1’ to this bit will put the PBF

into reset state.

MAC hardware reset. Writing ‘1’ to this bit will put the MAC 0

into reset state.

DMA hardware reset. Write ‘1’ to this bit to put DMA into

reset state.

0

3

2

1

0

MCU hardware reset. This bit will be automatically cleared

after several clock cycles.

0

HOST_CMD (offset: 0x0404,default :0x00000000)

Bits

31:0

Type Name

R/W HST_CMD

Description

Init Value

0

Host command code. The host writes this register and

triggers an interruption to 8051.

PBF_CFG (offset: 0x0408,default :0x00F40016)

Bits

31:27

Type Name

Description

Reserved

Init Value

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26:24 R/W NULL2_SEL

NULL2 frame buffer selection (reuse beacon buffer).

0: use beacon #0 buffer (address set by 0x42C[7:0])

1: use beacon #1 buffer (address set by 0x42C[15:8])

2: use beacon #2 buffer (address set by 0x42C[23:16])

3: use beacon #3 buffer (address set by 0x42C[31:24])

4: use beacon #4 buffer (address set by 0x430[7:0])

5: use beacon #5 buffer (address set by 0x430[15:8])

6: use beacon #6 buffer (address set by 0x430[23:16])

7: use beacon #7 buffer (address set by 0x430[31:24])

Queue depth of Tx1Q. The maximum number is 7.

Queue depth of Tx2Q. The maximum number is 20.

NULL0 frame auto mode. In this mode, all TXQ2 will be

enabled after NULL0 frame transmitted.

3’h0

23:21 R/W TX1Q_NUM

20:16 R/W TX2Q_NUM

3’h7

5’h14

0

15

14

13

R/W NULL0_MODE

R/W NULL1_MODE

R/W RX_DROP_MODE

0: disable

1: enable

NULL1 frame auto mode. In this mode, all TXQ (0/1/2) will

be disabled after NULL1 frame transmitted.

0: disable

1: enable

0

Rx drop mode. When set, PBF will drop Rx packet before

into DMA.

0: normal mode

1: drop mode

12

11

10

9

R/W TX0Q_MODE

R/W TX1Q_MODE

R/W TX2Q_MODE

R/W RX0Q_MODE

R/W HCCA_MODE

Tx0Q operation mode.

0: auto mode

1: manual mode

Tx1Q operation mode.

0: auto mode

1: manual mode

Tx2Q operation mode.

0: auto mode

1: manual mode

Rx0Q operation mode.

0: auto mode

0

1: manual mode

HCCA auto mode. In this mode, TXQ1 will be enabled when

is CF‐POLL arriving.

0: disable

8

1: enable

7:5

4

Reserved

Tx0Q enable

0: disable

1: enable

Tx1Q enable

0: disable

1: enable

Tx2Q enable

R/W TX0Q_EN

R/W TX1Q_EN

R/W TX2Q_EN

1

0

1

3

2

0: disable

1: enable

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1

0

R/W RX0Q_EN

Rx0Q enable

0: disable

1: enable

Reserved

1

MAX_PCNT (offset: 0x040C,default :0x1F3F9F9F)

Bits

Type Name

Description

Init Value

8’h1f

8’h3f

8’h9f

31:24 R/W MAX_TX0Q_PCNT

23:16 R/W MAX_TX1Q_PCNT

15:8

7:0

Maximum buffer page count of Tx0Q.

Maximum buffer page count of Tx1Q.

Maximum buffer page count of Tx2Q.

Maximum buffer page count of Rx0Q.

R/W MAX_TX2Q_PCNT

R/W MAX_RX0Q_PCNT

BUF_CTRL (offset:0x0410,default :0x00000000)

Bits

31:12

11

10

9

Type Name

Description

Reserved

Init Value

W1C WRITE_TX0Q

W1C WRITE_TX1Q

W1C WRITE_TX2Q

W1C WRITE_RX0Q

W1C NULL0_KICK

Manual write Tx0Q.

Manual write Tx1Q.

Manual write Tx2Q

Manual write Rx0Q

Start to send the NULL0 frame. This bit will be cleared after

the NULL0 frame is transmitted.

Start to send the NULL1 frame. This bit will be cleared after

the NULL1 frame is transmitted.

Buffer reset.

0

8

7

0

6

W1C NULL1_KICK

0

5

4

W1C BUF_RESET

W1C NULL2_KICK

0

Start to send NULL2 frame. This bit will be cleared after

NULL1 frame is transmitted.

3

2

1

W1C READ_TX0Q

W1C READ_TX1Q

W1C READ_TX2Q

Manual read Tx0Q.

Manual read Tx1Q.

Manual read Tx2Q

0

W1C READ_RX0Q

Manual read Rx0Q

0

MCU_INT_STA (offset:0x0414,default :0x00000000)

Bits

31:28

27

26

25

24

23

22

21

20

19

18

17

Type

Name

Description

Reserved

MAC interrupt 11: Reserved

MAC interrupt 10: Reserved

Init Value

R/W

MAC_INT_11

MAC_INT_10

MAC_INT_9

MAC_INT_8

MAC_INT_7

MAC_INT_6

MAC_INT_5

MAC_INT_4

MAC_INT_3

MAC_INT_2

MAC_INT_1

MAC_INT_0

0

MAC interrupt 9: Reserved

MAC interrupt 8: RX QoS CF‐Poll interrupt

MAC interrupt 7: TXOP early termination interrupt

MAC interrupt 6: TXOP early timeout interrupt

MAC interrupt 5: Reserved

MAC interrupt 4: GP timer interrupt

MAC interrupt 3: Auto wakeup interrupt

MAC interrupt 2: TX status interrupt

MAC interrupt 1: Pre‐TBTT interrupt

MAC interrupt 0: TBTT interrupt

Reserved

16

15:13

12

R/W

N2TX_INT

NULL2 frame Tx complete interrupt.

0

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DSRT3070_V1.2_092508

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RT3070

Datasheet

Preliminary

Revision September 25, 2008

11

10

9

8

7

6

5

4

3

R/W

DTX0_INT

DTX1_INT

DTX2_INT

DRX0_INT

HCMD_INT

N0TX_INT

N1TX_INT

BCNTX_INT

MTX0_INT

MTX1_INT

MTX2_INT

MRX0_INT

DMA to TX0Q frame transfer complete interrupt.

DMA to TX1Q frame transfer complete interrupt.

DMA to TX2Q frame transfer complete interrupt.

RX0Q to DMA frame transfer complete interrupt.

Host command interrupt.

NULL0 frame Tx complete interrupt.

NULL1 frame Tx complete interrupt.

Beacon frame Tx complete interrupt.

TX0Q to MAC frame transfer complete interrupt.

TX1Q to MAC frame transfer complete interrupt.

TX2Q to MAC frame transfer complete interrupt.

MAC to RX0Q frame transfer complete interrupt.

0

2

1

0

*This register is only for 8051

MCU_INT_ENA (offset:0x0418,default :0x00000000)

Bits

31:28

27

26

25

24

23

22

21

20

19

18

17

16

15:13

12

11

10

9

8

7

6

5

4

3

2

1

Type Name

Description

Reserved

Init Value

R/W MAC_INT11_EN

R/W MAC_INT10_EN

R/W MAC_INT9_EN

R/W MAC_INT8_EN

R/W MAC_INT7_EN

R/W MAC_INT6_EN

R/W MAC_INT5_EN

R/W MAC_INT4_EN

R/W MAC_INT3_EN

R/W MAC_INT2_EN

R/W MAC_INT1_EN

R/W MAC_INT0_EN

MAC interrupt 11 enable

MAC interrupt 10 enable

MAC interrupt 9 enable

MAC interrupt 8 enable

MAC interrupt 7 enable

MAC interrupt 6 enable

MAC interrupt 5 enable

MAC interrupt 4 enable

MAC interrupt 3 enable

MAC interrupt 2 enable

MAC interrupt 1 enable

MAC interrupt 0 enable

Reserved

0

R/W N2TX_INT_EN

R/W DTX0_INT_EN

R/W DTX1_INT_EN

R/W DTX2_INT_EN

R/W DRX0_INT_EN

R/W HCMD_INT_EN

R/W N0TX_INT_EN

R/W N1TX_INT_EN

R/W BCNTX_INT_EN

R/W MTX0_INT_EN

R/W MTX1_INT_EN

R/W MTX2_INT_EN

R/W MRX0_INT_EN

NULL2 frame Tx complete interrupt enabled.

0

DMA to TX0Q frame transfer complete interrupt enable.

DMA to TX1Q frame transfer complete interrupt enable.

DMA to TX2Q frame transfer complete interrupt enable.

RX0Q to DMA frame transfer complete interrupt enable.

Host command interrupt enable.

NULL0 frame Tx complete interrupt enable.

NULL1 frame Tx complete interrupt enable.

Beacon frame Tx complete interrupt enable.

TX0Q to MAC frame transfer complete interrupt enable.

TX1Q to MAC frame transfer complete interrupt enable.

TX2Q to MAC frame transfer complete interrupt enable.

MAC to RX0Q frame transfer complete interrupt enable.

0

*This register is only for 8051

TX0Q_IO (offset: 0x041C,default :0x00000000)

Bits

Type Name

Description

Reserved

Init Value

31:16

DSRT3070_V1.2_092508

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15:0

R/W TX0Q_IO

TX0Q IO port. This register is used in manual mode.

0

TX1Q_IO (offset: 0x0420,default :0x00000000)

Bits

31:16

15:0

Type Name

Description

Reserved

Init Value

0

R/W TX1Q_IO

TX1Q IO port. This register is used in manual mode.

TX2Q_IO (offset: 0x0424,default :0x00000000)

Bits

31:16

15:0

Type Name

Description

Reserved

Init Value

0

R/W TX2Q_IO

TX2Q IO port. This register is used in manual mode.

RX0Q_IO (offset: 0x0428,default :0x00000000)

Bits

31:16

15:0

Type Name

Description

Reserved

Init Value

0

R/W RX0Q_IO

RX0Q IO port. This register is used in manual mode.

BCN_OFFSET0 (offset: 0x042C,default :0xECE8E4E0)

Bits Type Name Description

Init Value

31:24 R/W BCN3_OFFSET

23:16 R/W BCN2_OFFSET

Beacon #3 address offset in shared memory. Unit is 64 byte. 8’hec

Beacon #2 address offset in shared memory. Unit is 64 byte. 8’he8

Beacon #1 address offset in shared memory. Unit is 64 byte. 8’he4

Beacon #0 address offset in shared memory. Unit is 64 byte. 8’he0

15:8

7:0

R/W BCN1_OFFSET

R/W BCN0_OFFSET

BCN_OFFSET1 (offset: 0x0430,default :0xFCF8F4F0)

Bits Type Name Description

Init Value

31:24 R/W BCN7_OFFSET

23:16 R/W BCN6_OFFSET

Beacon #7 address offset in shared memory. Unit is 64 byte. 8’hfc

Beacon #6 address offset in shared memory. Unit is 64 byte. 8’hf8

Beacon #5 address offset in shared memory. Unit is 64 byte. 8’hf4

Beacon #4 address offset in shared memory. Unit is 64 byte. 8’hf0

15:8

7:0

R/W BCN5_OFFSET

R/W BCN4_OFFSET

TXRXQ_STA (offset: 0x0434,default :0x22020202)

Bits

31:24 RO

23:16 RO

15:8

7:0

Type Name

Description

RxQ status

Tx2Q status

Tx1Q status

Tx0Q status

Init Value

8’h22

8’h02

RX0Q_STA

TX2Q_STA

TX1Q_STA

TX0Q_STA

RO

TXRXQ_PCNT (offset: 0x0438,default :0x00000000)

Bits

31:24 RO

23:16 RO

15:8

7:0

Type Name

Description

Init Value

8’h00

RX0Q_PCNT

TX2Q_PCNT

TX1Q_PCNT

TX0Q_PCNT

Page count in RxQ

Page count in Tx2Q

Page count in Tx1Q

Page count in Tx0Q

RO

PBF_DBG (offset: 0x043C,default :0x00000FE)

Bits

31:8

Type Name

Description

Reserved

Init Value

DSRT3070_V1.2_092508

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Datasheet

Preliminary

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7:0

RO

FREE_PCNT

Free page count

8’hFE

CAP_CTRL (offset: 0x0440,default :0x01400000)

Bits

31

Type Name

R/W CAP_ADC_FEQ

Description

Data source.

0: data from the ADC output

1: Data from the FEQ output

Data capture start

0: No action

Init Value

0

30

WC CAP_START

0

1: Start data capture (cleared automatically after capture

finished)

29

W1C MAN_TRIG

Manual capture trigger

0

28:16 R/W TRIG_OFFSET

15:13

Starting address offset before trigger point.

Reserved

13’h140

12:0

RO

START_ADDR

Starting address of captured data.

13’h000

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DSRT3070_V1.2_092508

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Datasheet

Preliminary

Revision September 25, 2008

4.3. TEST registers

RF_CSR_CFG (offset: 0x0500, default: 0x0000_0000)

Bits

31:18

17

Type Name

R

R/W1 RF_CSR_KICK

Description

Reserved

Write – kick RF register read/write

0: do nothing

Init Value

0

1: kick read/write process

Read – Polling RF register read/write

0: idle

1: busy

16

R/W RF_CSR_WR

R

0: read

1: write

Reserved

RF register ID

0

15:13

0

12:8 R/W TESTCSR_RFACC_REGNUM

0 for R0, 1 for R1 and so on.

Write – DATA written to RF

Read – DATA read from RF

7:0 R/W RF_CSR_DATA

0

RF_SETTING (offset: 0x0504, default: 0x0000_0005)

Bits

31:13

12:8

7

6

5

4:3

2

1

Type Name

R

Description

Reserved

RF_VGA value in test mode

Reserved

RF_DC_CAL_EN value in test mode

RF_PA_PE_G0 value in test mode

RF_LNA value in test mode

LDO123_PE value in test mode

RF_TR value in test mode

RF_PE value in test mode

Init Value

0

1

0

1

R

TESTCSR_RF_VGA

TESTCSR_RF_DC_CAL_EN

TESTCSR_RF_PA_PE_G0

TESTCSR_RF_LNA

TESTCSR_RF_LDO123_PE

TESTCSR_RF_TR

0

TESTCSR_RF_PE

Bits

31:13

12

11

10

9

8

7

6:5

4:0

Type Name

W

Description

Reserved

Init Value

0

1

0

1

0

W

TESTCSR_RF_PE

TESTCSR_RF_TR

TESTCSR_RF_LDO123_PE

TESTCSR_RF_PA_PE_G0

TESTCSR_RF_DC_CAL_EN

RF_PE value in test mode

RF_TR value in test mode

LDO123_PE value in test mode

RF_PA_PE_G0 value in test mode

RF_DC_CAL_EN value in test mode

Reserved

TESTCSR_RF_LNA

TESTCSR_RF_VGA

RF_LNA value in test mode

RF_VGA value in test mode

* Because read data and write data are not mapped to the same bit location, we describe the CSR with read side and

write side.

DSRT3070_V1.2_092508

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RF_TEST_CONTROL (offset: 0x0508, default: 0x0000_0000)

Bits

31:1

0

Type Name

R

R/W BYPASS_RF

Description

Reserved

Init Value

0

When set, RF control signals come from RF_SETTING

instead of MAC/BBP in normal operation mode

EFUSE_CTRL (offset: 0x0580, default: 0000_8800)

Bits

31

Type Name

Description

Init Value

0

R

SEL_EFUSE

Currently used NVM(Non‐Volatile Memory)

0: external EEPROM 1: internal effuse PROM

Write it – Start efuse read/write.

0: idle

30

R/W1 EFSROM_KICK

0

1: start read/write

Read it – busy bit to efuse read/write

0: read/write done

1: busy

29:26

R

Reserved

0

25:16 R/W EFSROM_AIN

Address to be read from/written to efuse PROM. The

address must be 16‐byte alignment. (This is to say, the last

4 bits must be 0)

15:14 R/W EFSROM_LDO_ON_TIME

13:8 R/W EFSROM_LDO_OFF_TIME

LDO read time (in 128μs)

LDO discharge time (in 128μs)

e‐fuse PROM access mode:

11: Write in physical view 10: reserved

01: Read in physical view 00: Read in logical view

Write it – Start efuse read/write.

0: idle

0x2

0x8

0

7:6

R/W EFSROM_MODE

5:0

R

EFSROM_AOUT

0

1: start read/write

Read it – busy bit to efuse read/write

0: read/write done

1: busy

RFUSE_DATA3 (offset: 0x0590, default: 0x0000_0000)

Bits

Type Name

Description

For write: data to be written to efuse PROM

For read: data read back from efuse PROM

Init Value

0

31:0 R/W EFSROM_DATA3

RFUSE_DATA2 (offset: 0x0594, default: 0x0000_0000)

Bits

31:0

Type Name

R/W EFSROM_DATA2

Description

For write: data to be written to efuse PROM

For read: data read back from efuse PROM

Init Value

0

RFUSE_DATA1 (offset: 0x0598, default: 0x0000_0000)

Bits

Type Name

Description

For write: data to be written to efuse PROM

For read: data read back from efuse PROM

Init Value

0

31:0 R/W EFSROM_DATA1

DSRT3070_V1.2_092508

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RFUSE_DATA0 (offset: 0x059c, default: 0x0000_0000)

Bits

Type Name

Description

For write: data to be written to efuse PROM

For read: data read back from efuse PROM

Init Value

0

31:0 R/W EFSROM_DATA0

BIST_0 (offset: 0x05C0, default: 0x0000_0000)

Bits

31

Type Name

W1 BBP_BIST_START

Description

1: to start BBP BIST

0: do nothing

Init Value

0

30

29

28

W1 MAC_BIST_START

1: to start MAC BIST

0: do nothing

1: to start USB PHY BIST

0: do nothing

USB BIST select full speed mode

1: full speed

0

W

USBPHY_BIST_START

USB_BIST_SPEED_W

0: high speed

27:24

23

22:16

15

14

13:12

11:8

7

6

5

4

3

2

1

0

R

Reserved

0

BIST_FAIL_ROM

BIST_EFSROM_FAIL

BIST_PBF_FAIL

BIST_SMEM_FAIL

BIST_SEC_FAIL

NMAC_BIST_FAIL

BIST_FAIL_DM

BIST_FAIL_M0

BIST_FAIL_M1

BIST_FAIL_PM

BIST_RX_FAIL

8051 ROM bist fail

Efuse ROM bist fail

PBF buffer bist fail

PBF shared memory bist fail

SEC bist fail

NMAC bist fail

8051 DM bist fail

USB M0 bist fail

USB M1 bist fail

8051 program memory bist fail

Asynchronous interface RX bist fail

Asynchronous interface TX bist fail

ANY bist fail

BIST_TX_FAIL

ANY_OTHER_FAIL

BIST_DONE

Whole bist finish

BIST_1 (offset: 0x05C4 default: 0x0000_0000)

Bits

31:18

18

Type Name

R

Description

Reserved

USB BIST select full speed mode

1: full speed

Init Value

0

R

USB _BIST_SPEED_R

BIST_USB_PHY_FINISH

17

0: high speed

16

15:8

7:0

R

BIST_USB_PHY_FAIL

BB_PMDO1

BB_PMDO

USB PHY bist finish

USB_PHY bist fails

BBP PMDO1

0

INTERNAL_1 (offset: 0x05C8 default: 0x0000_0000)

Bits

Type Name

Description

Reserved for future usage

Init Value

0

31:0 R/W INTERNAL_1

DSRT3070_V1.2_092508

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INTERNAL_2 (offset: 0x05CC default: 0x0000_0000)

Bits

Type Name

Description

Reserved for future usage

Init Value

0

31:0 R/W INTERNAL_2

BBP_CFG (offset: 0x05D0 default: 0x0000_0000)

Bits

31:21

20

19

18

17

16

15:10

9:0

Type Name

R

Description

Reserved

Init Value

0

R/W BBP_PLL_PD

R/W BBP_IDDQ_PD

R/W BBP_TEST_ADCDAC

R/W BBP_ADC5_ON

R/W BBP_PLLBYPASS

R

PLL_PD value in test mode

IDDQ_PD value in test mode

TEST_ADCDAC value in test mode

ADC5_ON value in test mode

PLLBYPASS value in test mode

Reserved

R/W BBP_PMDI

BBP_PMDI value in test mode

LDO_CFG0 (offset: 0x05D4 default: 0x0000_0000)

Bits

31

Type Name

R/W LDO25_LARGEA

Description

Init Value

0

LDO25_LARGEA value in test mode

LDO25_LEVEL value in test mode

LDO_CORE_VLEVEL value in test mode

BGSEL value in test mode

30:29 R/W LDO25_LEVEL

28:26 R/W LDO_CORE_VLEVEL

25:24 R/W BGSEL

1

23:16 R/W DELAY1

15:8 R/W DELAY2

Latency from usb suspend to pll_pd=1 (in 0.4μs)

Latency from usb suspend to ldo_pd=0 (in 0.4μs)

4

15

7:0

R/W DELAY3

Latency from usb suspend to ldo_core_pd=1 (in 0.4μs)

20

LDO_CFG1 (offset: 0x05D8 default: 0x0000_0000)

Bits

31:28

Type Name

R

Description

RESERVED

Init Value

0

27:16 R/W DELAY4

15:12

11:0 R/W DELAY5

Latency from usb resume to ldo_pd=1 (in 0.4us)

RESERVED

Latency from usb resume to pll_pd=0 (in 0.4us)

50

0

55

R

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DSRT3070_V1.2_092508

- 19 -

Form No.：QS-073-F02

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Kept by： DCC

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RT3070

Datasheet

Preliminary

Revision September 25, 2008

4.4. MAC registers

4.4.1. MAC System configuration registers (offset:0x1000)

ASIC_VER_ID (offset:0x1000, default :0x3070_0200)

Bits

31:16

15:0

Type

R

Name

VER_ID

REV_ID

Description

ASIC version ID

ASIC reversion ID

Initial value

16’h3070

16’h0200

13.1

MAC_SYS_CTRL (offset:0x1004, default :0x0000_0003)

Bits

31:8

7

Type

R

R/W

Name

Description

Reserved

Initial value

0

RX_TS_EN

Write 32‐bit hardware RX timestamp instead of (RXWI‐

>RSSI), and write (RXWI‐>RSSI) instead of (RXWI‐>SNR).

Note: For QA RX sniffer mode only.

1: enable

0: disable

6

5

4

R/W

WLAN_HALT_EN

PBF_LOOP_EN

CONT_TX_TEST

Enable external WLAN halt control signal

1: enable

0: disable

Packet buffer loop back enable (TX‐>RX)

1: enable

0: disable

0

Continuous TX production test; override MAC_RX_EN,

MAC_TX_EN

1: enable

0: disable

3

2

1

R/W

MAC_RX_EN

MAC_TX_EN

BBP_HRST

MAC RX enable

1: enable

0: disable

MAC TX enable

1: enable

0: disable

BBP hard‐reset

1: BBP in reset state

0: BBP in normal state

Note: Whole BBP including BBP registers will be reset.

MAC soft‐reset

0

1

0

R/W

MAC_SRST

1

1: MAC in reset state

0: MAC in normal state

Note: MAC registers and tables will NOT be reset.

Note: MAC hard‐reset is outside the scope of MAC registers.

MAC_ADDR_DW0 (offset:0x1008, default :0x0000_0000)

Bits

Type

R/W

Name

Description

Initial value

31:24

23:16

15:8

7:0

MAC_ADDR_3

MAC_ADDR_2

MAC_ADDR_1

MAC_ADDR_0

MAC address byte3

MAC address byte2

MAC address byte1

MAC address byte0

0

DSRT3070_V1.2_092508

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Form No.：QS-073-F02

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MAC_ADDR_DW1 (offset:0x100C, default :0x0000_0000)

Bits

Type

R

R/W

Name

Description

Reserved

MAC address byte5

MAC address byte4

Initial value

31:16

15:8

7:0

0

MAC_ADDR_5

MAC_ADDR_4

Note: Byte0 is the first byte on network. Its LSB bit is the first bit on network. For a MAC address captured on the

network with order 00:01:02:03:04:05, byte0=00, byte1=01 etc.

MAC_BSSID_DW0 (offset:0x1010, default :0x0000_0000)

Bits

Type

R/W

Name

Description

BSSID byte3

BSSID byte2

BSSID byte1

BSSID byte0

Initial value

31:24

23:16

15:8

7:0

BSSID_3

BSSID_2

BSSID_1

BSSID_0

0

MAC_BSSID_DW1 (offset: 0x1014, default: 0x0000_0000)

Bits

31:21

20:18

Type

R

R/W

Name

Description

Reserved

Multiple BSSID Beacon number

0: one back‐off beacon

1‐7: SIFS‐burst beacon count

Initial value

0

MULTI_BCN_NUM

17:16

R/W

MULTI_BSSID_MODE Multiple BSSID mode

In multiple‐BSSID AP mode, BSSID shall be the same as

0

MAC_ADDR, that is, this device owns multiple MAC_ADDR

in this mode.

The multiple MAC_ADDR/BSSID are distinguished by [bit2:

bit0] of byte5.

0: 1‐BSSID mode (BSS index = 0)

1: 2‐BSSID mode (byte5.bit0 as BSS index)

2: 4‐BSSID mode (byte5.bit1:0 as BSS index)

3: 8‐BSSID mode (byte5.bit2:0 as BSS index)

BSSID byte5

15:8

7:0

R/W

BSSID_5

BSSID_4

0

BSSID byte4

MAX_LEN_CFG (offset: 0x1018, default: 0x000A_0FFF)

Bits

31:20

19:16

Type

R

R/W

Name

Description

Reserved

Initial value

0

10

MIN_MPDU_LEN

Minimum MPDU length (unit: bytes)

MAC will drop the MPDU if the length is less than this

limitation. Applied only to MAC RX.

Reserved

Maximum PSDU length (power factor)

0: 2^13 = 8K bytes

15:14

13:12

R

R/W

0

MAX_PSDU_LEN

1: 2^14 = 16K bytes

2: 2^15 = 32K bytes

3: 2^16 = 64K bytes

MAC will NOT generate A‐MPDU with length greater than

this limitation. Applied only in MAC TX.

DSRT3070_V1.2_092508

Form No.：QS-073-F02

- 21 -

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RT3070

Datasheet

Preliminary

Revision September 25, 2008

11:0

R/W

MAX_MPDU_LEN

Maximum MPDU length (unit: bytes)

4095

MAC will drop the MPDU if the length is greater than this

limitation. Applied only in MAC RX.

BBP_CSR_CFG (offset: 0x101C, default: 0x0008_0000)

Bits

31:20

19

Type

R

R/W

Name

Description

Reserved

BBP Register R/W mode

1: parallel mode

Initial value

0

1

BBP_RW_MODE

0: serial mode

18

17

R/W

BBP_PAR_DUR

BBP_CSR_KICK

BBP Register parallel R/W pulse width

0: pulse width = 62.5ns

1: pulse width = 112.5ns

Note: Please set BBP_PAR_DUR=1 in 802.11J mode

Write ‐ kick BBP register read/write

0: do nothing

0

1: kick read/write process

Read ‐ Polling BBP register read/write progress

0: idle

1: busy

16

R/W

BBP_CSR_RW

BBP_ADDR

BBP_DATA

0: Write

1: Read

BBP register ID

0 for R0, 1 for R1, and so on.

Write ‐ Data written to BBP

Read ‐ Data read from BBP

0

15:8

7:0

RF_CSR_CFG0 (offset: 0x1020, default: 0x1600_0000)

Bits

31

Type

R/W

Name

RF_REG_CTRL

Description

Initial value

0

Write: 1 ‐ RF_REG0/1/2 to RF chip

Read: 0 – idle, 1 ‐ busy

RF_LE selection

0: RF_LE0 activate

1: RF_LE1 activate

RF_LE standby mode

0: RF_LE is high when standby

1: RF_LE is low when standby

RF register bit width

Default: 22

30

29

R/W

RF_LE_SEL

0

RF_LE_STBY

28:24

23:0

R/W

RF_REG_WIDTH

RF_REG_0

22

0

RF register0 ID and content

RF_CSR_CFG1 (offset: 0x1024, default: 0x0000_0000)

Bits

31:25

24

Type

R

R/W

Name

Description

Reserved

Gap between BB_CONTROL_RF and RF_LE

0: 3 system clock cycle (37.5μsec)

1: 5 system clock cycle (62.5μsec)

RF register1 ID and content

Initial value

0

RF_DUR

23:0

R/W

RF_REG_1

0

- 22 -

DSRT3070_V1.2_092508

Form No.：QS-073-F02

Rev.：1

Kept by： DCC

Ret. Time： 5 Years

RT3070

Datasheet

Preliminary

Revision September 25, 2008

RF_CSR_CFG2 (offset: 0x1028, default: 0x0000_0000)

Bits

31:24

23:0

Type

R

R/W

Name

Description

Reserved

RF register2 ID and content

Initial value

0

RF_REG_2

Note: Software should make sure the first bit (MSB in the specified bit number) written to RF is 0 for RF chip mode

selection.

LED_CFG (offset: 0x102C, default: 0x0903_461E)

Bits

31

30

Type

R

R/W

Name

Description

Reserved

LED polarity

Initial value

0

LED_POL

0: active low

1: active high

29:28

R/W

Y_LED_MODE

R_LED_MODE

Yellow LED mode

0: off

1: blinking upon TX

2: periodic slow blinking

3: always on

Reserved

Red LED mode

0

27:26

25:24

R

R/W

0

1

0: off

1: blinking upon TX

2: periodic slow blinking

3: always on

23:22

21:16

15:8

7:0

R

Reserved

0

3

30

70

R/W

SLOW_BLK_TIME

LED_OFF_TIME

LED_ON_TIME

Slow blinking period (unit: 1sec)

TX blinking off period (unit: 1ms)

TX blinking on period (unit: 1ms)

AMPDU_MAX_LEN_20M1S (offset: 0x1030, default: 0x7777_7777)

Bits

Type

R/W

Name

Description

Initial value

31:28

27:24

23:20

19:16

15:12

11:08

07:04

03:00

AMPDU_MAX_BW20_MCS7

AMPDU_MAX_BW20_MCS6

AMPDU_MAX_BW20_MCS5

AMPDU_MAX_BW20_MCS4

AMPDU_MAX_BW20_MCS3

AMPDU_MAX_BW20_MCS2

AMPDU_MAX_BW20_MCS1

AMPDU_MAX_BW20_MCS0

Maximum AMPDU for BW20 MCS7*

Maximum AMPDU for BW20 MCS6*

Maximum AMPDU for BW20 MCS5*

Maximum AMPDU for BW20 MCS4*

Maximum AMPDU for BW20 MCS3*

Maximum AMPDU for BW20 MCS2*

Maximum AMPDU for BW20 MCS1*

Maximum AMPDU for BW20 MCS0*

7

Note1*: 0‐2: 2K bytes, 3: 4K bytes, 4: 8K, 5: 16K, 6: 32K, 7: 64K

Note2: The value is applied together with 0x1018 MAX_PSDU_LEN.

AMPDU_MAX_LEN_20M2S (offset: 0x1034, default: 0x7777_7777)

Bits

Type

R/W

Name

Description

Initial value

31:28

27:24

23:20

AMPDU_MAX_BW20_MCS15

AMPDU_MAX_BW20_MCS14

AMPDU_MAX_BW20_MCS13

Maximum AMPDU for BW20 MCS15*

Maximum AMPDU for BW20 MCS14*

Maximum AMPDU for BW20 MCS13*

7

DSRT3070_V1.2_092508

- 23 -

Form No.：QS-073-F02

Rev.：1

Kept by： DCC

Ret. Time： 5 Years

RT3070

Datasheet

Preliminary

Revision September 25, 2008

19:16

15:12

11:08

07:04

03:00

R/W

AMPDU_MAX_BW20_MCS12

AMPDU_MAX_BW20_MCS11

AMPDU_MAX_BW20_MCS10

AMPDU_MAX_BW20_MCS9

AMPDU_MAX_BW20_MCS8

Maximum AMPDU for BW20 MCS12*

7

Maximum AMPDU for BW20 MCS11*

Maximum AMPDU for BW20 MCS10*

Maximum AMPDU for BW20 MCS9*

Maximum AMPDU for BW20 MCS8*

Note1*: 0‐2: 2K bytes, 3: 4K bytes, 4: 8K, 5: 16K, 6: 32K, 7: 64K

Note2: The value is applied together with 0x1018 MAX_PSDU_LEN.

AMPDU_MAX_LEN_40M1S (offset: 0x1038, default: 0x7777_7777)

Bits

Type

R/W

Name

Description

Initial value

31:28

27:24

23:20

19:16

15:12

11:08

07:04

03:00

AMPDU_MAX_BW40_MCS7

AMPDU_MAX_BW40_MCS6

AMPDU_MAX_BW40_MCS5

AMPDU_MAX_BW40_MCS4

AMPDU_MAX_BW40_MCS3

AMPDU_MAX_BW40_MCS2

AMPDU_MAX_BW40_MCS1

AMPDU_MAX_BW40_MCS0

Maximum AMPDU for BW40 MCS7*

Maximum AMPDU for BW40 MCS6*

Maximum AMPDU for BW40 MCS5*

Maximum AMPDU for BW40 MCS4*

Maximum AMPDU for BW40 MCS3*

Maximum AMPDU for BW40 MCS2*

Maximum AMPDU for BW40 MCS1*

Maximum AMPDU for BW40 MCS0*

7

Note1*: 0‐2: 2K bytes, 3: 4K bytes, 4: 8K, 5: 16K, 6: 32K, 7: 64K

Note2: The value is applied together with 0x1018 MAX_PSDU_LEN.

AMPDU_MAX_LEN_40M2S (offset: 0x103C, default: 0x7777_7777)

Bits

Type

R/W

Name

Description

Initial value

31:28

27:24

23:20

19:16

15:12

11:08

07:04

03:00

AMPDU_MAX_BW40_MCS15

AMPDU_MAX_BW40_MCS14

AMPDU_MAX_BW40_MCS13

AMPDU_MAX_BW40_MCS12

AMPDU_MAX_BW40_MCS11

AMPDU_MAX_BW40_MCS10

AMPDU_MAX_BW40_MCS9

AMPDU_MAX_BW40_MCS8

Maximum AMPDU for BW40 MCS15*

Maximum AMPDU for BW40 MCS14*

Maximum AMPDU for BW40 MCS13*

Maximum AMPDU for BW40 MCS12*

Maximum AMPDU for BW40 MCS11*

Maximum AMPDU for BW40 MCS10*

Maximum AMPDU for BW40 MCS9*

Maximum AMPDU for BW40 MCS8*

7

Note1*: 0‐2: 2K bytes, 3: 4K bytes, 4: 8K, 5: 16K, 6: 32K, 7: 64K

Note2: The value is applied together with 0x1018 MAX_PSDU_LEN.

AMPDU_MAX_LEN_40M2S (offset: 0x1040, default: 0x0000_0000)

Bits

31:07

06

Type

R

R/W

Name

Description

Reserved

Enable forced BA window size over BA

window size value in TXWI

Initial value

0

FORCE_BA_WINSIZE_EN

0: disable,

1: enable

05:00

R/W

FORCE_BA_WINSIZE

Forced BA window size

0

4.4.2. MAC Timing Control Registers (offset:0x1100)

XIFS_TIME_CFG (offset:0x1100, default :0x33A4_100A)

Bits

31:30

Type

R

Name

Description

Reserved

Initial value

DSRT3070_V1.2_092508

- 24 -

Form No.：QS-073-F02

Rev.：1

Kept by： DCC

Ret. Time： 5 Years

RT3070

Datasheet

Preliminary

Revision September 25, 2008

29

R/W

BB_RXEND_EN

EIFS_TIME

BB_RX_END signal enable

Refer BB_RX_END signal from BBP RX logic to start SIFS

defer.

0: disable

1

1: enable

28:20

19:16

EIFS time (unit: 1μs)

314

4

EIFS is the defer time after reception of a CRC error

packet. After deferring EIFS, the normal back‐off process

may proceed.

Delayed OFDM SIFS time compensator (unit: 1μs)

When BB_RX_END from BBP is a delayed version the

SIFS deferred will be (OFDM_SIFS_TIME ‐

OFDM_XIFS_TIME)

OFDM_XIFS_TIME

15:8

7:0

R/W

OFDM_SIFS_TIME

CCK_SIFS_TIME

OFDM SIFS time (unit: 1μs)

Applied after OFDM TX/RX.

CCK SIFS time (unit: 1μs)

Applied after CCK TX/RX.

16

10

Note1: EIFS = SIFS + ACK @ 1Mbps + DIFS = 10us (SIFS) + 192us (long preamble) + 14*8us (ACK) + 50us (DIFS) = 364.

However, MAC should start back‐off procedure after (EIFS‐DIFS).

Note2: EIFS is not applied if MAC is a TXOP initiator that owns the channel.

Note3: EIFS is not started if AMPDU is only partial corrupted.

Caution: It is recommended that both (CCK_SIFS_TIME) and (OFDM_SIFS_TIME) are no less than TX/RX transition time.

If the SIFS value is not long enough, a SIFS burst transmission may be replaced with a PIFS burst one.

BKOFF_SLOT_CFG (offset:0x1104, default :0x0000_0014)

Bits

Type

Name

Description

Initial value

31:12 R/W

Reserved

11:8

7:0

R/W

CC_DELAY_TIME

SLOT_TIME

Channel clear delay (unit: 1‐us)

This value specifies TX guard time after channel is clear.

Slot time (unit:1μs)

This value specifies the slot boundary after deferring

SIFS time.

2

20

Note: Default 20μs is for 11b/g. 11a and 11g‐short‐slot‐

mode is 9μs.

NAV_TIME_CFG (offset:0x1108, default :0x0000_8000)

Bits

31

Type

WC

Name

NAV_UPD

Description

NAV timer manual update command

0: Do nothing

Initial value

0

1: Update NAV timer with NAV_UPD_VAL

NAV timer manual update value (unit: 1μs)

NAV timer auto‐clear enable

When enabled, MAC will auto clear NAV timer after the

reception of CF‐End frame from previous NAV holder

STA.

30:16

15

R/W

NAV_UPD_VAL

NAV_CLR_EN

0

1

0: disable

1: enable

DSRT3070_V1.2_092508

- 25 -

Form No.：QS-073-F02

Rev.：1

Kept by： DCC

Ret. Time： 5 Years

RT3070

Datasheet

Preliminary

Revision September 25, 2008

14:0

R

NAV_TIMER

NAV timer (unit: 1μs)

0

The timer is set by other STA and will auto countdown to

zero. The STA who set the NAV timer is called the NAV

holder. When NAV timer is nonzero, MAC will not send

any packet.

CH_TIME_CFG (offset:0x110C, default: 0x0000_001E)

Bits

31:5

4

Type

R

R/W

Name

Description

Reserved

Count EIFS as channel busy

0: disable

Initial value

0

1

EIFS_AS_CH_BUSY

1: enable

3

2

1

0

R/W

NAV_AS_CH_BUSY

RX_AS_CH_BUSY

TX_AS_CH_BUSY

CH_STA_TIMER_EN

Count NAV as channel busy

0: disable

1: enable

Count RX busy as channel busy

0: disable

1: enable

Count TX busy as channel busy

0: disable

1: enable

Channel statistic timer enable

0: disable

1

0

1: enable

PBF_LIFE_TIMER (offset:0x1110, default: 0x0000_0000)

Bits

31:0

Type

R

Name

PBF_LIFE_TIMER

Description

TX/RX MPDU timestamp timer (free run)

Unit: 1us

Initial value

0

BCN_TIME_CFG (offset:0x1114, default: 0x00000640)

Bits

31:24

Type

R/W

Name

TSF_INS_COMP

Description

Initial value

0

TSF insertion compensation value (unit: 1μs)

When inserting TSF, add this value with local TSF timer

as the TX timestamp.

23:21

20

R

R/W

Reserved

BEACON frame TX enable

0

BCN_TX_EN

When enabled, MAC sends BEACON frame at TBTT

interrupt.

0: disable

1: enable

19

R/W

TBTT_TIMER_EN

TSF_SYNC_MODE

TBTT timer enable

When enabled, TBTT interrupt will be issued

periodically with period specified in (BCN_INTVAL).

0: disable

Local 64‐bit TSF timer synchronization mode

00: disable

0

1: enable

18:17

01: (STA infra‐structure mode) Upon the reception of

BEACON frame from associated BSS, local TSF is always

updated with remote TSF.

DSRT3070_V1.2_092508

- 26 -

Form No.：QS-073-F02

Rev.：1

Kept by： DCC

Ret. Time： 5 Years

RT3070

Datasheet

Preliminary

Revision September 25, 2008

10: (STA ad‐hoc mode) Upon the reception of BEACON

frame from associated BSS, local TSF is updated with

remote TSF only if the remote TSF is greater than local

TSF.

11: (AP mode) SYNC with nobody

16

R/W

TSF_TIMER_EN

BCN_INTVAL

Local 64‐bit TSF timer enable

When enabled, TSF timer will re‐start from zero.

0: disable

BEACON interval (unit: 64μs)

This value specified the interval between

Maximum beacon interval is about 4sec.

0

1: enable

15:0

1600

TBTT_SYNC_CFG (offset:0x1118, default: 0x0042_2010)

Bits

31:24

23:20

Type

R

R/W

Name

Description

Reserved

Initial value

0

BCN_CWMIN

BCN_AIFSN

BCN_EXP_WIN

Beacon transmission CWMIN after TBTT interrupt (unit: 4

slot)

Beacon transmission AIFSN after TBTT interrupt (unit:

slot)

Beacon expecting window duration (unit: 64μs)

The window starts from TBTT interrupt. The phase of

“TBTT interrupt train” will NOT be adjusted by the

beacon arrived within the window.

19:16

15:8

R/W

2

32

7:0

R/W

TBTT_ADJUST

IBSS mode TBTT phase adaptive adjustment step (unit: 16

1μs), default value is 16μs.

In IBSS mode (Ad hoc), if consecutive TX beacon failures

(or consecutive success) happened, TBTT timer will

adjust it phase to meet the external Ad hoc TBTT time.

TSF_TIMER_DW0 (offset:0x111C, default: 0x0000_0000)

Bits

31:0

Type

R

Name

TSF_TIMER_DW0

Description

Local TSF timer LSB 32 bits (unit: 1us)

Initial value

0

TSF_TIMER_DW1 (offset:0x1120, default: 0x0000_0000)

Bits

31:0

Type

R

Name

TSF_TIMER_DW1

Description

Local TSF timer MSB 32 bits (unit: 1us)

Initial value

0

TBTT_TIMER (offset:0x1124, default: 0x0000_0000)

Bits

Type

Name

Description

Initial value

31:17

16:0

R

Reserved

TBTT Timer (unit: 32μs)

The time remains till next TBTT.

When TBTT_TIMER_EN is enabled, the timer will down

count from BCN_INTVAL to zero.

When TBTT_TIMER_EN is disabled, the timer will stay in

zero.

0

TBTT_TIMER

DSRT3070_V1.2_092508

- 27 -

Form No.：QS-073-F02

Rev.：1

Kept by： DCC

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RT3070

Datasheet

Preliminary

Revision September 25, 2008

INT_TIMER_CFG (offset:0x1128, default: 0x0000_0320)

Bits

31:16

15:0

Type

R/W

Name

GP_TIMER

PRE_TBTT_TIMER

Description

Initial value

0

Period of general purpose interrupt timer (Unit: 64μs)

Pre‐TBTT interrupt time (unit: 64μs)

The value specified the interrupt timing before TBTT

interrupt.

INT_TIMER_EN (offset:0x112C, default: 0x0000_0000)

Bits

31:2

1

Type

R

R/W

Name

Description

Reserved

Initial value

0

GP_TIMER_EN

Periodic general purpose interrupt timer enable

0: disable

1: enable

0

R/W

PRE_TBTT_INT_EN

Pre‐TBTT interrupt enable

0: disable

0

1: enable

CH_IDLE_STA (offset:0x1130, default: 0x0000_0000)

Bits

31:0

Type

RC

Name

CH_IDLE_TIME

Description

Channel idle time (unit: 1μs)

Initial value

0

In application, the channel busy time can be derived by the equation:

CH_BUSY_TIME = host polling period – CH_IDLE_TIME

CH_BUSY_STA (offset:0x1134, default: 0x0000_0000)

Bits

31:0

Type

RC

Name

CH_BUSY_TIME

Description

Channel busy time (unit: 1μs)

Initial value

0

EXT_CH_BUSY_STA (offset:0x1138, default: 0x0000_0000)

Bits

31:0

Type

RC

Name

EXT_CH_BUSY_TIME

Description

Extension Channel busy time (unit: 1μs)

Initial value

0

4.4.3. MAC Power save configuration registers (offset:0x1200)

MAC_STATUS_REG (offset:0x1200, default: 0x0000_0000)

Bits

31:2

1

Type

R

Name

Description

Reserved

RX status

0: Idle

Initial value

0

RX_STATUS

1: Busy

0

R

TX_STATUS

TX status

0: Idle

0

1: Busy

PWR_PIN_CFG (offset:0x1204, default: 0x0000_000A)

Bits

31:4

3

Type

R

R/W

Name

Description

Reserved

AD/DA power down

PLL power down

Initial value

0

1

0

IO_ADDA_PD

IO_PLL_PD

2

DSRT3070_V1.2_092508

- 28 -

Form No.：QS-073-F02

Rev.：1

Kept by： DCC

Ret. Time： 5 Years

RT3070

Datasheet

Preliminary

Revision September 25, 2008

1

0

R/W

IO_RA_PE

IO_RF_PE

RA_PE

RF_PE

1

0

AUTO_WAKEUP_CFG (offset:0x1208, default: 0x0000_0014)

Bits

31:16

15

Type

R

R/W

Name

Description

Reserved

Auto wakeup interrupt enable

Auto wakeup interrupt will be issued after

#(SLEEP_TBTT_NUM) TBTTs’ at

Initial value

0

AUTO_WAKEUP_EN

WAKEUP_LEAD_TIME before the target wakeup

TBTT.

0: disable

1: enable

Note: Please make sure TBTT_TIMER_EN is

enabled.

14:8

7:0

R/W

SLEEP_TBTT_NUM

WAKEUP_LEAD_TIME

Number of sleeping TBTT

Auto wakeup lead time (unit: 1TU=1024μs)

0

20

4.4.4. MAC TX configuration registers (offset: 0x1300)

EDCA_AC0_CFG (BE) (offset: 0x1300, default: 0x0007_3200)

Bits

Type

R

R/W

Name

Description

Reserved

AC0 CWMAX (unit: power of 2)

AC0 CWMIN (unit: power of 2)

AC0 AIFSN (unit: # of slot time)

AC0 TXOP limit (unit: 32us)

Initial value

31:20

19:16

15:12

11:8

7:0

0

7

3

2

0

AC0_CWMAX

AC0_CWMIN

AC0_AIFSN

AC0_TXOP

EDCA_AC1_CFG (BK) (offset: 0x1304, default: 0x0007_3200)

Bits

Type

R

R/W

Name

Description

Reserved

AC1 CWMAX (unit: power of 2)

AC1 CWMIN (unit: power of 2)

AC1 AIFSN (unit: # of slot time)

AC1 TXOP limit (unit: 32us)

Initial value

31:20

19:16

15:12

11:8

7:0

0

7

3

2

0

AC1_CWMAX

AC1_CWMIN

AC1_AIFSN

AC1_TXOP

EDCA_AC2_CFG (VI) (offset: 0x1308, default: 0x0007_3200)

Bits

Type

R

R/W

Name

Description

Reserved

AC2 CWMAX (unit: power of 2)

AC2 CWMIN (unit: power of 2)

AC2 AIFSN (unit: # of slot time)

AC2 TXOP limit (unit: 32us)

Initial value

31:20

19:16

15:12

11:8

7:0

0

7

3

2

0

AC2_CWMAX

AC2_CWMIN

AC2_AIFSN

AC2_TXOP

EDCA_AC3_CFG (VO) (offset: 0x130C, default: 0x0007_3200)

Bits

31:20

19:16

Type

R

R/W

Name

Description

Reserved

AC3 CWMAX (unit: power of 2)

Initial value

0

7

AC3_CWMAX

DSRT3070_V1.2_092508

- 29 -

Form No.：QS-073-F02

Rev.：1

Kept by： DCC

Ret. Time： 5 Years

RT3070

Datasheet

Preliminary

Revision September 25, 2008

15:12

11:8

7:0

R/W

AC3_CWMIN

AC3_AIFSN

AC3_TXOP

AC3 CWMIN (unit: power of 2)

AC3 AIFSN (unit: # of slot time)

AC1 TXOP limit (unit: 32μs)

3

2

0

EDCA_TID_AC_MAP (offset: 0x1310, default: 0000_FA14)

Bits

Type

R

Name

Description

Reserved

Initial value

31:16

15:14

13:12

11:10

9:8

7:6

5:4

3:2

1:0

0

3

2

0

1

0

R/W

TID7_AC_MAP

TID6_AC_MAP

TID5_AC_MAP

TID4_AC_MAP

TID3_AC_MAP

TID2_AC_MAP

TID1_AC_MAP

TID0_AC_MAP

AC value as TID=7

AC value as TID=6

AC value as TID=5

AC value as TID=4

AC value as TID=3

AC value as TID=2

AC value as TID=1

AC value as TID=0

Note: default according 802.11e Table 20.23—User priority to Access Category mappings

TX_PWR_CFG_0 (offset: 0x1314, default: 0x6666_6666)

Bits

Type

R/W

Name

Description

Initial value

0x66

31:24

23:16

15:8

7:0

TX_PWR_OFDM_12

TX_PWR_OFDM_6

TX_PWR_CCK_5

TX_PWR_CCK_1

TX power for OFDM 12M/18M

TX power for OFDM 6M/9M

TX power for CCK5.5M/11M

TX power for CCK1M/2M

TX_PWR_CFG_1 (offset: 0x1318, default: 0x6666_6666)

Bits

Type

R/W

Name

Description

Initial value

0x66

31:24

23:16

15:8

7:0

TX_PWR_MCS_2

TX_PWR_MCS_0

TX_PWR_OFDM_48

TX_PWR_OFDM_24

TX power for HT MCS=2,3

TX power for HT MCS=0,1

TX power for OFDM 48M/54M

TX power for OFDM 24M/36M

TX_PWR_CFG_2 (offset: 0x131C, default: 0x6666_6666)

Bits

Type

R/W

Name

Description

Initial value

0x66

31:24

23:16

15:8

7:0

TX_PWR_MCS_10

TX_PWR_MCS_8

TX_PWR_MCS_6

TX_PWR_MCS_4

TX power for HT MCS=10,11

TX power for HT MCS=8,9

TX power for HT MCS=6,7

TX power for HT MCS=4,5

TX_PWR_CFG_3 (offset: 0x1320, default: 0x6666_6666)

Bits

Type

R/W

Name

Reserved

TX_PWR_MCS_14

TX_PWR_MCS_12

Description

Initial value

0x6666

0x66

31:16

15:8

7:0

TX power for HT MCS=14,15

TX power for HT MCS=12,13

0x66

TX_PWR_CFG_4 (offset: 0x1324, default: 0x0000_6666)

Bits

31:16

15:0

Type

R

R/W

Name

Reserved

Description

Initial value

0

0x6666

- 30 -

DSRT3070_V1.2_092508

Form No.：QS-073-F02

Rev.：1

Kept by： DCC

Ret. Time： 5 Years

RT3070

Datasheet

Preliminary

Revision September 25, 2008

TX_PIN_CFG (offset: 0x1328, default: 0x0005_0F0F)

Bits

31:20

19

18

17

16

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

Type

R

Name

Reserved

TRSW_POL

TRSW_EN

RFTR_POL

RFTR_EN

Description

Initial value

0

1

0

1

0

1

0

1

R/W

TRSW_EN polarity

TRSW_EN enable

RF_TR polarity

RF_TR enable

LNA_PE_G1_POL

LNA_PE_A1_POL

LNA_PE_G0_POL

LNA_PE_A0_POL

LNA_PE_G1_EN

LNA_PE_A1_EN

LNA_PE_G0_EN

LNA_PE_A0_EN

PA_PE_G1_POL

PA_PE_A1_POL

PA_PE_G0_POL

PA_PE_A0_POL

PA_PE_G1_EN

PA_PE_A1_EN

PA_PE_G0_EN

PA_PE_A0_EN

LNA_PE_G1 polarity

LNA_PE_A1 polarity

LNA_PE_G0 polarity

LNA_PE_A0 polarity

LNA_PE_G1 enable

LNA_PE_A1 enable

LNA_PE_G0 enable

LNA_PE_A0 enable

PA_PE_G1 polarity

PA_PE_A1 polarity

PA_PE_G0 polarity

PA_PE_A0 polarity

PA_PE_G1 enable

PA_PE_A1 enable

PA_PE_G0 enable

PA_PE_A0 enable

0

TX_BAND_CFG (offset: 0x132C, default: 0x0000_0004)

Bits

31:3

2

Type

R

R/W

Name

Reserved

5G_BAND_SEL_N

Description

Initial value

0

1

5G band selection PIN (complement of

5G_BAND_SEL_P)

1

0

R/W

5G_BAND_SEL_P

TX_BAND_SEL

5G band selection PIN

0: use lower 40Mhz band in 20Mhz TX

1: use upper 40Mhz band in 20Mhz TX

0

Note1: TX_BAND_SEL is only effective when TX/RX bandwidth control register R4 of BBP is set to 40 Mhz.

TX_SW_CFG0 (offset: 0x1330, default: 0x0004_080C)

Bits

Type

R/W

Name

Description

Initial value

0x0

0x4

0x8

0xC

31:24

23:16

15:8

7:0

DLY_RFTR_EN

DLY_TRSW_EN

DLY_PAPE_EN

DLY_TXPE_EN

Delay of RF_TR assertion

Delay of TR_SW assertion

Delay of PA_PE assertion

Delay of TX_PE assertion

Note1: The timing unit is 0.25us.

Note2: SIFS_TIME should compensate with DLY_TXPE_EN.

TX_SW_CFG1 (offset: 0x1334, default: 0x000C_0808)

Bits

31:24

23:16

Type

R

R/W

Name

Description

Reserved

Delay of RF_TR de‐assertion

Initial value

0

0xC

DLY_RFTR_DIS

DSRT3070_V1.2_092508

- 31 -

Form No.：QS-073-F02

Rev.：1

Kept by： DCC

Ret. Time： 5 Years

RT3070

Datasheet

Preliminary

Revision September 25, 2008

15:8

7:0

R/W

DLY_TRSW_DIS

DLY_PAPE_DIS

Delay of TR_SW de‐assertion

Delay of PA_PE de‐assertion

0x8

Note1: The timing unit is 0.25us.

Note2: The delay is started from TX_END event of BBP.

Note3: TX_PE is de‐asserted automatically as last data byte passed to BBP.

TX_SW_CFG2 (offset: 0x1338, default: 0x000C_0408)

Bits

Type

R/W

Name

Description

Initial value

0x0

0xC

0x4

0x8

31:24

23:16

15:8

7:0

DLY_LNA_EN

DLY_LNA_DIS

DLY_DAC_EN

DLY_DAC_DIS

Delay of LNA* assertion

Delay of LNA* de‐assertion

Delay of DAC_PE assertion

Delay of DAC_PE de‐assertion

Note1: The timing unit is 0.25us.

Note 2: LNA* includes LNA_A0, LNA_A1, LNA_G0, LNA_G1.

TXOP_THRES_CFG (offset: 0x133C, default: 0x0000_0000)

Bits

31:24 R/W

Type

Name

TXOP_REM_THRES

Description

Remaining TXOP threshold, unit: 32μs

Initial value

0

As the remaining TXOP is less than the threshold, the

TXOP is passed silently.

23:16 R/W

CF_END_THRES

RDG_IN_THRES

RDG_OUT_THRES

CF‐END threshold, unit: 32μs

0

As the remaining TXOP is greater than the threshold,

the CF‐END will be sent to release the remaining TXOP

reserved by long NAV.

Set 0xFF to disable CF_END transmission.

RX RDG threshold, unit: 32μs

As the remaining TXOP (specified in the duration field

of the RX frame with RDG=1) is greater than or equal

to the threshold, the granted reverse direction TXOP

may be used.

15:8 R/W

7:0

R/W

TX RDG threshold, unit: 32μs

As the remaining TXOP is greater than or equal to the

threshold, RDG in the TX frame may be set to one.

TXOP_CTRL_CFG (offset: 0x1340, default: 0x0000_243F)

Bits

31:20

19:16

Type

R

R/W

Name

Description

Reserved

Initial value

0

EXT_CW_MIN

Cwmin for extension channel backoff

When EXT_CCA_EN is enabled, 40Mhz transmission

will be suppressed to 20Mhz if the extension CCA is

busy or extension channel backoff is not finished.

Default: Cwmin=0, disable.

15:8

7

R/W

EXT_CCA_DLY

Extension CCA signal delay time (unit: μsec)

Create delayed version of extension CCA signal

reference time for extension channel IFS.

Default: (ofdm SIFS) + (long slot time) = 16 + 20 = 36

(μsec)

36

EXT_CCA_EN

Extension CCA reference enable

0

DSRT3070_V1.2_092508

- 32 -

Form No.：QS-073-F02

Rev.：1

Kept by： DCC

Ret. Time： 5 Years

RT3070

Datasheet

Preliminary

Revision September 25, 2008

When transmit in 40Mhz mode, defer until extension

CCA is also clear.

0: disable

1: enable

6

R/W

LSIG_TXOP_EN

TXOP_TRUN_EN

L‐SIG TXOP protection enable

Extension of mix mode L‐SIG protection range to

following ACK/CTS.

TXOP truncation enable

Bit5: reserved

0

5:0

0x3F

Bit4: truncation for MIMO power save RTS/CTS

Bit3: truncation for user TXOP mode

Bit2: truncation for TX rate group change

Bit1: truncation for AC change

Bit0: TXOP timeout truncation

0: disable

1: enable

TX_RTS_CFG (offset: 0x1344, default: 0x00FF_FF07)

Bits

31:24

24

Type

R

R/W

Name

Description

Reserved

RTS rate fallback enable

RTS threshold (unit: byte)

MPDU or AMPDU with length greater than RTS

threshold will be protected with RTS/CTS exchange

at the beginning of the TXOP.

Auto RTS retry limit

Initial value

0

RTS_FBK_EN

RTS_THRES

23:8

65535

7:0

R/W

RTS_RTY_LIMIT

7

TX_TIMEOUT_CFG (offset: 0x1348, default: 0x0000_1290)

Bits

31:24

23:16

Type

R

R/W

Name

Description

Reserved

TXOP timeout value for TXOP truncation

Unit: 1μsec

Initial value

0

15

TXOP_TIMEOUT

Note: It is recommended that (SLOT_TIME) >

(TXOP_TIMEOUT) > (RX_ACK_TIMEOUT)

Default: For 20μs long slot time.

RX ACK/CTS timeout value for TX procedure

Unit: 1μsec

Note: It is recommended that (SLOT_TIME) >

(TXOP_TIMEOUT) > (RX_ACK_TIMEOUT)

Default: For 20μs long slot time.

TX MPDU expiration time

15:8

R/W

RX_ACK_TIMEOUT

MPDU_LIFE_TIME

10

7:4

3:0

R/W

9

0

Expiration time = 2^(9+MPDU_LIFE_TIME) μs

Default value is 2^(9+9) ~= 256ms

Reserved

TX_RTY_CFG (offset: 0x134C, default: 0x2BB8_0407)

Bits

31

Type

R

Name

Description

Reserved

Initial value

0

DSRT3070_V1.2_092508

- 33 -

Form No.：QS-073-F02

Rev.：1

Kept by： DCC

Ret. Time： 5 Years

RT3070

Datasheet

Preliminary

Revision September 25, 2008

30

R/W

TX_AUTOFB_EN

AGG_RTY_MODE

NAG_RTY_MODE

LONG_RTY_THRES

TX retry PHY rate auto fallback enable

0: disable

1: enable

Aggregate MPDU retry mode

0: expired by retry limit

1: expired by MPDU life timer

Non‐aggregate MPDU retry mode

0: expired by retry limit

1: expired by MPDU life timer

Long retry threshold

0

29

1

28

0

27:16

3000

MPDU with length over this threshold is applied

with long retry limit.

15:8

7:0

R/W

LONG_RTY_LIMIT

SHORT_RTY_LIMIT

Long retry limit

Short retry limit

4

7

TX_LINK_CFG (offset: 0x1350, default: 0x007f_0020)

Bits

Type Name

Description

Initial value

31:24

23:16

15:13

12

R

R/W

REMOTE_MFS

Remote MCS feedback sequence number

Remote MCS feedback

Reserved

Piggyback CF‐ACK enable

0: disable

*

0x7F

0

REMOTE_MFB

TX_CFACK_EN

1: enable

11

10

9

R/W

TX_RDG_EN

RDG TX enable

0: disable

1: enable

MCS request TX enable

0: disable

0

TX_MRQ_EN

0

1: enable

REMOTE_UMFS_EN

TX_MFB_EN

Remote un‐solicit MFB enable

0: do not apply remote un‐solicit MFB (MFS=7)

1: apply un‐solicit MFB

TX apply remote MFB

0: disable

0

8

0

1: enable

7:0

REMOTE_MFB_LITETIME Remote MFB life time

32

Unit: 32μs

HT_FBK_CFG0 (offset: 0x1354, default: 0x6543_2100)

Bits

Type

Name

Description

Initial value

31:28 R/W

27:24 R/W

23:20 R/W

19:16 R/W

15:12 R/W

HT_MCS7_FBK

HT_MCS6_FBK

HT_MCS5_FBK

HT_MCS4_FBK

HT_MCS3_FBK

HT_MCS2_FBK

HT_MCS1_FBK

HT_MCS0_FBK

Auto fall back MCS as HT MCS =7

Auto fall back MCS as HT MCS =6

Auto fall back MCS as HT MCS =5

Auto fall back MCS as HT MCS =4

Auto fall back MCS as HT MCS =3

Auto fall back MCS as HT MCS =2

Auto fall back MCS as HT MCS =1

Auto fall back MCS as HT MCS =0

6

5

4

3

2

1

0

11:8

7:4

R/W

3:0

DSRT3070_V1.2_092508

Form No.：QS-073-F02

- 34 -

Rev.：1

Kept by： DCC

Ret. Time： 5 Years

RT3070

Datasheet

Preliminary

Revision September 25, 2008

HT_FBK_CFG1 (offset: 0x1358, default: 0xEDCB_A988)

Bits

Type

R/W

Name

Description

Initial value

31:28

27:24

23:20

19:16

15:12

11:8

7:4

HT_MCS15_FBK

HT_MCS14_FBK

HT_MCS13_FBK

HT_MCS12_FBK

HT_MCS11_FBK

HT_MCS10_FBK

HT_MCS9_FBK

HT_MCS8_FBK

Auto fall back MCS as HT MCS =15

Auto fall back MCS as HT MCS =14

Auto fall back MCS as HT MCS =13

Auto fall back MCS as HT MCS =12

Auto fall back MCS as HT MCS =11

Auto fall back MCS as HT MCS =10

Auto fall back MCS as HT MCS =9

Auto fall back MCS as HT MCS =8

14

13

12

11

10

9

8

3:0

Note1. The MCS is a fallback stopping state, as the fallback MCS is the same as current MCS.

Note2. HT TX PHY rates will not fallback to legacy PHY rates.

LG_FBK_CFG0 (offset: 0x135C, default: 0xEDCB_A988)

Bits

Type

R/W

Name

Description

Initial value

14

31:28

OFDM7_FBK

Auto fall back MCS as previous TX rate is OFDM

54Mbps.

27:24

23:20

19:16

15:12

11:8

7:4

R/W

OFDM6_FBK

OFDM5_FBK

OFDM4_FBK

OFDM3_FBK

OFDM2_FBK

OFDM1_FBK

OFDM0_FBK

Auto fall back MCS as previous TX rate is OFDM

48Mbps.

Auto fall back MCS as previous TX rate is OFDM

36Mbps.

Auto fall back MCS as previous TX rate is OFDM

24Mbps.

Auto fall back MCS as previous TX rate is OFDM

18Mbps.

Auto fall back MCS as previous TX rate is OFDM

12Mbps.

Auto fall back MCS as previous TX rate is OFDM

9Mbps.

Auto fall back MCS as previous TX rate is OFDM

6Mbps.

13

12

11

10

9

8

3:0

8

LG_FBK_CFG1 (offset: 0x1360, default: 0x0000_2100)

Bits

31:16

15:12

Type

R

R/W

Name

Description

Reserved

Auto fall back MCS as previous TX rate is CCK

11Mbps.

Auto fall back MCS as previous TX rate is CCK

5.5Mbps.

Auto fall back MCS as previous TX rate is CCK

2Mbps.

Initial value

0

2

CCK3_FBK

CCK2_FBK

CCK1_FBK

CCK0_FBK

11:8

7:4

R/W

1

0

3:0

Auto fall back MCS as previous TX rate is CCK

1Mbps.

Note1. Bit3 of each legacy fallback rate is selection of OFDM/CCK. 0=CCK, 1=OFDM.

DSRT3070_V1.2_092508

- 35 -

Form No.：QS-073-F02

Rev.：1

Kept by： DCC

Ret. Time： 5 Years

RT3070

Datasheet

Preliminary

Revision September 25, 2008

CCK_PROT_CFG (offset: 0x1364, default: 0x0010_0003)

Bits

31:27

26

Type

R

R/W

Name

Description

Reserved

RTS threshold enable on CCK TX

0: disable

Initial value

0

CCK_RTSTH_EN

1: enable

25:20

R/W

CCK_TXOP_ALLOW

CCK TXOP allowance

(0: disallow, 1: allow)

Bit25: allow GF‐40 TX

Bit24: allow GF‐20 TX

Bit23: allow MM‐40 TX

Bit22: allow MM‐20 TX

Bit21: allow OFDM TX

Bit20: allow CCK TX

TXOP protection type for CCK TX

0: None

1: Short NAV protection

2: Long NAV protection

3: Reserved (None)

Protection control frame type for CCK TX

0: None

1: RTS/CTS

2: CTS‐to‐self

3: Reserved (None)

Protection control frame rate for CCK TX

(Including RTS/CTS‐to‐self/CF‐END)

Default: CCK 11M

1

19:18

17:16

15:0

R/W

CCK_PROT_NAV

CCK_PROT_CTRL

CCK_PROT_RATE

0

0x0003

OFDM_PROT_CFG (offset: 0x1368, default: 0x0020_0003)

Bits

Type

Name

Description

Initial value

31:27

26

R

R/W

Reserved

RTS threshold enable on OFDM TX

0: disable

0

OFDM_RTSTH_EN

OFDM_PROT_TXOP

1: enable

25:20

19:18

R/W

OFDM TXOP allowance

(0: disallow, 1: allow)

Bit25: allow GF‐40 TX

Bit24: allow GF‐20 TX

Bit23: allow MM‐40 TX

Bit22: allow MM‐20 TX

Bit21: allow OFDM TX

Bit20: allow CCK TX

TXOP protection type for OFDM TX

0: None

2

OFDM_PROT_NAV

0

1: Short NAV protection

2: Long NAV protection

3: Reserved (None)

DSRT3070_V1.2_092508

- 36 -

Form No.：QS-073-F02

Rev.：1

Kept by： DCC

Ret. Time： 5 Years

RT3070

Datasheet

Preliminary

Revision September 25, 2008

17:16

15:0

R/W

OFDM_PROT_CTRL

OFDM_PROT_RATE

Protection control frame type for OFDM TX

0: None

1: RTS/CTS

2: CTS‐to‐self

3: Reserved (None)

Protection control frame rate for OFDM TX

(Including RTS/CTS‐to‐self/CF‐END)

Default: CCK 11M

0

0x0003

MM20_PROT_CFG (offset: 0x136C, default: 0x0040_4004)

Bits

31:27

26

Type

R

R/W

Name

Description

Reserved

RTS threshold enable on MM20 TX

0: disable

Initial value

0

MM20_RTSTH_EN

1: enable

25:20

R/W

MM20_PROT_TXOP

MM20 TXOP allowance

(0: disallow, 1: allow)

Bit25: allow GF‐40 TX

Bit24: allow GF‐20 TX

Bit23: allow MM‐40 TX

Bit22: allow MM‐20 TX

Bit21: allow OFDM TX

Bit20: allow CCK TX

TXOP protection type for MM20 TX

0: None

1: Short NAV protection

2: Long NAV protection

3: Reserved (None)

Protection control frame type for MM20 TX

0: None

1: RTS/CTS

2: CTS‐to‐self

3: Reserved (None)

Protection control frame rate for MM20 TX

(Including RTS/CTS‐to‐self/CF‐END)

Default: OFDM 24M

4

19:18

17:16

15:0

R/W

MM20_PROT_NAV

MM20_PROT_CTRL

MM20_PROT_RATE

0

0x4004

MM40_PROT_CFG (offset: 0x1370, default: 0x0080_4084)

Bits

31:27

26

Type

R

R/W

Name

Description

Reserved

RTS threshold enable on MM40 TX

0: disable

Initial value

0

MM40_RTSTH_EN

1: enable

25:20

R/W

MM40_PROT_TXOP

MM40 TXOP allowance

(0: disallow, 1: allow)

Bit25: allow GF‐40 TX

Bit24: allow GF‐20 TX

Bit23: allow MM‐40 TX

Bit22: allow MM‐20 TX

8

DSRT3070_V1.2_092508

- 37 -

Form No.：QS-073-F02

Rev.：1

Kept by： DCC

Ret. Time： 5 Years

RT3070

Datasheet

Preliminary

Revision September 25, 2008

Bit21: allow OFDM TX

Bit20: allow CCK TX

19:18

17:16

15:0

R/W

MM40_PROT_NAV

MM40_PROT_CTRL

MM40_PROT_RATE

TXOP protection type for MM40 TX

0: None

1: Short NAV protection

2: Long NAV protection

3: Reserved (None)

Protection control frame type for MM40 TX

0: None

1: RTS/CTS

2: CTS‐to‐self

3: Reserved (None)

Protection control frame rate for MM40 TX

(Including RTS/CTS‐to‐self/CF‐END)

Default: duplicate OFDM 24M

0

0x4084

GF20_PROT_CFG (offset: 0x1374, default: 0x0100_4004)

Bits

31:27

26

Type

R

R/W

Name

Description

Reserved

RTS threshold enable on GF20 TX

0: disable

Initial value

0

GF20_RTSTH_EN

1: enable

25:20

R/W

GF20_PROT_TXOP

GF20 TXOP allowance

(0: disallow, 1: allow)

Bit25: allow GF‐40 TX

Bit24: allow GF‐20 TX

Bit23: allow MM‐40 TX

Bit22: allow MM‐20 TX

Bit21: allow OFDM TX

Bit20: allow CCK TX

TXOP protection type for GF20 TX

0: None

1: Short NAV protection

2: Long NAV protection

3: Reserved (None)

Protection control frame type for GF20 TX

0: None

1: RTS/CTS

2: CTS‐to‐self

3: Reserved (None)

Protection control frame rate for GF20 TX

(Including RTS/CTS‐to‐self/CF‐END)

Default: OFDM 24M

16

19:18

17:16

15:0

R/W

GF20_PROT_NAV

GF20_PROT_CTRL

GF20_PROT_RATE

0

0x4004

GF40_PROT_CFG (offset: 0x1378, default: 0x0200_4084)

Bits

31:27

26

Type

R

R/W

Name

Description

Reserved

RTS threshold enable on GF40 TX

0: disable

Initial value

0

GF40_RTSTH_EN

DSRT3070_V1.2_092508

- 38 -

Form No.：QS-073-F02

Rev.：1

Kept by： DCC

Ret. Time： 5 Years

RT3070

Datasheet

Preliminary

Revision September 25, 2008

1: enable

25:20

R/W

GF40_PROT_TXOP

GF40 TXOP allowance

(0: disallow, 1: allow)

Bit25: allow GF‐40 TX

Bit24: allow GF‐20 TX

Bit23: allow MM‐40 TX

Bit22: allow MM‐20 TX

Bit21: allow OFDM TX

Bit20: allow CCK TX

16

19:18

17:16

15:0

R/W

GF40_PROT_NAV

GF40_PROT_CTRL

GF40_PROT_RATE

TXOP protection type for GF40 TX

0: None

1: Short NAV protection

2: Long NAV protection

3: Reserved (None)

Protection control frame type for GF40 TX

0: None

1: RTS/CTS

2: CTS‐to‐self

3: Reserved (None)

Protection control frame rate for GF40 TX

(Including RTS/CTS‐to‐self/CF‐END)

Default: duplicate OFDM 24M

0

0x4084

EXP_CTS_TIME (offset: 0x137C, default: 0x0038_013A)

Bits

31

Type

R

Name

Description

Reserved

Initial value

0

30:16

R/W

EXP_OFDM_CTS_TIME

Expected time for OFDM CTS response (unit: 1μs) 56

Used for outgoing NAV setting.

Default: SIFS + 6Mbps CTS

15

R

Reserved

0

14:0

R/W

EXP_CCK_CTS_TIME

Expected time for CCK CTS response (unit: 1μs)

Used for outgoing NAV setting.

Default: SIFS + 1Mbps CTS

314

EXP_ACK_TIME (offset: 0x1380, default: 0x0024_00CA)

Bits

31

Type

R

Name

Description

Reserved

Initial value

0

30:16

R/W

EXP_OFDM_ACK_TIME

Expected time for OFDM ACK response (unit: 1μs) 36

Used for outgoing NAV setting.

Default: SIFS + 6Mbps ACK preamble

15

R

Reserved

0

14:0

R/W

EXP_CCK_ACK_TIME

Expected time for OFDM ACK response (unit: 1μs) 202

Used for outgoing NAV setting.

Default: SIFS + 1Mbps ACK preamble

DSRT3070_V1.2_092508

- 39 -

Form No.：QS-073-F02

Rev.：1

Kept by： DCC

Ret. Time： 5 Years

RT3070

Datasheet

Preliminary

Revision September 25, 2008

4.4.5.

MAC RX configuration registers (offset: 0x1400)

RX_FILTR_CFG (offset: 0x1400, default: 0x0001_5F9F)

Bits

31:17

16

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

Type

R

Name

Description

Reserved

Drop reserve control subtype

Drop BAR

Drop BA

Drop PS‐Poll

Drop RTS

Drop CTS

Drop ACK

Initial value

0

1

0

1

0

1

0

1

R/W

DROP_CTRL_RSV

DROP_BAR

DROP_BA

DROP_PSPOLL

DROP_RTS

DROP_CTS

DROP_ACK

DROP_CFEND

DROP_CFACK

DROP_DUPL

DROP_BC

Drop CF‐END

Drop CF‐END + CF‐ACK

Drop duplicated frame

Drop broadcast frame

Drop multicast frame

Drop 802.11 version error frame

Drop frame that is not my BSSID

Drop not to me unicast frame

Drop physical error frame

Drop CRC error frame

DROP_MC

DROP_VER_ERR

DROP_NOT_MYBSS

DROP_UC_NOME

DROP_PHY_ERR

DROP_CRC_ERR

0

Note: 1: enable,

0: disable.

AUTO_RSP_CFG (offset: 0x1404, default: 0x0000_0003)

Bits

31:8

7

6

5

Type

R

R/W

Name

Description

Reserved

Initial value

0

CTRL_PWR_BIT

BAC_ACK_POLICY

CTRL_WRAP_EN

Power bit value in control frame

BA frame ‐> BAC ‐> Ack policy bit value

ACK/CTS Control Wrapper frame auto‐responding

0

enable

0: disable

1: enable

4

3

R/W

CCK_SHORT_EN

CTS_40M_REF

CCK short preamble auto response enable

0: disable

1: enable

In duplicate legacy CTS response mode, refer to

extension CCA to decide duplicate or not.

0: disable

0

1: enable

2

1

R/W

CTS_40M_MODE

Duplicate legacy CTS response mode

0: disable

1: enable

BAC ACK policy bit enable

0: disable; don’t care this bit

1: enable; no BA auto responding upon reception of

0

1

BAC_ACKPOLICY_EN

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BAR with no ACK policy

Auto responder enable

0

R/W

AUTO_RSP_EN

1

LEGACY_BASIC_RATE (offset: 0x1408, default: 0x0000_0000)

Bits

31: 12

11: 0

Type

R/W

Name

Description

Reserved

Initial value

0

LEGACY_BASIC_RATE

Legacy basic rate bit mask

Bit0: 1 Mbps is basic rate

Bit1: 2 Mbps is basic rate

Bit2: 5.5 Mbps is basic rate

Bit3: 11 Mbps is basic rate

Bit4: 6 Mbps is basic rate

Bit5: 9 Mbps is basic rate

Bit6: 12 Mbps is basic rate

Bit7: 18 Mbps is basic rate

Bit8: 24 Mbps is basic rate

Bit9: 36 Mbps is basic rate

Bit10: 48 Mbps is basic rate

Bit11: 54 Mbps is basic rate

0: disable

1: enable

HT_BASIC_RATE (offset: 0x140C, default: 0x8200_8000)

Bits

31: 0

Type

R/W

Name

Reserved

Description

Initial value

0

HT_CTRL_CFG (offset: 0x1410, default: 0x0000_0100)

Bits

31: 9

8: 0

Type

R

R/W

Name

Description

Reserved

Initial value

0

256

HT_CTRL_THRES

Remaining TXOP threshold for HT control frame

auto responding

(unit:μs)

SIFS_COST_CFG (offset: 0x1414, default: 0x0000_100A)

Bits

31:16

15:8

Type

R

R/W

Name

Description

Reserved

OFDM SIFS time (unit: 1μs)

Applied after OFDM TX/RX.

CCK SIFS time (unit: 1μs)

Applied after CCK TX/RX.

Initial value

OFDM_SIFS_COST

CCK_SIFS_COST

16

10

7:0

R/W

Note: The OFDM_SIFS_COST and CCK_SIFS_COST are used only for duration field calculation. It will not affect the

responding timing.

RX_PARSER_CFG (offset: 0x1418, default: 0x0FFF_0000)

Bits

31:28

27:16

Type

R

R/W

Name

Description

Reserved

Initial value

4095

LSIG_LEN_THRES

When the length in L‐SIG is longer than this

threshold, the L‐SIG TXOP will not be applied as NAV

DSRT3070_V1.2_092508

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Form No.：QS-073-F02

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RT3070

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channel reservation.

Reserved

Respect LSIG‐TXOP as channel reservation

0: disable

1: enable

Set NAV for all received frames

15:02

1

R

R/W

RX_LSIG_TXOP_EN

NAV_ALL_EN

0

R/W

0: disable (unicast to me frame will not set the NAV)

1: enable

4.4.6.

MAC Security Configuration Registers (offset:0x1500)

TX_SEC_CNT0 (offset:0x1500, default: 0x0000_0000)

Bits

31:16

15:0

Type

RC

Name

TX_SEC_ERR_CNT

TX_SEC_CPL_CNT

Description

TX SEC packet error count

TX SEC packet complete count

Initial value

0

RX_SEC_CNT0 (offset:0x1504, default: 0x0000_0000)

Bits

Type

Name

Description

Initial value

31:16

15:0

Reserved

RX SEC packet complete count

0

RC

RX_SEC_CPL_CNT

CCMP_FC_MUTE (offset:0x1508, default: 0xC78F_C78f)

Bits

31:16

15:0

Type

R/W

Name

HT_CCMP_FC_MUTE

LG_CCMP_FC_MUTE

Description

HT rate CCMP FC mute

Legacy rate CCMP FC mute

Initial value

0xc78f

4.4.7.

MAC HCCA/PSMP CSR (offset:0x1600)

TXOP_HLDR_ADDR0 (offset:0x1600, default :0x0000_0000)

Bits

Type

R/W

Name

Description

Initial value

31:24

23:16

15:8

7:0

TXOP_HOL_3

TXOP_HOL_2

TXOP_HOL_1

TXOP_HOL_0

TXOP holder MAC address byte3

TXOP holder MAC address byte2

TXOP holder MAC address byte1

TXOP holder MAC address byte0

0

TXOP_HLDR_ADDR1 (offset:0x1604, default :0x0000_0000)

Bits

Type

R

R/W

Name

Description

Reserved

TXOP holder MAC address byte5

TXOP holder MAC address byte4

Initial value

31:16

15:8

7:0

0

TXOP_HOL_5

TXOP_HOL_4

Note: Byte0 is the first byte on network. Its LSB bit is the first bit on network. For a MAC address captured on the

network with order 00:01:02:03:04:05, byte0=00, byte1=01 etc.

TXOP_HLDR_ET (offset:0x1608, default :0x0000_0000)

Bits

31:25

24

Type Name

R

Description

Reserved

Accumulate AMPDU enable

0: disable

Initial value

0

R/W

AMPDU_ACC_EN

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1: enable

23:19

18

R/W

TX_DMA_TIMEOUT

TX_FBK_THRES_EN

TX_FBK_THRES

When AMPDU_ACC_EN is enabled:

Wait at most (TX_DMA_TIMEOUT * 32) usec for the

MPDU for aggregation

Transmission MCS fallback threshold enable

0: disable

0

1: enable

17:16

When TX_FBK_THRES_EN is enabled, fallback when

0: less than 25% in AMPDU are success.

1: less than 50% in AMPDU are success.

2: less than 75% in AMPDU are success.

3: less than 100% in AMPDU are success.

Reserved

When PAPE_MAP1S_EN is enabled:

0: only turn on PAPE0 for 1S transmission

1: only turn on PAPE1 for 1S transmission

Turn on only on PAPE in 1S transmission

0: disable, 1: enable

15:5

4

R

R/W

0

PAPE_MAP

3

2

R/W

PAPE_MAP1S_EN

TX_BCN_HIPRI_DIS

0

Disable high priority beacon transmission

1: disable

0: enable

1

0

R/W

TX40M_BLK_EN

PER_RX_RST_EN

Block 40Mhz transmission as extension CCA is busy

0: disable

1: enable

Baseband RX_PE per RX reset enable

0: disable

0

1: enable

QOS_CFPOLL_RA_DW0 (offset:0x160C, default :0xXXXX_XXXX)

Bits

Type

Name

Description

Initial value

31:24

23:16

15:8

7:0

R

CFPOLL_A1_BYTE3

CFPOLL_A1_BYTE2

CFPOLL_A1_BYTE1

CFPOLL_A1_BYTE0

Byte3 of A1 of received QoS Data (+) CF‐Poll frame

Byte2 of A1 of received QoS Data (+) CF‐Poll frame

Byte1 of A1 of received QoS Data (+) CF‐Poll frame

Byte0 of A1 of received QoS Data (+) CF‐Poll frame

X

QOS_CFPOLL_A1_DW1 (offset:0x1610, default :0x0000_XXXX)

Bits

31:24

16

Type

R

Name

Description

Reserved

1: QoS CF‐Poll to me

Initial value

0

X

CFPOLL_A1_TOME

0: Qos CF‐Poll not to me

15:8

7:0

R

CFPOLL_A1_BYTE5

CFPOLL_A1_BYTE4

Byte5 of A1 of received QoS Data (+) CF‐Poll frame

Byte4 of A1 of received QoS Data (+) CF‐Poll frame

X

QOS_CFPOLL_QC (offset:0x1614, default :0x0000_XXXX)

Bits

Type

Name

Description

Initial value

31:24

15:8

7:0

R

Reserved

0

X

CFPOLL_QC_BYTE1

CFPOLL_QC_BYTE0

Byte1 of QC of received QoS Data (+) CF‐Poll frame

Byte0 of QC of received QoS Data (+) CF‐Poll frame

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Kept by： DCC

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Revision September 25, 2008

Note: CFPOLL_RA_DW0, CFPOLL_RA_DW1, and CFPOLL_QC are updated after the reception of QoS Data (+) CF‐Poll

frame and RX QoS CF‐Poll interrupt (RX_QOS_CFPOLL_INT) is launched then.

4.4.8.

MAC Statistic Counters (offset:0x1700)

RX_STA_CNT0 (offset:0x1700, default: 0x0000_0000)

Bits

31:16

15:0

Type

RC

Name

PHY_ERRCNT

CRC_ERRCNT

Description

RX PHY error frame count

RX CRC error frame count

Initial value

0

Note1: RX PHY error means PSDU length is shorter than indicated by PLCP.

Note2: RX PHY error is also treated as CRC error.

RX_STA_CNT1 (offset:0x1704, default: 0x0000_0000)

Bits

31:16

15:0

Type

RC

Name

PLPC_ERRCNT

CCA_ERRCNT

Description

RX PLCP error count

CCA false alarm count

Initial value

0

Note1: CCA false alarm means there is no PLCP after CCA indication.

Note2: RX PLCP error means there is no PSDU after PLCP indication.

RX_STA_CNT2 (offset:0x1708, default: 0x0000_0000)

Bits

31:16

15:0

Type

RC

Name

RX_OVFL_CNT

RX_DUPL_CNT

Description

RX FIFO overflow frame count

RX duplicated filtered frame count

Initial value

0

Note: MAC will NOT auto respond ACK/BA to the frame originator when the frame is lost due to RXFIFO overflow.

However, MAC will respond when the duplicated frame is filtered.

TX_STA_CNT0 (offset:0x170C, default: 0x0000_0000)

Bits

31:16

15:0

Type

RC

Name

TX_BCN_CNT

TX_FAIL_CNT

Description

TX beacon count

Failed TX count

Initial value

0

TX_STA_CNT1 (offset:0x1710, default: 0x0000_0000)

Bits

31:16

15:0

Type

RC

Name

TX_RTY_CNT

TX_SUCC_CNT

Description

TX retransmission count

Successful TX count

Initial value

0

TX_STA_CNT2 (offset:0x1714, default: 0x0000_0000)

Bits

31:16

15:0

Type

RC

Name

TX_UDFL_CNT

TX_ZERO_CNT

Description

TX underflow count

TX zero length frame count

Initial value

0

TX_STAT_FIFO (offset:0x1718, default: 0x0000_0000)

Bits

31:16

15:8

7

Type

Name

Description

TX success rate

TX WCID

Initial value

R

TXQ_RATE

TXQ_WCID

TXQ_ACKREQ

*

TX acknowledgment required

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0: not required

1: required

6

5

R

TXQ_AGG

TXQ_OK

TX aggregate

*

0: non‐aggregated

1: aggregated

TX success

0: failed

1: success

4:1

0

R

RC

TXQ_PID

TXQ_VLD

TX Packet ID (Latched from TXWI)

TX status queue valid

0: queue empty

1: valid

*

0

Note: TX status FIFO size = 16.

TX_NAG_AGG_CNT (offset:0x171C, default: 0x0000_0000)

Bits

31:16

15:0

Type

RC

Name

TX_AGG_CNT

TX_NAG_CNT

Description

Aggregate TX count

Non‐aggregate TX count

Initial value

0

TX_AGG_CNT0 (offset:0x1720, default: 0x0000_0000)

Bits

31:16

15:0

Type

RC

Name

TX_AGG_2_CNT

TX_AGG_1_CNT

Description

Aggregate Size = 2 MPDU count

Aggregate Size = 1 MPDU count

Initial value

0

TX_AGG_CNT1 (offset:0x1724, default: 0x0000_0000)

Bits

31:16

15:0

Type

RC

Name

TX_AGG_4_CNT

TX_AGG_3_CNT

Description

Aggregate Size = 4 MPDU count

Aggregate Size = 3 MPDU count

Initial value

0

TX_AGG_CNT2 (offset:0x1728, default: 0x0000_0000)

Bits

31:16

15:0

Type

RC

Name

TX_AGG_6_CNT

TX_AGG_5_CNT

Description

Aggregate Size = 6 MPDU count

Aggregate Size = 5 MPDU count

Initial value

0

TX_AGG_CNT3 (offset:0x172C, default: 0x0000_0000)

Bits

31:16

15:0

Type

RC

Name

TX_AGG_8_CNT

TX_AGG_7_CNT

Description

Aggregate Size = 8 MPDU count

Aggregate Size = 7 MPDU count

Initial value

0

TX_AGG_CNT4 (offset:0x1730, default: 0x0000_0000)

Bits

31:16

15:0

Type

RC

Name

TX_AGG_10_CNT

TX_AGG_9_CNT

Description

Aggregate Size = 10 MPDU count

Aggregate Size = 9 MPDU count

Initial value

0

TX_AGG_CNT5 (offset:0x1734, default: 0x0000_0000)

Bits

31:16

15:0

Type

RC

Name

TX_AGG_12_CNT

TX_AGG_11_CNT

Description

Aggregate Size = 12 MPDU count

Aggregate Size = 11 MPDU count

Initial value

0

DSRT3070_V1.2_092508

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TX_AGG_CNT6 (offset:0x1738, default: 0x0000_0000)

Bits

31:16

15:0

Type

RC

Name

TX_AGG_14_CNT

TX_AGG_13_CNT

Description

Aggregate Size = 14 MPDU count

Aggregate Size = 13 MPDU count

Initial value

0

TX_AGG_CNT7 (offset:0x173C, default: 0x0000_0000)

Bits

31:16

15:0

Type

RC

Name

TX_AGG_16_CNT

TX_AGG_15_CNT

Description

Aggregate Size > 16 MPDU count

Aggregate Size = 15 MPDU count

Initial value

0

MPDU_DENSITY_CNT (offset:0x1740, default: 0x0000_0000)

Bits

31:16

15:0

Type

RC

Name

RX_ZERO_DEL_CNT

TX_ZERO_DEL_CNT

Description

RX zero length delimiter count

TX zero length delimiter count

Initial value

0

RTS_TX_CNT (offset:0x1744, default: 0x0000_0000)

Bits

31:16

15:0

Type

RC

Name

RTS_TX_FAIL_CNT

RTS_TX_OK_CNT

Description

RTS TX fail count

RTS TX OK count

Initial value

0

CTS_TX_CNT (offset:0x1748, default: 0x0000_0000)

Bits

31:16

15:0

Type

R

RC

Name

Description

Reserved

CTS‐to‐self TX count

Initial value

0

CTSTS_TX_CNT

4.4.9.

MAC search table (offset: 0x1800)

RX WCID search entry format (8 bytes)

Offset

0x00

0x01

0x02

0x03

0x04

0x05

0x06

Type

R/W

Name

Description

Initial value

0x00

WC_MAC_ADDR0

WC_MAC_ADDR1

WC_MAC_ADDR2

WC_MAC_ADDR3

WC_MAC_ADDR4

WC_MAC_ADDR5

BA_SESS_MASK0

Client MAC address byte0

Client MAC address byte1

Client MAC address byte2

Client MAC address byte3

Client MAC address byte4

Client MAC address byte5

0x00

BA session mask (lower)

Bit0 for TID0

0x00

Bit7 for TID7

0x07

R/W

BA_SESS_MASK1

BA session mask (upper)

Bit8 for TID8

0x00

Bit15 for TID15

RX WCID search table (offset:0x1800)

Offset

0x1800

0x1808

….

Type

R/W

Name

Description

Initial value

WC_ENTRY_0

WC_ENTRY_1

….

WC MAC address with WCID=0

WC MAC address with WCID=1

WC MAC address with WCID=2~253

0

DSRT3070_V1.2_092508

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Form No.：QS-073-F02

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0x1FF0

0x1FF8

R/W

WC_ENTRY_254

WC_ENTRY_255

WC MAC address with WCID=254

Reserved (shall not be used)

0

Note1: WCID=Wireless Client ID

DSRT3070_V1.2_092508

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Form No.：QS-073-F02

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Revision September 25, 2008

4.5.Security table/CIS/Beacon/NULL frame (offset: 0x4000)

4.5.1 Security Entry format

Security Key Format (8DW)

Offset

0x00

0x04

0x08

0x0C

0x10

0x14

0x18

0x1C

Note:

Type

R/W

Name

Description

Initial value

SECKEY_DW0

SECKEY_DW1

SECKEY_DW2

SECKEY_DW3

TXMIC_DW0

TXMIC_DW1

RXMIC_DW0

RXMIC_DW1

Security key byte3~0

Security key byte7~4

Security key byte11~8

Security key byte15~12

TX MIC key byte3~0

TX MIC key byte7~4

RX MIC key byte3~0

RX MIC key byte7~4

*

1. For WEP40, CKIP40, only byte4~0 of security key are valid.

2. For WEP104, CKIP104, only byte12~0 of security key are valid.

3. For TKIP, AES, all the bytes of security key are valid.

4. TX/RX MIC key is used only for TKIP MIC calculation.

IV/EIV format (2 DW)

When TXINFO.WIV=0, hardware will auto lookup IV/EIV from this table and update IV/EIV after encryption is finished.

Offset

0x00

0x04

Type

R/W

Name

IV_FIELED

EIV_FIELED

Description

IV field

EIV field

Initial value

*

Note1: The key index and extension IV bit shall be initialized by the software. The MSB octet of IV will not be modified

by hardware.

Note2: IV/EIV packet number (PN) counter modes:

a. For WEP40, WEP104, CKIP40, CKIP104, CKIP128 mode, PN=IV[23:0]. EIV[31:0] is not used.

b. For TKIP mode, PN = {EIV[31:0], IV[7:0], IV[23:16]}, IV[15:8]=(IV[7:0] | 0x20) & 0x7f) is generated by hardware.

c. For AES‐CCMP, PN = {EIV[31:0], IV[15:0]}.

d. PN = PN + 1 after each encryption.

Note3: Software may initialize the PN counter to any value.

WCID attribute entry format (1DW)

Offset

31:10

9:7

Type

R/W

Name

Description

Reserved

Initial value

*

RXWI_UDF

RXWI user define field

This field is tagged in the RXWI.UDF fields for the

WCID.

6:4

3:1

R/W

BSS_IDX

RX_PKEY_MODE

Multiple‐BSS index for the WCID

Pair‐wise key security mode

0: No security

*

1: WEP40

DSRT3070_V1.2_092508

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Form No.：QS-073-F02

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RT3070

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Revision September 25, 2008

2: WEP104

3: TKIP

4: AES‐CCMP

5: CKIP40

6: CKIP104

7: CKIP128

0

R/W

RX_PKEY_EN

Key table selection

0: shared key table

1: pair‐wise key table

*

Share key mode entry format (1DW)

Bits

31