RT54SX16-1CQ256M [ETC]
Field Programmable Gate Array (FPGA) ; 现场可编程门阵列(FPGA)的\n型号: | RT54SX16-1CQ256M |
厂家: | ETC |
描述: | Field Programmable Gate Array (FPGA)
|
文件: | 总36页 (文件大小:775K) |
中文: | 中文翻译 | 下载: | 下载PDF数据表文档文件 |
v2.0
54SX Family FPGAs
RadTolerant and HiRel
High Density Devices
Features
• 16,000 and 32,000 Available Logic Gates
RadTolerant 54SX Family
• Up to 228 User I/Os
• Tested Total Ionizing Dose (TID) Survivability Level
• Up to 1,080 Dedicated Flip-Flops
• Radiation Performance to 100Krads (Si) (ICC Standby
Parametric)
Easy Logic Integration
• Devices Available from Tested Pedigreed Lots
• Up to 160 MHz On-Chip Performance
• Offered as Class B and E-Flow (Actel Space Level Flow)
• QMl Certified Devices
• Non-Volatile, User Programmable
• Highly Predictable Performance with 100% Automatic
Place and Route
• 100% Resource Utilization with 100% Pin Locking
• Mixed Voltage Support—3.3V Operation with 5.0V Input
Tolerance for Low Power Operation
HiRel 54SX Family
• Fastest HiRel FPGA Family Available
• JTAG Boundary Scan Testing in Compliance with IEEE
Standard 1149.1
• Up to 240 MHz On-Chip Performance
• Low Cost Prototyping Vehicle for RadTolerant Devices
• Secure Programming Technology Prevents Reverse
Engineering and Design Theft
• Offered as Commercial or Military Temperature Tested
and Class B
• Permanently Programmed for Operation on Power-Up
• Cost Effective QML MIL-Temp Plastic Packaging Options
• Standard Hermetic Packaging Offerings
• QML Certified Devices
• Unique In-System Diagnostic and Debug Facility with
Silicon Explorer
• Supported by Actel’s Designer Series and DeskTOP Series
Development Systems with Automatic Timing Driven
Place and Route
• Predictable, Reliable, and Permanent Antifuse Technology
Performance
SX Product Profile
Device
RT54SX16
A54SX16
RT54SX32
A54SX32
Capacity
System Gates
Logic Gates
24,000
16,000
24,000
16,000
48,000
32,000
48,000
32,000
Logic Modules
Register Cells
Combinatorial Cells
User I/Os (Maximum)
JTAG
1,452
528
924
179
1,452
528
924
180
Yes
2,880
1,080
1,800
227
2,880
1,080
1,800
228
Yes
Yes
Yes
Packages (by pin count)
CQFP
208, 256
208, 256
208, 256
208, 256
March 2001
1
© 2001 Actel Corporation
54SX Family FPGAs RadTolerant and HiRel
Ordering Information
RT54SX32
–
1
CQ
256
B
Application (Temperature Range)
Blank = Commercial (0 to +70°C)
M = Military (–55 to +125°C)
B = MIL-STD-883
E = E-Flow (Actel Space Level Flow)
Package Lead Count
Package Type
CQ = Ceramic Quad Flat Pack
Speed Grade
Blank = Standard Speed
–1 = Approximately 15% Faster than Standard
Part Number
A54SX16= 16,000 Gates
A54SX32= 32,000 Gates
RT54SX16=16,000 Gates—RadTolerant
RT54SX32=32,000 Gates—Rad Tolerant
Product Plan
Speed Grade
Application
Std
–1*
C
M
B
E
RT54SX16 Devices
208-Pin Ceramic Quad Flat Pack (CQFP)
256-Pin Ceramic Quad Flat Pack (CQFP)
A54SX16 Devices
✔
✔
✔
✔
✔
✔
✔
✔
✔
✔
✔
✔
208-Pin Ceramic Quad Flat Pack (CQFP)
256-Pin Ceramic Quad Flat Pack (CQFP)
RT54SX32 Devices
✔
✔
✔
✔
✔
✔
✔
✔
✔
✔
—
—
208-Pin Ceramic Quad Flat Pack (CQFP)
256-Pin Ceramic Quad Flat Pack (CQFP)
A54SX32 Devices
✔
✔
✔
✔
✔
✔
✔
✔
✔
✔
✔
✔
208-Pin Ceramic Quad Flat Pack (CQFP)
✔
✔
✔
✔
✔
✔
✔
✔
✔
✔
—
—
256-Pin Ceramic Quad Flat Pack (CQFP)
Contact your Actel sales representative for product availability.
Applications:
C = Commercial
M = Military
Availability: ✔
= Available
= Planned
* Speed Grade: –1 = Approx. 15% Faster than Standard
P
B = MIL-STD-883
—
= Not Planned
E = E-flow (Actel Space Level Flow)
Ceramic Device Resources
User I/Os
CQFP 208-Pin CQFP 256-Pin
Device
RT54SX16
A54SX16
RT54SX32
A54SX32
174
175
173
174
179
180
227
228
Package Definitions: CQFP = Ceramic Quad Flat Pack
(Contact your Actel sales representative for product availability.)
2
v2.0
54SX Family FPGAs RadTolerant and HiRel
General Description
radiation effects is both device and lot dependent. The
customer must evaluate and determine the applicability of
these devices to their specific design and environmental
requirements.
Actel’s RadTolerant (RT) and HiRel versions of the SX
Family of FPGAs offer all of these advantages for
applications such as commercial and military satellites,
deep space probes, and all types of military and high
reliability equipment.
Actel will provide total dose radiation testing along with the
test data on each pedigreed lot that is available for sale.
These reports are available on our website or you can
contact your local sales representative to receive a copy. A
listing of available lots and devices will also be provided.
These results are only provided for reference and for
customer information.
The RT and HiRel versions are fully pin compatible allowing
designs to migrate across different applications that may or
may not have radiation requirements. Also, the HiRel
devices can be used as a low cost prototyping tool for RT
designs.
The programmable architecture of these devices offer high
performance, design flexibility, and fast and inexpensive
prototyping—all without the expense of test vectors, NRE
charges, long lead times, and schedule and cost penalties
for design modifications that are required by ASIC devices.
For
a radiation performance summary, see Radiation
Performance of Actel Products at http://www.actel.com/hirel
.
This summary will also show single event upset (SEU) and single
event latch-up (SEL) testing that has been performed on Actel
FPGAs.
Device Description
QML Certification
The RT54SX16 and A54SX16 devices have 16,000 available
gates and up to 179 I/Os. The RT54SX32 and A54SX32 have
32,000 available gates and up to 228 I/Os. All of these
devices support JTAG boundary scan testability.
Actel has achieved full QML certification, demonstrating
that quality management, procedures, processes, and
controls are in place and comply with MIL-PRF-38535, the
performance specification used by the Department of
All of these devices are available in Ceramic Quad Flat Pack
(CQFP) packaging, with 208-pin and 256-pin versions. The
256-pin version offers the user the highest I/O capability,
while the 208-pin version offers pin compatibility with the
commercial Plastic Quad Flat Pack (PQFP-208). This
compatibility allows the user to prototype using the very low
cost plastic package and then switch to the ceramic
package for production. For more information on plastic
packages, refer to the SX family FPGAs data sheet at:
Defense for monolithic integrated circuits.
QML
certification is a good example of Actel's commitment to
supplying the highest quality products for all types of
high-reliability, military and space applications.
Many suppliers of microelectronics components have
implemented QML as their primary worldwide business
system. Appropriate use of this system not only helps in the
implementation of advanced technologies, but also allows
for a quality, reliable and cost-effective logistics support
throughout QML products’ life cycles.
http://www.actel.com/docs/datasheets/A54SXDS.pdf
The A54SX16 and A54SX32 are manufactured using a 0.35µ
technology at the Chartered Semiconductor facility in
Singapore. These devices offer the highest speed
performance available in FPGAs today.
Disclaimer
All radiation performance information is provided for
information purposes only and is not guaranteed. The total
dose effects are lot-dependent, and Actel does not
guarantee that future devices will continue to exhibit
similar radiation characteristics. In addition, actual
performance can vary widely due to a variety of factors,
including but not limited to, characteristics of the orbit,
radiation environment, proximity to satellite exterior,
amount of inherent shielding from other sources within the
satellite and actual bare die variations. For these reasons,
Actel does not guarantee any level of radiation survivability,
and it is solely the responsibility of the customer to
determine whether the device will meet the requirements
of the specific design.
The RT54SX16 and RT54SX32 are manufactured using a
0.6µ technology at the Matsushita (MEC) facility in Japan.
These devices offer levels of radiation survivability far in
excess of typical CMOS devices.
Radiation Survivability
Total dose results are summarized in two ways. First by the
maximum total dose level that is reached when the parts
fail to meet a device specification but remain functional.
For Actel FPGAs, the parameter that exceeds the
specification first is ICC, the standby supply current. Second
by the maximum total dose that is reached prior to the
functional failure of the device.
The RT SX devices have varying total dose radiation
survivability. The ability of these devices to survive
v2.0
3
54SX Family FPGAs RadTolerant and HiRel
SX Family Architecture
The SX family architecture was designed to satisfy
next-generation performance and integration requirements
for production-volume designs in a broad range of
applications.
antifuse interconnect elements, which are embedded
between the M2 and M3 layers. The antifuses are normally
open circuit and, when programmed, form a permanent
low-impedance connection.
The extremely small size of these interconnect elements
gives the SX family abundant routing resources and provides
excellent protection against design pirating. Reverse
engineering is virtually impossible, because it is extremely
difficult to distinguish between programmed and
unprogrammed antifuses, and there is no configuration
bitstream to intercept.
Programmable Interconnect Element
Actel’s SX family provides much more efficient use of silicon
by locating the routing interconnect resources between the
Metal 2 (M2) and Metal 3 (M3) layers (Figure 1). This
completely eliminates the channels of routing and
interconnect resources between logic modules (as
implemented on SRAM FPGAs and previous generations of
antifuse FPGAs), and enables the entire floor of the device
to be spanned with an uninterrupted grid of logic modules.
Additionally, the interconnects (i.e., the antifuses and metal
tracks) have lower capacitance and lower resistance than
any other device of similar capacity, leading to the fastest
signal propagation in the industry.
Interconnection between these logic modules is achieved
using Actel’s patented metal-to-metal programmable
Routing Tracks
Metal 3
Amorphous Silicon/
Dielectric Antifuse
Tungsten Plug Via
Metal 2
Metal 1
Tungsten Plug
Contact
Silicon Substrate
Figure 1 • SX Family Interconnect Elements
Logic Module Design
programmable clock polarity, selectable on
a
The SX family architecture has been called
a
register-by-register basis (Figure 3 on page 5). This provides
the designer with additional flexibility while allowing
mapping of synthesized functions into the SX FPGA. The
clock source for the R-cell can be chosen from the
hard-wired clock or the routed clock.
“sea-of-modules” architecture because the entire floor of
the device is covered with a grid of logic modules with
virtually no chip area lost to interconnect elements or
routing (see Figure 2 on page 5). Actel provides two types of
logic modules, the register cell (R-cell) and the
combinatorial cell (C-cell).
The C-cell implements a range of combinatorial functions
up to 5-inputs (Figure 4 on page 6). Inclusion of the DB
input and its associated inverter function dramatically
increases the number of combinatorial functions that can be
implemented in a single module from 800 options in
previous architectures to more than 4,000 in the SX
The R-cell contains a flip-flop featuring more control signals
than in previous Actel architectures, including
asynchronous clear, asynchronous preset, and clock enable
(using the S0 and S1 lines). The R-cell registers feature
4
v2.0
54SX Family FPGAs RadTolerant and HiRel
Channelled Array Architecture
Sea-of-Modules Architecture
Figure 2 • Channelled Array and Sea-of-Modules Architectures
Routed
Data Input
S1
S0
PSET
Direct
Connect
Input
D
Q
Y
HCLK
CLKA,
CLKB
CLRB
CKS
CKP
Figure 3 • R-Cell
Module Organization
architecture. An example of the improved flexibility
enabled by the inversion capability is the ability to integrate
a 3-input exclusive-OR function into a single C-cell. This
facilitates construction of 9-bit parity-tree functions with 2
ns propagation delays. At the same time, the C-cell
structure is extremely synthesis-friendly, simplifying the
overall design and reducing synthesis time.
Actel has arranged all C-cell and R-cell logic modules into
horizontal banks called Clusters. There are two types of
Clusters: Type 1 contains two C-cells and one R-cell, while
Type 2 contains one C-cell and two R-cells.
To increase design efficiency and device performance, Actel
has further organized these modules into SuperClusters
(see Figure 5 on page 6). SuperCluster 1 is a two-wide
grouping of Type 1 clusters. SuperCluster 2 is a two-wide
group containing one Type 1 cluster and one Type 2 cluster.
SX devices feature more SuperCluster 1 modules than
SuperCluster 2 modules because designers typically require
more combinatorial logic than flip-flops.
Chip Architecture
The SX family’s chip architecture provides
a
uniqueapproach to module organization and chip routing
that delivers the best register/logic mix for a wide variety of
new and emerging applications.
v2.0
5
54SX Family FPGAs RadTolerant and HiRel
D0
D1
Y
D2
D3
Sa
Sb
DB
A0 B0
A1 B1
Figure 4 • C-Cell
R-Cell
C-Cell
D0
Routed
Data Input
S1
D1
S0
PSET
Y
D2
D3
Direct
Connect
Input
D
Q
Y
Sa
Sb
HCLK
CLKA,
CLKB
CLRB
DB
CKS
CKP
A0 B0
A1 B1
Cluster 1
Cluster 2
Cluster 2
Cluster 1
Type 1 SuperCluster
Type 2 SuperCluster
Figure 5 • Cluster Organization
Routing Resources
DirectConnect is a horizontal routing resource that provides
connections from a C-cell to its neighboring R-cell in a given
SuperCluster. DirectConnect uses a hard-wired signal path
requiring no programmable interconnection to achieve its
fast signal propagation time of less than 0.1 ns.
Clusters and SuperClusters can be connected through the
use of two innovative local routing resources called
FastConnect and DirectConnect that enable extremely fast
and predictable interconnections of modules within
Clusters and SuperClusters (see Figure 6 and Figure 7 on
page 7). This routing architecture also dramatically reduces
the number of antifuses required to complete a circuit,
ensuring the highest possible performance.
FastConnect enables horizontal routing between any two
logic modules within a given SuperCluster, and vertical
routing with the SuperCluster immediately below it. Only
one programmable connection is used in a FastConnect
path, delivering maximum pin-to-pin propagation of 0.4 ns.
6
v2.0
54SX Family FPGAs RadTolerant and HiRel
In addition to DirectConnect and FastConnect, the
architecture makes use of two globally-oriented routing
resources known as segmented routing and high-drive
routing. Actel’s segmented routing structure provides a
variety of track lengths for extremely fast routing between
SuperClusters. The exact combination of track lengths and
antifuses within each path is chosen by the 100% automatic
place and route software to minimize signal propagation
delays.
DirectConnect
• No antifuses
FastConnect
• One antifuse
Routing Segments
• Typically 2 antifuses
• Max. 5 antifuses
Type 1 SuperClusters
Figure 6 • DirectConnect and FastConnect for Type 1 SuperClusters
DirectConnect
• No antifuses
FastConnect
• One antifuse
Routing Segments
• Typically 2 antifuses
• Max. 5 antifuses
Type 2 SuperClusters
Figure 7 • DirectConnect and FastConnect for Type 2 SuperClusters
v2.0
7
54SX Family FPGAs RadTolerant and HiRel
Clock Resources
Other Architecture Features
Actel’s high-drive routing structure provides three clock
networks. The first clock, called HCLK, is hardwired from the
HCLK buffer to the clock select MUX in each R-cell. HCLK
cannot be connected to combinational logic. This provides a
fast propagation path for the clock signal, enabling the 5.8 ns
clock-to-out (pad-to-pad) performance of the RT54SX devices.
The hard-wired clock is tuned to provide clock skew is less
than 0.5ns worst case.
Performance
The combination of architectural features described above
enables RT54SX devices to operate with internal clock
frequencies exceeding 160 MHz, enabling very fast
execution of complex logic functions. Thus, the RT54SX
family is an optimal platform upon which to integrate the
functionality previously contained in multiple CPLDs. In
addition, designs that previously would have required a gate
array to meet performance goals can now be integrated into
an RT54SX device with dramatic improvements in cost and
time-to-market. Using timing-driven place-and-route tools,
designers can achieve highly deterministic device
performance. With RT54SX devices, designers do not need
to use complicated performance-enhancing design
techniques such as redundant logic to reduce fanout on
critical nets or the instantiation of macros in HDL code to
achieve high performance.
The remaining two clocks (CLKA, CLKB) are global clocks
that can be sourced from external pins or from internal logic
signals within the RT54SX device. CLKA and CLKB may be
connected to sequential cells or to combinational logic. If
CLKA or CLKB is sourced from internal logic signals then the
external clock pin cannot be used for any other input and
must be tied low or high. Figure 8 describes the clock circuit
used for the constant load HCLK. Figure 9 describes the
CLKA and CLKB circuit used in RT54SX devices with the
exception of RT54SX72S.
I/O Modules
Each I/O on an RT54SX device can be configured as an
input, an output, a tristate output, or a bidirectional pin.
Even without the inclusion of dedicated registers, these
I/Os, in combination with array registers, can achieve
clock-to-out (PAD-to-PAD) timing as fast as 5.8 ns. I/O cells
including embedded latches and flip-flops require
instantiation in HDL code. This is a design complication not
encountered in RT54SX FPGAs. Fast PAD-to-PAD timing
ensures that the device will have little trouble interfacing
with any other device in the system, which in turn enables
parallel design of system components and reduces overall
design time.
Constant Load
Clock Network
HCLKBUF
Figure 8 • RT54SX Constant Load Clock Pad
Clock Network
From Internal Logic
Power Requirements
The RT54SX family supports either 3.3V or 5.0V I/O voltage
operation and is designed to tolerate 5V inputs in each case
(Table 1). Power consumption is extremely low due to the
very short distances signals are required to travel to
complete a circuit. Power requirements are further reduced
due to the small number of antifuses in the path, and
because of the low resistance properties of the antifuses.
The antifuse architecture does not require active circuitry
to hold a charge (as do SRAM or EPROM), making it the
lowest-power architecture on the market.
CLKBUF
CLKBUFI
CLKINT
CLKINTI
Figure 9 • RT54SX Clock Pads
Table 1 • Supply Voltages
Maximum Maximum
Input
Tolerance
Output
Drive
VCCA VCCI VCCR
A54SX16
A54SX32
3.3V 3.3V 5.0V
3.3V
5.0V
3.3V
3.3V
RTSX16
RTSX32
3.3V 3.3V 5.0V
8
v2.0
54SX Family FPGAs RadTolerant and HiRel
Boundary Scan Testing (BST)
Table 2 • Boundary Scan Pin Functionality
All RT54SX devices are IEEE 1149.1 (JTAG) compliant.
They offer superior diagnostic and testing capabilities by
providing Boundary Scan Testing (BST) and probing
capabilities. These functions are controlled through the
special test pins in conjunction with the program fuse. The
functionality of each pin is described in Table 2. Figure 10
is a block diagram of the RT54SX JTAG circuitry.
Program Fuse Blown
(Dedicated Test Mode)
Program Fuse Not Blown
(Flexible Mode)
TCK, TDI, TDO are
dedicated test pins
TCK, TDI, TDO are flexible
and may be used as I/Os
No need for pull-up resistor Use a pull-up resistor of
for TMS
10k Ω on TMS
TDI
Data Registers (DRs)
0
1
output
stage
TDO
Instruction Register (IR)
clocks and/or controls
TMS
TCK
TAP Controller
TRST external
hard-wired pin
Figure 10 • RT54SX JTAG Circuitry
Configuring Diagnostic Pins
is automatically enabled on both the TMS and TDI pins. In
dedicated test mode, TCK, TDI, and TDO are dedicated test pins
and become unavailable for pin assignment in the Pin Editor.
The TMS pin will function as specified in the IEEE 1149.1
(JTAG) Specification.
The JTAG and Probe pins (TDI, TCK, TMS, TDO, PRA, and
PRB) are placed in the desired mode by selecting the
appropriate check boxes in the “Variation” dialog window.
This dialog window is accessible through the Design Setup
Wizard under the Tools menu in Actel’s Designer software.
Flexible Mode
TRST pin
When the “Reserve JTAG” box is not selected (default setting
in Designer software), the RT54SX is placed in flexible mode,
which allows the TDI, TCK, and TDO pins to function as user
I/Os or BST pins. In this mode the internal pull-up resistors on
the TMS and TDI pins are disabled. An external 10k Ω pull-up
resistor to VCCI is required on the TMS pin.
The TRST pin functions as a Boundary Scan Reset pin. The
TRST pin is an asynchronous, active-low input to initialize
or reset the BST circuit. An internal pull-up resistor is
automatically enabled on the TRST pin.
Dedicated Test Mode
The TDI, TCK, and TDO pins are transformed from user I/Os
into BST pins when a rising edge on TCK is detected while
TMS is at logical low. Once the BST pins are in test mode
they will remain in BST mode until the internal BST state
When the “Reserve JTAG” box is checked in the Designer
software, the RT54SX is placed in Dedicated Test mode, which
configures the TDI, TCK, and TDO pins for BST or in-circuit
verification with Silicon Explorer II. An internal pull-up resistor
v2.0
9
54SX Family FPGAs RadTolerant and HiRel
machine reaches the “logic reset” state. At this point the
BST pins will be released and will function as regular I/O
pins. The "logic reset” state is reached 5 TCK cycles after
the TMS pin is set to logical HIGH.
iteration. The probe circuitry is accessed by Silicon Explorer
II, an easy to use integrated verification and logic analysis
tool that can sample data at 100 MHz (asynchronous) or
66 MHz (synchronous). Silicon Explorer attaches to a PC’s
standard COM port, turning the PC into a fully functional 18
channel logic analyzer. Silicon Explorer allows designers to
complete the design verification process at their desks and
reduces verification time from several hours per cycle to a
few seconds.
The program fuse determines whether the device is in
Dedicated Test or Flexible mode. The default (fuse not
programmed) is Flexible mode.
Development Tool Support
The RT54SX RadTolerant devices are fully supported by
Actel’s line of FPGA development tools, including the Actel
DeskTOP Series and Designer Series’ tools. The Actel
DeskTOP Series is an integrated design environment for PCs
that includes design entry, simulation, synthesis, and
place-and-route tools. Designer Series is Actel’s suite of
FPGA development point tools for PCs and Workstations
that includes the ACTgen Macro Builder, Designer Series
with DirectTime timing driven place-and-route and analysis
tools, and device programming software.
The Silicon Explorer II tool uses the boundary scan ports
(TDI, TRST, TCK, TMS, and TDO) to select the desired nets
for verification. The selected internal nets are assigned to
the PRA/PRB pins for observation. Figure 11 illustrates the
interconnection between Silicon Explorer II and the FPGA
to perform in-circuit verification.
Design Considerations
For prototyping, the TDI, TCK, TDO, PRA, and PRB pins
should not be used as input or bidirectional ports. Because
these pins are active during probing, critical signals input
through these pins are not available while probing. In
addition, the security fuse should not be programmed during
prototyping because doing so disables the probe circuitry.
RT54SX Probe Circuit Control Pins
The RT54SX RadTolerant devices contain internal probing
circuitry that provides built-in access to every node in a
design, enabling 100-percent real-time observation and
analysis of a device's internal logic nodes without design
RT54SX-S FPGA
TRST
TCK
TMS
Serial Connection
Silicon Explorer II
TDO
PRA
PRB
Figure 11 • Probe Setup
10
v2.0
54SX Family FPGAs RadTolerant and HiRel
Recommended Operating Conditions
3.3V/5V Operating Conditions
Recommended Operating Conditions1
Symbol
Parameter
Limits
Units
Parameter
Commercial
Military
Units
VCCR
VCCA
VCCI
VI
DC Supply Voltage
DC Supply Voltage
DC Supply Voltage
Input Voltage
–0.3 to +6.0
–0.3 to +4.0
–0.3 to +4.0
–0.5 to +5.5
–0.5 to +3.6
V
V
V
V
V
Temperature
Range1
0 to +70
–55 to +125
°C
3.3V Power2
Supply Tolerance
10
5
10
10
%VCC
%VCC
VO
Output Voltage
5V Power Supply 2
Tolerance
I/O Source Sink
Current2
IIO
–30 to +5.0
–40 to +125
mA
Notes:
1. Ambient temperature (TA) is used for commercial and
industrial; case temperature (TC) is used for military.
2. All power supplies must be in the recommended operating range
for 250µs. For more information, please refer to the
Power-Up Design Considerations application note at
http://www.actel.com/appnotes.
TSTG
Storage Temperature
°C
Notes:
1. Stresses beyond those listed in the Absolute Maximum Ratings
table may cause permanent damage to the device. Exposure to
absolute maximum rated conditions for extended periods may
affect device reliability. Device should not be operated outside
the Recommended Operating Conditions.
2. The I/O source sink numbers refer to tristated inputs and
outputs
Electrical Specifications
Commercial
Military
Symbol
Parameter
Min.
Max.
Min.
Max.
Units
(IOH = –20µA) (CMOS)
(IOH = –8mA) (TTL)
(IOH = –6mA) (TTL)
(VCCI – 0.1)
VCCI
VCCI
(VCCI – 0.1)
VCCI
VOH
2.4
V
2.4
VCCI
(IOL= 20µA) (CMOS)
(IOL = 12mA) (TTL)
(IOL = 8mA) (TTL)
0.10
0.50
VOL
V
0.50
0.8
VIL
Low Level Inputs
0.8
V
V
VIH
High Level Inputs
2.0
2.0
tR, tF
CIO
Input Transition Time tR, tF
CIO I/O Capacitance
Standby Current, ICC
50
10
50
10
25
ns
pF
mA
ICC
4.0
ICC(D)
ICC(D) Dynamic
I
VCC Supply Current
See the “Power Dissipation” section on page 13.
v2.0
11
54SX Family FPGAs RadTolerant and HiRel
Power-Up Sequencing
RT54SX16, A54SX16, RT54SX32, A54SX32
VCCA
VCCR
VCCI
Power-Up Sequence
Comments
5.0V First
3.3V Second
No possible damage to device.
3.3V
5.0V
3.3V
3.3V First
Possible damage to device.
5.0V Second
Power-Down Sequencing
RT54SX16, A54SX16, RT54SX32, A54SX32
VCCA
VCCR
VCCI
Power-Down Sequence
Comments
5.0V First
3.3V Second
Possible damage to device.
3.3V
5.0V
3.3V
3.3V First
No possible damage to device.
5.0V Second
Package Thermal Characteristics
The device junction to case thermal characteristic is θjc,
and the junction to ambient air characteristic is θja. The
thermal characteristics for θja are shown with two different
air flow rates.
Maximum junction temperature is 150°C.
A sample calculation of the absolute maximum power
dissipation allowed for an RT54SX16 in a CQFP 256-pin
package at military temperature and still air is as follows:
Max. junction temp. (°C) – Max. ambient temp. (°C)
150°C – 125°C
------------------------------------
= 1.09W
------------------------------------------------------------------------------------------------------------------------------
Absolute Maximum Power Allowed =
=
θja (°C/W)
23°C/W
θja
Package Type
Pin Count
θjc
Still Air
Units
RT54SX16
Ceramic Quad Flat Pack (CQFP)
Ceramic Quad Flat Pack (CQFP)
RT54SX32
208
256
7.5
4.6
29
23
°C/W
°C/W
Ceramic Quad Flat Pack (CQFP)
Ceramic Quad Flat Pack (CQFP)
A54SX16
208
256
6.9
3.5
35
20
°C/W
°C/W
Ceramic Quad Flat Pack (CQFP)
Ceramic Quad Flat Pack (CQFP)
A54SX32
208
256
7.9
5.6
30
25
°C/W
°C/W
Ceramic Quad Flat Pack (CQFP)
Ceramic Quad Flat Pack (CQFP)
208
256
7.6
4.8
30
24
°C/W
°C/W
12
v2.0
54SX Family FPGAs RadTolerant and HiRel
Power Dissipation
and load device inputs. An additional component of the
active power dissipation is the totempole current in CMOS
transistor pairs. The net effect can be associated with an
equivalent capacitance that can be combined with
frequency and voltage to represent active power dissipation.
P = [ICCstandby + ICCactive] * VCCA + IOL * VOL * N +
I
OH *(VCCA – VOH) * M
where:
ICCstandby is the current flowing when no inputs or
outputs are changing.
Equivalent Capacitance
The power dissipated by a CMOS circuit can be expressed by
Equation 1:
ICCactive is the current flowing due to CMOS switching.
IOL, IOH are TTL sink/source currents.
Power (µW) = CEQ * VCCA2 * F
(1)
VOL, VOH are TTL level output voltages.
where:
N equals the number of outputs driving TTL loads to VOL.
M equals the number of outputs driving TTL loads to VOH.
CEQ
VCCA
F
= Equivalent capacitance in pF
= Power supply in volts (V)
= Switching frequency in MHz
Accurate values for N and M are difficult to determine
because they depend on the design and on the system I/O.
The power can be divided into two components: static and
active.
Equivalent capacitance is calculated by measuring
ICCactive at a specified frequency and voltage for each
circuit component of interest. Measurements have been
Static Power Component
made over a range of frequencies at a fixed value of VCCA
.
The power due to standby current is typically a small
component of the overall power. Standby power is shown
below for military, worst case conditions (70°C).
Equivalent capacitance is frequency-independent so that
the results may be used over a wide range of operating
conditions. Equivalent capacitance values are shown below.
ICC
VCC
Power
CEQ Values (pF)
20 mA
3.6V
72 mW
To calculate the active power dissipated from the complete
design, the switching frequency of each part of the logic
must be known. Equation 2 shows a piece-wise linear
summation over all components.
Active Power Component
Power dissipation in CMOS devices is usually dominated by
the active (dynamic) power dissipation. This component is
frequency-dependent, a function of the logic and the
external I/O. Active power dissipation results from charging
internal chip capacitances of the interconnect,
unprogrammed antifuses, module inputs, and module
outputs, plus external capacitance due to PC board traces
Power =VCCA2 * [(m * CEQM * fm)modules
+
(n * CEQI * fn)inputs+ (p * (CEQO + CL) * fp)outputs
+
0.5 * (q1 * CEQCR * fq1)routed_Clk1 + (r1 * fq1)routed_Clk1
0.5 * (q2 * CEQCR * fq2)routed_Clk2+ (r2 * fq2)routed_Clk2
+
+
0.5 * (s1 * CEQCD * fs1)dedicated_CLK
]
(2)
RT54SX16
A54SX16
RT54SX32
A54SX32
Equivalent Capacitance (pF)
Modules
CEQM
CEQI
7.0
2.0
3.9
1.0
7.0
2.0
3.9
1.0
Input Buffers
Output Buffers
CEQO
CEQCR
CEQCD
10.0
0.4
5.0
10.0
0.6
5.0
Routed Array Clock Buffer Loads
Dedicated Clock Buffer Loads
Fixed Capacitance (pF)
0.2
0.3
0.25
0.15
0.34
0.23
routed_Clk1
r1
r2
120
120
60
60
210
210
107
107
routed_Clk2
Fixed Clock Loads
Clock Loads on Dedicated Array Clock
s1
528
528
1,080
1,080
v2.0
13
54SX Family FPGAs RadTolerant and HiRel
Determining Average Switching Frequency
To determine the switching frequency for a design, you must
have a detailed understanding of the data input values to
the circuit. The following guidelines are meant to represent
worst-case scenarios so that they can be generally used to
predict the upper limits of power dissipation. These
guidelines are as follows:
where:
m
n
p
= Number of logic modules switching at fm
= Number of input buffers switching at fn
= Number of output buffers switching at fp
= Number of clock loads on the first routed array
clock
= Number of clock loads on the second routed
array clock
= Fixed capacitance due to first routed array
clock
= Fixed capacitance due to second routed array
clock
= Fixed number of clock loads on the dedicated
array clock = (528 for A54SX16)
q1
q2
r1
r2
s1
Logic Modules (m)
Inputs Switching (n)
Outputs Switching (p)
=
=
=
80% of modules
# inputs/4
# output/4
First Routed Array Clock Loads (q1) =
40% of
sequential
modules
Second Routed Array Clock Loads
(q2)
=
40% of
sequential
modules
CEQM = Equivalent capacitance of logic modules in pF
CEQI = Equivalent capacitance of input buffers in pF
CEQO = Equivalent capacitance of output buffers in pF
CEQCR = Equivalent capacitance of routed array clock in
pF
CEQCD = Equivalent capacitance of dedicated array
clock in pF
CL
fm
fn
fp
fq1
fq2
Load Capacitance (CL)
Average Logic Module Switching
Rate (fm)
=
=
35 pF
F/10
Average Input Switching Rate (fn) =
Average Output Switching Rate (fp) =
F/5
F/10
F/2
Average First Routed Array Clock
Rate (fq1)
=
= Output lead capacitance in pF
= Average logic module switching rate in MHz
= Average input buffer switching rate in MHz
= Average output buffer switching rate in MHz
= Average first routed array clock rate in MHz
= Average second routed array clock rate in MHz
Average Second Routed Array Clock =
Rate (fq2)
Average Dedicated Array Clock Rate =
(fs1)
F/2
F
14
v2.0
54SX Family FPGAs RadTolerant and HiRel
Temperature and Voltage Derating Factors
(Normalized to Worst-Case Commercial, TJ = 70°C, VCCA = 3.0V)
Junction Temperature (TJ)
VCCA
3.0
–40
0.78
0.73
0.69
0
25
70
85
125
1.16
1.08
1.02
0.87
0.82
0.77
0.89
0.83
0.78
1.00
0.93
0.87
1.04
0.97
0.92
3.3
3.6
54SX Timing Model*
Input Delays
Internal Delays
Predicted
Routing
Delays
Output Delays
I/O Module
Combinatorial
Cell
I/O Module
tINY = 2.2 ns
tIRD2 = 1.2 ns
t
DHL = 2.8 ns
tRD1 = 0.7 ns
tRD4 = 2.2 ns
tRD8 = 4.3 ns
tPD =0.9 ns
I/O Module
tDHL = 2.8 ns
Register
Cell
Register
Cell
D
D
Q
Q
tRD1 = 0.7 ns
tRD1 = 0.7 ns
tENZH = 2.8 ns
tSUD = 0.8 ns
tHD = 0.0 ns
t
RCO = 0.6 ns
tRCO = 0.6 ns
Routed
Clock
tRCKH = 2.8 ns (100% Load)
FMAX = 175 MHz
Hard-Wired
Clock
tHCKH = 1.3 ns
FHMAX = 240 MHz
*Values shown for A54SX16-1 at worst-case commercial conditions.
Hard-Wired Clock
Routed Clock
External Set-Up = tINY + tIRD1 + tSUD – tHCKH
External Set-Up = tINY + tIRD1 + tSUD – tRCKH
= 2.2 + 0.7 + 0.8 – 2.4 = 1.3 ns
Clock-to-Out (Pin-to-Pin)
= 2.2 + 0.7 + 0.8 – 1.7 = 2.0 ns
Clock-to-Out (Pin-to-Pin)
= tHCKH + tRCO + tRD1 + tDHL
= tRCKH + tRCO + tRD1 + tDHL
= 1.7 + 0.6 + 0.7 + 2.8 = 5.8 ns
= 2.4 + 0.6 + 0.7 + 2.8 = 6.5 ns
v2.0
15
54SX Family FPGAs RadTolerant and HiRel
Output Buffer Delays
E
D
To AC test loads (shown below)
PAD
TRIBUFF
VCC
VCC
VCC
In
GND
1.5V
50%
VOH
En
Out
GND
10%
50%
En
GND
90%
50%
50%
VCC
50%
VOH
50%
1.5V
VOL
Out
VOL
Out
GND
1.5V
1.5V
tDLH
tDHL
tENZL
tENLZ
tENZH
tENHZ
AC Test Loads
Load 1
Load 2
(Used to measure rising/falling edges)
(Used to measure propagation delay)
VCC
GND
To the output under test
50 pF
R to VCC for tPLZ/tPZL
R to GND for tPHZ/tPZH
R = 1 kΩ
To the output under test
50 pF
Input Buffer Delays
C-Cell Delays
S
A
B
Y
Y
PAD
INBUF
VCC
GND
S, A or B
50% 50%
VCC
3V
In
0V
50%
1.5V
VCC
1.5V
50%
Out
50%
GND
tPD
tPD
Out
GND
50%
VCC
50%
Out
GND
tPD
50%
tPD
tINY
tINY
16
v2.0
54SX Family FPGAs RadTolerant and HiRel
Register Cell Timing Characteristics
Flip-Flops
D
Q
PRESET
CLR
CLK
(Positive edge triggered)
tHD
D
tHP
tHPWH
,
tSUD
tRPWH
CLK
tHPWL
,
tRPWL
tRCO
Q
tCLR
tPRESET
CLR
tWASYN
PRESET
Long Tracks
Timing Characteristics
Some nets in the design use long tracks. Long tracks are
special routing resources that span multiple rows, columns,
or modules. Long tracks employ three and sometimes five
antifuse connections. This increases capacitance and
resistance, resulting in longer net delays for macros
connected to long tracks. Typically up to 6% of nets in a fully
utilized device require long tracks. Long tracks contribute
approximately 4 ns to 8.4 ns delay. This additional delay is
represented statistically in higher fanout (FO=24) routing
delays in the data sheet specifications section.
Timing characteristics for 54SX devices fall into three
categories: family-dependent, device-dependent, and
design-dependent. The input and output buffer
characteristics are common to all 54SX family members.
Internal routing delays are device dependent. Design
dependency means actual delays are not determined until
after placement and routing of the user’s design is
complete. Delay values may then be determined by using
the DirectTime Analyzer utility or performing simulation
with post-layout delays.
Timing Derating
Critical Nets and Typical Nets
54SX devices are manufactured in a CMOS process.
Therefore, device performance varies according to
temperature, voltage, and process variations. Minimum
timing parameters reflect maximum operating voltage,
minimum operating temperature, and best-case processing.
Maximum timing parameters reflect minimum operating
voltage, maximum operating temperature, and worst-case
processing.
Propagation delays are expressed only for typical nets,
which are used for initial design performance evaluation.
Critical net delays can then be applied to the most
time-critical paths. Critical nets are determined by net
property assignment prior to placement and routing. Up to
6 percent of the nets in a design may be designated as
critical, while 90 percent of the nets in a design are typical.
v2.0
17
54SX Family FPGAs RadTolerant and HiRel
A54SX16 Timing Characteristics
(Worst-Case Military Conditions, VCCR = 4.75V, VCCA, VCCI = 3.0V, TJ = 125°C)
C-Cell Propagation Delays1
‘–1’ Speed
‘Std’ Speed
Parameter
Description
Min.
Max.
Min.
Max.
Units
tPD
Internal Array Module
0.9
1.0
ns
Predicted Routing Delays2
tDC
FO=1 Routing Delay, Direct Connect
0.1
0.6
0.7
1.2
1.7
2.2
4.3
5.6
9.4
12.4
0.1
0.7
0.8
1.4
2.0
2.6
5.0
6.6
11.0
14.6
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
tFC
FO=1 Routing Delay, Fast Connect
FO=1 Routing Delay
FO=2 Routing Delay
FO=3 Routing Delay
FO=4 Routing Delay
FO=8 Routing Delay
FO=12 Routing Delay
FO=18 Routing Delay
FO=24 Routing Delay
tRD1
tRD2
tRD3
tRD4
tRD8
tRD12
tRD18
tRD24
R-Cell Timing
tRCO
tCLR
tSUD
tHD
Sequential Clock-to-Q
0.6
0.6
0.8
0.8
ns
ns
ns
ns
ns
Asynchronous Clear-to-Q
Flip-Flop Data Input Set-Up
Flip-Flop Data Input Hold
Asynchronous Pulse Width
0.8
0.0
2.4
0.9
0.0
2.9
tWASYN
I/O Module Input Propagation Delays
tINYH
tINYL
Input Data Pad-to-Y HIGH
Input Data Pad-to-Y LOW
2.2
2.2
2.6
2.6
ns
ns
Predicted Input Routing Delays3
tIRD1
tIRD2
tIRD3
tIRD4
tIRD8
tIRD12
tIRD18
tIRD24
Notes:
FO=1 Routing Delay
FO=2 Routing Delay
FO=3 Routing Delay
FO=4 Routing Delay
FO=8 Routing Delay
FO=12 Routing Delay
FO=18 Routing Delay
FO=24 Routing Delay
0.7
1.2
1.7
2.2
4.3
5.6
9.4
12.4
0.8
1.4
ns
ns
ns
ns
ns
ns
ns
ns
2.0
2.6
5.0
6.6
11.0
14.6
1. For dual-module macros, use tPD + tRD1 + tPDn , tRCO + tRD1 + tPDn or tPD1 + tRD1 + tSUD , whichever is appropriate.
2. Routing delays are for typical designs across worst-case operating conditions. These parameters should be used for estimating device
performance. Post-route timing analysis or simulation is required to determine actual worst-case performance. Post-route timing is
based on actual routing delay measurements performed on the device prior to shipment.
3. Routing delays are for typical designs across worst-case operating conditions. These parameters should be used for estimating device
performance. Post-route timing analysis or simulation is required to determine actual worst-case performance. Post-route timing is
based on actual routing delay measurements performed on the device prior to shipment.
18
v2.0
54SX Family FPGAs RadTolerant and HiRel
A54SX16 Timing Characteristics (continued)
(Worst-Case Military Conditions, VCCR = 4.75V, VCCA, VCCI = 3.0V, TJ = 125°C)
I/O Module – TTL Output Timing1
‘–1’ Speed
‘Std’ Speed
Parameter
Description
Min.
Max.
Min.
Max.
Units
tDLH
Data-to-Pad LOW to HIGH
Data-to-Pad HIGH to LOW
Enable-to-Pad, Z to L
Enable-to-Pad, Z to H
Enable-to-Pad, L to Z
Enable-to-Pad, H to Z
Delta LOW to HIGH
2.8
2.8
3.3
3.3
ns
ns
tDHL
tENZL
tENZH
tENLZ
tENHZ
dTLH
dTHL
2.3
2.8
ns
2.8
3.3
ns
4.5
5.2
ns
2.2
2.6
ns
0.05
0.05
0.06
0.08
ns/pF
ns/pF
Delta HIGH to LOW
Dedicated (Hard-Wired) Array Clock Network
tHCKH
Input LOW to HIGH
(Pad to R-Cell Input)
1.7
1.9
2.0
2.2
ns
tHCKL
Input HIGH to LOW
(Pad to R-Cell Input)
ns
ns
tHPWH
tHPWL
tHCKSW
tHP
Minimum Pulse Width HIGH
Minimum Pulse Width LOW
Maximum Skew
2.1
2.1
2.4
2.4
ns
0.4
0.4
ns
Minimum Period
4.2
4.9
ns
fHMAX
Maximum Frequency
240
205
MHz
Routed Array Clock Networks
tRCKH
tRCKL
tRCKH
tRCKL
tRCKH
tRCKL
Input LOW to HIGH (Light Load)
(Pad to R-Cell Input)
2.4
2.7
2.9
2.9
2.8
2.9
2.9
3.1
3.3
3.5
3.3
3.5
ns
ns
ns
ns
ns
Input HIGH to LOW (Light Load)
(Pad to R-Cell Input)
Input LOW to HIGH (50% Load)
(Pad to R-Cell Input)
Input HIGH to LOW (50% Load)
(Pad to R-Cell Input)
Input LOW to HIGH (100% Load)
(Pad to R-Cell Input)
Input HIGH to LOW (100% Load)
(Pad to R-Cell Input)
ns
ns
ns
ns
ns
ns
tRPWH
tRPWL
Min. Pulse Width HIGH
3.1
3.1
3.7
3.7
Min. Pulse Width LOW
tRCKSW
tRCKSW
tRCKSW
Note:
Maximum Skew (Light Load)
Maximum Skew (50% Load)
Maximum Skew (100% Load)
0.6
0.8
0.8
0.8
0.9
0.9
1. Delays based on 35 pF loading, except for tENZL and tENZH . For tENZL and tENZH the loading is 5 pF.
v2.0
19
54SX Family FPGAs RadTolerant and HiRel
RT54SX16 Timing Characteristics
(Worst-Case Military Conditions, VCCR = 4.75V, VCCA, VCCI = 3.0V, TJ = 125°C)
C-Cell Propagation Delays1
‘–1’ Speed
‘Std’ Speed
Parameter
Description
Min.
Max.
Min.
Max.
Units
tPD
Internal Array Module
1.7
1.8
ns
Predicted Routing Delays2
tDC
FO=1 Routing Delay, Direct Connect
0.2
1.1
0.2
1.3
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
tFC
FO=1 Routing Delay, Fast Connect
FO=1 Routing Delay
FO=2 Routing Delay
FO=3 Routing Delay
FO=4 Routing Delay
FO=8 Routing Delay
FO=12 Routing Delay
FO=18 Routing Delay
FO=24 Routing Delay
tRD1
1.3
1.5
tRD2
2.2
2.6
tRD3
3.1
3.6
tRD4
4.0
4.7
tRD8
7.8
9.0
tRD12
tRD18
tRD24
R-Cell Timing
10.1
17.0
22.4
11.9
19.8
26.3
tRCO
tCLR
tSUD
tHD
Sequential Clock-to-Q
1.5
1.5
2.0
2.0
ns
ns
ns
ns
ns
Asynchronous Clear-to-Q
Flip-Flop Data Input Set-Up
Flip-Flop Data Input Hold
Asynchronous Pulse Width
2.0
0.0
4.4
2.2
0.0
5.3
tWASYN
I/O Module Input Propagation Delays
tINYH
tINYL
Input Data Pad-to-Y HIGH
Input Data Pad-to-Y LOW
4.0
4.0
4.7
4.7
ns
ns
Predicted Input Routing Delays3
tIRD1
tIRD2
tIRD3
tIRD4
tIRD8
tIRD12
tIRD18
tIRD24
Notes:
FO=1 Routing Delay
FO=2 Routing Delay
FO=3 Routing Delay
FO=4 Routing Delay
FO=8 Routing Delay
FO=12 Routing Delay
FO=18 Routing Delay
FO=24 Routing Delay
1.3
2.2
1.5
2.6
ns
ns
ns
ns
ns
ns
ns
ns
3.1
3.6
4.0
4.7
7.8
9.0
10.1
17.0
22.4
11.9
19.8
26.3
1. For dual-module macros, use tPD + tRD1 + tPDn , tRCO + tRD1 + tPDn or tPD1 + tRD1 + tSUD , whichever is appropriate.
2. Routing delays are for typical designs across worst-case operating conditions. These parameters should be used for estimating device
performance. Post-route timing analysis or simulation is required to determine actual worst-case performance. Post-route timing is
based on actual routing delay measurements performed on the device prior to shipment.
3. Routing delays are for typical designs across worst-case operating conditions. These parameters should be used for estimating device
performance. Post-route timing analysis or simulation is required to determine actual worst-case performance. Post-route timing is
based on actual routing delay measurements performed on the device prior to shipment.
20
v2.0
54SX Family FPGAs RadTolerant and HiRel
RT54SX16 Timing Characteristics (continued)
(Worst-Case Military Conditions, VCCR = 4.75V, VCCA, VCCI = 3.0V, TJ = 125°C)
I/O Module – TTL Output Timing1
‘–1’ Speed
‘Std’ Speed
Parameter
Description
Min.
Max.
Min.
Max.
Units
tDLH
Data-to-Pad LOW to HIGH
Data-to-Pad HIGH to LOW
Enable-to-Pad, Z to L
Enable-to-Pad, Z to H
Enable-to-Pad, L to Z
Enable-to-Pad, H to Z
Delta LOW to HIGH
5.1
5.1
6.0
6.0
ns
ns
tDHL
tENZL
tENZH
tENLZ
tENHZ
dTLH
dTHL
4.2
5.1
ns
5.1
6.0
ns
8.1
9.4
ns
4.0
4.7
ns
0.09
0.09
0.11
0.15
ns/pF
ns/pF
Delta HIGH to LOW
Dedicated (Hard-Wired) Array Clock Network
tHCKH
Input LOW to HIGH
(Pad to R-Cell Input)
3.1
3.5
3.6
4.0
ns
tHCKL
Input HIGH to LOW
(Pad to R-Cell Input)
ns
ns
tHPWH
tHPWL
tHCKSW
tHP
Minimum Pulse Width HIGH
Minimum Pulse Width LOW
Maximum Skew
3.8
3.8
4.4
4.4
ns
0.8
0.8
ns
Minimum Period
7.6
8.9
ns
fHMAX
Maximum Frequency
130
110
MHz
Routed Array Clock Networks
tRCKH
tRCKL
tRCKH
tRCKL
tRCKH
tRCKL
Input LOW to HIGH (Light Load)
(Pad to R-Cell Input)
4.4
4.9
5.3
5.3
5.1
5.3
5.3
5.6
6.0
6.3
6.0
6.3
ns
ns
ns
ns
ns
Input HIGH to LOW (Light Load)
(Pad to R-Cell Input)
Input LOW to HIGH (50% Load)
(Pad to R-Cell Input)
Input HIGH to LOW (50% Load)
(Pad to R-Cell Input)
Input LOW to HIGH (100% Load)
(Pad to R-Cell Input)
Input HIGH to LOW (100% Load)
(Pad to R-Cell Input)
ns
ns
ns
ns
ns
ns
tRPWH
tRPWL
Min. Pulse Width HIGH
5.6
5.6
6.7
6.7
Min. Pulse Width LOW
tRCKSW
tRCKSW
tRCKSW
Note:
Maximum Skew (Light Load)
Maximum Skew (50% Load)
Maximum Skew (100% Load)
1.1
1.5
1.5
1.5
1.7
1.7
1. Delays based on 35 pF loading, except for tENZL and tENZH . For tENZL and tENZH the loading is 5 pF.
v2.0
21
54SX Family FPGAs RadTolerant and HiRel
A54SX32 Timing Characteristics
(Worst-Case Military Conditions, VCCR = 4.75V, VCCA, VCCI = 3.0V, TJ = 125°C)
C-Cell Propagation Delays1
‘–1’ Speed
‘Std’ Speed
Parameter
Description
Min.
Max.
Min.
Max.
Units
tPD
Internal Array Module
0.9
1.0
ns
Predicted Routing Delays2
tDC
FO=1 Routing Delay, Direct Connect
0.1
0.6
0.7
1.2
1.7
2.2
4.3
5.6
9.4
12.4
0.1
0.7
0.8
1.4
2.0
2.6
5.0
6.6
11.0
14.6
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
tFC
FO=1 Routing Delay, Fast Connect
FO=1 Routing Delay
FO=2 Routing Delay
FO=3 Routing Delay
FO=4 Routing Delay
FO=8 Routing Delay
FO=12 Routing Delay
FO=18 Routing Delay
FO=24 Routing Delay
tRD1
tRD2
tRD3
tRD4
tRD8
tRD12
tRD18
tRD24
R-Cell Timing
tRCO
tCLR
tSUD
tHD
Sequential Clock-to-Q
0.6
0.6
0.8
0.8
ns
ns
ns
ns
ns
Asynchronous Clear-to-Q
Flip-Flop Data Input Set-Up
Flip-Flop Data Input Hold
Asynchronous Pulse Width
0.8
0.0
2.4
0.9
0.0
2.9
tWASYN
I/O Module Input Propagation Delays
tINYH
tINYL
Input Data Pad-to-Y HIGH
Input Data Pad-to-Y LOW
2.2
2.2
2.6
2.6
ns
ns
Predicted Input Routing Delays3
tIRD1
tIRD2
tIRD3
tIRD4
tIRD8
tIRD12
tIRD18
tIRD24
Notes:
FO=1 Routing Delay
FO=2 Routing Delay
FO=3 Routing Delay
FO=4 Routing Delay
FO=8 Routing Delay
FO=12 Routing Delay
FO=18 Routing Delay
FO=24 Routing Delay
0.7
1.2
1.7
2.2
4.3
5.6
9.4
12.4
0.8
1.4
ns
ns
ns
ns
ns
ns
ns
ns
2.0
2.6
5.0
6.6
11.0
14.6
1. For dual-module macros, use tPD + tRD1 + tPDn , tRCO + tRD1 + tPDn or tPD1 + tRD1 + tSUD , whichever is appropriate.
2. Routing delays are for typical designs across worst-case operating conditions. These parameters should be used for estimating device
performance. Post-route timing analysis or simulation is required to determine actual worst-case performance. Post-route timing is
based on actual routing delay measurements performed on the device prior to shipment.
3. Routing delays are for typical designs across worst-case operating conditions. These parameters should be used for estimating device
performance. Post-route timing analysis or simulation is required to determine actual worst-case performance. Post-route timing is
based on actual routing delay measurements performed on the device prior to shipment.
22
v2.0
54SX Family FPGAs RadTolerant and HiRel
A54SX32 Timing Characteristics (continued)
(Worst-Case Military Conditions, VCCR = 4.75V, VCCA, VCCI = 3.0V, TJ = 125°C)
I/O Module – TTL Output Timing1
‘–1’ Speed
‘Std’ Speed
Parameter
Description
Min.
Max.
Min.
Max.
Units
tDLH
Data-to-Pad LOW to HIGH
Data-to-Pad HIGH to LOW
Enable-to-Pad, Z to L
Enable-to-Pad, Z to H
Enable-to-Pad, L to Z
Enable-to-Pad, H to Z
Delta LOW to HIGH
2.8
2.8
3.3
3.3
ns
ns
tDHL
tENZL
tENZH
tENLZ
tENHZ
dTLH
dTHL
2.3
2.8
ns
2.8
3.3
ns
4.5
5.2
ns
2.2
2.6
ns
0.05
0.05
0.06
0.08
ns/pF
ns/pF
Delta HIGH to LOW
Dedicated (Hard-Wired) Array Clock Network
tHCKH
Input LOW to HIGH
(Pad to R-Cell Input)
1.7
1.9
2.0
2.2
ns
tHCKL
Input HIGH to LOW
(Pad to R-Cell Input)
ns
ns
tHPWH
tHPWL
tHCKSW
tHP
Minimum Pulse Width HIGH
Minimum Pulse Width LOW
Maximum Skew
2.1
2.1
2.4
2.4
ns
0.4
0.4
ns
Minimum Period
4.2
4.8
ns
fHMAX
Maximum Frequency
240
205
MHz
Routed Array Clock Networks
tRCKH
tRCKL
tRCKH
tRCKL
tRCKH
tRCKL
Input LOW to HIGH (Light Load)
(Pad to R-Cell Input)
2.4
2.7
2.9
2.9
2.8
2.9
2.9
3.1
3.3
3.5
3.3
3.5
ns
ns
ns
ns
ns
Input HIGH to LOW (Light Load)
(Pad to R-Cell Input)
Input LOW to HIGH (50% Load)
(Pad to R-Cell Input)
Input HIGH to LOW (50% Load)
(Pad to R-Cell Input)
Input LOW to HIGH (100% Load)
(Pad to R-Cell Input)
Input HIGH to LOW (100% Load)
(Pad to R-Cell Input)
ns
ns
ns
ns
ns
ns
tRPWH
tRPWL
Min. Pulse Width HIGH
3.1
3.1
3.7
3.7
Min. Pulse Width LOW
tRCKSW
tRCKSW
tRCKSW
Note:
Maximum Skew (Light Load)
Maximum Skew (50% Load)
Maximum Skew (100% Load)
0.6
0.8
0.8
0.8
0.9
0.9
1. Delays based on 35 pF loading, except tENZL and tENZH . For tENZL and tENZH the loading is 5 pF.
v2.0
23
54SX Family FPGAs RadTolerant and HiRel
RT54SX32 Timing Characteristics
(Worst-Case Military Conditions, VCCR = 4.75V, VCCA, VCCI = 3.0V, TJ = 125°C)
C-Cell Propagation Delays1
‘–1’ Speed
‘Std’ Speed
Parameter
Description
Min.
Max.
Min.
Max.
Units
tPD
Internal Array Module
1.7
1.8
ns
Predicted Routing Delays2
tDC
FO=1 Routing Delay, Direct Connect
0.2
1.1
0.2
1.3
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
tFC
FO=1 Routing Delay, Fast Connect
FO=1 Routing Delay
FO=2 Routing Delay
FO=3 Routing Delay
FO=4 Routing Delay
FO=8 Routing Delay
FO=12 Routing Delay
FO=18 Routing Delay
FO=24 Routing Delay
tRD1
1.3
1.5
tRD2
2.2
2.6
tRD3
3.1
3.6
tRD4
4.0
4.7
tRD8
7.8
9.0
tRD12
tRD18
tRD24
R-Cell Timing
10.1
17.0
22.4
11.9
19.8
26.3
tRCO
tCLR
tSUD
tHD
Sequential Clock-to-Q
1.5
1.5
2.0
2.0
ns
ns
ns
ns
ns
Asynchronous Clear-to-Q
Flip-Flop Data Input Set-Up
Flip-Flop Data Input Hold
Asynchronous Pulse Width
2.0
0.0
4.4
2.2
0.0
5.3
tWASYN
I/O Module Input Propagation Delays
tINYH
tINYL
Input Data Pad-to-Y HIGH
Input Data Pad-to-Y LOW
4.0
4.0
4.7
4.7
ns
ns
Predicted Input Routing Delays3
tIRD1
tIRD2
tIRD3
tIRD4
tIRD8
tIRD12
tIRD18
tIRD24
Notes:
FO=1 Routing Delay
FO=2 Routing Delay
FO=3 Routing Delay
FO=4 Routing Delay
FO=8 Routing Delay
FO=12 Routing Delay
FO=18 Routing Delay
FO=24 Routing Delay
1.3
2.2
1.5
2.6
ns
ns
ns
ns
ns
ns
ns
ns
3.1
3.6
4.0
4.7
7.8
9.0
10.1
17.0
22.4
11.9
19.8
26.3
1. For dual-module macros, use tPD + tRD1 + tPDn , tRCO + tRD1 + tPDn or tPD1 + tRD1 + tSUD , whichever is appropriate.
2. Routing delays are for typical designs across worst-case operating conditions. These parameters should be used for estimating device
performance. Post-route timing analysis or simulation is required to determine actual worst-case performance. Post-route timing is
based on actual routing delay measurements performed on the device prior to shipment.
3. Routing delays are for typical designs across worst-case operating conditions. These parameters should be used for estimating device
performance. Post-route timing analysis or simulation is required to determine actual worst-case performance. Post-route timing is
based on actual routing delay measurements performed on the device prior to shipment.
24
v2.0
54SX Family FPGAs RadTolerant and HiRel
RT54SX32 Timing Characteristics (continued)
(Worst-Case Military Conditions, VCCR = 4.75V, VCCA, VCCI = 3.0V, TJ = 125°C)
I/O Module – TTL Output Timing1
‘–1’ Speed
‘Std’ Speed
Parameter
Description
Min.
Max.
Min.
Max.
Units
tDLH
Data-to-Pad LOW to HIGH
Data-to-Pad HIGH to LOW
Enable-to-Pad, Z to L
Enable-to-Pad, Z to H
Enable-to-Pad, L to Z
Enable-to-Pad, H to Z
Delta LOW to HIGH
5.1
5.1
6.0
6.0
ns
ns
tDHL
tENZL
tENZH
tENLZ
tENHZ
dTLH
dTHL
4.2
5.1
ns
5.1
6.0
ns
8.1
9.4
ns
4.0
4.7
ns
0.09
0.09
0.11
0.15
ns/pF
ns/pF
Delta HIGH to LOW
Dedicated (Hard-Wired) Array Clock Network
tHCKH
Input LOW to HIGH
(Pad to R-Cell Input)
3.1
3.5
3.6
4.0
ns
tHCKL
Input HIGH to LOW
(Pad to R-Cell Input)
ns
ns
tHPWH
tHPWL
tHCKSW
tHP
Minimum Pulse Width HIGH
Minimum Pulse Width LOW
Maximum Skew
3.8
3.8
4.4
4.4
ns
0.8
0.8
ns
Minimum Period
7.6
8.9
ns
fHMAX
Maximum Frequency
130
110
MHz
Routed Array Clock Networks
tRCKH
tRCKL
tRCKH
tRCKL
tRCKH
tRCKL
Input LOW to HIGH (Light Load)
(Pad to R-Cell Input)
4.4
4.9
5.3
5.3
5.1
5.3
5.3
5.6
6.0
6.3
6.0
6.3
ns
ns
ns
ns
ns
Input HIGH to LOW (Light Load)
(Pad to R-Cell Input)
Input LOW to HIGH (50% Load)
(Pad to R-Cell Input)
Input HIGH to LOW (50% Load)
(Pad to R-Cell Input)
Input LOW to HIGH (100% Load)
(Pad to R-Cell Input)
Input HIGH to LOW (100% Load)
(Pad to R-Cell Input)
ns
ns
ns
ns
ns
ns
tRPWH
tRPWL
Min. Pulse Width HIGH
5.6
5.6
6.7
6.7
Min. Pulse Width LOW
tRCKSW
tRCKSW
tRCKSW
Note:
Maximum Skew (Light Load)
Maximum Skew (50% Load)
Maximum Skew (100% Load)
1.1
1.5
1.5
1.5
1.7
1.7
1. Delays based on 35 pF loading, except tENZL and tENZH . For tENZL and tENZH the loading is 5 pF.
v2.0
25
54SX Family FPGAs RadTolerant and HiRel
Pin Description
CLKA,
Clock A and B
TDI, I/O
Test Data Input
CLKB
Serial input for boundary scan testing and diagnostic probe.
In flexible mode, TDI is active when the TMS pin is set LOW
(refer to Table 2 on page 9). This pin functions as an I/O
when the boundary scan state machine reaches the “logic
reset” state.
These pins are clock inputs for clock distribution networks.
Input levels are compatible with standard TTL or LVTTL
specifications. The clock input is buffered prior to clocking
the R-cells. If not used, this pin must be set LOW or HIGH on
the board. It must not be left floating.
TDO, I/O
Test Data Output
GND
Ground
Serial output for boundary scan testing. In flexible mode,
TDO is active when the TMS pin is set LOW (refer to Table 2
on page 9). This pin functions as an I/O when the boundary
scan state machine reaches the “logic reset” state.
LOW supply voltage.
HCLK
Dedicated (Hard-wired)
Array Clock
TMS
Test Mode Select
This pin is the clock input for sequential modules. Input
levels are compatible with standard TTL or LVTTL
specifications. This input is directly wired to each R-cell and
offers clock speeds independent of the number of R-cells
being driven. If not used, this pin must be set LOW or HIGH
on the board. It must not be left floating.
The TMS pin controls the use of the IEEE 1149.1 Boundary
Scan pins (TCK, TDI, TDO, TRST). In flexible mode when
the TMS pin is set LOW, the TCK, TDI, and TDO pins are
boundary scan pins (refer to Table 2 on page 9). Once the
boundary scan pins are in test mode, they will remain in that
mode until the internal boundary scan state machine
reaches the “logic reset” state. At this point, the boundary
scan pins will be released and will function as regular I/O
pins. The “logic reset” state is reached 5 TCK cycles after
the TMS pin is set HIGH. In dedicated test mode, TMS
functions as specified in the IEEE 1149.1 specifications.
I/O
Input/Output
The I/O pin functions as an input, output, tristate, or
bidirectional buffer. Based on certain configurations, input
and output levels are compatible with standard TTL or
LVTTL specifications. Unused I/O pins are automatically
tristated by the Designer Series software.
TRST
Boundary Scan Reset Pin
NC
No Connection
The TRST pin functions as an active-low input to
asynchronously initialize or reset the boundary scan circuit.
The TRST pin is equipped with an internal pull-up resistor.
This pin is not connected to circuitry within the device.
These pins can be driven to any voltage or can be left
floating with no effect on the operation of the device.
VCCI
Supply Voltage
PRA, I/O,
PRB, I/O
Probe A/B
Supply voltage for I/Os. See Table 1 on page 8.
VCCA
Supply Voltage
The Probe pin is used to output data from any user-defined
design node within the device. This independent diagnostic
pin can be used in conjunction with the other probe pin to
allow real-time diagnostic output of any signal path within
the device. The Probe pin can be used as a user-defined I/O
when verification has been completed. The pin’s probe
capabilities can be permanently disabled to protect
programmed design confidentiality.
Supply voltage for Array. See Table 1 on page 8.
VCCR
Supply Voltage
Supply voltage for input tolerance (required for internal
biasing). See Table 1 on page 8.
TCK, I/O
Test Clock (Input)
Test clock input for diagnostic probe and device
programming. In flexible mode, TCK becomes active when
the TMS pin is set LOW (see Table 2 on page 9). This pin
functions as an I/O when the JTAG state machine reaches
the “logic reset “ state.
26
v2.0
54SX Family FPGAs RadTolerant and HiRel
Package Pin Assignments
208-Pin CQFP (Top View)
208 207 206 205 204 203 202 201 200
164 163 162 161 160 159 158 157
Pin #1
Index
1
2
3
4
5
6
7
8
156
155
154
153
152
151
150
149
208-Pin
CQFP
44
45
46
47
48
49
50
51
52
113
112
111
110
109
108
107
106
105
53 54 55 56 57 58 59 60 61
97 98 99 100 101 102 103 104
v2.0
27
54SX Family FPGAs RadTolerant and HiRel
208-Pin CQFP
Pin A54SX16
RT54SX16
Function
A54SX32
Function
RT54SX32
Function
Pin
A54SX16
RT54SX16
Function
A54SX32
Function
RT54SX32
Function
Number Function
Number Function
1
2
GND
TDI, I/O
I/O
GND
TDI, I/O
I/O
GND
TDI, I/O
I/O
GND
TDI, I/O
I/O
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
3
I/O
I/O
I/O
I/O
4
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
5
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
6
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
7
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
8
I/O
I/O
I/O
I/O
VCCI
I/O
VCCI
I/O
VCCI
I/O
VCCI
I/O
9
I/O
I/O
I/O
I/O
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
Notes:
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
TMS
VCCI
I/O
TMS
VCCI
I/O
TMS
VCCI
I/O
TMS
VCCI
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
NC
NC
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
PRB, I/O
GND
VCCA
GND
VCCR
I/O
PRB, I/O
GND
VCCA
GND
VCCR
I/O
PRB, I/O
GND
VCCA
GND
VCCR
I/O
PRB, I/O
GND
VCCA
GND
VCCR
I/O
VCCR
GND
VCCA
GND
I/O
VCCR
GND
VCCA
GND
I/O
VCCR
GND
VCCA
GND
I/O
VCCR
GND
VCCA
GND
I/O
I/O
TRST
I/O
I/O
TRST
I/O
HCLK
I/O
HCLK
I/O
HCLK
I/O
HCLK
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
VCCI
VCCA
I/O
VCCI
VCCA
I/O
VCCI
VCCA
I/O
VCCI
VCCA
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
VCCI
I/O
VCCI
I/O
VCCI
I/O
VCCI
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
TDO, I/O
I/O
TDO, I/O
I/O
TDO, I/O
I/O
TDO, I/O
I/O
GND
GND
GND
GND
1.
2.
Pin 30 in RT54SX16 and RT54SX32-CQ208 are TRST pins.
Pin 65 in A54SX32 and RT54SX32-CQ208 are No Connects.
28
v2.0
54SX Family FPGAs RadTolerant and HiRel
208-Pin CQFP (Continued)
Pin
A54SX16
RT54SX16
Function
A54SX32
Function
RT54SX32
Function
Pin
A54SX16
RT54SX16
Function
A54SX32
Function
RT54SX32
Function
Number Function
Number Function
105
106
107
108
109
110
111
GND
I/O
GND
I/O
GND
I/O
GND
I/O
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
177
178
179
180
181
182
183
184
185
186
187
188
189
190
191
192
193
194
195
196
197
198
199
200
201
202
203
204
205
206
207
208
GND
I/O
GND
I/O
GND
I/O
GND
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
Notes:
I/O
I/O
I/O
I/O
VCCI
I/O
VCCI
I/O
VCCI
I/O
VCCI
I/O
I/O
I/O
I/O
I/O
VCCA
VCCI
I/O
VCCA
VCCI
I/O
VCCA
VCCI
I/O
VCCA
VCCI
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
CLKA
CLKB
VCCR
GND
VCCA
GND
PRA, I/O
I/O
CLKA
CLKB
VCCR
GND
VCCA
GND
PRA, I/O
I/O
CLKA
CLKB
VCCR
GND
VCCA
GND
PRA, I/O
I/O
CLKA
CLKB
VCCR
GND
VCCA
GND
PRA, I/O
I/O
GND
VCCA
GND
VCCR
I/O
GND
VCCA
GND
VCCR
I/O
GND
VCCA
GND
VCCR
I/O
GND
VCCA
GND
VCCR
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
VCCA
GND
I/O
VCCA
GND
I/O
VCCA
GND
I/O
VCCA
GND
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
VCCI
I/O
VCCI
I/O
VCCI
I/O
VCCI
I/O
I/O
I/O
I/O
I/O
VCCI
I/O
VCCI
I/O
VCCI
I/O
VCCI
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
TCK, I/O
TCK, I/O
TCK, I/O
TCK, I/O
1.
2.
Pin 30 in RT54SX16 and RT54SX32-CQ208 are TRST pins.
Pin 65 in A54SX32 and RT54SX32-CQ208 are No Connects.
v2.0
29
54SX Family FPGAs RadTolerant and HiRel
Package Pin Assignments (continued)
256-Pin CQFP (Top View)
256 255 254 253 252 251 250 249 248
200 199 198 197 196 195 194 193
Pin #1
Index
1
2
3
4
5
6
7
8
192
191
190
189
188
187
186
185
256-Pin
CQFP
56
57
58
59
60
61
62
63
64
137
136
135
134
133
132
131
130
129
65 66 67 68 69 70 71 72 73
121 122 123 124 125 126 127 128
30
v2.0
54SX Family FPGAs RadTolerant and HiRel
256-Pin CQFP
Pin
A54SX16
RT54SX16
Function
A54SX32
Function
RT54SX32
Function
Pin
A54SX16
RT54SX16
Function
A54SX32
Function
RT54SX32
Function
Number Function
Number Function
1
2
GND
TDI, I/O
I/O
GND
TDI, I/O
I/O
GND
TDI, I/O
I/O
GND
TDI, I/O
I/O
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
I/O
NC
I/O
I/O
NC
I/O
I/O
I/O
I/O
I/O
3
I/O
I/O
4
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
5
I/O
I/O
I/O
I/O
NC
I/O
NC
I/O
I/O
I/O
6
I/O
I/O
I/O
I/O
I/O
I/O
7
I/O
I/O
I/O
I/O
GND
I/O
GND
I/O
GND
I/O
GND
I/O
8
I/O
I/O
I/O
I/O
9
I/O
I/O
I/O
I/O
NC
I/O
NC
I/O
I/O
I/O
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
Note:
I/O
I/O
I/O
I/O
I/O
I/O
TMS
NC
NC
I/O
TMS
NC
NC
I/O
TMS
I/O
TMS
I/O
NC
I/O
NC
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
NC
I/O
NC
I/O
I/O
I/O
NC
I/O
NC
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
NC
I/O
NC
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
NC
I/O
NC
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
NC
I/O
NC
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
VCCI
GND
VCCA
GND
NC
I/O
VCCI
GND
VCCA
GND
NC
I/O
VCCI
GND
VCCA
GND
I/O
VCCI
GND
VCCA
GND
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
TRST
I/O
I/O
TRST
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
NC
I/O
NC
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
PRB, I/O
GND
VCCI
GND
VCCA
I/O
PRB, I/O
GND
VCCI
GND
VCCA
I/O
PRB, I/O
GND
VCCI
GND
VCCA
I/O
PRB, I/O
GND
VCCI
GND
VCCA
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
NC
I/O
NC
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
HCLK
I/O
HCLK
I/O
HCLK
I/O
HCLK
I/O
I/O
I/O
I/O
I/O
VCCA
I/O
VCCA
I/O
VCCA
I/O
VCCA
I/O
NC
I/O
NC
I/O
I/O
I/O
I/O
I/O
NC
I/O
NC
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
NC
I/O
NC
I/O
I/O
I/O
NC
I/O
NC
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
1. Pin 34 in RT54SX16 and RT54SX32-CQ256 are TRST pins.
v2.0
31
54SX Family FPGAs RadTolerant and HiRel
256-Pin CQFP
Pin A54SX16
RT54SX16
Function
A54SX32
Function
RT54SX32
Function
Pin
A54SX16
RT54SX16
Function
A54SX32
Function
RT54SX32
Function
Number Function
Number Function
105
106
107
108
109
110
111
I/O
NC
I/O
I/O
NC
I/O
I/O
I/O
I/O
I/O
I/O
GND
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
TDO, I/O
I/O
GND
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
VCCA
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
GND
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
TDO, I/O
I/O
GND
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
VCCA
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
177
178
179
180
181
182
183
184
185
186
187
188
189
190
191
192
193
194
195
196
197
198
199
200
201
202
203
204
205
206
207
208
209
210
GND
VCCR
GND
VCCI
I/O
GND
VCCR
GND
VCCI
I/O
GND
VCCR
GND
VCCI
I/O
GND
VCCR
GND
VCCI
I/O
I/O
I/O
I/O
I/O
GND
I/O
GND
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
NC
I/O
NC
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
NC
I/O
NC
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
VCCA
GND
GND
I/O
VCCA
GND
GND
I/O
VCCA
GND
GND
I/O
VCCA
GND
GND
I/O
NC
I/O
NC
I/O
I/O
I/O
NC
TDO, I/O
NC
GND
I/O
NC
TDO, I/O
NC
GND
I/O
NC
I/O
NC
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
NC
I/O
NC
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
NC
I/O
NC
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
NC
I/O
NC
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
GND
I/O
GND
I/O
GND
I/O
GND
I/O
I/O
I/O
NC
NC
NC
VCCA
I/O
NC
NC
NC
VCCA
I/O
NC
NC
I/O
NC
NC
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
NC
I/O
NC
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
NC
I/O
NC
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
NC
I/O
NC
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
NC
NC
NC
NC
NC
NC
NC
I/O
NC
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
Note:
1. Pin 34 in RT54SX16 and RT54SX32-CQ256 are TRST pins.
32
v2.0
54SX Family FPGAs RadTolerant and HiRel
256-Pin CQFP
Pin
A54SX16
RT54SX16
Function
A54SX32
Function
RT54SX32
Function
Pin
A54SX16
RT54SX16
Function
A54SX32
Function
RT54SX32
Function
Number Function
Number Function
211
212
213
214
215
216
217
218
219
220
221
222
223
224
225
226
227
228
229
230
231
232
233
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
234
235
236
237
238
239
240
241
242
243
244
245
246
247
248
249
250
251
252
253
254
255
256
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
NC
I/O
NC
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
NC
GND
I/O
NC
GND
I/O
I/O
I/O
I/O
I/O
I/O
I/O
GND
I/O
GND
I/O
I/O
I/O
I/O
I/O
CLKA
CLKB
VCCI
GND
VCCR
GND
PRA, I/O
I/O
CLKA
CLKB
VCCI
GND
VCCR
GND
PRA, I/O
I/O
CLKA
CLKB
VCCI
GND
VCCR
GND
PRA, I/O
I/O
CLKA
CLKB
VCCI
GND
VCCR
GND
PRA, I/O
I/O
I/O
I/O
I/O
I/O
NC
I/O
NC
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
NC
I/O
NC
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
NC
NC
I/O
I/O
NC
I/O
NC
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
NC
I/O
NC
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
NC
NC
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
TCK, I/O
TCK, I/O
TCK, I/O
TCK, I/O
Note:
1. Pin 34 in RT54SX16 and RT54SX32-CQ256 are TRST pins.
v2.0
33
54SX Family FPGAs RadTolerant and HiRel
List of Changes
The following table lists critical changes that were made in the current version of the document.
Previous version Changes in current version (Preliminary v 1.5.1 (web-only))
Page
Power up and down sequencing information was modified: damage to the device is
possible when 3.3V is powered up first and when 5.0V is powered down first.
13
Preliminary v1.5
The last line of equation 2 was cut off in the previous version. It has been replaced in
14
the existing version.
The User I/Os changed.
1, 2, 3
The following sections are new or were updated: Clock Resources , Performance ,
I/O Modules , Power Requirements , Boundary Scan Testing (BST) , and Configuring
Diagnostic Pins , TRST pin , Dedicated Test Mode , and Flexible Mode ,
Development Tool Support , RT54SX Probe Circuit Control Pins , and Design
8-10
26
Considerations .
Preliminary v1.5.2
The “Pin Description” on page 26 has been updated.
Note that the “Package Characteristics and Mechanical Drawings” section has been
eliminated from the data sheet. The mechanical drawings are now contained in a
separate document, “Package Characteristics and Mechanical Drawings,” available
on the Actel web site.
Data Sheet Categories
In order to provide the latest information to designers, some data sheets are published before data has been fully
characterized. These data sheets are marked as “Advanced” or Preliminary” data sheets. The definition of these categories
are as follows:
Advanced
The data sheet contains initial estimated information based on simulation, other products, devices, or speed grades. This
information can be used as estimates, but not for production.
Preliminary
The data sheet contains information based on simulation and/or initial characterization. The information is believed to be
correct, but changes are possible.
Unmarked (production)
The data sheet contains information that is considered to be final.
34
v2.0
54SX Family FPGAs RadTolerant and HiRel
v2.0
35
Actel and the Actel logo are registered trademarks of Actel Corporation.
All other trademarks are the property of their owners.
http://www.actel.com
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Actel Corporation
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USA
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