RTL8019 [ETC]
Realtek Full-Duplex Ethernet Controller with Plug and Play Function(RealPNP); 瑞昱全双工以太网控制器，带有即插即用功能（ RealPNP ）
| 型号： | RTL8019 |
| 厂家： | 
ETC |
| 描述： | Realtek Full-Duplex Ethernet Controller with Plug and Play Function(RealPNP) |
| 文件： | 总50页 (文件大小：388K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
RTL8019
Realtek Full-Duplex Ethernet
Controller with Plug and Play
Function (RealPNP)
ADVANCE INFORMATION
REALTEK SEMI-CONDUCTOR CO., LTD.
HEAD OFFICE
1F, NO. 11, INDUSTRY E. RD. IX, SCIENCE-BASED
INDUSTRIAL PARK, HSINCHU 30077, TAIWAN, R.O.C.
TEL:886-35-780211 FAX:886-35-776047
OFFICE
3F, NO. 56, WU-KUNG 6 RD.,
TAIPEI HSIEN, TAIWAN, R.O.C.
TEL: 886-2-2980098 FAX: 886-2-2980094, 2980097
LS003.6
1995.04.25
ADVANCE INFORMATION
RTL8019
CONTENTS
1. FEATURES
3
4
5
2. GENERAL DESCRIPTION
3. PIN CONFIGURATION
4. PIN DESCRIPTION
4.1. Power Pins
6
6
7
8
8
4.2. ISA Bus Interface Pins
4.3. Memory Interface Pins (including SRAM, BROM, EEPROM)
4.4. Medium Interface Pins
4.5. LED Output Pins
5. REGISTER DESCRIPTIONS
5.1. Group 1: NE2000 Registers
5.1.1. Register Table
9
9
5.1.2. Register Functions
11
11
11
17
23
25
25
5.1.2.1. NE2000 Compatible Registers
5.1.2.2. RTL8019 Defined Registers
5.2. Group 2: Plug and Play (PnP) Registers
5.2.1. Card Control Registers
5.2.2. Logical Device Control Registers
5.2.3. Logical Device Configuration Registers
6. FUNCTIONAL DESCRIPTIONS
6.1. RTL8019 Configuration Modes
6.2. Plug and Play
26
28
28
29
33
34
35
37
38
41
6.2.1. Initiation Key
6.2.2. Isolation Protocol
6.2.3. Plug and Play Isolation Sequence
6.2.4. Reading Resource Data
6.3. 9346 Contents
6.4. Local Memory Bus Control
6.5. LED Behaviors
6.6. Loopback Diagnostic Operation
LS003.6
ADVANCE INFORMATION
RTL8019
1. FEATURES
m 100-pin PQFP
m Compliant to Ethernet II and IEEE802.3 10Base5, 10Base2, 10BaseT
m Software compatible with NE2000 on both 8 and 16-bit slots
m Supports both jumper and jumperless modes
m Supports Microsoft's Plug and Play configuration for jumperless mode
m Supports Full-Duplex Ethernet function to double channel bandwidth
m Supports three level power down modes:
- Sleep
- Power down with internal clock running
- Power down with internal clock halted
m Built-in data prefetch function to improve performance
m Provides auto-detect capability between integrated 10BaseT transceiver and Attachment Unit
Interface (AUI).
m Supports auto polarity correction for 10BaseT
m Support 8 IRQ lines
m Supports 16 I/O base address options
m Supports 16K, 32K, 64K and 16K-page mode access to BROM (up to 256 pages with 16K
bytes/page)
m Supports BROM disable command to release memory after remote boot
m Use two 8K or single 32K byte SRAM as local buffer memory
m Use 9346 (64*16-bit EEPROM) to store resource configurations and ID parameters
m Capable of programming blank 9346 on board for manufacturing convenience
m Support 4 diagnostic LED pins with programmable outputs
LS003.6
ADVANCE INFORMATION
RTL8019
2. General Description
The RTL8019 is a highly integrated Ethernet Controller which offers a simple solution to
implement a Plug and Play NE2000 compatible adapter with full-duplex and power down features.
With the three level power down control features, the RTL8019 is made to be an ideal choice of
the network device for a GREEN PC system. The full-duplex function enables simultaneously
transmission and reception on the twisted-pair link to a full-duplex Ethernet switching hub. This
feature not only increases the channel bandwidth from 10 to 20 Mbps but also avoids the
performance degrading problem due to the channel contention characteristics of the Ethernet
CSMA/CD protocol. The Microsoft's Plug and Play function can relieve the users from pains of
taking care the adapter's resource configurations such as IRQ, I/O, and memory address, etc.
However, for special applications not to be used as a Plug and Play compatible device, the
RTL8019 also supports the jumper and proprietary jumperless options.
To offer a fully plug and play solution, the RTL8019 provides the auto-detect capability between
the integrated 10BaseT transceiver and AUI interface. Besides, the 10BaseT transceiver can
automatically correct the polarity error on its receiving pair. Furthermore, 8 IRQ lines and 16 I/O
base address options are provided for grand resource configuration flexibility.
The RTL8019 supports 16k, 32k & 64k byte BROM. It also offers the page mode function which
can support up to 4M-byte BROM within only 16k-byte system memory space. Besides, the
BROM disable command is provided to release the BROM memory space for other system usage
(e.g. EMM386, etc.) after the BROM program is loaded.
LS003.6
ADVANCE INFORMATION
RTL8019
3. PIN CONFIGURATION
65 MA12
64 MA13
63 LED2
62 LED1
61 LED0
60 LEDBNC
59 TPIN+
58 TPIN-
57 VDD
56 RX+
55 RX-
54 CD+
53 CD-
52 GND
51 X2
[PNP]
[JP]
[BA21] [BS4]
[BA20] [BS3]
[BA19] [BS2]
[BA18] [BS1]
[BA17] [BS0]
[BA16] [IOS3]
[BA15]
66 MA11
67 MA10
68 MA9
69 MA8
70 MA7
71 MA6
72 MA5
73 MA4
74 MA3
75 MA2
76 MA1
77 MA0
78 VDD
79 EECS
80 MWRB
[LED_TX] [MCSB]
[LED_RX] [LED_CRS]
[LED_COL][LED_LINK]
[BA14] [IOS2]
[EESK]
[IOS1]
[EEDI] [IOS0]
[EEDO][PL1]
[PL0]
81 MRDB
82 BCSB
50 X1
49 TX+
48 TX-
83 MD7 [BD7]
84 GND
85 MD6 [BD6]
47 VDD
46 TPOUT-
45 TPOUT+
44 GND
43 SD7
86 MD5
[BD5]
87 MD4 [BD4]
[BD3]
88 MD3
[BD2] [IRQS2]
89 MD2
42 SD6
90 MD1 [BD1] [IRQS1]
91 MD0 [BD0] [IRQS0]
92 VDD
93 SD15
94 SD14
41 SD5
40 SD4
39 SD3
38 SD2
RTL8019
37 SD1
95 SD13
36 SD0
96 SD12
97 SD11
98 SD10
35 GND
34 IOCHRDY
33 AEN
32 RSTDRV
31 SMEMRB
99 SD9
100 SD8
30 IOWB
1
2
3
4
5
6
7
8
9
IOCS16B [SLOT16]
29 IORB
28 SA19
27 SA18
26 SA17
25 SA16
24 SA15
23 SA14
22 SA11
21 SA9
20 SA8
19 SA7
18 SA6
VDD
INT7
INT6
INT5
INT4
INT3
INT2
INT1
[IRQ15]
[IRQ12]
[IRQ11]
[IRQ10]
[IRQ5]
[IRQ4]
[IRQ3]
[IRQ2/9]
10 INT0
11 SA0
12 SA1
13 SA2
14 SA3
15 GND
17 SA5
16 SA4
LS003.6
ADVANCE INFORMATION
RTL8019
4. PIN DESCRIPTIONS
4.1. Power Pins
No.
Name
Type
Description
2, 47, 57,
78, 92
VDD
P
+5V DC power
Ground
15, 35, 44,
52, 84
GND
P
4.2. ISA Bus Interface Pins
No.
Name
Type
Descriptions
33
AEN
I
Address Enable. This ISA signal must be low for a valid
I/O command.
3-10
INT7-0
I/O
Interrupt request lines which are mapped to IRQ15, IRQ12,
IRQ11, IRQ10, IRQ5, IRQ4, IRQ3, IRQ2/9 respectively.
Only one line is selected to reflect the interrupt requests at
one time. All other lines are tri-stated. The RTL8019 also
uses these pins as inputs to monitor the actual state of the
corresponding interrupt lines on ISA bus. The result is
recorded in the INTR register, which may be used by
software to detect interrupt conflict.
34
1
IOCHRDY
O
This ISA signal is driven low to insert wait cycles to current
host read/write command.
IOCS16B
[SLOT16]
I/O
Upon power-on reset, this pin acts as an input named
SLOT16 to detect whether a 16-bit or 8-bit slot is in use. To
do this, it is connected to a pull-down resistor (about 27KW)
externally. At the falling edge of RSTDRV, the RTL8019
senses this pin's state. If it is sensed high, the adapter is
thought to be placed on a 16-bit slot where this pin is
connected to the host's IOCS16B pin, which is typically
pulled up by a 300W resistor on the mother board. If it is
sensed low, the adapter is thought to be placed on an 8-bit
slot where this pin is merely pulled low by the 27KW
resistor. After having latched the input state, this pin is
switched as the IOCS16B signal which is an open-drain
output and is driven low during a 16-bit host data transfer.
It is decoded from AEN and SA9-0.
29
30
32
IORB
IOWB
I
I
I
Host I/O read command.
Host I/O write command.
RSTDRV
High active hardware reset signal from the ISA bus. Pulses
with high level less than 800ns are ignored.
28-16,
14-11
SA19-14,
SA11, SA9-0
I
I/O
I
Host address bus.
93-100,
43-36
SD15-0
Host data bus.
31
SMEMRB
Host memory read command.
LS003.6
ADVANCE INFORMATION
RTL8019
4.3. Memory Interface Pins (including SRAM, BROM, EEPROM)
No.
Name
Type
Description
82
BCSB
O
BROM chip select. Active low signal, asserted when BROM
is read.
79
EECS
O
9346 chip select. Active high signal, asserted when 9346 is
read/write.
64-77
MA13-0
MD7-0
O
I/O
O
I
SRAM address bus.
SRAM data bus.
83,85-91
[66-73]
[83,85-91]
[74]
[BA21-14]
[BD7-0]
[EESK]
[EEDI]
BROM address.
BROM data bus.
O
O
I
9346 serial data clock
9346 serial data input
9346 serial data output
[75]
[76]
[EEDO]
The following pins are defined for jumper options. Their
states are latched at the falling edge of RSTDRV, then they
are changed to serve as the SRAM bus. Each of them is
internally pulled down by a 100KW resistor. Therefore, the
input will be low when left open and high when pulled up
by a 10K resistor externally.
[64]
[65]
[JP]
I
I
When high, this pin selects jumper mode. When low, it
selects jumperless modes (including RT jumperless and Plug
and Play).
[PNP]
When it is high in jumperless mode (i.e. JP=low), the
RTL8019 is forced into Plug and Play mode regardless of
the contents of 9346.
The following pins are don't care in jumperless mode
(JP=low).
[66-70]
[71,73-75]
[76-77]
[89-91]
81
[BS4-0]
[IOS3-0]
[PL1-0]
[IRQS2-0]
MRDB
I
I
Select BROM size and base address.
Select I/O base address.
I
Select network medium type.
Select one interrupt line among INT7-0.
SRAM read strobe.
I
O
O
80
MWRB
SRAM write strobe.
LS003.6
ADVANCE INFORMATION
RTL8019
4.4. Medium Interface Pins
No.
Name
Type
Description
54,53
CD+,CD-
I
This AUI collision input pair carries the differential
collision input signal from the MAU.
56,55
49,48
RX+,RX-
TX+,TX-
I
This AUI receive input pair carries the differential receive
input signal from the MAU.
O
This AUI transmit output pair contains differential line
drivers which send Manchester encoded data to the MAU.
These outputs are source followers and require 270 ohm
pull-down resistors to GND.
59,58
45,46
TPIN+,
TPIN-
I
This TP input pair receives the 10 Mbits/s differential
Manchester encoded data from the twisted-pair wire.
TPOUT+,
TPOUT-
O
This pair carries the differential TP transmit output. The
output Manchester encoded signals have been pre-distorted
to prevent overcharge on the twisted-pair media and thus
reduce jitter.
50
51
X1
X2
I
20Mhz crystal or external oscillator input.
O
Crystal feedback output. This output is used in crystal
connection only. It must be left open when X1 is driven with
an external oscillator.
4.5. LED Output Pins
No.
Name
Type
Description
60
LEDBNC
O
This pin goes high when RTL8019's medium type is set to
10Base2 mode or auto-detect mode with link test failure.
Otherwise, this pin is low. This pin can be used to control
the power of the DC convertor for CX MAU and connected
to an LED to indicate the used medium type.
61
LED0
O
O
When LEDS0 bit (in CONFIG3 register of RTL8019
Page3) is 0, this pin acts as LED_COL. When LEDS0=1, it
acts as LED_LINK.
62,63
LED1,LED2
When LEDS1 bit (in CONFIG3 register of RTL8019 Page3)
is 0, these 2 pins act as LED_RX & LED_TX respectively.
When LEDS1=1, these pins act as LED_CRS & MCSB.
Please refer to section 6.5 for details of the lightening
behavior of all LEDs.
[MCSB]
O
This is the SRAM chip select signal. It goes low to validate
the SRAM read/write operation. When SRAM is not
accessed, this pin goes high to put SRAM into standby mode
and thus save power.
LS003.6
ADVANCE INFORMATION
RTL8019
5. Register Descriptions
The registers in RTL8019 can be roughly divided into two groups by their address and functions --
one for NE2000, the other for Plug and Play (PnP).
5.1. Group 1: NE2000 Registers
This group includes 4 pages of registers which are selected by bit PS0 & PS1 in the CR register.
Each page contains 16 registers. Besides those registers compatible with NE2000, the RTL8019
defines some registers for software configuration and feature enhancement.
5.1 1. Register Table
No (Hex)
Page0
Page1
[R/W]
Page2
[R]
Page3
[R]
[W]
[R]
[W]
CR
CR
CR
CR
CR
CR
00
CLDA0
CLDA1
BNRY
TSR
PSTART
PAR0
PAR1
PAR2
PAR3
PAR4
PAR5
CURR
MAR0
MAR1
MAR2
MAR3
MAR4
MAR5
MAR6
MAR7
PSTART
01
02
03
04
05
06
07
08
9346CR
BPAGE
CONFIG0
CONFIG1
CONFIG2
CONFIG3
-
CSNSAV
-
-
9346CR
BPAGE
-
CONFIG1
CONFIG2
CONFIG3
-
PSTOP
BNRY
TPSR
TBCR0
TBCR1
ISR
PSTOP
-
TPSR
NCR
-
FIFO
-
ISR
-
CRDA0
CRDA1
RSAR0
RSAR1
RBCR0
RBCR1
RCR
-
-
-
09
HLTCLK
-
0A
0B
0C
0D
0E
0F
8019ID0
8019ID1
-
-
-
-
-
-
-
INTR
RSR
RCR
TCR
DCR
IMR
-
-
-
-
CNTR0
CNTR1
CNTR2
TCR
DCR
IMR
Remote DMA Port
Reset Port
10-17
18-1F
Notes: "-" denotes reserved. Registers with names typed in bold italic format are RTL8019 defined
registers and are not supported in a standard NE2000 adapter.
LS003.6
ADVANCE INFORMATION
RTL8019
Page 0 (PS1=0, PS0=0)
No.
Name
Type Bit 7 Bit 6 Bit 5
Bit 4 Bit 3 Bit 2 Bit 1
Bit 0
00H
01H
CR
R/W PS1
PS0
A6
RD2
A5
RD1
A4
RD0
A3
TXP
A2
STA
A1
A9
A9
A9
A9
-
A9
STP
A0
A8
A8
A8
A8
PTX
A8
NC0
TBC0
D0
CLDA0
PSTART
CLDA1
PSTOP
BNRY
TSR
TPSR
NCR
TBCR0
FIFO
R
W
R
A7
A15
A15
A15
A14
A14
A14
A14
CDH
A14
0
A13
A13
A13
A13
0
A13
0
TBC5
D5
A12
A12
A12
A12
CRS
A12
0
A11
A11
A11
A11
ABT
A11
NC3
TBC3
D3
A10
A10
A10
A10
COL
A10
NC2
TBC2
D2
02H
W
03H
04H
R/W A15
R
W
R
OWC
A15
0
05H
06H
NC1
TBC1
D1
W
R
TBC7
D7
TBC6
D6
TBC4
D4
TBCR1
ISR
CRDA0
RSAR0
CRDA1
RSAR1
W
TBC15 TBC14 TBC13 TBC12 TBC11 TBC10 TBC9
TBC8
PRX
A0
A0
A8
A8
0
RBC0
0
RBC8
PRX
SEP
CNT0
CRC
CNT0
WTS
CNT0
PRXE
07H
08H
R/W RST
RDC
A6
A6
A14
A14
1
CNT
A5
A5
A13
A13
0
OVW
A4
A4
A12
A12
1
TXE
A3
A3
A11
A11
0
RXE
A2
A2
A10
A10
0
PTX
A1
A1
A9
A9
0
R
W
R
W
R
W
R
W
R
W
R
W
R
W
R
W
A7
A7
A15
A15
0
09H
0AH 8019ID0
RBCR0
0BH 8019ID1
RBCR1
0CH RSR
RCR
0DH CNTR0
TCR
RBC7
0
RBC6
1
RBC5
1
RBC4
1
RBC3
0
RBC2
0
RBC1
0
RBC15 RBC14 RBC13 RBC12 RBC11 RBC10 RBC9
DFR
-
CNT7
-
CNT7
-
CNT7
-
DIS
-
CNT6
-
CNT6
FT1
CNT6
RDCE
PHY
MON
CNT5
-
CNT5
FT0
MPA
PRO
0
AM
CNT3
ATD
CNT3
LS
FAE
AB
CNT2
LB1
CNT2
LAS
CRC
AR
CNT1
LB0
CNT1
BOS
CNT1
PTXE
CNT4
OFST
CNT4
ARM
CNT4
0EH CNTR1
DCR
0FH
CNTR2
IMR
CNT5
CNTE
CNT3
CNT2
RXEE
OVWE TXEE
Page 1 (PS1=0, PS0=1)
No.
00H
01H
02H
03H
04H
05H
06H
07H
08H
09H
0AH MAR2
0BH MAR3
0CH MAR4
0DH MAR5
0EH MAR6
Name
CR
Type
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Bit 7
PS1
DA7
DA15
DA23
DA31
DA39
DA47
A15
Bit 6
PS0
DA6
DA14
DA22
DA30
DA38
DA46
A14
Bit 5
RD2
DA5
DA13
DA21
DA29
DA37
DA45
A13
Bit 4
RD1
DA4
DA12
DA20
DA28
DA36
DA44
A12
Bit 3
RD0
DA3
DA11
DA19
DA27
DA35
DA43
A11
Bit 2
TXP
DA2
DA10
DA18
DA26
DA34
DA42
A10
Bit 1
STA
Bit 0
STP
PAR0
PAR1
PAR2
PAR3
PAR4
PAR5
CURR
MAR0
MAR1
DA1
DA9
DA17
DA25
DA33
DA41
A9
DA0
DA8
DA16
DA24
DA32
DA40
A8
FB7
FB6
FB5
FB4
FB3
FB2
FB1
FB9
FB0
FB8
FB15
FB23
FB31
FB39
FB47
FB55
FB63
FB14
FB22
FB30
FB38
FB46
FB54
FB62
FB13
FB21
FB29
FB37
FB45
FB53
FB61
FB12
FB20
FB28
FB36
FB44
FB52
FB60
FB11
FB19
FB27
FB35
FB43
FB51
FB59
FB10
FB18
FB26
FB34
FB42
FB50
FB58
FB17
FB25
FB33
FB41
FB49
FB57
FB16
FB24
FB32
FB40
FB48
FB56
0FH
MAR7
LS003.6
ADVANCE INFORMATION
RTL8019
Page 2(PS1=1, PS0=0)
No.
Name
CR
PSTART
PSTOP
-
Type
R/W
R
Bit 7
PS1
A15
A15
Bit 6
PS0
A14
A14
Bit 5
RD2
A13
Bit 4
RD1
A12
Bit 3
RD0
A11
Bit 2
TXP
A10
Bit 1
STA
A9
Bit 0
STP
A8
00H
01H
02H
03H
04H
05H
|
R
A13
A12
A11
A10
A9
A8
TPSR
-
R
A15
A14
A13
A12
A11
A10
A9
A8
0BH
0CH RCR
0DH TCR
0EH DCR
R
R
R
R
-
-
-
-
-
-
MON
-
FT0
CNTE
PRO
OFST
ARM
AM
ATD
LS
AB
AR
SEP
LB1
LAS
RXEE
LB0
BOS
PTXE
CRC
WTS
PRXE
FT1
RDCE
0FH
IMR
OVWE TXEE
Page 3(PS1=1, PS0=1)
No.
00H
01H
Name
CR
9346CR
Type
Bit 7
Bit 6
Bit 5
Bit 4
RD1
-
Bit 3
RD0
EECS
EECS
BP3
Bit 2
Bit 1
Bit 0
R/W PS1
R
W
R/W BP7
R
R
PS0
RD2
TXP
STA
STP
EEDO
EEM1
EEM1
EEM0
EEM0
BP6
-
-
-
EESK
EESK
BP2
BNC
IOS2
-
EEDI
EEDI
BP1
0
IOS1
-
-
-
02H
03H
04H
BPAGE
CONFIG0
CONFIG1
BP5
-
BP4
-
BP0
-
JP
0
IRQEN IRQS2 IRQS1 IRQS0 IOS3
IOS0
W* IRQEN
PL1
W* PL1
-
-
-
-
-
05H
06H
CONFIG2
CONFIG3
R
PL0
PL0
BSELB BS4
BSELB
BS3
BS2
-
BS1
-
BS0
-
-
-
-
-
R
W*
PNP
-
FUDUP LEDS1 LEDS0
SLEEP PWRDN ACTIVEB
SLEEP PWRDN
-
-
-
-
07H
08H
09H
TEST1
CSNSAV
HLTCLK
R/W Reserved
R
CSN7
HLT7
CSN6
HLT6
CSN5
HLT5
CSN4
HLT4
CSN3
HLT3
CSN2
HLT2
CSN1
HLT1
CSN0
HLT0
W
0AH TEST2
R/W Reserved
INT7
0BH
0CH
|
INTR
-
R
INT6
INT5
INT4
INT3
INT2
INT1
INT0
0FH
Note: The registers marked with type='W*' can be written only if bits EEM1=EEM0=1.
5.1.2. Register Functions
5.1.2.1. NE2000 Compatible Registers
CR: Command Register (00H; Type=R/W)
This register is used to select register pages, enable or disable remote DMA operation and
issue commands.
LS003.6
ADVANCE INFORMATION
RTL8019
Bit
Symbol
Description
7, 6
PS1, PS0
PS1
0
0
1
1
PS0
0
1
0
1
Register Page
Remark
0
1
2
3
NE2000 compatible
NE2000 compatible
NE2000 compatible
RTL8019 Configuration
5-3
RD2-0
RD2
RD1
RD0
Function
0
0
0
0
1
0
0
1
1
*
0
1
0
1
*
Not allowed
Remote Read
Remote Write
Send Packet
Abort/Complete remote DMA
2
1
0
TXP
STA
STP
This bit must be set to transmit a packet. It is internally reset either after the
transmission is completed or aborted. Writing a 0 has no effect.
The STA bit controls nothing. It only reflects the value written to this bit.
POWER UP=0.
This bit is the STOP command. When it is set, no packets will be received or
transmitted. POWER UP=1.
STA
STP
Function
Start Command
Stop Command
1
0
0
1
ISR: Interrupt Status Register (07H; Type=R/W in Page0)
This register reflects the NIC status. The host reads it to determine the cause of an interrupt.
Individual bits are cleared by writing a "1" into the corresponding bit. It must be cleared
after power up.
Bit
Symbol
Description
7
RST
This bit is set when NIC enters reset state and is cleared when a start command is
issued to the CR. It is also set when receive buffer overflows and is cleared when
one or more packets have been read from the buffer.
Set when remote DMA operation has been completed.
Set when MSB of one or more of the network tally counters has been set.
This bit is set when the receive buffer has been exhausted.
Transmit error bit is set when a packet transmission is aborted due to excessive
collisions.
6
5
4
3
RDC
CNT
OVW
TXE
2
RXE
This bit is set when a packet received with one or more of the following errors:
- CRC error
- Frame alignment error
-Missed packet
1
0
PTX
PRX
This bit indicates packet transmitted with no errors.
This bit indicates packet received with no errors.
LS003.7
ADVANCE INFORMATION
RTL8019
IMR: Interrupt Mask Register (0FH; Type=W in Page0, Type=R in Page2)
All bits correspond to the bits in the ISR register. POWER UP=all 0s. Setting individual
bits will enable the corresponding interrupts.
DCR: Data Configuration Register (0EH; Type=W in Page0, Type=R in Page2)
Bit
7
Symbol
Description
-
Always 1
6, 5
4
FT1, FT0 FIFO threshold select bit 1 and 0.
ARM
Auto-initialize Remote
0: Send Packet Command not executed.
1: Send Packet Command executed.
Loopback Select
3
LS
0: Loopback mode selected. Bits 1 and 2 of the TCR must also be
programmed for Loopback operation.
1: Normal Operation
2
1
LAS
BOS
This bit must be set to zero. NIC only supports dual 16-bit DMA mode.
POWER UP =1
Byte Order Select(Not implement)
0: MS byte placed on MD15-8 and LS byte on MD7-0. (32xxx,80x86)
1: MS byte placed on MD7-0 and LS byte on MD15-8. (680x0)
Word Transfer Select
0
WTS
0: byte-wide DMA transfer
1: word-wide DMA transfer
LS003.7
ADVANCE INFORMATION
RTL8019
TCR: Transmit Configuration Register (0DH; Type=W in Page0, Type=R in Page2)
Bit
7
Symbol
Description
-
Always 1.
6
5
-
-
Always 1.
Always 1.
4
3
OFST
ATD
Collision Offset Enable.
Auto Transmit Disable.
0: normal operation
1: reception of multicast address hashing to bit 62 disables transmitter,
reception of multicast address hashing to bit 63 enables transmitter.
2, 1
LB1, LB0
LB1
LB0
Mode
Remark
Normal Operation
Internal Lookback
External Lookback
External Lookback
0
0
1
1
0
1
0
1
0
1
2
3
0
CRC
The NIC CRC logic comprises a CRC generator for transmitter and a CRC
checker for receiver. This bit controls the activity of the CRC logic. If this bit set,
CRC is inhibited by transmitter. Otherwise CRC is appended by transmitter.
Conditions
CRC Logic Activities
CRC Bit
Mode
normal
normal
loopback
loopback
CRC Generator CRC Checker
0
1
0
1
enabled
disabled
enabled
disabled
enabled
enabled
disabled
enabled
TSR:Transmit Status Register (04H; Type=R in Page0)
This register indicates the status of a packet transmission.
Bit
Symbol
Description
7
OWC
Out of Window Collision. It is set when a collision is detected after a slot time
(51.2us). Transmissions are rescheduled as in normal collisions.
CD Heartbeat. The NIC watches for a collision signal (i.e. CD Heartbeat signal)
during the first 6.4us of the interframe gap following a transmission. This bit is
set if the transceiver fails to send this signal.
6
CDH
5
4
3
2
1
0
-
Always 0.
CRS
ABT
COL
-
Carrier Sense lost bit is set when the carrier is lost during transmitting a packet.
It indicates the NIC aborted the transmission because of excessive collisions.
It indicates the transmission collided with some other station on the network.
Always 1.
PTX
This bit indicates the transmission completes with no errors.
LS003.7
ADVANCE INFORMATION
RTL8019
RCR:
Receive Configuration Register (0CH; Type=W in Page0, Type=R in Page2)
Bit
7
6
Symbol
Description
-
-
Always 1.
Always 1.
5
MON
When monitor mode bit is set, received packets are checked for address match,
good CRC and frame alignment but not buffered to memory. Otherwise, packets
will be buffered to memory.
4
PRO
If PRO=1, all packets with physical destination address accepted.
If PRO=0, physical destination address must match the node address programmed
in PAR0-5.
3
2
1
0
AM
AB
If AM=1, packets with multicast destination address are accepted.
If AM=0, packets with multicast destination address are rejected.
If AB=1, packets with broadcast destination address are accepted.
If AB=0, packets with broadcast destination address are rejected.
If AR=1, packets with length fewer than 64 bytes are accepted.
If AR=0, packets with length fewer than 64 bytes are rejected.
If SEP=1, packets with receive errors are accepted.
AR
SEP
If SEP=0, packets with receive errors are rejected.
RSR: Receive Status Register (0CH; Type=R in Page0)
Bit
7
6
Symbol
DFR
DIS
Description
Defferring. Set when a carrier or a collision is detected.
Receiver Disabled. When the NIC enters the monitor mode, this bit is set and
receiver is disabled. Reset when receiver is enabled after leaving the monitor
mode.
5
4
PHY
MPA
PHY bit is set when the received packet has a multicast or broadcast destination
address. It is reset when the received packet has a physical destination address.
Missed Packet bit is set when the incoming packet can not be accepted by NIC
because of a lack of receive buffer or if NIC is in monitor mode. Increment
CNTR2 tally counter.
3
2
-
Always 0.
FAE
Frame Alignment Error bit reflects the incoming packet didn't end on a byte
boundary and CRC did not match at last byte boundary. Increment CNTR0 tally
counter.
1
0
CRC
PRX
CRC error bit reflects packet received with CRC error. This bit will also be set
for FAE errors. Increment CNTR1 tally counter.
This bit indicates packet received with no errors.
CLDA0, 1: Current Local DMA Registers (01H & 02H; Type=R in Page0)
These two registers can be read to get the current local DMA address.
PSTART: Page Start Register (01H; Type=W in Page0, Type=R in Page 2)
The Page Start register sets the start page address of the receive buffer ring.
PSTOP:
BNRY:
Page Stop Register (02H; Type=W in Page0, Type=R in Page2)
The Page Stop register sets the stop page address of the receive buffer ring.
Boundary Register (03H; Type=R/W in Page0)
This register is used to prevent overwrite of the receive buffer ring. It is typically
used as a pointer indicating the last receive buffer page the host has read.
LS003.7
ADVANCE INFORMATION
RTL8019
TPSR:
Transmit Page Start Register (04H; Type=W in Page0)
This register sets the start page address of the packet to the transmitted.
TBCR0,1: Transmit Byte Count Registers (05H & 06H; Type=W in Page0)
These two registers set the byte counts of the packet to be transmitted.
NCR:
FIFO:
Number of Collisions Register (05H; Type=R in Page0)
The register records the number of collisions a node experiences during a packet
transmission.
First In First Out Register (06H; Type=R in Page0)
This register allows the host to examine the contents of the FIFO after loopback.
CRDA0, 1: Current Remote DMA Address registers (08H & 09H; Type=R in Page0)
These two registers contain the current address of remote DMA.
RSAR0,1: Remote Start Address Registers (08H & 09H; Type=W in Page0)
These two registers set the start address of remote DMA.
RBCR0,1: Remote Byte Count Registers (0AH & 0BH; Type=W in Page0)
These two registers se the data byte counts of remote DMA.
CNTR0:
CNTR1:
CNTR2:
PAR0-5:
Frame Alignment Error Tally Counter Register (0DH; Type=R in Page0)
CRC Error Tally Counter Register (0EH; Type=R in Page0)
Missed Packet Tally Counter Register (0FH; Type=R in Page0)
Physical Address Registers (01H - 06H; Type=R/W in Page1)
These registers contain my Ethernet node address and are used to compare the
destination adderss of incoming packets for acceptation or rejection.
CURR:
Current Page Register (07H; Type=R/W in Page1)
This register points to the page address of the first receive buffer page to be used for
a packet reception.
MAR0-7: Multicast Address Register (08H - 0FH; Type=R/W in Page1)
These registers provide filtering bits of multicast addresses hashed by the CRC logic.
LS003.7
ADVANCE INFORMATION
RTL8019
5.1.2.2. RTL8019 Defined Registers
Page 0 (PS1=0, PS0=0)
Two registers are defined to contain the RTL8019 chip ID.
No.
0AH
0BH
Name
8019ID0
8019ID1
Type
R
R
Bit7-0
50H (ASCII code of "P")
70H (ASCII code of "p")
Page 3(PS1=1, PS0=1)
Page3 Power Up Values before loading jumper states and 9346 contents
No.
Name
CR
Type
R/W
R/W
R/W
R
R/W
R/W
R/W
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
00H
01H
02H
03H
04H
05H
06H
07H
08H
09H
0AH
0BH
0CH
|
0
0
0
-
1
*
*
0
0
0
-
*
*
*
1
-
0
-
*
0
*
0
-
0
-
*
*
*
0
*
0
*
*
*
*
0
*
0
*
*
*
0
0
*
0
0
*
*
0
1
*
0
0
*
*
1
9346CR
BPAGE
CONFIG0
CONFIG1
CONFIG2
CONFIG3
-
CSNSAV
HLTCLK
-
R
W
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
INTR
R
*
*
*
*
*
*
*
*
-
0FH
LS003.7
ADVANCE INFORMATION
RTL8019
Page3 Content Descriptions
9346CR: 9346 Command Register (01H; Type=R/W except Bit0=R)
Bit
Symbol
Description
7-6
EEM1-0
These 2 bits select the RTL8019 operating mode.
EEM1 EEM0
Operating Mode
Normal (DP8390 compatible)
Auto-load:
0
0
0
1
Entering this mode will make the RTL8019 load
the contents of 9346 like when the RSTDRV
signal is asserted.
This auto-load operation will take about 2ms.
After it is completed, the RTL8019 goes back to
the normal mode automatically (EEM1=EEM0
=0) and the CR register is reset to 21H.
9346 programming:
In this mode, both the local & remote DMA
operation of 8390 are disabled. The 9346 can be
directly accessed via bit3-0 which now reflect the
states of EECS, EESK,EEDI, & EEDO pins
respectively.
1
1
0
1
Config register write enable:
Before writing to the Page3 CONFIG1-3
registers, the RTL8019 must be placed in this
mode. This will prevent RTL8019's
configurations from accidental change.
5-4
3
2
1
0
-
Not used.
EECS
EESK
EEDI
EEDO
These bits reflect the state of EECS, EESK, EEDI & EEDO pins in auto-load or
9346 programming mode.
BPAGE: BROM Page Register (02H; Type=R/W)
This register selects a BROM page to be read by the host. Totally it can select 256 pages with 16k
bytes per page. Thus the maximum BROM size is 256*16k=4M bytes.
CONFIG0: RTL8019 Configuration Register 0 (03H; Type=R)
Bit
7-4
3
Symbol
Description
-
JP
Not used
This bit reflects the state of JP input. It, when set, indicates the RTL8019 is in
jumper mode.
2
BNC
-
When set, this bit indicates that the RTL8019 is using the 10Base2 thin cable as
its networking medium. This bit will be set in the following 2 cases:
(1) PL1=PL0=0 (auto-detect) and link test fails
(2) PL1=PL0=1 (10 Base 2)
1-0
Always 0s.
LS003.7
ADVANCE INFORMATION
RTL8019
CONFIG1: RTL8019 Configuration Register 1 (04H; Type=R except Bit7=R/W)
Bit
Symbol
Description
7
IRQEN
IRQ Enable:
This bit controls the state of the interrupt request line selected by IRQS2-0. If
this bit is set, the interrupt line goes high upon an interrupt request and will be
low when there is no interrupt request.
The interrupt line will be forced to tri-state if this bit is reset.
This bit's power-up initial value is 1 and may be modified by software if
EEM1=EEM0=1 in 9346CR register.
6-4
IRQS2-0 IRQ Select :
These 3 bits select one of INT7-0 to reflect the RTL8019's interrupt request
status. All unselected interrupt lines will be tri-stated.
IRQS2 IRQS1 IRQS0
Interrupt Line Assigned ISA IRQ
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
INT0
INT1
INT2
INT3
INT4
INT5
INT6
INT7
IRQ2/9
IRQ3
IRQ4
IRQ5
IRQ10
IRQ11
IRQ12
IRQ15
3-0
IOS3-0
Select I/O base address.
IOS3
IOS2
IOS1
IOS0
I/O Base
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
300H
320H
340H
360H
380H
3A0H
3C0H
3E0H
200H
220H
240H
260H
280H
2A0H
2C0H
2E0H
LS003.7
ADVANCE INFORMATION
RTL8019
CONFIG2: RTL8019 Configuration Register 2 (05H; Type=R except Bit[7:5]=R/W)
Bit
Symbol
Description
7-6
PL1-0
Select network medium types.
PL1
PL0
Medium Type
0
0
TP/CX auto-detect
(10BaseT link test is
enabled)
0
1
10BaseT with link test
disabled
1
1
0
1
10Base5
10Base2
5
BSELB
BS4-0
This bit, when set, forces the BROM disabled regardless of the contents of BS4-
0. Its power-up initial value is 0 and can be modified by software if
EEM1=EEM0=1 in 9346CR register.
4-0
These bits select the BROM size & memory base address.
BS4 BS3 BS2 BS1 BS0
BROM Base & size
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
1
1
1
1
1
1
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
*
0
0
0
0
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
*
0
0
1
1
0
0
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
*
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
Disabled
C000h, 32K
C800h, 32K
D000h, 32K
D800h, 32K
C000h, 64K
D000h, 64K
C000h, 16K
C400h, 16K
C800h, 16K
CC00h, 16K
D000h, 16K
D400h, 16K
D800h, 16K
DC00h, 16K
C000h, Page
C400h, Page
C800h, Page
CC00h, Page
D000h, Page
D400h, Page
D800h, Page
DC00h, Page
The RTL8019 supports a special BROM mode: page mode. In page mode, the
BROM always occupies 16K-byte host memory space. However the actual BROM
size can be up to 4M bytes.
The BROM is divided into several 16K-byte pages. The power on boot page is set
to page 0 and the program in page 0 is responsible to select the other pages by the
BPAGE register and load their programs.
In page mode, bits BP7-0 of BPAGE register are mapped to the BA21-14 pins to
select the proper BROM page. In other modes, BA21-16 are not used and the
BA15-14 outputs are shown in the following table.
LS003.7
ADVANCE INFORMATION
RTL8019
BROM size
16K
BA14
BA15
high
high
high
SA14
SA14
32K
64K
SA15
LS003.7
ADVANCE INFORMATION
RTL8019
CONFIG3: RTL8019 Configuration Register 3 (06H; Type=R except Bit[2:1]=R/W)
Bit
Symbol
Description
7
PNP
This bit is negligible in jumper mode. In jumperless mode it, when set, indicates
the RTL8019 is operating in Plug and Play mode. This bit is set when the PNP
pin is high or the PNP bit in 9346 is set in jumperless mode.
6
FUDUP
When this bit is set, RTL8019 is set to the full-duplex mode which enables
simultaneously transmission and reception on the twisted-pair link to a full-
duplex Ethernet switching hub. This feature not only increases the channel
bandwidth from 10 to 20 Mbps but also avoids the performance degrading
problem due to the channel contention characteristics of the Ethernet CSMA/CD
protocol.
5-4
LEDS1-0 These two bits select the outputs to LED2-0 pins.
LEDS0
LED0 Pin
LED_COL
LED_LINK
0
1
LEDS1
LED1 Pin
LED2 Pin
0
1
LED_RX
LED_CRS
LED_TX
MCSB
Please refer to section 6.5 for the behavior of LEDs.
The MCSB signal is defined to put the local buffer SRAM into standby mode
while DMA is not in progress and thus save powers.
3
2
-
Reserved. Must not write a 1 to this bit.
This bit, when set, puts RTL8019 into sleep mode.
SLEEP
In sleep mode, all LED signals (P.S. MCSB is not an LED signal) except
LEDBNC are forced high to turn off the LEDs. The RTL8019 still handles the
network transmission and reception like in normal mode. The LEDBNC is not
affected by this bit.
This bit's power-up initial value is 0 and can be modified by software when
EEM1=EEM0=1.
1
PWRDN This bit , when set, puts RTL8019 into power down mode.
RTL8019 supports two kinds of power down modes, which is selected by the
contents of the HLTCLK register:
(1) mode 1: power down with clock running
(2) mode 2: power down with clock halted
In both power down modes, the RTL8019's serial network interface and
transceiver are turned off. All network activities are ignored.
All LED signals except LEDBNC are forced high. The LEDBNC is forced low to
disable the DC convertor for coaxial transceiver.
In power down mode2, the RTL8019 stops its internal clock for minimal power
consumption. Registers except HLTCLK are typically not accessible in this mode.
This bit's initial value comes from 9346 and can be modified if EEM1=EEM0=1
in 9346CR register.
0
ACTIVEB This bit is the inverse of bit 0 in PnP Activate register (index 30H).
When RTL8019 is deactivated, all BROM memory read and I/O accesses to the
Group1 registers except the HLTCLK register are ignored.
The HLTCLK register and PnP logic work the same as when RTL8019 is active.
Note: The PnP logical device control register is the only way to activate
RTL8019. Therefore, the HLTCLK register is allowed to be written to prevent
RTL8019 from dying when it is inactive in the clock-halted power-down mode.
LS003.7
ADVANCE INFORMATION
RTL8019
CSNSAV: CSN Save Register (08H; Type=R)
This register is provided to backup the CSN assigned to the PnP CSN register.
HLTCLK: Halt Clock Register (09H; Type=W)
This is the only active one of Group1 registers when RTL8019 is inactivated.
Writing to this register is invalid if RTL8019 is not in power down mode. (i.e. If PWRDN bit in
CONFIG3 register is zero.)
The data written to this register determines the RTL8019's power down mode.
Data
52H (ASCII code of 'R')
48H (ASCII code of 'H')
Other values
Power Down Mode
Mode 1 - clock Running
Mode 2 - clock Halted
Ignored
INTR: Interrupt Register (0BH; Type=R)
This register reflects the ISA bus states of INT7-0 pins.
5.2. Group 2: Plug and Play (PnP) Registers
Auto-configuration Ports
Three 8-bit I/O ports are defined for the PnP read/write operations. They are called Auto-
configuration ports and are listed below.
Port Name
ADDRESS
Type
W
Location
279H (Printer status port)
WRITE_DATA
READ_DATA
W
R
A79H (Printer status port + 800H)
Relocatable in range 200H to 3FFH
The Plug and Play registers are accessed by first writing the address of the desired register, which is
called "Register Index" in the following paragraph, to the ADDRESS port, followed by a read of
data from the READ_DATA port or a write of data to the WRITE_DATA port. A write to the
ADDRESS port may be followed by any number of WRITE_DATA or READ_DATA accesses to
the same indexed register without the need to write to the ADDRESS port before each access.
The Address port is also the write destination of the initiation key, which will be described later.
Plug and Play Registers
The Plug and Play registers may be divided into card registers and logical device registers.
According to the Plug and Play specification, a PnP card may contain more than one logical
devices. The card registers are unique for each card. However, the logical device registers are
repeated for each logical device on the card. Furthermore, all card registers are card control
registers, while the logical device registers can be divided into logical device control registers and
configuration registers. Although an RTL8019 card contains only one logical device, the following
paragraph still depicts the Plug and Play registers by the same PnP categorizing method.
p.s. Those registers or bits not mentioned below are all read only with value=0.
5.2.1. Card Control Registers
LS003.7
ADVANCE INFORMATION
RTL8019
Index
Name
Type
Definition
00H
Set RD_DATA port
W
The location of the READ_DATA port is determined by writing
to this register. Bits[7:0] become ISA I/O read port address
bits[9:2]. Address bits[1:0] of the READ_DATA port are
always 1.
01H
02H
Serial Isolation
Config Control
R
A read to this register causes a PnP card in the Isolation state to
compare one bit of the card's serial ID. This process will be
described in more details in section 6.
W
Bit[0] - Reset command
Setting this bit will reset all logical devices and restore
configuration registers to their power-up values.
The CSN is preserved.
Bit[1] - Wait for Key command
Setting this bit makes the PnP card return to the
Wait for Key state. The CSN is preserved.
Bit[2] - PnP Reset CSN command
Setting this bit will reset the card's CSN to 0.
Both the CSN (index 06H) and CSNSAV (index F5H) registers
are reset.
Note that the hardware will automatically clear the bits and
there is no need for software to clear them.
03H
04H
Wake[CSN]
W
R
A write to this register will cause all cards that have a CSN that
matches the write data[7:0] to go from the Sleep state to either
the Isolation state if the write data for this command is zero or
the Config state if the write data is not zero.
A read from this register reads the next byte of resource data.
The Status register must be polled until bit[0] is set before this
register may be read.
Resource Data
Status
05H
06H
R
Bit[0] when set indicates it is okay to read the next data byte
from the Resource Data register.
Card Select Number
(CSN)
R/W
A write to this register sets a card's CSN. The CSN is a value
uniquely assigned to each ISA PnP card after the serial
identification process so that each card may be individually
selected during a Wake[CSN] command. The CSN value
written to this register will also be recorded to the CSNSAV
register located at PnP register index F5H and Group 1 Page3
offset 08H.
07H
Logical Device
Number
R
00H (Only one logical device in RTL8019).
LS003.7
ADVANCE INFORMATION
RTL8019
5.2.2. Logical Device Control Registers
Index
Name
Activate
Type
Definition
30H
R/W
For each logical device there is one Activate register that
controls whether or not the logical device is active on the ISA
bus. Bit[0], if set, activates the logical device. Before a logical
device is activated, I/O range check must be disabled.
31H
I/O Range Check
R/W
This register is used to perform a conflict check on the I/O port
range programmed for use by a logical device.
Bit[1] - This bt, when set, enables I/O range check.
I/O range check is only valid when the logical device is
inactive.
Bit[0] - If set, this bit forces the logical device to respond to I/O
reads of the logical device's assigned I/O range with a 55H
when I/O range check is in operation. If clear, the logical device
drives AAH.
5.2.3. Logical Device Configuration Registers
Memory Configuration Registers
Index
Name
Type
Definition
40H
BROM base address
bits[23:16]
R/W
Bits[23:20] & bit[17] are read only with values=0.
All other bits are read/write bits.
41H
42H
BROM base address
bits[15:0]
Memory Control
R/W
R
Bits[13:8] are read only with values=0.
All other bits are read/write bits.
00H. (Only 8-bit operation is supported for BROM)
Note: The BROM size of RTL8019 is determined by the 9346 contents but not the memory
configuration registers.
I/O Configuration Registers
Index
Name
Type
Definition
60H I/O base address bits[15:8]
R/W
Bits[15:10] are read only with values=0.
All other bits are read/write bits.
61H I/O base address bits[7:0]
R/W
Bits[4:0] are read only with values=0.
All other bits are read/write bits.
LS003.7
ADVANCE INFORMATION
RTL8019
Interrupt Configuration Registers
Index
Name
Type
Definition
70H
IRQ level
R/W
Read/write value indicating a selected interrupt level.
Bits[3:0] select which ISA interrupt level is used. One selects IRQ1,
fifteen selects IRQ15. IRQ0 is not a valid interrupt selection and
represents no interrupt selection.
71H
IRQ type
R
Read/Write value indicating which type of interrupt is used for the IRQ
selected above.
Bit[1] - Level, 1=high, 0=low
Bit[0] - Type, 1=level, 0=edge
For RTL8019, this register is read only with value=02H.
DMA Configuration Registers
Index
74H
75H
Name
Type
R
R
Definition
DMA channel select 0
DMA channel select 1
04H (indicating no DMA channel is needed)
04H (indicating no DMA channel is needed)
Vendor Defined Registers
Index
F0H
F1H
F2H
F3H
F4H
F5H
F6H
Name
CONFIG0
CONFIG1
CONFIG2
CONFIG3
-
Type
Definition
R
R
R
R
-
Direct mapping of the Page3 CONFIG0 register.
Direct mapping of the Page3 CONFIG1 register.
Direct mapping of the Page3 CONFIG2 register.
Direct mapping of the Page3 CONFIG3 register.
CSNSAV
Vendor Control
R
W
Direct mapping of the Page3 CSNSAV register.
Bit[2] - RT Reset CSN command
Setting this bit will reset the card's CSN in the CSN register
(index 06H) to 0.
The CSNSAV register is not affected.
This bit is cleared by hardware automatically.
6. Functional Descriptions
6.1. RTL8019 Configuration Modes
The RTL8019 supports 3 configuration modes: jumper, RT jumperless, and PnP.
JP Pin
High
Low
Low
Low
PNP Pin
PNP Bit in 9346
Configuration Mode
Jumper
Plug and Play (PnP)
Plug and Play (PnP)
RT Jumperless
*
High
*
*
*
1
0
Low
P.S. "*" denotes don't care.
LS003.7
ADVANCE INFORMATION
RTL8019
The RTL8019's resource configuration informations such as I/O base address, BROM memory
base address, and interrupt request line, etc., are stored in the CONFIG3-0 registers in Group1
Page3 as well as the PnP logical device configuration registers. Their power-up default values may
come from the states of jumper pins in jumper mode or the contents of 9346 in PnP and RT
jumperless mode. Their values can be modified by software via the logical device configuration
registers in all 3 modes. The update values will be recorded to the CONFIG3-0 registers, too. This
new configuration is only valid temporarily and will be lost after an auto-load command, an active
RSTDRV, or PC power off . Permanent changes of configuration must be done by changing the
jumper states or the contents of 9346. Note that the BROM size can not be modified temporarily.
The Plug and Play logic can work in all the three configuration modes except that an RT defined
initiation key, named RT initiation key, should be used instead of the PnP initiation key. In other
words, the RT initiation key is supported in all configuration modes while the PnP initiation key is
only supported in the PnP mode. By using the RT initiation key, the software can put RTL8019 to
the PnP Config state and access the logical device configuration registers even in the jumper and
RT jumperless modes.
The differences between the 3 configuration modes are shown in the following table.
Configuration Mode
Jumper
RT Jumperless
Plug and Play
Resource of Power-up Value
Supported Initiation Key
RT Initiation Key
RT Initiation Key
Jumper Pins
9346
9346
RT and PnP Initiation Key
Initial Values of CONFIG1-3 Registers after RSTDRV or Auto-load Command
CONFIG1
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
IOS2
Bit 1
IOS1
Bit 0
IOS0
jumper
9346
Mode
IRQEN IRQS2 IRQS1 IRQS0 IOS3
Jumper
RT Jumperless
Plug and Play
1
1
jumper jumper jumper jumper jumper jumper
9346
9346
9346
9346
9346
9346
CONFIG2
Bit 7
PL1
Bit 6
Bit 5
Bit 4
Bit 3
BS3
Bit 2
BS2
Bit 1
BS1
Bit 0
BS0
Mode
PL0 BSELB BS4
Jumper
RT Jumperless
Plug and Play
jumper jumper
0
0
jumper jumper jumper jumper
jumper
9346
9346
9346
9346
9346
9346
9346
CONFIG3
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Mode
PNP FUDUP LEDS1 LEDS0
-
-
-
SLEEP PWRDN ACTIVEB
Jumper
RT Jumperless
Plug and Play
0
0
1
9346
9346
9346
9346
9346
9346
0
0
9346
9346
9346
9346
6.2. Plug and Play
LS003.7
ADVANCE INFORMATION
RTL8019
6.2.1. Initiation Key
The Plug and Play logic is quiescent on power up and must be enabled by software. This is done by
a predefined series of writes (32 I/O writes) to the ADDRESS port, which is called the initiation
key. The write sequence is decoded by RTL8019. If the proper series of I/O writes is detected, then
the Plug and Play auto-configuration ports are enabled. The write sequence will be reset and must
be issued from the beginning if any data mismatch occurs. The exact sequence for the initiation key
is listed below in hexadecimal notation.
PnP Initiation Key
6A, B5, DA, ED, F6, FB, 7D, BE,
DF, 6F, 37, 1B, 0D, 86, C3, 61,
B0, 58, 2C, 16, 8B, 45, A2, D1,
E8, 74, 3A, 9D, CE, E7, 73, 39
RT Initiation Key
DA, 6D, 36, 1B, 8D, 46, 23, 91,
48, A4, D2, 69, 34, 9A, 4D, 26,
13, 89, 44, A2, 51, 28, 94, CA,
65, 32, 19, 0C, 86, 43, A1, 50
LS003.7
ADVANCE INFORMATION
RTL8019
6.2.2. Isolation Protocol
A simple algorithm is used to isolate each Plug and Play card. This algorithm uses the signals on the ISA bus
and requires lock-step operation between the Plug and Play hardware and the isolation software.
State
Isolation
Read from serial isolation register
yes
Get one bit from serial identifier
no
ID bit="1H"
Drive "55H"
on SD[7:0]
Leave SD [7:0]
in high-impedance
no
SD[1:0]="01"
yes
Wait for next read from serial isolation register
Leave SD [7:0]
in high impedance
Drive
"AAH" on
SD[7:0]
no
SD[1:0]="10"
yes
After I/O read completes
fetch next ID bit from
serial identifier
ID=0
other card ID=1
no
Read all 72 bits
from serial
identifier
State
Sleep
yes
One card
isolated
Figure 1. Plug and Play ISA Card Isolation Algorithm
LS003.7
ADVANCE INFORMATION
RTL8019
Serial Identifier
The key element of the Plug and Play isolation protocol is that each card contains a unique number,
named serial identifier. The serial identifier is a 72-bit unique, non-zero number composed of two
32-bit fields and an 8-bit checksum. The first 32-bit field is a vendor identifier. The other 32-bits
can be any value, for example, a serial number, part of a LAN address, or a static number, as long
as there will never be two cards in a single system with the same 64-bit number. The serial identifier
is accessed bit-serially by the isolation logic and is used to differentiate the cards.
Check-
sum
Serial Number
Vendor ID
Byte 0 Byte 3
Byte 2 Byte 1 Byte 0 Byte 3
Byte 2 Byte 1 Byte 0
7:0
7:0
7:0
7:0
7:0
7:0
7:0
7:0
7:0
Shift
Figure 2. Shifting of Serial Identifier
The shift order for all Plug and Play serial isolation and resource data is defined as bit[0], bit[1],
and so on through bit[7].
Hardware Protocol
The isolation protocol can be invoked by the Plug and Play software at any time. The initiation key
described earlier, puts all cards into configuration mode. The hardware on each card expects 72
pairs of I/O read accesses to the READ_DATA port. The card's response to these reads depends
on the value of each bit of the serial identifier which is being examined one bit at a time, in the
sequence shown in Figure 1.
If the current bit of the serial identifier is a "1", then the card will drive the data bus to 55H to
complete the first I/O read cycle. If the bit is "0", then the card puts its data bus driver into high
impedance. All cards in high impedance will check the data bus during the I/O read cycle to sense if
another card is driving SD[1:0] to "01". During the second I/O read, the card(s) that drove the
55H, will now drive a AAH. All high impedance card will check the data bus to sense if another
card is driving SD[1:0] to "10."
If a high impedance card sensed another card driving the data bus with the appropriate data during
both cycles, then that card ceases to participate in the current iteration of card isolation. Such
cards, which lose out, will participate in future iterations of the isolation protocol.
NOTE: During each read cycle, the Plug and Play hardware drives the entire 8-bit data bus,
but only checks the lower 2 bits.
If a card was driving the bus or if the card was in high impedance and did not sense another card
driving the bus, then it should prepare for the next pair of I/O reads. The card shifts the serial
identifier by one bit and uses the shifted bit to decide its response.
The above sequence is repeated for the entire 72-bit serial identifier.
LS003.7
ADVANCE INFORMATION
RTL8019
At the end of this process, one card remains. This card is assigned a handle referred to as the Card
Select Number (CSN) that will be used later to select the card. Cards which have been assigned a
CSN will not participate in subsequent iterations of the isolation protocol. Cards must be assigned a
CSN before they will respond to the other PnP commands.
It should be noted that the protocol permits the 8-bit checksum to be stored in non-volatile memory
on the card or generated by the on-card logic in real-time. The checksum algorithm is implemented
as a Linear Feedback Shift Register (LFSR), which is shown in Figure 3.
Vendor ID/
Serial number
7
0
6
4
0
3
1
2
0
1
1
0
0
5
1
Shift out
Read of Serial
Isolation register
1
Reset values
Figure 3. Checksum LFSR
The LFSR resets to 6AH upon receiving the Wake[CSN] command. The next shift value for the
LFSR is calculated as LFSR[1] XOR LFSR[0] XOR Serial Data. The LFSR is shifted right one bit
at the conclusion of each pair of reads to the Serial Isolation register. LFSR[7] is assigned the next
shift value described above.
After the first 64 pairs of reads of the Serial Isolation register, the LFSR will have the value of
serial identifier checksum.
Plug and Play cards must not drive the IOCHRDY signal during serial isolation. However, cards
may drive IOCHRDY at any other time.
Software Protocol
The Plug and Play software sends the initiation key to all Plug and Play cards to place them into
configuration mode. The software is then ready to perform the isolation protocol.
The Plug and Play software generates 72 pairs of I/O read cycles from the READ_DATA port. The
software checks the data returned from each pair of I/O reads for the 55H or AAH driven by the
hardware. If both 55H or AAH are read back, then the software assumes that the hardware had a
"1" bit in that position. All other results are assumed to be a "0".
During the first 64 bits, software generates a checksum using the received data. The checksum is
compared with the checksum read back in the last 8 bits of the sequence.
LS003.7
ADVANCE INFORMATION
RTL8019
There are two other special considerations for the software protocol. During an iteration, it is
possible that the 55H and AAH combination is never detected. It is also possible that the checksum
does not match. If either of these cases occur on the first iteration, it must be assumed that the
READ_DATA port is in conflict. If a conflict is detected, then the READ_DATA port is relocated.
The above process is repeated until a non-conflicting location for the READ_DATA port is found.
The entire range between 200H and 3FFH is available, however in practice it is expected that only
a few locations will be tried before software determines that no Plug and Play cards are present.
During subsequent iterations, the occurrence of either of these two special cases should be
interpreted as the absence of any further Plug and Play cards (i.e. the last card was found in the
previous iteration). This terminates the isolation protocol.
NOTE: The software must delay 1 msec prior to starting the first pair of isolation reads, and
must wait 250 msec between each subsequent pair of isolation reads. This delay gives the
ISA card time to access information from possibly very slow storage devices.
LS003.7
ADVANCE INFORMATION
RTL8019
6.2.3. Plug and Play Isolation Sequence
The Plug and Play isolation sequence is divided into four states: Wait for Key, Sleep, Isolation,
and Config states. The state transitions for the Plug and Play ISA card are shown below.
Power up
RSTDRV or
Reset command
Set CSN=0
Active Commands
State
no active
commands
Wait for Key
initiation key
State
Active Commands
Reset
Sleep
Reset CSN
Wait for Key
Wake [CSN]
(WAKE=0) AND (CSN=0)
(WAKE<>0) AND (WAKE=CSN)
Lose serial isolation OR
(WAKE<>CSN)
WAKE<>CSN
State
State
Active Commands
Active Commands
Reset
Reset
Reset CSN
Reset CSN
Wait for Key
Wake [CSN]
Resource Data
Status
Set CSN
Config
Wait for Key
Set RD_DATA Port
Serial isolation
Wake [CSN]
Set CSN
Isolation
Logical Device
I/O Range Check
Activate
Configuration Registers
NOTES:
1. CSN= Card Select Number
2. RSTDRV causes a state transition
from the current state to Wait for Key and sets all CSNs to zero
3. The Wait for Key command causes a state transition from the
current state to Wait for Key
4. The Reset CSN commands include PnP Reset CSN and RT Reset CSN commands.
The former sets all ISA PnP cards' CSNs to zero while the latter only sets RTL8019
PnP cards' CSNs to zero. Both commands do not cause a state transition.
Figure 4. Plug and Play ISA Card State Transitions
LS003.7
ADVANCE INFORMATION
RTL8019
On power up, all PnP cards detect RSTDRV, set their CSN to 0, and enter the Wait for Key state.
There is a required 2 msec delay from either a RSTDRV or a PnP Reset command to any Plug and
Play port access to allow a card to load initial configuration information from a non-volatile device,
which is 9346 for RTL8019.
Cards in the Wait for Key state do not respond to any access to their auto-configuration ports until
the initiation key is detected. Cards ignore all ISA access to their Plug and Play interface.
When the cards have received the initiation key, they enter the Sleep state. In this state, the cards
listen for a Wake[CSN] command with the write data set to 00H. This wake[CSN] command will
send all cards to the Isolation state and reset the serial identifier/resource data pointer to the
beginning.
The first time the cards enter the Isolation state it is necessary to set the READ_DATA port
address using the Set RD_DATA port command. The software should then verify the selected
READ_DATA port address is not in conflict with any other devices by the isolation protocol.
Next, 72 pairs of reads are performed to the Serial Isolation register to isolate a card as described
previously. If the checksum read from the card is valid, then this means one card has been isolated.
The isolated card remains in the Isolation state while all other cards have failed the isolation
protocol and have returned to the Sleep state. The CSN on this card is set to a unique number.
Writing this value causes this card to transition to the Config state. Sending a Wake[0] command
causes this card to transition back to Sleep state and all cards with a CSN value of zero to
transition to the Isolation state. This entire process is repeated until no Plug and Play cards are
detected.
6.2.4. Reading Resource Data
Each PnP card supports a resource data structure stored in a non-volatile device (e.g. 9346) to
describe the resources supported and those requested by the functions on the card. The Plug and
Play resource management software will arbitrate resources and setup the logical device
configuration registers according to the resource data.
Card resource data may only be read from cards in the Config state. A card may get to the Config
state by one of two different methods. A card enters the Config state in response to the card
"winning" the serial isolation protocol and having a CSN assigned. The card also enters the Config
state in response to receiving a Wake[CSN] command that matches the card's CSN.
As described above, all Plug and Play cards function as if their serial identifier and their resource
data both come from the same serial device. As also stated above, the pointer to the serial device is
reset in response to any Wake[CSN] command. This implies that if a card enters the Config state
directly in response to a Wake[CSN] command, the 9-byte serial identifier must be read first before
the card resource data is accessed. The Vendor ID and Unique Serial Number is valid; however, the
checksum byte, when read in this way, is not valid. A card that enters the Config state after the
isolation protocol has been run has already accessed all 72 bits of the serial identifier and the first
read of the Resource Data register will return resource data.
LS003.7
ADVANCE INFORMATION
RTL8019
Card resource data is read by first polling the Status register and waiting for bit[0] to be set. When
this bit is set it means that one byte of resource data is ready to be read from the Resource Data
register. After the Resource Data register is read, the Status register must be polled before reading
the next byte of resource data. This process is repeated until all resource data is read. The format of
resource data is described in the following section.
The above operation implies that the hardware is responsible for accumulating 8 bits of data in the
Resource Data register. When this operation is complete, the status bit[0] is set. When a read is
performed on the Resource Data register, the status bit[0] is cleared, eight more bits are shifted
into the Resource Data register, then the status bit[0] is set again.
6.3. 9346 Contents
The 9346 is a 1k-bit EEPROM. Although it is actually addressed by words, we list its contents by
bytes below for convenience.
Bytes
Contents
Comments
00H - 03H (4 bytes)
Power-up initial value of Page3 and PnP
logical device configuration registers
00H
01H
02H
03H
CONFIG1
CONFIG2
CONFIG3
Not used
04H - 11H (14 bytes)
NE2000 IDPROM
04H - 09H Ethernet ID 0-5
0AH - 11H Product ID 0-7
Ethernet node address
Assigned by card makers; negligible
12H - 1AH (9 bytes)
Plug and Play Serial Identifier
Plug and Play Resource Data
12H - 15H Vendor ID 0-3
16H - 19H Serial Number 0-3
1AH
Serial ID Checksum
1BH - 7FH (101 bytes)
Detail values of 9346 CONFIG1-3 bytes
Bit 7
Bit 6
IRQS2
PL0
Bit 5
IRQS1
*
Bit 4
IRQS0
BS4
Bit 3
IOS3
BS3
Bit 2
IOS2
BS2
Bit 1
IOS1
BS1
Bit 0
IOS0
BS0
CONFIG1
*
CONFIG2 PL1
CONFIG3 PNP
FUDUP LEDS1
LEDS0
*
*
PWRDN
ACTIVEB
P.S. '*' denotes don't care.
Example : Plug and Play Resource Data for RTL8019 (Total 73+5 bytes)
TAG
Plug and Play Version Number
Length: fixed
3 bytes
Item byte
0AH
PnP version
Vendor version
10H
10H
LS003.7
ADVANCE INFORMATION
RTL8019
TAG
TAG
ANSI Identifier String
Item byte
Length bits 7-0
Length bits 15-8
Identifier string
Length: variable
37 bytes
82H
22H
00H
'REALTEK PLUG & PLAY ETHERNET CARD', 00H
Logical Device ID
Item byte
Logical device ID0-3
Flag 0
Length: fixed 7 bytes
16H
4AH, 8CH, 80H, 19H
02H or 03H (use 03H when BROM is enabled)
00H
Flag 1
TAG
TAG
Compatible Device ID (NE2000 compatible) Length: fixed
5 bytes if given
Item byte
1CH
Compatible ID0-3
41H, D0H, 80H, D6H
I/O Format
Length: fixed
8 bytes
Item byte
I/O information
Min. I/O base bits 7-0
Min. I/O base bits 15-8
Max. I/O base bits 7-0
47H
00H
20H
02H
80H
Max. I/O base bits 15-8 03H
Base alignment
Range length
20H
20H
TAG
TAG
IRQ Format
Item byte
IRQ mask bits 7-0
IRQ mask bits 15-8
IRQ information
Length: fixed
Length: fixed
4 bytes
23H
38H
9EH
01H
Memory Format (optional)
Item byte
Length bits 7-0
12 bytes
81H
09H
00H
40H
00H
0CH
C0H
0DH
00H
This example uses 16k-byte BROM.
Length bits 15-8
Memory information
Min. base bits 15-8
Min. base bits 23-16
Max. base bits 15-8
Max. base bits 23-16
Base alignment bits 7-0
Base alignment bits 15-8 40H
Range length bits 15-8 40H
Range length bits 23-16 00H
TAG
END Tag
Length: fixed
2 bytes
Item byte
79H
Checksum
2's complement of the sum of all the above resource data
i.e. 2's complement of (0AH+10H+10H+.......+79H)
LS003.7
ADVANCE INFORMATION
RTL8019
6.4. Local Memory Bus Control
The local memory bus of RTL8019 is shared by the SRAM, BROM & 9346 EEPROM.
The following diagram demonstrates their connection relationship.
9346
EESK
EEDI
EEDO
MA3-1
EECS
EECS
RTL8019
8K SRAM#1
MD7-0
A12-0
D7-0
MA13-2
MA1
MA0
MA13-1
MD7-0
MRDB
MWRB
EECS
MCSB
BCSB
MRDB
MWRB
VCC
OE
WE
CS2
CS1
MA0
BROM
8K SRAM#2
D7-0
CE
A12-0
D7-0
A21-14
MD7-0
BCSB
MA11-4
MA13-1
MD7-0
MRDB
OE
MWRB
WE
CS2
CS1
OE
MA0
EECS or MCSB
32K SRAM
MA13-1
A12-0
D7-0
MD7-0
MRDB
OE
WE
A13
CS
MWRB
MA0
EECS or MCSB
Figure 5. Local Memory Bus Block Diagram
LS003.7
ADVANCE INFORMATION
RTL8019
The access control of local memory bus is depicted in the following table.
Note : 1.Combinations not listed in the table will never happen.
2.'BUS' indicates the device owns the local memory bus.
3.'EN' indicates the device is active (enabled) but not driving the local memory data bus.
4.'DIS' indicates the device is in standby mode (disabled).
5.Using MCSB instead of EECS for SRAM may reduce up to 40ma power consumption
in idle state.
(1) MCSB is not used
MCSB BCSB EECS MA0 MWRB MRDB BROM 9346
SRAM
Comments
8K#1 8K#2
32K
EN
EN
-
-
-
-
-
-
-
L
H
H
H
H
H
H
L
L
H
L
L
L
L
H
H
H
L
H
L
H
H
H
H
H
L
H
H
H
L
L
*
BUS
DIS
DIS
DIS
DIS
DIS
DIS
DIS
DIS
BUS
DIS
DIS
DIS
DIS
DIS
DIS
DIS
BUS
DIS
BUS
DIS
EN
EN
read BROM
idle
DIS
DIS
BUS
DIS
BUS
DIS access 9346
BUS read SRAM#1
BUS read SRAM#2
BUS write SRAM#1
BUS write SRAM#2
H
L
*
(2) MCSB is used
MCSB BCSB EECS MA0 MWRB MRDB BROM 9346
SRAM
8K#1 8K#2
Comments
32K
H
H
H
L
L
L
L
L
H
H
H
H
H
H
L
L
H
L
L
L
L
H
H
H
L
H
L
H
H
H
H
H
L
H
H
H
L
L
*
BUS
DIS
DIS
DIS
DIS
DIS
DIS
DIS
DIS
BUS
DIS
DIS
DIS
DIS
DIS
DIS
DIS
BUS
DIS
BUS
DIS
DIS
DIS
DIS
DIS
BUS
DIS
BUS
DIS read BROM
DIS idle
DIS access 9346
BUS read SRAM#1
BUS read SRAM#2
BUS write SRAM#1
BUS write SRAM#2
H
L
*
6.5. LED Behaviors
This section describes the lighting behaviors of the LED output signals which may be selected by
LEDS1 and LEDS0 bits in the Page3 CONFIG3 register.
P.S. It is assumed that the LED is on when the signal goes low.
LS003.7
ADVANCE INFORMATION
RTL8019
(1) LED_TX: Tx LED
Power On
LED=low
No
Transmitting Packet?
Yes
+
LED=high for (100 10) ms
+
LED=low for (6 2) ms
(2) LED_RX: Rx LED
Power On
LED=low
No
Receiving Packet?
Yes
+
LED=high for (100 10) ms
+
LED=low for (6 2) ms
LS003.7
ADVANCE INFORMATION
RTL8019
(3) LED_CRS=LED_TX+LED_RX: Carrier Sense LED
Power On
LED=low
No
Tx or Rx Packet?
Yes
+
LED=high for (100 10) ms
+
LED=low for (6 2) ms
(4) LED_COL: Collision LED
Power On
LED=high
No
Collision (except Heartbeat)?
Yes
+
LED=low for (10 5) ms
LS003.7
ADVANCE INFORMATION
RTL8019
LED Output States in Power Down Modes
LED Output
LEDBNC
LED_LINK
LED_COL
LED_TX
Normal Mode / Idle
Sleep Mode
-
Power Down Mode
-
-
Low
High
High
High
High
High
High
High
High
High
High
High
Low
Low
Low
LED_RX
LED_CRS
6.6. Loopback Diagnostic Operation
6.6.1. Loopback operation
The RTL8019 provides 3 loopback modes. By loopback test, we can verify the integrity of data
path, CRC logic, address recognition logic and cable connection status.
Mode 1: Loopback through the NIC (LB1=0, LB0=1 in TCR).
The NRZ data is not transmitted to the SNI but instead it's loopbacked to the NIC's Rx
deserializer. The traffic on the cable is ignored.
NIC
8390
SNI
83910
Ref:
Mode 2: Loopback through the SNI (LB1=1, LB0=0 in TCR)
The Manchester encoded data is not transmitted to the MAU. It's loopbacked through
the SNI to NIC. The traffic on the cable is ignored.
MAU
8392/RTL8005
NIC
8390
SNI
83910
Ref:
Mode 3: Loopback through the cable (LB1=1, LB0=1 in TCR)
The packets are transmitted via the MAU onto the network and RTL8009 receives all
incoming packets (not only the MAU-loopbacked Tx data) in the meantime.
CABLE
NIC
8390
SNI
83910
MAU
8392/RTL8005
Ref:
LS003.7
ADVANCE INFORMATION
RTL8019
q Alignment of the Reception FIFO
The reception FIFO is an 8-byte ring structure. The first received byte is put at location zero.
When the location pointer goes to the end of the FIFO, it wraps to the beginning of the FIFO and
overwrites the previous data. At the end of the packet reception, the FIFO contents are in the
"order" (from the ring structure's view) as shown below.
(1) CRC enabled (CRC bit in TCR=0)
s 1-byte received packet data
s 4-byte CRC
s 1-byte lower byte count
s 1-byte upper byte count
s 1-byte upper byte count
(2) CRC disabled (CRC bit in TCR=1)
s 5-byte received packet data
s 1-byte lower byte count
s 1-byte upper byte count
s 1-byte upper byte count
6.6.2. To Implement Loopback Test
(1) To verify the integrity of data path
s set RCR=00h to accept physical packet
s set PAR0-5 to accept packet
s set DCR=40h (8-bit slot) or 43h (16-bit slot)
s set TCR=02h, 04h, 06h to do loopback test 1, 2, 3 respectively
s set CRC enabled (CRC=0 in TCR)
s clear ISR
s tx a packet and check ISR
s check FIFO after loopback
Note: Loopback mode 3 is sensitive to the network traffic, so the values of FIFO may be not
correct.
(2) To verify CRC logic
q Select a loopback mode (e.g. mode 2) to test
A. To test CRC generator
s set RCR=00h to accept physical packet
s set PAR0-5 to accept packet
s set TCR=04h (CRC enabled)
s set DCR=40h (8-bit slot) or 43h (16-bit slot)
s clear ISR
s tx a packet
s check CRC bytes in FIFO after loopback
LS003.7
ADVANCE INFORMATION
RTL8019
B. To test CRC checker
s set RCR=00h to accept physical packet
s set PAR0-5 to accept packet
s set TCR=05h (CRC disabled)
s set DCR=40h (8-bit slot) or 43h (16-bit slot)
s clear ISR
s tx a packet with good or bad CRC appended by program
s check FIFO, ISR & RSR after loopback
For bad CRC, expected: ISR=06h, RSR=02h (Tx: OK, Rx:CRC error)
For good CRC, expected: ISR=02h, RSR=01h (Tx:OK, Rx: OK)
Note: In loopback mode, the received packets are not stored to SRAM, so PRX bit in ISR isn't set.
(3) To verify the address recognition function
q Select a loopback mode (e.g. mode 2) to test
A. Right physical destination address
s set RCR=00h to accept physical packet
s set PAR0-5 to accept packet
s set TCR=04h (CRC enabled)
s set DCR=40h (8-bit slot) or 43h (16-bit slot)
s clear ISR
s tx a packet
s check ISR after loopback
Expected: ISR=06h (packets accepted, Rx CRC error)
B. Wrong physical destination address
s set RCR=00h to accept physical packet
s set PAR0-5 to reject packet
s set TCR=04h (CRC enabled)
s set DCR=40h (8-bit slot) or 43h (16-bit slot)
s clear ISR
s tx a packet
s check ISR after loopback
Expected: ISR=02h (packets rejected, Rx no response)
LS003.7
ADVANCE INFORMATION
RTL8019
(4) To Test Cable Connection
q There are four physical medium types in RTL8019.
We perform loopback mode 3 to test the cable connection status.
s set RCR=00h to accept physical packet
s set PAR0-5 to accept packet
s set TCR=06h (CRC enabled)
s set DCR=40h (8-bit slot) or 43h (16-bit slot)
s clear ISR
s tx a packet
s check TSR after loopback
A. 10Base2
If cable OK, get TSR=03h (Tx OK).
If cable FAIL, get TSR=0Eh (Collision and Tx aborted).
B. 10Base5
If cable OK, get TSR=03h (Tx OK).
If MAU connected but cable FAIL, get TSR=0Eh (Tx collision and Tx aborted).
If MAU not connected, get TSR=53h (Carrier sense is lost during transmission and CD heartbeat
fails.).
C. 10BaseT with link test disabled
RTL8019 disables link test in this case, so cable OK or FAIL doesn't affect TSR; get TSR=03h.
D. Auto-detection (10BaseT with link test enabled)
RTL8019 automatically switches from 10BaseT to 10Base 2 if the twisted-pair wire is not
connected (10BaseT link test fails).
If twisted-pair wire OK, get TSR=03h (Tx OK) & BNC=0 in CONFIG2
If twisted-pair wire FAIL but coaxial cable OK, get TSR=03h (Tx OK) & BNC=1 in CONFIG2
Otherwise, get TSR=0Eh (same as 10Base2 connection fail).
LS003.7
ADVANCE INFORMATION
RTL8019
7. Electrical Specifications and Timings
7.1. Absolute Maximum Ratings
Operating Temperature ........................................................................................... 0 to 70
Storage Temperature .............................................................................................. -65 to
140
All Outputs and Supply Voltages, with respect to Ground ........................................ -0.5V to 7V
Power Dissipation ..................................................................................................
Warning:
Stresses beyond those listed under "Absolute Maximum Ratings" may cause permanent damage to
the device. These are stress ratings only.
Functionality at or above these limits is not recommended and extended exposure to "Absolute
Maximum Ratings" may affect device reliability.
+
7.2. D.C. Characteristics (Tc=0 to 70 , Vcc=5V 5%)
Symbol
Vil
Parameter
Input Low Voltage
Min.
2.0
Typ.
Max.
Unit
V
Conditions
0.8
Vih
Input Low Voltage
V
Vol1
Voh1
Vol2
Voh2
Vol3
Output Low Voltage 1
Output High Voltage 1
Output Low Voltage 2
Output High Voltage 2
Output Low Voltage 3
0.4
3.5
0.4
4.0
0.6
0.6
V
Iol=16mA, Note 1
Ioh=8mA, Note 1
Iol=4mA, Note 2
Ioh=4mA, Note 2
Iol=24mA, Note 3
3.0
V
V
3.5
V
0.6
150
10
V
Rpull-low Internal Pull-Low Resistance
II Input Leakage Current
50
100
KW
mA
-10
Note 1: Apply only to INT7 ~ INT0, SD15 ~ SD0.
Note 2: Apply only to MD7 ~ MD0, MA13 ~ MA0, LED Pins, EECS, MWRB, MRDB, BCSB.
Note 3: Apply only to IOCHRDY, IOCS16B
LS003.7
ADVANCE INFORMATION
RTL8019
7.3. A.C. Timing Characteristics
(1) ISA I/O Read/Write
AEN
SA0-11
T2
T1
IOCS16B
IORB,
IOWB
T3
IOCHRDY
T6
T5
T4
SD0-15 (read)
T8
T7
SD0-15 (write)
Symbol
T1
Parameter
Min.
Typ.
20
Max.
Unit
ns
Host address valid to IOCS16B low
Host address invalid to IOCS16B high
T2
30
ns
T3
IOCHRDY goes low from falling edge of
IORB or IOWB when wait state insertion is
needed.
50
50
ns
T4
T5
Read data valid from falling edge of IORB or
IOWB when no wait state insertion is needed.
50
ns
ns
Read data valid to IOCHRDY high when wait
state is needed
25
T6
T7
T8
Read data hold after IORB rising edge
Write data setup to IOWB rising edge
Write data hold from IOWB rising edge
10
10
10
30
10
10
30
ns
ns
ns
LS003.7
ADVANCE INFORMATION
RTL8019
(2) SRAM Read/Write
T1
T1
20MHz
MA13-1
MA0
BCSB
EECS
MCSB
T3
T2
MRDB or
MWRB
T4
T5
MD7-0
(read)
T7
T6
MD7-0
(write)
Symbol
Parameter
SRAM access cycle (1 byte)
Min.
Typ.
100
25
Max.
Unit
ns
T1
T2
MA13-0,MCSB ready to MRDB or MWRB
goes low
ns
T3
T4
T5
T6
T7
MRDB or MWRB low width
50
ns
ns
ns
ns
ns
Read data setup to MRDB high
5
5
Read data hold from MRDB rising edge
Write data setup to MWRB rising edge
Write data hold from MWRB rising edge
75
25
LS003.7
ADVANCE INFORMATION
RTL8019
(3) BROM Read
SA19-0
SMEMRB
T1
T3
T2
IOCHRDY
BA14-21
T5
T4
T6
T7
BCSB
SD7-0
Symbol
Parameter
Min.
Typ.
Max.
Unit
ns
T1
T2
T3
T4
T5
T6
T7
SMEMRB low to IOCHRDY low
IOCHRDY low width
30
200
ns
SMEMRB low to BA14-21 valid
SMEMRB low to BCSB valid
30
30
30
30
30
ns
ns
BA14-21 hold from SMEMRB rising edge
BCSB hold from SMEMRB rising edge
Read data hold from SMEMRB rising edge
ns
ns
ns
LS003.7
ADVANCE INFORMATION
RTL8019
(4) Serial EEPROM (9346) Auto-load
EESK
EECS
EEDI
0
0
0
0
A0
A2 A1
1
1
EEDO
D1 D0
D15 D14
T1
T4
T2
EESK
T3
T5
EEDI
T6
EECS
EEDO
T7
T8
Symbol
Parameter
Min.
Typ.
Max.
Unit
T1
T2
T3
T4
T5
T6
T7
T8
EESK high width
EESK low width
3.2
3.2
ms
ms
ms
ms
ms
ns
ns
ns
EEDI setup to EESK rising edge
EEDI hold from EESK rising edge
3.0
3.0
3.0
EECS goes high to EESK rising edge
EECS goes low from EESK falling edge
EEDO setup to EESK falling edge
EEDO hold from EESK falling edge
0
20
10
REALTEK Semiconductor Co., Ltd. reserved all rights of this document. No part of this
document may be copied or reproduced in any form or by any means or transferred to any third
party without the prior written consent of REALTEK Semiconductor Co., Ltd. REALTEK
reserves the right to change products or specifications without notice. This document has been
carefully checked and is believed to be accurate. However REALTEK Semiconductor Co., Ltd.
assumes no responsibility for inaccuracies.
LS003.7
ADVANCE INFORMATION
RTL8019
Note:
Symbol Dimension in
mil
Dimension in
mm
1.Dimension D & E do not include interlead flash.
2.Dimension b does not include dambar protrusion/intrusion.
3.Controlling dimension: Millimeter
4.General appearance spec. should be based on final visual
inspection spec.
Min Typ Max Min Typ Max
106.3 118.1 129.9 2.70
4.3 20.1 35.8 0.11
102.4 112.2 122.0 2.60
7.1 11.8 16.5 0.18
1.6 5.9 10.2 0.04
541.3 551.2 561.0 13.75
777.6 787.4 797.2 19.75
19.7 25.6 31.5 0.50
726.4 740.2 753.9 18.45
962.6 976.4 990.2 24.45
39.4 47.2 55.1 1.00
88.6 94.5 104.3 2.25
3.9
3.30
0.91
3.10
0.42
0.26
14.25
20.25
0.80
19.15
25.15
1.40
2.65
0.10
12°
A
A1
A2
b
3.00
0.51
2.85
0.30
0.15
14.00
20.00
0.65
18.80
24.80
1.20
c
TITLE : 100L QFP ( 14x20 mm**2 ) FOOTPRINT 4.8 mm
PACKAGE OUTLINE DRAWING
D
E
e
LEADFRAME MATERIAL:
APPROVE
DWG NO.
REV NO.
SCALE
HD
HE
L
L1
y
CHECK
Ricardo Chen DATE
SHT NO. 1 OF
REALTEK SEMI-CONDUCTOR CO., LTD
2.40
0°
12°
0°
LS003.7
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