RTL8139C_PLUS_技术文档

RTL8139C(L)+

REALTEK 3.3V SINGLE CHIP

FAST ETHERNET CONTROLLER

WITH POWER MANAGEMENT

RTL8139C(L)+

6.32 Transmit Priority Polling Register (TPPoll) ...... 38

6.33 C+ Command Register (C+CR)......................... 38

6.34 Receive Descriptor Start Address Register (RDSAR)... 39

6.35 Early Transmit Threshold Register (ETThR) .... 39

6.36 Function Event Register..................................... 40

6.37 Function Event Mask Register........................... 41

6.38 Function Present State Register ......................... 42

6.39 Function Force Event Register/MII Register............. 43

7. EEPROM Contents................................................... 44

7.1 Summary of EEPROM Registers......................... 46

7.2 Summary of EEPROM Power Management Registers 46

8. PCI Configuration Space Registers......................... 47

8.1 PCI Bus Interface................................................. 47

8.1.1 Byte Ordering............................................... 47

8.1.2 Interrupt Control........................................... 47

8.1.3 Latency Timer .............................................. 47

8.1.4 32-Bit Data Operation .................................. 48

8.1.5 64-Bit Addressing ........................................ 48

8.2 Bus Operation ...................................................... 48

8.2.1 Target Read .................................................. 48

8.2.2 Target Write ................................................. 49

8.2.3 Master Read.................................................. 50

8.2.4 Master Write................................................. 51

8.2.5 Configuration Access ................................... 51

8.3 Packet Buffering .................................................. 51

8.3.1 Transmit Buffer Manager............................. 52

8.3.2 Receive Buffer Manager .............................. 52

8.3.3 Packet Recognition....................................... 52

8.4 PCI Configuration Space Table ........................... 53

8.5 PCI Configuration Space Functions..................... 55

8.6 TheDefaultValueAfterPower-on(RSTBasserted)...... 59

8.7 PCI Power Management Functions...................... 60

8.8 Vital Product Data (VPD).................................... 62

9. Functional Description ............................................. 63

9.1 Transmit & Receive Operations in C mode ......... 63

9.1.1 Transmit........................................................ 63

9.1.2 Receive......................................................... 63

9.2 Transmit & Receive Operations in C+ mode....... 63

9.2.1 Transmit........................................................ 64

9.2.2 Receive......................................................... 70

9.3 Line Quality Monitor ........................................... 73

9.4 Clock Recovery Module ...................................... 73

9.5 Loopback Operation............................................. 73

9.6 Tx Encapsulation with the Internal PHYceiver............ 73

1. Features........................................................................ 3

2. General Description.................................................... 4

3. Block Diagram............................................................. 5

4. Pin Assignments .......................................................... 6

5. Pin Descriptions .......................................................... 7

5.1 Power Management/Isolation Interface ................. 7

5.2 PCI Interface .......................................................... 8

5.3 FLASH/BootPROM/EEPROM/MII Interface ..... 10

5.4 Power Pins ........................................................... 11

5.5 LED Interface....................................................... 11

5.6 Attachment Unit Interface.................................... 12

5.7 Test and Other Pins.............................................. 12

6. Register Descriptions................................................ 13

6.1 Receive Status Register in Rx Packet Header...... 15

6.2 Transmit Status Register ...................................... 16

6.3 Dump Tally Counter Command Register (DTCCR)... 17

6.4 ERSR: Early Rx Status Register .......................... 18

6.5 Command Register............................................... 18

6.6 Interrupt Mask Register ....................................... 19

6.7 Interrupt Status Register....................................... 20

6.8 Transmit Configuration Register.......................... 21

6.9 Receive Configuration Register ........................... 22

6.10 9346CR: 93C46 (93C56) Command Register ... 25

6.11 Configuration Register 0 (CONFIG 0) .............. 25

6.12 Configuration Register 1 (CONFIG 1) .............. 26

6.13 Media Status Register ........................................ 27

6.14 Configuration Register3 (CONFIG 3) ............... 28

6.15 Configuration Register4 (CONFIG 4) ............... 29

6.16 Multiple Interrupt Select Register...................... 30

6.17 PCI Revision ID................................................. 30

6.18 Transmit Status of All Descriptors Register (TSAD).. 30

6.19 Basic Mode Control Register............................. 31

6.20 Basic Mode Status Register ............................... 32

6.21 Auto-negotiation Advertisement Register.......... 33

6.22 Auto-Negotiation Link Partner Ability Register ... 34

6.23 Auto-negotiation Expansion Register ................ 34

6.24 Disconnect Counter............................................ 35

6.25 False Carrier Sense Counter............................... 35

6.26 NWay Test Register........................................... 35

6.27 RX_ER Counter................................................. 35

6.28 CS Configuration Register................................. 36

6.29 Low Address of a Tx Descriptor with Tx DMA Ok 36

6.30 Flash Memory Read/Write Register (FLASH) .. 36

6.31 Configuration Register 5 (Config5) ................... 37

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RTL8139C(L)+

9.7 Collision............................................................... 73

9.8 Rx Decapsulation with the Internal PHYceiver ........... 74

9.9 Flow Control ........................................................ 74

9.9.1. Control Frame Transmission ....................... 74

9.9.2. Control Frame Reception............................. 74

9.10 Medium Auto-Detect ......................................... 75

9.11 Cable Connection Status .................................... 75

9.11 Cable Connection Status .................................... 76

9.12 MII Redundant Link........................................... 77

9.13 Memory Functions ............................................. 78

9.13.1 Memory Read Line (MRL)......................... 78

9.13.2 Memory Read Multiple (MRM) ................. 78

9.13.3 Memory Write and Invalidate (MWI) ........ 79

9.13.4 Dual Address Cycle (DAC)........................ 79

9.14 LED Functions................................................... 80

9.14.1 10/100 Mbps Link Monitor ........................ 80

9.14.2 LED_RX..................................................... 80

9.14.3 LED_TX..................................................... 81

9.14.4 LED_TX+LED_RX ................................... 81

9.15 Physical Layer Interfaces................................... 82

9.15.1 Media Independent Interface (MII)............ 82

9.15.2 MII Management Interface......................... 82

10. Application Diagram .............................................. 83

11. Electrical Characteristics....................................... 84

11.1 Temperature Limit Ratings ................................ 84

11.2 DC Characteristics ............................................. 84

11.2.1 Supply Voltage........................................... 84

11.3 AC Characteristics ............................................. 85

11.3.1 FLASH/BOOT ROM Timing..................... 85

11.3.2 PCI Bus Operation Timing......................... 87

11.3.3 MII Timing................................................. 94

12. Mechanical Dimensions.......................................... 98

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Rev.1.5

RTL8139C(L)+

1. Features

ꢀ

128 pin QFP/LQFP (pin-to-pin compatible with the ꢀ Supports 25MHz crystal or 25MHz OSC as the internal

RTL8139C(L))

clock source. The frequency deviation of either crystal or

OSC must be within 50 PPM

Software compatible to the RTL8139 series when

configured in RTL8139C mode (C mode)

ꢀ

Compliant to PC99 and PC2001 standards

Supports descriptor-based buffer management when ꢀ Supports Wake-On-LAN function and remote wake-up

configured in RTL8139C+ mode (C+ mode)

Supports Microsoft* NDIS5 Checksum Offloads (IP,

TCP, UDP), and Largesend Offload in C+ mode

Supports IEEE802.1Q VLAN tagging in C+ mode

Supports Transmit (Tx) Priority Queue for QoS, CoS

applications in C+ mode

Integrated Fast Ethernet MAC, PHY and transceiver in

one chip

10Mbps and 100Mbps operation

(Magic Packet*, LinkChg and Microsoft wake-up

frame)

Supports 4 Wake-On-LAN (WOL) signals (active high,

active low, positive pulse, and negative pulse)

Supports auxiliary power-on internal reset, to be ready

for remote wake-up when main power still remains off

Supports auxiliary power auto-detect, and sets the

related capability of power management registers in PCI

configuration space

Includes a programmable, PCI burst size and early

Tx/Rx threshold

Supports a 32-bit general-purpose timer with the

external PCI clock as clock source, to generate

timer-interrupt

Contains two large (2Kbyte) independent receive (Rx)

and transmit (Tx) FIFOs

Advanced power saving mode when LAN function or

wakeup function is not used

Uses 93C46 (64*16-bit EEPROM) or 93C56

(128*16-bit EEPROM) to store resource configuration,

ID parameter, and VPD data. The 93C56 can also be

used to store the CIS data structure for the CardBus

application

Supports LED pins for various network activity

indications

Supports digital and analog loopback capability on both

ports

Half/Full duplex capability

ꢀ

Supports

10Mbps

and

100Mbps

N-way

Auto-negotiation operation

ꢀ

PCI local bus single-chip Fast Ethernet controller

ꢁ

Compliant to PCI Revision 2.2

Supports PCI clocks 16.75MHz-40MHz

Supports PCI target fast back-to-back transaction

Supports Memory Read Line, Memory Read

Multiple, Memory Write and Invalidate, and

Dual Address Cycle, when set to C+ mode.

ꢀ

ꢁ

Provides PCI bus master data transfers and PCI

memory space or I/O space mapped data

transfers of the RTL8139C(L)+'s operational

registers

ꢀ

ꢁ

Supports PCI VPD (Vital Product Data)

Supports ACPI, PCI power management

Supports optional PCI multi-function with

additional function in slave mode only.

ꢀ

Supports CardBus. The CIS can be stored in the 93C56

or expansion ROM

Supports either MII or Boot ROM interface, though

only one interface can be implemented at a time. Up to

128K byte Boot ROM interface for both EPROM and

Flash memory can be supported

Supports Full Duplex Flow Control (IEEE 802.3x)

3.3V power supply with 5V tolerant I/Os

* Third-party brands and names are the property of their

respective owners.

Note: The model number of the QFP package is RTL8139C+. The LQFP package model number is RTL8139CL+.

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RTL8139C(L)+

2. General Description

The Realtek RTL8139C(L)+ is a highly integrated and cost-effective single-chip Fast Ethernet controller that provides 32-bit

performance, PCI bus master capability, and full compliance with IEEE 802.3u 100Base-T specifications and IEEE 802.3x Full

Duplex Flow Control. It also supports Advanced Configuration Power management Interface (ACPI), PCI power management

for modern operating systems that is capable of Operating System Directed Power Management (OSPM) to achieve the most

efficient power management. The RTL8139CL+ is suitable for applications such as CardBus or mobile with built-in network

controller. The CIS data can be stored in either the 93C56 EEPROM or an external expansion ROM.

In addition to the ACPI feature, the RTL8139C(L)+ also supports remote wake-up (including AMD Magic Packet, LinkChg,

and Microsoft wake-up frame) in both ACPI and APM environments. The RTL8139C(L)+ is capable of performing an internal

reset through the application of auxiliary power. When auxiliary power is on and the main power remains off, the

RTL8139C(L)+ is ready and waiting for the Magic Packet or Link Change to wake the system up. Also, the LWAKE pin

provides 4 different output signals including active high, active low, positive pulse, and negative pulse. The versatility of the

RTL8139C(L)+ LWAKE pin provides motherboards with the Wake-On-LAN (WOL) function. The RTL8139C(L)+ also

supports Analog Auto-Power-down, that is, the analog part of the RTL8139C(L)+ can be shut down temporarily according to

user requirements or when the RTL8139C(L)+ is in a power down state with the wakeup function disabled. In addition, when the

analog part is shut down and the IsolateB pin is low (i.e. the main power is off), then both the analog and digital parts stop

functioning and power consumption of the RTL8139C(L)+ will be negligible. The RTL8139C(L)+ also supports an auxiliary

power auto-detect function, and will auto-configure related bits of their own PCI power management registers in PCI

configuration space.

The PCI Vital Product Data (VPD) is also supported to provide the information that uniquely identifies hardware (i.e., the

RTL8139C(L)+ LAN card). The information may consist of part number, serial number, and other detailed information.

In order to provide a lower cost system, the RTL8139C(L)+ is capable of using a 25MHz crystal as its internal clock source. A

25MHz OSC can also be used.

There are 2 modes of buffer management modes which are supported by the RTL8139C(L)+. The first, C mode, is just like the

buffer management algorithm which former RTL8139 series products use; the second is C+ mode (set only by software to the

relative C+ mode registers and descriptors) which is an enhanced descriptor-based design especially suitable for server

applications. The RTL8139C(L)+ is hardware compatible to the RTL8139C(L), and is software backwards compatible to the

RTL8139 series when set to C mode (the default setting). The RTL8139C(L)+ can be configured by software to apply a new

buffer management algorithm, i.e., enhanced descriptor-based buffer management architecture, which is an essential design as a

modern network server card.

The RTL8139C(L)+ fully complies to Microsoft NDIS5 (IP, TCP, UDP) Checksum and Segmentation Task-offload features,

and supports IEEE802.1Q VLAN (Virtual Bridged Local Area Network). All of the above RTL8139C(L)+ new features

contribute to lower CPU utilization, which is a plus when serving as a network server card. Also, the RTL8139C(L)+ boosts its

PCI performance by supporting PCI Memory Read Line & Memory Read Multiple when transmitting, Memory Write and

Invalidate when receiving. To be better qualified as a server card, the RTL8139C(L)+ also supports the PCI Dual Address Cycle

(DAC) command, when the assigned buffers reside at the physical memory addresses higher than 4 Gigabytes. For QoS and CoS

requirements, the RTL8139C(L)+ supports hardware high priority queuing to reduce software implementation effort and

significantly improve performance.

The RTL8139C(L)+ keeps network maintenance costs low and eliminates usage barriers. It is the easiest way to upgrade a network

from 10 to 100Mbps. It also supports full-duplex operation, making 200Mbps of bandwidth possible at no additional cost. To

improve compatibility with other brands’ products, the RTL8139C(L)+ is also capable of receiving packets with InterFrameGap no

less than 40 Bit-Time. The RTL8139C(L)+ is highly integrated and requires no “glue” logic or external memory. It includes an

interface for a boot ROM and can be used in diskless workstations, providing maximum network security and ease of management.

For special applications, the RTL8139C(L)+ also supports an MII interface, which can be used, for example, to provide a redundant

link with an external PHYceiver, or a connection to a Fiber channel with a Fiber transceiver. Because of pin count limitation, the

RTL8139C(L)+ does not support a Boot ROM interface when the MII interface is used, and vice versa.

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RTL8139C(L)+

3. Block Diagram

MAC

Boot ROM

Interface

EEPROM

Interface

LED Driver

Power Control Logic

Early Interrupt

Threshold

Register

Interrupt

Control

Logic

Early Interrupt

Control Logic

PCI

Interface

Transmit/

FIFO

Control

Logic

Receive

Logic

FIFO

MII

Interface

PHY

100M

5B 4B

Decoder

Data

Alignment

RXD

Descrambler

RXC 25M

10/100

half/full

Switch

Logic

MII

Interface

TXD

4B 5B

Encoder

Scrambler

TXC 25M

10/100M Auto-negotiation

Control Logic

Link pulse

10M

TXC10

TXD10

Manchester coded

waveform

10M Output waveform

shaping

RXC10

RXD10

Data Recovery

Receive low pass filter

Transceiver

TD+

TXC 25M

TXD

3 Level

Driver

TXO+

TXO -

Parrallel

to Serial

Variable Current

Baseline

Peak

Detect

wander

Correction

RXIN+

RXIN-

3 Level

Comparator

MLT-3

to NRZI

Adaptive

Equalizer

ck

data

RXC 25M

RXD

Serial to

Parrallel

Master

PPL

Slave

PLL

Control

Voltage

25M

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Rev.1.5

RTL8139C(L)+

4. Pin Assignments

84 RTSET

83 LWAKE/CSTSCHG

82 RTT2

AGND

85 GND

86 RXIN-

87 RXIN+

88 OEB

81 RTT3

AGND

80 GND

79 X1

78 X2

89 WEB

AVDD

90 VDD

77 VDD

91 TXD-

92 TXD+

76 PMEB

75 CLKRUNB

AGND

74 GND

93 GND

94 NC

73 NC

95 ISOLATEB

72 NC

AVDD

96 VDD

71 NC

97 LED2

70 MA16/MRXER

69 MA15/MRXD3

68 MA14/MRXD2

67 MA13/MRXD1

66 MA12/MRXD0

65 MA11/MRXDV

98 LED1

99 LED0

100 MD7/MDC

101 MD6/MDIO

102 MD5/MLINK

103 MD4/MFDUP

104 MD3

64 MA10/MCOL

63 MA9/MRXC

62 GND

105 MD2

106 VDD

61 MA8/AUXD/MTXD3

60 MA7/MTXD2

59 VDD

107 MD1

108 MD0

109 VDD

58 VDD

57 MA6/9356SEL/MTXD1

56 GND

110 ROMCSB

111 GND

112 GND

55 GND

113 GND

54 NC

114 INTAB

115 RSTB

53 MA5/MTXD0

52 MA4/MTXE

51 MA3/MTXC

116 CLK

117 GNTB

118 REOB

119 VDD

120 AD31

121 AD30

122 AD29

123 AD28

124 GND

125 AD27

126 AD26

127 AD25

128 AD24

RTL8139C(L)+

50

EECS

49 MA2/EESK

48 MA1/EEDI

47 MA0/EEDO

46 VDD

45 AD0

44 AD1

43 AD2

42 AD3

41 AD4

40 GND

39 AD5

1

2

3

4

5

6

7

8

9

VDD

38 AD6

CBE3B

IDSEL

AD23

AD22

AD21

GND

37 AD7

36 CBE0B

35 VDD

34 AD8

33 AD9

32 AD10

31 AD11

30 GND

29 AD12

28 AD13

27 AD14

26 AD15

25 VDD

24 CBE1B

23 PAR

AD20

AD19

10 AD18

11 AD17

12 VDD

13 AD16

14 CBE2B

15 FRAMEB

16 IRDYB

17 TRDYB

18 GND

22 SERRB

21 PERRB

20 STOPB

19 DEVSELB

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Rev.1.5

RTL8139C(L)+

5. Pin Descriptions

In order to reduce pin count, and therefore size and cost, some pins have multiple functions. In those cases, the functions are

separated with a “/” symbol. Refer to the Pin Assignment diagram for a graphical representation.

5.1 Power Management/Isolation Interface

Symbol

PMEB

Type

Pin No

Description

O/D

76

Power Management Event: Open drain, active low. Used by the

RTL8139C(L)+ to request a change in its current power management

state and/or to indicate that a power management event has occurred.

Isolate Pin: Active low. Used to isolate the RTL8139C(L)+ from the

PCI bus. The RTL8139C(L)+ does not drive its PCI outputs (excluding

PME#) and does not sample its PCI input (including RST# and

PCICLK) as long as the Isolate pin is asserted.

(PME#)

ISOLATEB

I

95

83

(ISOLATE#)

LWAKE/

O

LAN WAKE-UP Signal (When CardB_En=0, bit2 Config3): This

signal is used to inform the motherboard to execute the wake-up

process. The motherboard must support Wake-On-LAN (WOL). There

are 4 choices of output, including active high, active low, positive pulse,

and negative pulse, that may be asserted from the LWAKE pin. Please

refer to the LWACT bit in the CONFIG1 register and the LWPTN bit in

the CONFIG4 register for the setting of this output signal. The default

output is an active high signal.

CSTSCHG

Once a PME event is received, the LWAKE and PMEB assert at the

same time when the LWPME (bit4, CONFIG4) is set to 0. If the

LWPME is set to 1, the LWAKE asserts only when the PMEB asserts

and the ISOLATEB is low.

CSTSCHG Signal (When CardB_En=1, bit2 Config3): This signal

is used in CardBus applications only and is used to inform the

motherboard to execute the wake-up process whenever a PME event

occurs. This is always an active high signal, and the setting of LWACT

(bit 4, Config1), LWPTN (bit2, Config4), and LWPME (bit4, Config4)

mean nothing in this case.

This pin is a 3.3V signaling output pin.

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RTL8139C(L)+

5.2 PCI Interface

Symbol

AD31-0

Type

Pin No

Description

T/S

120-123, 125-128, 4-6, PCI address and data multiplexed pins.

8-11, 13, 26-29, 31-34,

37-39, 41-45

C/BE3-0

CLK

T/S

I

2, 14, 24, 36

116

PCI bus command and byte enables multiplexed pins.

Clock: This PCI Bus clock provides timing for all transactions and bus

phases, and is input to PCI devices. The rising edge defines the start of

each phase. The clock frequency ranges from 0 to 33MHz.

For network operation to be functional, the PCI Bus clock frequency

should be higher than 16.75MHz.

CLKRUNB

I/O

75

Clock Run: This signal is used by the RTL8139C(L)+ to request starting (or

speeding up) the clock, CLK. CLKRUNB also indicates the clock status. For the

RTL8139C(L)+, CLKRUNB is an open drain output as well as an input. The

RTL8139C(L)+ requests the central resource to start, speed up, or maintain the

interface clock by the assertion of CLKRUNB. For the host system, it is an S/T/S

signal. The host system (central resource) is responsible for maintaining

CLKRUNB asserted, and for driving it high to the negated (deasserted) state.

Device Select: As a bus master, the RTL8139C(L)+ samples this signal

to insure that a PCI target recognizes the destination address for the data

transfer. As a target, the RTL8139C(L)+ asserts this signal low when it

recognizes its target address after FRAMEB is asserted.

DEVSELB

FRAMEB

S/T/S

19

15

Cycle Frame: As a bus master, this pin indicates the beginning and

duration of an access. FRAMEB is asserted low to indicate the start of a

bus transaction. While FRAMEB is asserted, data transfer continues.

When FRAMEB is deasserted, the transaction is in the final data phase.

As a target, the device monitors this signal before decoding the address

to check if the current transaction is addressed to it.

GNTB

I

117

Grant: This signal is asserted low to indicate to the RTL8139C(L)+that

the central arbiter has granted ownership of the bus to the

RTL8139C(L)+. This input is used when the RTL8139C(L)+is acting

as a bus master.

REQB

IDSEL

INTAB

T/S

I

118

3

Request: The RTL8139C(L)+will assert this signal low to request the

ownership of the bus from the central arbiter.

Initialization Device Select: This pin allows the RTL8139C(L)+to

identify when configuration read/write transactions are intended for it.

Interrupt A: Used to request an interrupt. It is asserted low when an

interrupt condition occurs, as defined by the Interrupt Status, and

Interrupt Mask registers.

O/D

114

IRDYB

S/T/S

16

Initiator Ready: This indicates the initiating agent’s ability to complete

the current data phase of the transaction.

As a bus master, this signal will be asserted low when the

RTL8139C(L)+is ready to complete the current data phase transaction.

This signal is used in conjunction with the TRDYB signal. Data

transaction takes place at the rising edge of CLK when both IRDYB and

TRDYB are asserted low. As a target, this signal indicates that the

master has put data on the bus.

TRDYB

S/T/S

17

Target Ready: This indicates the target agent’s ability to complete the

current phase of the transaction.

As a bus master, this signal indicates that the target is ready for the data

during write operations and with the data during read operations. As a

target, this signal will be asserted low when the (slave) device is ready

to complete the current data phase transaction. This signal is used in

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RTL8139C(L)+

conjunction with the IRDYB signal. Data transaction takes place at the

rising edge of CLK when both IRDYB and TRDYB are asserted low.

Parity: This signal indicates even parity across AD31-0 and C/BE3-0

including the PAR pin. As a master, PAR is asserted during address and

write data phases. As a target, PAR is asserted during read data phases.

Parity Error: When the RTL8139C(L)+is the bus target and a parity

error is detected, the RTL8139C(L)+asserts this PERRB pin low.

System Error: If an address parity error is detected and Configuration

Space Status register bit 15 (detected parity error) is enabled,

RTL8139C(L)+ asserts both SERRB pin low and bit 14 of Status

register in Configuration Space.

PAR

T/S

23

PERRB

SERRB

S/T/S

O/D

21

22

STOPB

RSTB

S/T/S

I

20

Stop: Indicates the current target is requesting the master to stop the

current transaction.

115

Reset: When RSTB is asserted low, the RTL8139C(L)+ performs an

internal system hardware reset. RSTB must be held for a minimum of 120 ns.

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RTL8139C(L)+

5.3 FLASH/BootPROM/EEPROM/MII Interface

Symbol

Type

Pin No

Description

In Boot PROM (or flash) Mode:

MA[16:9], MA7,

MA[5:3]

O

70-63, 60, 53-51

MA16-3: (In Boot PROM mode only)

Output pins as Boot PROM address bus. These pins are used to access

up to a 128k-byte flash memory or EPROM.

MA8: (In both Boot PROM mode and MII mode)

MA8

O, I

I

61

57

70

Input pin as Aux. Power detect pin to detect if Aux. power exists or not,

when initial power-on or PCI reset is de-asserted. Besides connecting

this pin to Boot PROM or MII TXD3, it should be pulled high to the

Aux. power via a resistor to detect Aux. power. If this pin is not pulled

high to the Aux. power, the RTL8139C(L)+ assumes that no Aux.

power exists. To support wakeup from ACPI D3cold or APM

power-down, this pin must be pulled high to Aux. power via a resistor.

MA6/9356SEL: (In both Boot PROM mode and MII mode)

Input pin as 9356 select pin at initial power-up. When this pin is

pulled high with a 10KΩ resistor, the 93C56 EEPROM is used to

store the resource data and CIS for the RTL8139C(L)+. The

RTL8139C(L)+ latches the status of this pin at power-up to

determine what EEPROM(93C46 or 93C56) is used, afterwards, this

pin is used as MA6 or MTXD1.

MA6

In MII mode:

MRXER(MA16)

MII Receive Error: (MA16 in MII mode)

This pin is asserted to indicate that invalid symbol has been detected

in 100Mbps MII mode. This signal is synchronized to RXC and can be

asserted for a minimum of one receive clock. When asserted during a

packet reception, it sets the ISE bit of the RSR register in the header of

the Rx packet.

MRXD[3:0](MA

[15:12])

I

69-66

65

MII Receive Data: (MA15-12 in MII mode)

This is a group of 4 data signals aligned on nibble boundaries which

are driven synchronous to the RXC by the external physical unit.

MII Receive Data Valid: (MA11 in MII mode)

MRXDV(MA11)

MCOL(MA10)

MRXC(MA9)

Data valid is asserted by an external PHY when receive data is

present on the MRXD[3:0] lines, and it is deasserted at the end of the

packet. This signal is valid on the rising of the MRXC.

MII Collision Detected: (MA10 in MII mode)

I

64

This signal is asserted high synchronously by the external physical

unit upon detection of a collision on the medium. It will remain

asserted as long as the collision condition persists.

I

63

MII Receive Clock: (MA9 in MII mode)

This is a continuous clock that is recovered from the incoming data.

MRXC is 25MHz in 100Mbps and 2.5Mhz in 10Mbs.

MII Transmit Data: (MA8-5 in MII mode)

MTXD[3:0](MA

[8:5])

O

61, 60, 57, 53

Four parallel transmit data lines which are driven synchronous to the

MTXC for transmission by the external physical layer chip.

10

2001/12/06

Rev.1.5

RTL8139C(L)+

MTXE(MA4)

MTXC(MA3)

O

I

52

51

MII Transmit Enable: (MA4 in MII mode)

Indicates the presence of valid nibble data on MTXD[3:0].

MII Transmit Clock: (MA3 in MII mode)

MTXC is a continuous clock that provides a timing reference for the

transfer of MTXD[3:0], MTXE. In MII mode, it uses the 25 MHz or

2.5 MHz supplied by the external PMD device.

MA2/EESK

O

49

The MA2-0 pins are switched to EESK, EEDI, EEDO in 93C46

(93C56) programming or auto-load mode.

MA1/EEDI

MA0/EEDO

EECS

O

O, I

O

48

47

50

93C46 (93C56) Chip Select

Boot PROM data bus in Boot PROM mode.

MD0-7

I/O

108, 107, 105-100

MDC(MD7)

O

100

MDC: (MD7 at MII mode)

Management Data Clock: Synchronous clock to the MDIO

management data input/output serial interface which may be

asynchronous to transmit and receive clocks.

MDIO: (MD6 in MII mode)

MDIO(MD6)

I/O

101

Management Data: Bi-directional signal used to transfer management

information.

MLINK(MD5)

MFDUP(MD4)

I

102

103

MLINK: (MD5 in MII mode) link status notification from external

PHYceiver.

MFDUP: (MD4 in MII mode) full-duplex status notification from

external PHYceiver.

ROMCSB

OEB

O

110

88

ROM Chip Select: This is the chip select signal of the Boot PROM.

Output Enable: This enables the output buffer of the Boot PROM or

Flash memory during a read operation.

WEB

O

89

Write Enable: This signal strobes data into the Flash memory during a

write cycle.

5.4 Power Pins

Symbol

VDD

Type

Pin No

Description

P

1, 12, 25, 35, 46, 58,

59, 106, 109, 119

77, 90, 96

Digital Power +3.3V

AVDD

GND

P

Analog Power +3.3V

Digital Ground

7, 18, 30, 40, 55, 56,

62, 111, 112, 113, 124

74, 80, 85, 93

AGND

P

Analog Ground

5.5 LED Interface

Symbol

Type

Pin No

99, 98, 97

Description

LED0, 1, 2

O

LED pins

LEDS1-0

LED0

00

01

10

11

Tx/Rx

Tx

LINK10/ACT

LINK100

LINK10

LINK10/100

FULL

LINK10/100 LINK100/ACT

Rx FULL

LED1

LED2

During power down mode, the LEDs are OFF.

11

2001/12/06

Rev.1.5

RTL8139C(L)+

5.6 Attachment Unit Interface

Symbol

Type

Pin No

92

Description

100/10BASE-T transmit (Tx) Data

TXD+

O

I

TXD-

RXIN+

RXIN-

X1

91

87

100/10BASE-T receive (Rx) Data

25 MHz crystal/OSC. Input

Crystal Feedback Output: This output is used in crystal connection

only. It must be left open when X1 is driven with an external 25MHz

oscillator.

I

86

I

79

X2

O

78

5.7 Test and Other Pins

Symbol

RTT2-3

Type

TEST

I/O

Pin No

81, 82

84

Description

Chip test pins.

RTSET

This pin must be pulled low by a resistor. Please refer to the application

circuit for correct value.

Reserved

NC

-

54, 71, 72, 73, 94

12

2001/12/06

Rev.1.5

RTL8139C(L)+

6. Register Descriptions

The RTL8139C(L)+ provides the following set of operational registers mapped into PCI memory space or I/O space.

Offset

R/W

Tag

Description

0000h

R/W

IDR0

ID Register 0: The ID registers 0-5 are only permitted to write by

4-byte access. Read access can be byte, word, or double word access.

The initial value is autoloaded from the EEPROM EthernetID field.

0001h

0002h

R/W

-

IDR1

IDR2

IDR3

IDR4

IDR5

-

ID Register 1

ID Register 2

0003h

ID Register 3

0004h

ID Register 4

0005h

ID Register 5

0006h-0007h

0008h

Reserved

R/W

MAR0

Multicast Register 0: The MAR registers 0-7 are only permitted to

write by 4-byte access. Read access can be byte, word, or double word

access. Driver is responsible for initializing these registers.

Multicast Register 1

0009h

000Ah

R/W

MAR1

MAR2

MAR3

MAR4

MAR5

MAR6

MAR7

TSD0

Multicast Register 2

000Bh

Multicast Register 3

000Ch

Multicast Register 4

000Dh

Multicast Register 5

000Eh

Multicast Register 6

000Fh

Multicast Register 7

0010h-0013h

Transmit Status of Descriptor 0 Dump Tally Counter

(C mode only)

Transmit Status of Descriptor 1

(C mode only)

Command Register (C+ mode

only)

0014h-0017h

R/W

TSD1

0018h-001Bh

001Ch-001Fh

0020h-0023h

R/W

TSD2

TSD3

Transmit Status of Descriptor 2 (C mode only)

Transmit Status of Descriptor 3 (C mode only)

Transmit Start Address (32-bit) Transmit Normal Priority

TSAD0

TSAD1

TSAD2

TSAD3

TNPDS

of Descriptor0 (C mode only,

double-word alignment)

Descriptors Start address

(64-bit). (C+ mode only, 256-byte

alignment)

0024h-0027h

0028h-002Bh

002Ch-002Fh

0030h-0033h

R/W

Transmit Start Address (32-bit)

of Descriptor1 (C mode only,

double-word alignment)

THPDS

Transmit Start Address (32-bit) Transmit High Priority

of Descriptor2 (C mode only,

double-word alignment)

Descriptors Start address

(64-bit). (C+ mode only, 256-byte

alignment)

Transmit Start Address (32-bit)

of Descriptor3 (C mode only,

double-word alignment)

RBSTART

Receive (Rx) Buffer Start Address (C mode only, double-word

alignment)

Early Receive (Rx) Byte Count Register

Early Rx Status Register

Command Register

0034h-0035h

0036h

R

R/W

R

ERBCR

ERSR

CR

CAPR

CBR

0037h

0038h-0039h

003Ah-003Bh

Current Address of Packet Read (C mode only, the initial value is 0FFF0h)

Current Buffer Address: The initial value is 0000h. It reflects total

received byte-count in the Rx buffer. (C mode only)

Interrupt Mask Register

Interrupt Status Register

Transmit (Tx) Configuration Register

Receive (Rx) Configuration Register

003Ch-003Dh

003Eh-003Fh

0040h-0043h

0044h-0047h

R/W

IMR

ISR

TCR

RCR

13

2001/12/06

Rev.1.5

RTL8139C(L)+

0048h-004Bh

004Ch-004Fh

R/W

TCTR

MPC

Timer Count Register: This register contains

a

32-bit

general-purpose timer. Writing any value to this 32-bit register will

reset the original timer and begin to count from zero.

Missed Packet Counter: Indicates the number of packets discarded

due to Rx FIFO overflow. It is a 24-bit counter. After a s/w reset, MPC

is cleared. Only the lower 3 bytes are valid.

Writing any value to this register will reset MPC.

93C46 (93C56) Command Register

0050h

0051h

R/W

-

9346CR

CONFIG0

CONFIG1

-

Configuration Register 0

0052h

Configuration Register 1

0053H

Reserved

R /W

0054h-0057h

TimerInt

Timer Interrupt Register: When a nonzero value is written to this

register, the Timeout bit of the ISR register will be set whenever the

TCTR reaches this value. The Timeout bit will never be set as long as

the TimerInt register is zero.

0058h

0059h

R/W

-

MSR

CONFIG3

CONFIG4

-

MULINT

RERID

-

TSAD

BMCR

BMSR

Media Status Register

Configuration register 3

005Ah

Configuration register 4

005Bh

Reserved

005Ch-005Dh

005Eh

R/W

R

Multiple Interrupt Select

PCI Revision ID = 10h

005Fh

-

R

Reserved

0060h-0061h

0062h-0063h

0064h-0065h

0066h-0067h

0068h-0069h

006Ah-006Bh

006Ch-006Dh

006Eh-006Fh

0070h-0071h

0072h-0073h

0074h-0075h

0076-0077h

0078h-007Bh

007Ch-007Fh

0080h

Transmit Status of All Descriptors (C mode only)

Basic Mode Control Register

R/W

R

Basic Mode Status Register

R/W

R

ANAR

ANLPAR

ANER

Auto-Negotiation Advertisement Register

Auto-Negotiation Link Partner Register

Auto-Negotiation Expansion Register

Disconnect Counter

R

DIS

FCSC

R

False Carrier Sense Counter

R/W

R

NWAYTR

REC

N-way Test Register

RX_ER Counter

R/W

-

CSCR

CS Configuration Register

-

Reserved

R/W

-

PHY1_PARM

TW_PARM

PHY2_PARM

-

PHY Parameter 1

Twister Parameter

PHY Parameter 2

0081h

0082-0083h

0084h

Reserved

R

_TDOKLAddr

CRC0

Low Address of a Tx Descriptor with Tx DMA Ok

Power Management CRC register0 for wakeup frame0

Power Management CRC register1 for wakeup frame1

Power Management CRC register2 for wakeup frame2

Power Management CRC register3 for wakeup frame3

Power Management CRC register4 for wakeup frame4

Power Management CRC register5 for wakeup frame5

Power Management CRC register6 for wakeup frame6

Power Management CRC register7 for wakeup frame7

Power Management wakeup frame0 (64bit)

Power Management wakeup frame1 (64bit)

Power Management wakeup frame2 (64bit)

Power Management wakeup frame3 (64bit)

Power Management wakeup frame4 (64bit)

Power Management wakeup frame5 (64bit)

R/W

0085h

0086h

0087h

CRC1

CRC2

CRC3

0088h

CRC4

0089h

CRC5

008Ah

CRC6

008Bh

CRC7

008Ch–0093h

0094h–009Bh

009Ch–00A3h

00A4h–00ABh

00ACh–00B3h

00B4h–00BBh

Wakeup0

Wakeup1

Wakeup2

Wakeup3

Wakeup4

Wakeup5

14

2001/12/06

Rev.1.5

RTL8139C(L)+

00BCh–00C3h

00C4h–00CBh

00CCh

R/W

W

Wakeup6

Wakeup7

LSBCRC0

LSBCRC1

LSBCRC2

LSBCRC3

LSBCRC4

LSBCRC5

LSBCRC6

LSBCRC7

FLASH

Config5

TPPoll

Power Management wakeup frame6 (64bit)

Power Management wakeup frame7 (64bit)

LSB of the mask byte of wakeup frame0 within offset 12 to 75

LSB of the mask byte of wakeup frame1 within offset 12 to 75

LSB of the mask byte of wakeup frame2 within offset 12 to 75

LSB of the mask byte of wakeup frame3 within offset 12 to 75

LSB of the mask byte of wakeup frame4 within offset 12 to 75

LSB of the mask byte of wakeup frame5 within offset 12 to 75

LSB of the mask byte of wakeup frame6 within offset 12 to 75

LSB of the mask byte of wakeup frame7 within offset 12 to 75

Flash memory read/write register

00CDh

00CEh

00CFh

00D0h

00D1h

00D2h

00D3h

00D4h-00D7h

00D8h

Configuration register 5

00D9h

Transmit Priority Polling register (C+ mode only)

Reserved

00DAh-00DFh

00E0h-00E1h

00E2h-00E3h

00E4h-00EBh

-

R/W

--

R/W

C+CR

C+ Command Register (C+ mode only)

-

Reserved

RDSAR

Receive Descriptor Start Address Register (C+ mode only,

256-byte alignment)

00ECh

R/W

-

ETThR

-

C+ Early Transmit Threshold Register (C+ mode only)

Reserved

00EDh-00EFh

00F0h-00F3h

00F4h-00F7h

00F8h-00FBh

00FCh-00FFh

R/W

R

FER

Function Event Register (Cardbus only)

FEMR

FPSR

Function Event Mask Register (CardBus only)

Function Present State Register (CardBus only)

Function Force Event Register (CardBus only)/MII Register

(Auto-Detect or MII mode only)

W

FFER/MIIR

6.1 Receive Status Register in Rx Packet Header

(C mode only)

Bit

15

R/W

R

Symbol

MAR

Description

Multicast Address Received: This bit set to 1 indicates that a multicast

packet is received.

14

13

R

PAM

BAR

Physical Address Matched: This bit set to 1 indicates that the destination

address of this packet matches the value written in ID registers.

Broadcast Address Received: This bit set to 1 indicates that a broadcast

packet is received. BAR, MAR bit will not be set simultaneously.

Reserved

12-6

5

-

R

-

ISE

Invalid Symbol Error: (100BASE-TX only) This bit set to 1 indicates

that an invalid symbol was encountered during the reception of this packet.

Runt Packet Received: This bit set to 1 indicates that the received packet

length is smaller than 64 bytes ( i.e. media header + data + CRC < 64

bytes )

4

R

RUNT

3

2

1

0

R

LONG

CRC

FAE

Long Packet: This bit set to 1 indicates that the size of the received

packet exceeds 4k bytes.

CRC Error: When set, indicates that a CRC error occurred on the

received packet.

Frame Alignment Error: When set, indicates that a frame alignment

error occurred on this received packet.

ROK

Receive OK: When set, indicates that a good packet is received.

15

2001/12/06

Rev.1.5

RTL8139C(L)+

6.2 Transmit Status Register

(TSD0-3)(Offset 0010h-001Fh, R/W, C mode only)

The read-only bits (CRS, TABT, OWC, CDH, NCC3-0, TOK, TUN) will be cleared by RTL8139C(L)+ when the Transmit Byte

Count (bit12-0) in the corresponding Tx descriptor is written. It is not affected when software writes to these bits. These registers

are only permitted to write by double-word access. After software reset, all bits except OWN bit are reset to “0”.

Bit

31

R/W

R

Symbol

CRS

Description

Carrier Sense Lost: This bit is set to 1 when the carrier is lost during

transmission of a packet.

30

29

R

TABT

OWC

Transmit Abort: This bit is set to 1 if the transmission of a packet was

aborted. This bit is read only, writing to this bit is not affected.

Out of Window Collision: This bit is set to 1 if the RTL8139C(L)+

encountered an "out of window" collision during the transmission of a

packet.

28

R

CDH

CD Heart Beat: The same as RTL8139(A/B).

This bit is cleared in the 100 Mbps mode.

27-24

NCC3-0

Number of Collision Count: Indicates the number of collisions

encountered during the transmission of a packet.

23-22

21-16

-

Reserved

R/W

ERTXTH5-0

Early Tx Threshold: Specifies the threshold level in the Tx FIFO to

begin the transmission. When the byte count of the data in the Tx FIFO

reaches this level, (or the FIFO contains at least one complete packet)

the RTL8139C(L)+ will transmit this packet.

000000 = 8 bytes

These fields count from 000001 to 111111 in unit of 32 bytes.

This threshold must be avoided from exceeding 2K byte.

15

14

R

TOK

TUN

Transmit OK: Set to 1 indicates that the transmission of a packet was

completed successfully and no transmit underrun occurs.

Transmit FIFO Underrun: Set to 1 if the Tx FIFO was exhausted

during the transmission of a packet. The RTL8139C(L)+can re-transfer

data if the Tx FIFO underruns and can also transmit the packet to the

wire successfully even though the Tx FIFO underruns. That is, when

TSD<TUN>=1, TSD<TOK>=0 and ISR<TOK>=1 (or ISR<TER>=1).

OWN: The RTL8139C(L)+sets this bit to 1 when the Tx DMA

operation of this descriptor was completed. The driver must set this bit

to 0 when the Transmit Byte Count (bit0-12) is written. The default

value is 1.

Descriptor Size: The total size in bytes of the data in this descriptor. If

the packet length is more than 1792 byte (0700h), the Tx queue will be

invalid, i.e. the next descriptor will be written only after the OWN bit of

that long packet's descriptor has been set.

13

R/W

OWN

SIZE

12-0

16

2001/12/06

Rev.1.5

RTL8139C(L)+

6.3 Dump Tally Counter Command Register (DTCCR)

(Offset 0010h-0017h, R/W, C+ mode only)

Bit

63-6

R/W

Symbol

Description

CntrAddr Starting address of the 12 Tally Counters being dumped to. (64-byte alignment, 64

bytes long)

Offset of

Counter

Description

starting

address

0

8

TxOk

RxOk

TxErr

64-bit counter of Tx DMA Ok packets.

64-bit counter of Rx Ok packets.

16

64-bit packet counter of Tx errors including Tx

abort, carrier lost, Tx underrun (should occur only

on jumbo frames), and out of window collision.

32-bit packet counter of Rx errors including CRC

error packets (should be larger than 8 bytes) and

missed packets.

24

RxErr

28

30

32

36

40

48

56

MissPkt 16-bit counter of missed packets (CRC Ok)

resulted from Rx FIFO full.

FAE

16-bit counter of Frame Alignment Error packets

(MII mode only)

Tx1Col 32-bit counter of Tx Ok packets with only 1

collision occurring before Tx Ok.

TxMCol 32-bit counter of Tx Ok packets with more than 1

and less than 16 collisions happened before Tx Ok.

RxOkPh 64-bit counter of all Rx Ok packets with physical

y

addresses matching destination ID.

RxOkBrd 64-bit counter of all Rx Ok packets with broadcast

destination ID.

RxOkMu 32-bit counter of all Rx Ok packets with multicast

l

destination ID.

60

62

TxAbt

16-bit counter of Tx abort packets.

TxUndrn 16-bit counter of Tx underrun and discard packets

(only possible on jumbo frames).

5-4

3

-

Reserved

R/W

Cmd

Command:

-

When set, the RTL8139C(L)+ begins dumping 13 Tally counters to the

address specified above.

-

When this bit is reset by RTL8139C(L)+, the dumping is completed.

2-0

-

Reserved

17

2001/12/06

Rev.1.5

RTL8139C(L)+

6.4 ERSR: Early Rx Status Register

(Offset 0036h, R)

Bit

7-4

3

R/W

Symbol

-

Description

-

Reserved

R

ERGood

Early Rx Good packet: This bit is set whenever a packet is completely

received and the packet is good. This bit is cleared when writing 1 to it.

Early Rx Bad packet: This bit is set whenever a packet is completely

received and the packet is bad. Writing 1 will clear this bit.

2

1

R

ERBad

EROVW

Early Rx OverWrite: This bit is set when the RTL8139C(L)+'s local

address pointer is equal to CAPR. In the early mode, this is different

from buffer overflow. It happens that the RTL8139C(L)+ detected an

Rx error and wanted to fill another packet data from the beginning

address of that error packet. Writing 1 will clear this bit.

Early Rx OK: The power-on value is 0. It is set when the Rx byte count

of the arriving packet exceeds the Rx threshold. After the whole packet

is received, the RTL8139C(L)+ will set ROK or RER in ISR and clear

this bit simultaneously. Setting this bit will invoke a ROK interrupt.

0

R

EROK

6.5 Command Register

(Offset 0037h, R/W)

This register is used for issuing commands to the RTL8139C(L)+. These commands are issued by setting the corresponding bits for

the function. A global software reset along with individual reset and enable/disable for transmitter and receiver are provided here.

Bit

7-5

4

R/W

-

R/W

Symbol

Description

-

Reserved

RST

Reset: Setting to 1 forces the RTL8139C(L)+ to a software reset state

which disables the transmitter and receiver, reinitializes the FIFOs,

resets the system buffer pointer to the initial value (Tx buffer is at

TSAD0, Rx buffer is empty). The values of IDR0-5 and MAR0-7 and

PCI configuration space will have no changes. This bit is 1 during the

reset operation, and is cleared to 0 by the RTL8139C(L)+ when the reset

operation is complete.

3

2

R/W

RE

TE

Receiver Enable: When set to 1, and the receive state machine is idle,

the receive machine becomes active. This bit will read back as a 1

whenever the receive state machine is active. After initial power-up,

software must insure that the receiver has completely reset before

setting this bit.

Transmitter Enable: When set to 1, and the transmit state machine is

idle, then the transmit state machine becomes active. This bit will read

back as a 1 whenever the transmit state machine is active. After initial

power-up, software must insure that the transmitter has completely reset

before setting this bit.

1

0

-

R

-

Reserved

BUFE

Buffer Empty: Rx Buffer Empty; There is no packet stored in the Rx

buffer ring.

18

2001/12/06

Rev.1.5

RTL8139C(L)+

6.6 Interrupt Mask Register

(Offset 003Ch-003Dh, R/W)

This register masks the interrupts that can be generated from the ISR. Writing a “1” to the bit enables the corresponding interrupt.

During a hardware reset, all mask bits are cleared. Setting a mask bit allows the corresponding bit in the ISR to cause an interrupt.

ISR bits are always set to 1, however, if the condition is present, regardless of the state of the corresponding mask bit.

Bit

15

R/W

Symbol

SERR

Description

System Error Interrupt: 1: Enable, 0: Disable.

14

13

12

11

10

9

R/W

-

TimeOut

Time Out Interrupt: 1: Enable, 0: Disable.

Cable Length Change Interrupt: 1: Enable, 0: Disable.

Reserved

LenChg

-

Reserved

-

Reserved

-

8

R/W

_SWInt

_TDU

Software Interrupt: 1: Enable, 0: Disable.

Tx Descriptor Unavailable Interrupt: 1: Enable, 0: Disable.

Rx FIFO Overflow Interrupt: 1: Enable, 0: Disable.

Packet Underrun/Link Change Interrupt: 1: Enable, 0: Disable.

Rx Buffer Overflow/Rx Descriptor Unavailable Interrupt:

1: Enable, 0: Disable.

7

6

FOVW

PUN/LinkChg

RBO/_RDU

5

4

3

2

1

0

R/W

TER

TOK/TI

RER

Tx Error Interrupt: 1: Enable, 0: Disable.

Tx (OK) Interrupt: 1: Enable, 0: Disable.

Rx Error Interrupt: 1: Enable, 0: Disable.

Rx OK Interrupt: 1: Enable, 0: Disable.

ROK

19

2001/12/06

Rev.1.5

RTL8139C(L)+

6.7 Interrupt Status Register

(Offset 003Eh-003Fh, R/W)

This register indicates the source of an interrupt when the INTA pin goes active. Enabling the corresponding bits in the Interrupt

Mask Register (IMR) allows bits in this register to produce an interrupt. When an interrupt is active, one of more bits in this register

are set to a “1”. The interrupt Status Register reflects all current pending interrupts, regardless of the state of the corresponding mask

bit in the IMR. Writing a 1 to any bit will reset that bit, but writing a 0 has no effect.

Bit

15

R/W

Symbol

SERR

Description

System Error: Set to 1 when the RTL8139C(L)+ signals a system error

on the PCI bus.

14

13

R/W

TimeOut

LenChg

Time Out: Set to 1 when the TCTR register reaches to the value of the

TimerInt register.

Cable Length Change: Cable length is changed after Receiver is

enabled.

12

11

10

9

-

Reserved

-

Reserved

-

Reserved

-

Reserved

8

R/W

_SWInt

Software Interrupt: (C+ mode only)

i. Set to 1 whenever FSWInt (bit0, offset D9h, TPPoll register) is

written 1 by software.

ii. Reserved bit in C mode.

7

R/W

_TDU

Tx Descriptor Unavailable: (C+ mode only)

i. When set, indicates Tx descriptor is unavailable.

ii. Reserved bit in C mode.

6

5

4

R/W

FOVW

Rx FIFO Overflow: Caused by RBO/RDU, poor PCI performance, or

overloaded PCI traffic.

Packet Underrun/Link Change: Set to 1 when CAPR is written but

Rx buffer is empty, or when link status is changed.

Rx Buffer Overflow: (C mode only)

Set when receive (Rx) buffer ring storage resources have been

exhausted.

PUN/LinkChg

RBO/_RDU

Rx Descriptor Unavailable: (C+ mode only)

When set, indicates Rx descriptor is unavailable.

The MPC (Missed Packet Counter, offset 4Ch-4Fh) indicates the

number of packets discarded after the Rx FIFO overflow.

Transmit (Tx) Error: Indicates that a packet transmission was

aborted, due to excessive collisions, according to the TXRR setting

Transmit (Tx) OK: (C mode only)

3

2

R/W

TER

TOK/TI

Indicates that a packet transmission is completed successfully.

Transmit Interrupt: (C+ mode only)

Indicates that the DMA of the last descriptor of a Tx packet has

completed and the last descriptor has been closed.

1

0

R/W

RER

ROK

Receive (Rx) Error: Indicates that a packet has either a CRC error or a

frame alignment error (FAE). The collided frame will not be recognized

as a CRC error if the length of this frame is shorter than 16 bytes.

Receive (Rx) OK: In normal mode, this indicates the successful

completion of a packet reception. In early mode, this indicates that the

Rx byte count of the arriving packet exceeds the early Rx threshold.

20

2001/12/06

Rev.1.5

RTL8139C(L)+

6.8 Transmit Configuration Register

(Offset 0040h-0043h, R/W)

This register defines the Transmit Configuration for the RTL8139C(L). It controls such functions as Loopback, Heartbeat, Auto

Transmit Padding, programmable Interframe Gap, Fill and Drain Thresholds, and maximum DMA burst size. The TCR register

can only be changed after having set the TE (bit2, Command register, offset 0037h).

Bit

31

30-26

R/W

Symbol

-

HWVERID

Description

-

Reserved

Hardware Version ID:

R

Bit30 Bit29 Bit28 Bit27 Bit26 Bit23

RTL8139

RTL8139A

RTL8139A-G

RTL8139B

RTL8130

RTL8139C

RTL8139C+

Reserved

1

0

1

0

1

0

1

0

1

0

1

All other combination

25-24

R/W

IFG1, 0

Interframe Gap Time: This field allows adjustment of the interframe

gap time below the standards of 9.6 us for 10Mbps, 960 ns for

100Mbps. The time can be programmed from 9.6 us to 8.4 us (10Mbps)

and 960ns to 840ns (100Mbps). Note that any value of IFG [2:0] other

than (0,1,1) will violate the IEEE 802.3 standard.

The formula for the inter frame gap is:

IFG[2:0]

IFG@100MHz (nS)

960

IFG@10MHz (uS)

9.6

0

1

0

1

0

1

0

1

0

1

0

1

0

960 + 8 * 10

960 + 16 * 10

960 + 24 * 10

960 + 32 * 10

960 + 40 * 10

960 + 48 * 10

960 + 96 * 10

9.6 +8 * 0.1

9.6 + 16 * 0.1

9.6 + 24 * 0.1

9.6 + 32 * 0.1

9.6 + 40 * 0.1

9.6 + 48 * 0.1

9.6 + 96 * 0.1

23

22-20

19

R

-

8139A-G

RTL8139A rev.G ID = 1. For others, this bit is 0.

-

Reserved.

R/W

IFG2

LBK1, LBK0

InterFrameGap2

18, 17

Loopback Test: There will be no packet on the TX+/- lines under the

Loopback test condition. The loopback function must be independent of

the link state.

00 : Normal operation

01 : Reserved

10 : Reserved

11 : Loopback mode

16

R/W

CRC

Append CRC:

0: A CRC is appended at the end of a packet

1: No CRC appended at the end of a packet

15-11

10-8

-

Reserved

R/W

MXDMA2, 1, 0

Max DMA Burst Size per Tx DMA Burst: This field sets the maximum

size of transmit DMA data bursts according to the following table:

000 = 16 bytes

001 = 32 bytes

010 = 64 bytes

21

2001/12/06

Rev.1.5

RTL8139C(L)+

011 = 128 bytes

100 = 256 bytes

101 = 512 bytes

110 = 1024 bytes

111 = 2048 bytes

7-4

R/W

TXRR

Tx Retry Count: These are used to specify additional transmission

retries in multiples of 16 (IEEE 802.3 CSMA/CD retry count). If the

TXRR is set to 0, the transmitter will re-transmit 16 times before

aborting due to excessive collisions. If the TXRR is set to a value

greater than 0, the transmitter will re-transmit a number of times equal

to the following formula before aborting:

Total retries = 16 + (TXRR * 16)

The TER bit in the ISR register or transmit descriptor will be set when

the transmission fails and reaches to this specified retry count.

Reserved

Clear Abort: (C mode only) Setting this bit to 1 causes the

RTL8139C(L)+ to retransmit the packet at the last transmitted

descriptor when this transmission was aborted. Setting this bit is only

permitted in the transmit abort state.

3-1

0

-

W

-

CLRABT

6.9 Receive Configuration Register

(Offset 0044h-0047h, R/W)

This register is used to set the receive configuration for the RTL8139C(L)+. Receive properties such as accepting error packets,

runt packets, setting the receive drain threshold etc. are controlled here.

Bit

R/W

-

Symbol

Description

31-28

27-24

-

Reserved

R/W

ERTH3, 2, 1, 0

Early Rx Threshold Bits: These bits are used to select the Rx threshold

multiplier of the whole packet that has been transferred to the system

buffer in early mode when the frame protocol is under the

RTL8139C(L)+'s definition.

0000 = No early Rx threshold

0010 = 2/16

0001 = 1/16

0011 = 3/16

0101 = 5/16

0111 = 7/16

1001 = 9/16

1011 = 11/16

1101 = 13/16

1111 = 15/16

0100 = 4/16

0110 = 6/16

1000 = 8/16

1010 = 10/16

1100 = 12/16

1110 = 14/16

Reserved

23-18

-

22

2001/12/06

Rev.1.5

RTL8139C(L)+

17

R/W

MulERINT

Multiple Early Interrupt Select:

In C mode:

When this bit is set, any received packet invokes early interrupt

according to the MULINT<MISR[11:0]> setting in early mode.

When this bit is reset, the packets of familiar protocols (IPX, IP,

NDIS, etc) invoke early interrupts according to the

RCR<ERTH[3:0]> setting in early mode. The packets of

unfamiliar protocols will invoke early interrupts according to the

setting of MULINT<MISR[11:0]>.

In C+ mode:

This bit enables/disables early interrupt according to the

MULINT<MISR[11:0]> setting.

Receive Error Packets Larger than 8 Bytes: The RTL8139C(L)+

receives error packets with length larger than 8 bytes after setting the

RER8 bit to 1.

The RTL8139C(L)+ receives error packets larger than 64-bytes when

the RER8 bit is cleared. The power-on default is zero.

16

R/W

RER8

If AER or AR is set, the RER bit will be set when the RTL8139C(L)+

receives an error packet whose length is larger than 8 bytes. The RER8

setting is “ Don’t care “ in this situation.

Rx FIFO Threshold: Specifies the Rx FIFO Threshold level. When the

number of the received data bytes from a packet, which is being received

into the RTL8139C(L)+'s Rx FIFO, has reached this level (or the FIFO

contains a complete packet), the receive PCI bus master function will

begin to transfer the data from the FIFO to the host memory. This field

sets the threshold level according to the following table:

000 = 16 bytes

15-13

RXFTH2, 1, 0

001 = 32 bytes

010 = 64 bytes

011 = 128 bytes

100 = 256 bytes

101 = 512 bytes

110 = 1024 bytes

111 = No Rx threshold. The RTL8139C(L)+ begins the transfer of data

after having received a whole packet in the FIFO.

(C mode only)

12-11

10-8

R/W

RBLEN1, 0 (C

mode only)

Rx Buffer Length: This field indicates the size of the Rx ring buffer.

00 = 8k + 16 byte

01 = 16k + 16 byte

10 = 32K + 16 byte

11 = 64K + 16 byte

MXDMA2, 1, 0

Max DMA Burst Size per Rx DMA Burst: This field sets the

maximum size of the receive DMA data bursts according to the

following table:

010 = 64 bytes

011 = 128 bytes

100 = 256 bytes

Other combinations are reserved.

23

2001/12/06

Rev.1.5

RTL8139C(L)+

7

R/W

WRAP (C mode

only)

0: The RTL8139C(L)+ will transfer the rest of the packet data into the

beginning of the Rx buffer if this packet has not been completely

moved into the Rx buffer and the transfer has arrived at the end of

the Rx buffer.

1: The RTL8139C(L)+ will keep moving the rest of the packet data into

the memory immediately after the end of the Rx buffer, if this packet

has not been completely moved into the Rx buffer and the transfer

has arrived at the end of the Rx buffer. The software driver must

reserve at least 1.5K bytes buffer to accept the remainder of the

packet. We assume that the remainder of the packet is X bytes. The

next packet will be moved into the memory from the X byte offset at

the top of the Rx buffer.

This bit is invalid when Rx buffer is selected to 64K bytes.

EEPROM Select: This bit reflects what type of EEPROM is used.

0: The EEPROM used is 9346.

6

5

R

9356SEL

AER

1: The EEPROM used is 9356.

R/W

Accept Error Packets: This bit determines if packets with CRC error,

alignment error and/or collided fragments will be accepted or rejected.

0: Reject error packets

1: Accept error packets

4

R/W

AR

Accept Runt Packets: This bit allows the receiver to accept packets

that are smaller than 64 bytes. The packet must be at least 8 bytes long to

be accepted as a runt.

0: Reject runt packets

1: Accept runt packets

3

2

1

0

R/W

AB

AM

Accept Broadcast Packets: This bit allows the receiver to accept or

reject broadcast packets.

0: Reject broadcast packets

1: Accept broadcast packets

Accept Multicast Packets: This bit allows the receiver to accept or

reject multicast packets.

0: Reject multicast packets

1: Accept multicast packets

APM

AAP

Accept Physical Match Packets: This bit allows the receiver to accept

or reject physical match packets.

0: Reject physical match packets

1: Accept physical match packets

Accept Physical Address Packets: This bit allows the receiver to

accept or reject packets with a physical destination address.

0: Reject packets with a physical destination address

1: Accept packets with a physical destination address

24

2001/12/06

Rev.1.5

RTL8139C(L)+

6.10 9346CR: 93C46 (93C56) Command Register

(Offset 0050h, R/W)

Bit

7-6

R/W

Symbol

EEM1-0

Description

These 2 bits select the RTL8139C(L)+ operating mode.

EEM1

EEM0

Operating Mode

0

Normal: RTL8139C(L)+ network/host communication

mode.

0

1

Auto-load: Entering this mode will make the

RTL8139C(L)+ load the contents of 93C46 (93C56), as

when the RSTB signal is asserted. This auto-load

operation will take about 2 ms. After it is completed, the

RTL8139C(L)+ goes back to the normal mode

automatically (EEM1 = EEM0 = 0) and all the other

registers are reset to default values.

1

0

1

93C46 (93C56) Programming: In this mode, both

network and host bus master operations are disabled. The

93C46 (93C56) can be directly accessed via bit3-0 which

now reflect the states of EECS, EESK, EEDI, & EEDO

pins respectively.

Config. Register Write Enable: Before writing to the

CONFIG0, 1, 3, 4 registers, and bits 13, 12, 8 of BMCR

(offset 62h-63h), the RTL8139C(L)+ must be placed in

this mode. This will protect the RTL8139C(L)+

configuration from accidental change.

4-5

3

-

Reserved

R/W

R

EECS

EESK

EEDI

EEDO

These bits reflect the state of EECS, EESK, EEDI & EEDO pins in

auto-load or 93C46 (93C56) programming mode.

2

1

0

Note: EESK, EEDI and EEDO are invalid during BootROM/FLASH

access.

6.11 Configuration Register 0 (CONFIG 0)

(Offset 0051h, R/W)

Bit

7-3

2-0

R/W

Symbol

Description

-

Reserved.

Select Boot ROM size (Autoloaded from EEPROM)

R

BS2, BS1, BS0

BS2

BS1

BS0

Description

0

1

0

1

0

1

0

1

0

1

0

1

0

1

No Boot ROM

8K Boot ROM

16K Boot ROM

32K Boot ROM

64K Boot ROM

128K Boot ROM

unused

25

2001/12/06

Rev.1.5

RTL8139C(L)+

6.12 Configuration Register 1 (CONFIG 1)

(Offset 0052h, R/W)

Bit

7-6

5

R/W

Symbol

LEDS1-0

Description

Refer to LED PIN definition. These bits initial value com from 93C46/93C56.

Driver Load: Software may use this bit to make sure that the driver has been

loaded. Writing 1 is 1. Writing 0 is 0. When the command register bits IOEN,

MEMEN, BMEN of PCI configuration space are written, the RTL8139C(L)+

will automatically clear this bit.

DVRLOAD

4

R/W

LWACT

LWAKE Active Mode: The LWACT and LWPTN bits in the CONFIG4

register are used to program the output signal of the LWAKE pin. According to

the combination of these two bits, there may be 4 choices of LWAKE signal, i.e.,

active high, active low, positive (high) pulse, and negative (low) pulse. The

output pulse width is about 150 ms. In CardBus mode applications, LWACT and

LWPTN have no meaning.

The default value of each of these two bits is 0, i.e., the default output signal of

the LWAKE pin is an active high signal.

LWAKE output

LWACT

0

1

0

Active high*

Active low

LWPTN

1

Positive pulse

Negative pulse

* Default value.

3

2

1

R

MEMMAP

IOMAP

VPD

Memory Mapping: The operational registers are mapped into PCI memory space.

I/O Mapping: The operational registers are mapped into PCI I/O space.

Enable Vital Product Data: Set to 1 to enable vital product data. The VPD data

is stored in 93C46 or 93C56 from within offset 40h-7Fh. If this bit is set, the

New_Cap bit in RTL8139C(L)+’s PCI Configuration Space (Offset 06H) is set,

and the VPD registers are from offset 60H to 67H in the PCI configuration space

of the RTL8139C(L)+.

R/W

0

R/W

PMEn

Power Management Enable: Writable only when 93C46CR register

EEM1=EEM0=1

Let A denote the New_Cap bit (bit 4 of the Status Register) in the PCI

Configuration space offset 06H.

Let B denote the Cap_Ptr register in the PCI Configuration space offset 34H.

Let C denote the Cap_ID (power management) register in the PCI Configuration

space offset 50H.

Let D denote the power management registers in the PCI Configuration space

offset from 52H to 55H.

Let E denote the Next_Ptr (power management) register in the PCI Configuration

space offset 51H.

PMEn setting:

- 0: A=B=C=E=0, D is invalid. (Assume VPD bit = 0)

- 1: A=1, B=50h, C=01h, D is valid, E is valid and depends on whether or not

VPD is enabled.

26

2001/12/06

Rev.1.5

RTL8139C(L)+

6.13 Media Status Register

(Offset 0058h, R/W)

This register allows configuration of a variety of device and PHY options, and provides PHY status information.

Bit

7

R/W

Symbol

Description

TXFCE/

Tx Flow Control Enable: The flow control is valid in full-duplex

LdTXFCE

mode only. This register’s default value comes from 93C46 (93C56).

RTL8139C(L)+

ANE = 1

Remote

NWAY FLY mode

NWAY mode only

No NWAY

TXFCE/LdTXFCE

R/O

R/W

ANE = 1

ANE = 0 &

-

full-duplex mode

ANE = 0 &

-

invalid

half-duplex mode

NWAY FLY mode: NWAY with flow control capability

NWAY mode only: NWAY without flow control capability

Rx Flow Control Enable: The flow control is enabled in full-duplex

mode only. The default value comes from 93C46 (93C56).

Reserved

6

R/W

RXFCE

5

4

-

R

-

Aux_Status

Aux. Power Present Status: The value of this bit is fixed after each PCI reset.

1: Aux. Power is present

0: Aux. Power is absent

3

2

R

SPEED_10

LINKB

Media Speed: Set when current media is 10 Mbps mode. Reset when

current media is 100 Mbps mode.

Inverse of Link Status:

0: Link OK

1: Link Fail

1

0

R

TXPF

RXPF

Transmit Pause Flag: Set when the RTL8139C(L)+ sends a pause

packet. Reset when the RTL8139C(L)+ sends a timer done packet.

Receive Pause Flag: Set when the RTL8139C(L)+ is in backoff state

because a pause packet has been received. Reset when pause state is clear.

27

2001/12/06

Rev.1.5

RTL8139C(L)+

6.14 Configuration Register3 (CONFIG 3)

(Offset 0059h, R/W)

Bit

R/W

Symbol

Description

7

R

GNTSel

Grant Select: Select the Frame’s asserted time after the Grant signal

has been asserted. The Frame and Grant are the PCI signals.

0: No delay

1: Delay one clock from GNT assertion

6

R/W

PARM_En

Parameter Enable: (These parameters are used in 100Mbps mode.)

Setting to 0 and 9346CR register EEM1=EEM0=1 enable the

PHY1_PARM, PHY2_PARM, TW_PARM be written via software.

Setting to 1 will allow parameters to be auto-loaded from the 93C46

(93C56) and disable writing to the PHY1_PARM, PHY2_PARM and

TW_PARM registers via software. The PHY1_PARM, PHY2_PARM,

and TW_PARM can be auto-loaded from EEPROM in this mode. The

parameter auto-load process is executed every time when the Link is

working properly in 100Mbps mode.

5

R/W

Magic

Magic Packet: This bit is valid when the PWEn bit of CONFIG1

register is set. The RTL8139C(L)+ will assert the PMEB signal to

wakeup the operating system when the Magic Packet is received.

Once the RTL8139C(L)+ has been enabled for Magic Packet wakeup

and has been put into an adequate state, it scans all incoming packets

addressed to the node for a specific data sequence, which indicates to

the controller that this is a Magic Packet frame. A Magic Packet frame

must also meet the basic requirements: Destination address + Source

address + data + CRC

The destination address may be the node ID of the receiving station or a

multicast address, which includes the broadcast address.

The specific sequence consists of 16 duplications of 6 byte ID registers,

with no breaks or interrupts. This sequence can be located anywhere

within the packet, but must be preceded by a synchronization stream, 6

bytes of FFh. The device will also accept a multicast address, as long as

the 16 duplications of the IEEE address match the address of the ID

registers.

If the Node ID is 11h 22h 33h 44h 55h 66h, then the format of the magic

frame format is as follows:

Destination address + source address + MISC + FF FF FF FF FF FF +

MISC + 11 22 33 44 55 66 + 11 22 33 44 55 66 + 11 22 33 44 55 66 +

11 22 33 44 55 66 + 11 22 33 44 55 66 + 11 22 33 44 55 66 + 11 22 33

44 55 66 + 11 22 33 44 55 66 + 11 22 33 44 55 66 + 11 22 33 44 55 66

+ 11 22 33 44 55 66 + 11 22 33 44 55 66 + 11 22 33 44 55 66 + 11 22

33 44 55 66 + 11 22 33 44 55 66 + 11 22 33 44 55 66 + MISC + CRC

Link Up: This bit is valid when the PWEn bit of the CONFIG1 register

is set. The RTL8139C(L)+, in adequate power state, will assert the

PMEB signal to wakeup the operating system when the cable

connection is re-established.

4

R/W

LinkUp

28

2001/12/06

Rev.1.5

RTL8139C(L)+

3

2

1

R

CardB_En

CLKRUN_En

FuncRegEn

Card Bus Enable:

Set to 1 to enable CardBus related registers and functions.

Set to 0 to disable CardBus related registers and functions.

CLKRUN Enable:

Set to 1 to enable CLKRUN.

Set to 0 to disable CLKRUN.

Functions Registers Enable: CardBus only

Set to 1 to enable the 4 Function Registers (Function Event Register,

Function Event Mask Register, Function Present State Register, and

Function Force Event Register) for CardBus application.

Set to 0 to disable the 4 Function Registers for CardBus application.

Fast Back to Back Enable: Set to 1 to enable Fast Back to Back.

0

R

FBtBEn

6.15 Configuration Register4 (CONFIG 4)

(Offset 005Ah, R/W)

Bit

R/W

Symbol

Description

7

R/W

RxFIFOAutoClr

Clear Rx FIFO Overflow: Set to 1, the RTL8139C(L)+ will clear Rx

FIFO overflow automatically.

6

5

R/W

AnaOff

Analog Power Off: This bit can not be auto-loaded from EEPROM

(9346 or 9356).

0: Normal working state. This is also the power-on default value.

1: Turn off the analog power of the RTL8139C(L)+ internally.

Long Wake-up Frame: The initial power-on value is 0. This bit does not

participate in EEPROM autoload, and PCI RST# has no effect to this bit.

LongWF

0: The RTL8139C(L)+ supports up to 8 wake-up frames, each with

masked bytes selected from offset 12 to 75.

1: The RTL8139C(L)+ supports up to 5 wake-up frames, each with

16-bit CRC algorithm for MS Wakeup Frame, the low byte of 16-bit

CRC should be placed at the corresponding CRC register, and the

high byte of the 16-bit CRC should be placed at the corresponding

LSBCRC register. Wake-up frames 0 and 1 are the same as above,

except that the masked bytes start from offset 0 to 63. Wake-up

frames 2 and 3 are merged into one long wake-up frame with

masked bytes selected from offset 0 to 127. Wake-up frames 4 & 5

and 6 & 7 are merged respectively into two other long wake-up

frames. Please refer to 7.4 PCI Power Management functions for a

detailed description.

4

R/W

LWPME

LANWAKE vs PMEB:

0: The LWAKE and PMEB are asserted at the same time.

1: The LWAKE can only be asserted when the PMEB is asserted and

the ISOLATEB is low.

In CardBus applications, this bit has no meaning.

3

2

1

0

-

Reserved

R/W

-

LWPTN

-

LWAKE Pattern: Please refer to LWACT bit in the CONFIG1 register.

Reserved

R/W

PBWakeup

Pre-Boot Wakeup: The initial value comes from the EEPROM

autoload.

0: Pre-Boot Wakeup enabled

1: Pre-Boot Wakeup disabled (suitable for CardBus and MiniPCI

application.)

29

2001/12/06

Rev.1.5

RTL8139C(L)+

6.16 Multiple Interrupt Select Register

(Offset 005Ch-005Dh, R/W)

If the received packet data is not the familiar protocol (IPX, IP, NDIS, etc.) to RTL8139C(L)+, RCR<ERTH[3:0]> will not be

used to transfer data in early mode. This register will be written to the received data length in order to make early Rx interrupt for

the unfamiliar protocol.

Bit

15-12

11-0

R/W

-

R/W

Symbol

-

MISR11-0

Description

Reserved

Multiple Interrupt Select: Indicates that the RTL8139C(L)+ makes an

rx interrupt after RTL8139C(L)+ has transferred the byte data into the

system memory. If the value of these bits is zero, there will be no early

interrupt as soon as the RTL8139C(L)+ prepares to execute the first PCI

transaction of the received data. Bit1, 0 must be zero.

The ERTH3-0 bits should not be set to 0 when the multiple interrupt

select register is used.

ꢂ

The above is true when MulERINT=0 (bit17, RCR). When MulERINT=1, any received packet invokes early interrupt

according to MISR[11:0] setting in early mode.

In C+ mode, all packets are unfamiliar packets.

6.17 PCI Revision ID

(Offset 005Eh, R)

Bit

R/W

Symbol

Description

7-0

R

Revision ID

The value in PCI Configuration Space offset 08h is 10h.

6.18 Transmit Status of All Descriptors Register (TSAD)

(Offset 0060h-0061h, R/W, C mode only)

Bit

15

14

13

12

11

10

9

R/W

R

Symbol

TOK3

TOK2

TOK1

TOK0

TUN3

TUN2

TUN1

TUN0

TABT3

TABT2

TABT1

TABT0

OWN3

OWN2

OWN1

OWN0

Description

TOK bit of Descriptor 3

TOK bit of Descriptor 2

TOK bit of Descriptor 1

TOK bit of Descriptor 0

TUN bit of Descriptor 3

TUN bit of Descriptor 2

TUN bit of Descriptor 1

TUN bit of Descriptor 0

TABT bit of Descriptor 3

TABT bit of Descriptor 2

TABT bit of Descriptor 1

TABT bit of Descriptor 0

OWN bit of Descriptor 3

OWN bit of Descriptor 2

OWN bit of Descriptor 1

OWN bit of Descriptor 0

R

8

R

7

R

6

R

5

R

4

R

3

R

2

R

1

R

0

R

30

2001/12/06

Rev.1.5

RTL8139C(L)+

6.19 Basic Mode Control Register

(Offset 0062h-0063h, R/W)

Bit

Name

Description/Usage

This bit sets the status and control registers of the PHY (register

0062-0074H) in a default state. This bit is self-clearing.

1: Software reset

Default/Attribute

15

Reset

0, RW

0: Normal operation

14

13

-

Reserved

-

Spd_Set

This bit sets the network speed in UTP mode. This bit‘s initial

value comes from 93C46 (93C56).

1: 100Mbps

0, RW

0: 10Mbps

12

Auto Negotiation This bit enables/disables the N-Way auto-negotiation function in

0, RW

Enable

(ANE)

UTP mode. When set to 1 to enable auto-negotiation, bit13 will be

ignored.

Set to 0 disables auto-negotiation, and bits 13 and 8 will

determine the link speed and the data transfer mode, respectively.

This bit‘s initial value comes from 93C46 (93C56).

The initial value comes from EEPROM.

11

10

9

MLinkP

0, R

1: MLINK pin = high ꢃMII link OK

0: MLINK pin = low ꢃMII link OK

The initial value comes from EEPROM.

MFDupP

1: MFDUP pin = high ꢃMII interface is in full duplex mode

0: MFDUP pin = low ꢃMII interface is in full duplex mode

This bit allows the NWay auto-negotiation function to be reset in

UTP mode.

Restart Auto

Negotiation

0, RW

1: Re-start auto-negotiation

0: Normal operation

8

Duplex Mode

In UTP mode:

0, RW

This bit sets the duplex mode. 1 = full-duplex; 0 = normal

operation. This bit‘s initial value comes from 93C46 (93C56).

If bit12 = 1, read = status write = register value.

If bit12=1, ie the chip is in N-Way mode, and the link partner is

in N-Way mode as well, then this bit is a read-only status bit

showing N-Way results.

Else, this bit is a command bit to force the chip to run in either

full-duplex or half duplex mode.

If bit12 = 0, read = write = register value.

In MII mode (Read only):

This bit is a status bit, indicating either the external PHY chip is

in full-duplex mode or half-duplex mode.

1: Indicating that the external PHY is in full-duplex mode.

0: Indicating that the external PHY is in half-duplex mode.

Reserved

7-0

-

31

2001/12/06

Rev.1.5

RTL8139C(L)+

6.20 Basic Mode Status Register

(Offset 0064h-0065h, R)

Bit

Name

Description/Usage

Default/Attribute

15

100Base-T4

1: Enable 100Base-T4 support

0: Suppress 100Base-T4 support.

0, RO

14

13

12

11

100Base_TX_ FD 1: Enable 100Base-TX full duplex support

0: Suppress 100Base-TX full duplex support

1, RO

100BASE_TX_H 1: Enable 100Base-TX half-duplex support

D

0: Suppress 100Base-TX half-duplex support

1: Enable 10Base-T full duplex support

0: Suppress 10Base-T full duplex support

10Base_T_FD

10_Base_T_HD 1: Enable 10Base-T half-duplex support

0: Suppress 10Base-T half-duplex support

10-8

7-6

-

Reserved

-

Medium1,

Medium0

These two bits are used to select medium mode. The initial values

of these 2 bits come from EEPROM autoload.

(Medium1,

Medium0) = (0,0),

R/W

Medium Mode

Medium0

0

1

UTP

X

Medium1

0

AutoDetect

MII

1

In AutoDetect mode, the priority is UTP > MII.

5

4

3

2

1

0

Auto Negotiation 1: Auto-negotiation process completed

0, RO

1, RO

0, RO

1, RO

Complete

0: Auto-negotiation process not completed

1: Remote fault condition detected (cleared on read)

0: No remote fault condition detected

Remote Fault

Auto Negotiation 1: Link had not been experienced fail state

0: Link had been experienced fail state

Link Status

1: Valid link established

0: No valid link established

1: Jabber condition detected

0: No jabber condition detected

1: Extended register capability

0: Basic register capability only

Jabber Detect

Extended

Capability

This register indicates RTL8139C(L)+’s internal PHYceiver status, and medium mode.

32

2001/12/06

Rev.1.5

RTL8139C(L)+

6.21 Auto-negotiation Advertisement Register

(Offset 0066h-0067h, R/W)

Bit

Name

Description/Usage

Default/Attribute

15

NP

Next Page bit.

0, RO

0: Transmitting the primary capability data page

1: Transmitting the protocol specific data page

1: Acknowledge reception of link partner capability data word

1: Advertise remote fault detection capability

0: Do not advertise remote fault detection capability

Reserved

14

13

ACK

RF

0, RO

0, RW

12-11

10

-

Pause

1: flow control is supported by local node

0: flow control is not supported by local mode

The default value

comes from

EEPROM, RO

0, RO

9

8

T4

TXFD

TX

1: 100Base-T4 is supported by local node

0: 100Base-T4 not supported by local node

1: 100Base-TX full duplex is supported by local node

0: 100Base-TX full duplex not supported by local node

1: 100Base-TX is supported by local node

1, RW

7

0: 100Base-TX not supported by local node

6

10FD

10

1: 10Base-T full duplex supported by local node

0: 10Base-T full duplex not supported by local node

1: 10Base-T is supported by local node

1, RW

5

1, RW

0: 10Base-T not supported by local node

4-0

-

Selector

Binary encoded selector supported by this node. Currently only

CSMA/CD <00001> is specified. No other protocols are supported.

<00001>, RW

This register indicates Nway advertisement info of RTL8139C(L)+’s internal PHYceiver.

33

2001/12/06

Rev.1.5

RTL8139C(L)+

6.22 Auto-Negotiation Link Partner Ability Register

(Offset 0068h-0069h, R)

Bit

Name

Description/Usage

Default/Attribute

15

NP

Next Page bit.

0, RO

0: Transmitting the primary capability data page

1: Transmitting the protocol specific data page

1: Link partner acknowledges reception of local node’s capability

data word.

14

ACK

0, RO

13

12-11

10

RF

-

Pause

1: Link partner is indicating a remote fault

Reserved

0, RO

-

0, RO

1: Flow control is supported by link partner

0: Flow control is not supported by link partner

1: 100Base-T4 is supported by link partner

0: 100Base-T4 not supported by link partner

1: 100Base-TX full duplex is supported by link partner

0: 100Base-TX full duplex not supported by link partner

1: 100Base-TX is supported by link partner

0: 100Base-TX not supported by link partner

1: 10Base-T full duplex is supported by link partner

0: 10Base-T full duplex not supported by link partner

1: 10Base-T is supported by link partner

0: 10Base-T not supported by link partner

Link Partner's binary encoded node selector. Currently only

CSMA/CD <00001> is specified.

9

8

T4

TXFD

TX

0, RO

7

0, RO

6

10FD

10

0, RO

5

0, RO

4-0

Selector

<00000>, RO

When current medium mode is at UTP, this register shows the Nway Link partner’s ability.

6.23 Auto-negotiation Expansion Register

(Offset 006Ah-006Bh, R)

This register contains additional status of internal PHYceiver for NWay auto-negotiation.

Bit

15-5

4

Name

-

Description/Usage

Default/Attribute

Reserved, This bit is always set to 0.

-

MLF

Status indicating if a multiple link fault has occurred.

1: Fault occurred

0, RO

0: No fault occurred.

3

LP_NP_ABLE

Status indicating if the link partner supports Next Page negotiation.

1: Supported

0, RO

0: Not supported.

2

1

NP_ABLE

PAGE_RX

This bit indicates if the local node is able to send additional Next

Pages.

This bit is set when a new Link Code Word Page has been received.

The bit is automatically cleared when the auto-negotiation link

partner’s ability register (register 5) is read by management.

0, RO

0

LP_NW_ABLE 1: Link partner supports N-Way auto-negotiation.

0, RO

34

2001/12/06

Rev.1.5

RTL8139C(L)+

6.24 Disconnect Counter

(Offset 006Ch-006Dh, R)

This register is valid only when in UTP mode.

Bit

15-0

Name

DCNT

Description/Usage

This 16-bit counter increments by 1 for every disconnect event. It

rolls over when becomes full. It is cleared to zero by a read

command.

Default/Attribute

h'[0000],

R

6.25 False Carrier Sense Counter

(Offset 006Eh-006Fh, R)

This counter provides information required to implement the “False Carriers” attribute within the MAU managed object class of

Clause 30 of the IEEE 802.3u specification. This register is valid only when in UTP mode.

Bit

15-0

Name

FCSCNT

Description/Usage

This 16-bit counter increments by 1 for each false carrier event. It is

cleared to zero by a read command.

Default/Attribute

h'[0000],

R

6.26 NWay Test Register

(Offset 0070h-0071h, R/W)

This register is valid only when in UTP mode.

Bit

15-8

7

Name

-

Description/Usage

Default/Attribute

Reserved

-

NWLPBK

-

1: Set NWay to loopback mode.

0, RW

-

0, RW

0, RO

6-4

3

Reserved

ENNWLE

FLAGABD

FLAGPDF

FLAGLSC

1: LED0 Pin indicates linkpulse

2

1: Auto-neg experienced ability detect state

1: Auto-neg experienced parallel detection fault state

1: Auto-neg experienced link status check state

1

0

6.27 RX_ER Counter

(Offset 0072h-0073h, R)

This register is valid only when in UTP mode.

Bit

15-0

Name

RXERCNT

Description/Usage

This 16-bit counter increments by 1 for each valid packet received.

It is cleared to zero by a read command.

Default/Attribute

h'[0000],

R

35

2001/12/06

Rev.1.5

RTL8139C(L)+

6.28 CS Configuration Register

(Offset 0074h-0075h, R/W)

This register is valid only when in UTP mode.

Bit

15

Name

Testfun

-

Description/Usage

Default/Attribute

1: Auto-neg speeds up internal timer

0,WO

-

14-10

9

Reserved

LD

Active low TPI link disable signal. When low, TPI still transmits

link pulses and TPI stays in good link state.

The HEART BEAT function is only valid in 10Mbps mode.

1: HEART BEAT enable

1, RW

8

HEART BEAT

1, RW

0: HEART BEAT disable.

7

6

JBEN

1: Enable jabber function

1, RW

0: Disable jabber function

F_LINK_100

Used to login force good link in 100Mbps for diagnostic purposes.

1: DISABLE

0: ENABLE.

5

4

3

F_Connect

-

Con_status

Assertion of this bit forces the disconnect function to be bypassed.

Reserved

0, RW

-

0, RO

This bit indicates the status of the connection.

1: Valid connected link detected

0: Disconnected link detected

2

Con_status_En

Assertion of this bit configures LED1 pin to indicate connection

status.

0, RW

1

0

-

Reserved

Bypass Scramble

-

PASS_SCR

0, RW

6.29 Low Address of a Tx Descriptor with Tx DMA Ok

(Offset 0082h-0083h, R)

Bit

15-0

R/W

R

Symbol

_TDOKLAddr

Description

This is a 16-bit address indicating the low part address of a Tx

descriptor that has already asserted an interrupt of Tx DMA complete.

6.30 Flash Memory Read/Write Register (FLASH)

(Offset 00D4h-00D7h, R/W)

Bit

R/W

Symbol

Description

31-24

R/W

MD7-MD0

Flash Memory Data Bus: These bits set and reflect the state of the

MD7 - MD0 pins, during write and read process respectively.

Reserved

23-21

20

-

W

ROMCSB

OEB

Chip Select: This bit sets the state of the ROMCSB pin.

Output Enable: This bit sets the state of the OEB pin.

Write Enable: This bit sets the state of the WEB pin.

Enable software access to flash memory:

19

18

WEB

17

SWRWEn

0: Disable read/write access to flash memory via software

1: Enable read/write access to flash memory via software and disable

the EEPROM access during flash memory access via software

Flash Memory Address Bus: These bits set the state of the MA16-0

pins.

16-0

W

MA16-MA0

36

2001/12/06

Rev.1.5

RTL8139C(L)+

6.31 Configuration Register 5 (Config5)

(Offset 00D8h, R/W)

This register, unlike other Config registers, is not protected by 93C46 Command register. Therefore, there is no need to enable

Config register write prior to writing to Config5.

Bit

7

R/W

-

Symbol

-

Description

Reserved

6

R/W

BWF

Broadcast Wakeup Frame:

0: Disable Broadcast Wakeup Frame with mask bytes of only DID

field = FF FF FF FF FF FF.

1: Enable Broadcast Wakeup Frame with mask bytes of only DID

field = FF FF FF FF FF FF.

The power-on default value of this bit is 0.

5

4

3

R/W

MWF

UWF

Multicast Wakeup Frame:

0: Disable Multicast Wakeup Frame with mask bytes of only DID

field, which is a multicast address.

1: Enable Multicast Wakeup Frame with mask bytes of only DID

field, which is a multicast address.

The power-on default value of this bit is 0.

Unicast Wakeup Frame:

0: Disable Unicast Wakeup Frame with mask bytes of only DID field,

which is its own physical address.

1: Enable Unicast Wakeup Frame with mask bytes of only DID field,

which is its own physical address.

The power-on default value of this bit is 0.

FIFOAddrPtr

FIFO Address Pointer: (Realtek internal use only to test FIFO

SRAM)

0: Both Rx and Tx FIFO address pointers are updated in ascending

way from 0 and upwards. The initial FIFO address pointer is 0.

1: Both Rx and Tx FIFO address pointers are updated in a descending

method from 1FFh and downwards. The initial FIFO address

pointer is 1FFh.

This bit does not participate in the EEPROM auto-load. The FIFO

address pointers can not be reset, except initial power-on.

The power-on default value of this bit is 0.

Link Down Power Saving mode:

2

R/W

LDPS

1: Disable.

0: Enable. When cable is disconnected (Link Down), the analog part

will power down itself (PHY Tx part & part of twister)

automatically except PHY Rx part and part of twister to monitor

SD signal in case that cable is re-connected and Link should be

established again.

1

0

R/W

LANWake

PME_STS

LANWake Signal Enable/Disable:

1: Enable LANWake signal

0: Disable LANWake signal

PME_Status Bit: Always sticky; can be reset by PCI RST# and

software.

1: The PME_Status bit can be reset by PCI reset or by software.

0: The PME_Status bit can only be reset by software.

ꢂ

Config5 register, offset D8h: (SYM_ERR register is changed to Config5, the function of SYM_ERR register is no longer

supported by RTL8139C.)

The 3 bits (bit2-0) are auto-loaded from EEPROM Config5 byte to RTL8139C Config5 register.

37

2001/12/06

Rev.1.5

RTL8139C(L)+

6.32 Transmit Priority Polling Register (TPPoll)

(Offset 00D9h, R/W, C+ mode only)

Bit

7

R/W

W

Symbol

HPQ

Description

High Priority Queue Polling:

i. Write a 1 to this bit by software to notify the RTL8139C(L)+

that there is high priority packet(s) waiting to be transmitted.

ii. The RTL8139C(L)+ will clear this bit automatically after all

high priority packets have been transmitted.

iii. Writing 0 to this bit has no effect.

Normal Priority Queue Polling:

6

W

NPQ

i. Write a 1 to this bit by software to notify the RTL8139C(L)+ that

there is a normal priority packet(s) waiting to be transmitted.

ii. The RTL8139C(L)+ will clear this bit automatically after all

normal priority packets have been transmitted.

iii. Writing 0 to this bit has no effect.

5-1

0

-

W

-

Reserved

FSWInt

Forced Software Interrupt:

i. Writing a 1 to this bit will trigger an interrupt, and the _SWInt

bit (bit8, ISR, offset3Eh-3Fh) will set.

ii. The RTL8139C(L)+ will clear this bit automatically after the

_SWInt bit (bit8, ISR) is cleared.

iii. Writing 0 to this bit has no effect.

6.33 C+ Command Register (C+CR)

(Offset 00E0h-00E1h, R/W, C+ mode only)

This register is the key to entering C+ mode operation before configuring other C+ mode registers and descriptors. This register

is word access only, byte access to this register has no effect.

Recommendation to C+ mode programming: Enable C+ mode functions in C+CR register first, => Enable transmit/receive in

Command register (offset 37h), => Configure other related registers (ex. Descriptor start address, TCR, RCR, …).

Bit

15-9

8

R/W

Symbol

Description

-

Reserved

-

Reserved (Home LAN Enable, always 0)

Reserved

7

6

R/W

RxVLAN

Receive VLAN De-tagging Enable: (In C+ mode)

1: Enable; 0: Disable

5

4

R/W

RxChkSum

DAC

Receive Checksum Offload Enable: (In C+ mode)

1: Enable; 0: Disable

PCI Dual Address Cycle Enable: (In C+ mode)

1: Enable; 0: Disable

When set, the RTL8139C(L)+ will perform Tx/Rx DMA using PCI

Dual Address Cycle only when the High 32-bit buffer address is not

equal to 0.

3

R/W

MulRW

PCI Multiple Read/Write Enable: (In C+ mode)

1: Enable; 0: Disable

2

1

0

-

R/W

C+Rx

C+Tx

Receive Enable: (In C+ mode) 1: Enable; 0: Disable

Transmit Enable: (In C+ mode) 1: Enable; 0: Disable

38

2001/12/06

Rev.1.5

RTL8139C(L)+

6.34 Receive Descriptor Start Address Register (RDSAR)

(Offset 00E4h-00EBh, R/W, C+ mode only)

Bit

63-0

R/W

Symbol

RDSA

Description

Receive Descriptor Start Address: (64-bit address)

Bit[31:0]: Offset E7h-E4h, low 32-bit address.

Bit[63:32]: Offset EBh-E8h, high 32-bit address.

6.35 Early Transmit Threshold Register (ETThR)

(Offset 00ECh, R/W, C+ mode only)

Bit

7-6

R/W

Symbol

TestMode

Description

Test Mode: For RTL8139C(L)+ to operate normally, please set to

“Normal” mode. The Test1-3 modes are for testing only.

Bit[7:6] Mode

Description

(0,0)

(0,1)

Normal

Test1

RTL8139C(L)+ operation mode

Test mode 1: To test waveform’s rise

time and fall time.

(1,0)

(1,1)

Test2

Test3

Test mode 2: Internal test signals

output from Boot ROM interface.

Test mode 3: Receive signals output

from Boot ROM interface.

5-0

R/W

ETTh

Early Tx Threshold:

1. Specifies the threshold level in the Tx FIFO to begin the

transmission. When the byte count of the data in the Tx FIFO

reaches this level, (or the FIFO contains at least one complete

packet) the RTL8139C(L)+ will transmit this packet.

000000 = 8 bytes

2. These fields count from 000001 to 111111 in unit of 32 bytes.

3. This threshold must be avoided from exceeding 2K byte.

39

2001/12/06

Rev.1.5

RTL8139C(L)+

6.36 Function Event Register

(Offset 00F0h-00F3h, R/W)

Bit

31-16

15

R/W

-

Symbol

-

Description

Reserved

R/W

INTR

Interrupt: Set to 1 when INTR field in the Function Force Event

Register is set. Writing a 1 may clear this bit. Writing a 0 has no effect.

This bit must not be affected by RST# pin and software reset.

Reserved

General Wakeup: Set to 1 when the GWAKE field in the Function

Present State Register changes its state from 0 to 1. This bit can also be

set when the GWAKE bit of the Function Force Register is set.

Writing a 1 may clear this bit. Writing a 0 has no effect. This bit can

not be affected by the RST#.

14-5

4

-

R/W

GWAKE

3-0

-

Reserved

ꢂ

This register is valid only when Card_En=1 (bit3, Config3) and FuncRegEn=1 (bit1, Config3).

The Function Event (Offset F0h), Function Event Mask (Offset F4h), Function Present State (Offset F8h), and Function

Force Event (Offset FCh) registers have some corresponding fields with the same names. The GWAKE and INTR bits

of these registers reflect the wake-up event signaled on the SCTCSCHG pin. The operation of CSTCSCHG pin is

similar to PME# pin except that the CSTCSCHG pin is asserted high.

40

2001/12/06

Rev.1.5

RTL8139C(L)+

6.37 Function Event Mask Register

(Offset 00F4h-00F7h, R/W)

Bit

31-16

15

R/W

-

Symbol

-

Description

Reserved

R/W

INTR

Interrupt Mask: When cleared (0), setting of the INTR bit in either

the Function Present State Register or the Function Event Register will

neither cause assertion of the INT# signal while the CardBus PC Card

interface is powered up, nor cause a system Wakeup (CSTSCHG)

while the interface is powered off.

Setting this bit to 1 enables the INTR bit in both the Function Present

State Register and the Function Event Register to generate the INT#

signal (and the system Wakeup if the corresponding WKUP field in

this Function Event Mask Register is also set).

This bit is not affected by RST#.

14

R/W

WKUP

Wakeup Mask: When cleared (0), the Wakeup function is disabled,

i.e., the setting of this bit in the Function Event Register will not assert

the CSTSCHG signal.

Setting this bit to 1 enables the fields in the Function Event Register to

assert the CSTSCHG signal.

This bit is not affected by RST#.

13-5

4

-

Reserved

R/W

GWAKE

General Wakeup Mask: When cleared (0), setting this bit in the

Function Event Register will not cause the CSTSCHG pin to assert.

Setting this bit to 1 enables the GWAKE field in the Function Event

Register to assert CSTSCHG pin if bit14 of this register is also set.

This bit is not affected by RST#.

3-0

-

Reserved

ꢂ

This register is valid only when Card_En=1 (bit3, Config3) and FuncRegEn=1 (bit1, Config3).

41

2001/12/06

Rev.1.5

RTL8139C(L)+

6.38 Function Present State Register

(Offset 00F8h-00FBh, R)

Bit

31-16

15

R/W

Symbol

-

Description

-

Reserved

R

INTR

Interrupt: This bit is set when one of the ISR register bits has been set

to 1 and remains set (1), until all of the ISR register bits have been

cleared.

It is not affected by RST#.

14-5

4

-

R

-

Reserved

GWAKE

General Wakeup: This bit reflects the current state of the Wakeup

event(s), and is just like the PME_Status bit of the PMCSR register.

This bit remains set (1) until the PME_Status bit of the PMCSR

register is cleared.

It is not affected by RST#.

3-0

-

Reserved

ꢂ

This register is valid only when Card_En=1 (bit3, Config3) and FuncRegEn=1 (bit1, Config3).

This read-only register reflects the current state of the function.

42

2001/12/06

Rev.1.5

RTL8139C(L)+

6.39 Function Force Event Register/MII Register

(Offset 00FCh-00FFh, W)/(Offset 00FCh, R/W)

Bit

R/W

Symbol

Description

31

R

MII

1: The RTL8139C(L)+ processes current network traffic through its

external MII interface.

0: The RTL8139C(L)+ processes current network traffic through its

UTP interface (via its embedded phyceiver).

30

R

UTP

1: The RTL8139C(L)+ processes current network traffic through its

UTP interface (via its embedded phyceiver).

0: The RTL8139C(L)+ processes current network traffic through its

external MII interface.

29-28

27

-

Reserved

R/W

MDM

Management Data Mode: Setting this bit indicates that the MDIO

pin is output, and the state of the MDIO pin reflects with the MDO bit.

When this pin is reset, the MDIO pin is input. The MDI bit reflects the

state of the MDIO pin. The default value is "0".

MII Management Data-OUT: Used by the RTL8139C+ to write

data to the MDIO pin.

26

25

R/W

MDO

MDI

MII Management Data-IN: Used by the RTL8139C+ to read data

from the MDIO pin.

24

23-16

15

R/W

-

W

MDC

-

INTR

Management Data Clock: This bit reflects the state of the MDC pin.

Reserved

Interrupt: Writing a 1 sets the INTR bit in the Function Event

Register. However, the INTR bit in the Function Present State

Register is not affected and continues to reflect the current state of the

ISR register.

Writing a 0 to this bit has no effect.

14-5

4

-

W

-

Reserved

GWAKE

General Wakeup: Setting this bit to 1, sets the GWAKE bit in the

Function Event Register. However, the GWAKE bit in the Function

Present State Register is not affected and continues to reflect the

current state of the Wakeup request.

Writing a 0 to this bit has no effect.

Reserved

3-0

-

ꢂ

This register (except bits 31-30, and bits 27-24) is valid only when Card_En=1 (bit3, Config3) and FuncRegEn=1 (bit1,

Config3). The bit31-30, and bit27-24 are valid only when FuncRegEn=0 (bit1, Config3).

MII Register is valid (i.e. bits 31, 30, 27-24, are valid) only when current Medium select is set to Auto-Dectect or MII mode.

Bit7, and bit6 indicate current network traffic path that the RTL8139C(L)+ uses. When FuncRegEn=1 (bit1, Config3) in

CardBus mode, these 2 bits are reserved bits.

ꢂ

Bits 3-0 provide a path for software to access the MII registers of an external PHYceiver. When FuncRegEn=1 (bit1,

Config3) in CardBus mode, these 4 bits are reserved bits.

43

2001/12/06

Rev.1.5

RTL8139C(L)+

7. EEPROM Contents

(93C46 or 93C56)

The 93C46 is a 1K-bit EEPROM (the 93C56 is a 2K-bit EEPROM). Although it is actually addressed by words, its contents are

listed below by bytes for convenience. After the valid duration of the RSTB pin or auto-load command in 9346CR, the

RTL8139C(L) performs a series of EEPROM read operations from the 93C46 (93C56) address 00H to 31H.

ꢄ

It is suggested to obtain Realtek approval before changing the default settings of the EEPROM.

Bytes

00h

Contents

29h

Description

These 2 bytes contain the ID code word for the RTL8139C(L)+. The RTL8139C(L)+

will load the contents of the EEPROM into the corresponding location if the ID word

(8129h) is correct, otherwise, the Vendor ID and Device ID of the PCI configuration

space are hex 10EC and 8129 respectively.

01h

81h

02h-03h

04h-05h

06h-07h

08h-09h

0Ah

0Bh

0Ch

VID

DID

PCI Vendor ID, PCI configuration space offset 00h-01h.

PCI Device ID, PCI configuration space offset 02h-03h.

SVID

PCI Subsystem Vendor ID, PCI configuration space offset 2Ch-2Dh.

PCI Subsystem ID, PCI configuration space offset 2Eh-2Fh.

SMID

MNGNT

MXLAT

MSRBMCR

PCI Minimum Grant Timer, PCI configuration space offset 3Eh.

PCI Maximum Latency Timer, PCI configuration space offset 3Fh.

Bits 7-6 map to bits 7-6 of the Media Status register (MSR), Bits 5, 4, 3, 2, 0 map to bits

13, 12, 8, 3, 2 of the Basic Mode Control register (BMCR). If the network speed is set to

Auto-Detect mode (i.e. Nway mode), then Bit 1=0 means the local RTL8139C(L)+

supports flow control (IEEE 802.3x). In this case, Bit 10=1 in Auto-negotiation

Advertisement Register (offset 66h-67h).

Bit 1=1 means the local RTL8139C(L)+ does not support flow control. In this case, Bit

10=0 in Auto-negotiation Advertisement. This is because that there are Nway switch

hubs which keep sending flow control pause packets for no reason, if the link partner

supports Nway flow control.

Bit

7

6

5

4

3

2

1

-

0

Load-to TXFCE/L RXFC Spd_Set ANE MLinkP MFdupP

Duplex

Mode

dTXFCE

(bit7,

E

(bit13,

(bit12,

(bit3,

(bit2,

BMCR)

(bit6, BMCR )

MSR)

BMCR ) BMCR )

(bit8,

MSR)

BMCR)

0Dh

CONFIG3

RTL8139C(L)+ Configuration register 3, operational register offset 59H.

0Eh-13h

Ethernet ID

After auto-load command or hardware reset, the RTL8139C(L)+ loads the Ethernet ID

to IDR0-IDR5 of the RTL8139C(L)+'s I/O registers.

14h

15h

16h-17h

CONFIG0

CONFIG1

PMC

RTL8139C(L)+ Configuration register 0, operational registers offset 51h.

RTL8139C(L)+ Configuration register 1, operational registers offset 52h.

Reserved. Do not change this field without Realtek approval.

Power Management Capabilities. PCI configuration space address 52h and 53h.

Reserved

Reserved. Do not change this field without Realtek approval.

RTL8139C(L)+ Configuration register 4, operational registers offset 5Ah.

18h

19h

-

CONFIG4

1Ah-1Dh

PHY1_PARM_U Reserved. Do not change this field without Realtek approval.

PHY Parameter 1-U for RTL8139C. Operational registers of the RTL8139C(L)+ are

from 78h to 7Bh.

1Eh

PHY2_PARM_U Reserved. Do not change this field without Realtek approval.

PHY Parameter 2-U for RTL8139C. Operational register of the RTL8139C(L)+ is 80h.

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2001/12/06

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RTL8139C(L)+

1Fh

CONFIG_5

Do not change this field without Realtek approval.

Bit5, 3: Reserved.

Bit7: Medium1 at BMSR. Medium select bit1.

Bit6: Medium0 at BMSR. Medium select bit0.

Bit5: PCI multi-function enable.

Set to 1: Enable PCI multi-function capability. The RTL8139C+ can be a

multi-function device with an external PCI device at slave mode on the same

PCB, ex. an external software modem.

Set to 0: Disable PCI multi-function capability.

Bit4: Reserved

Bit2: Link Down Power Saving mode:

Set to 1: Disable.

Set to 0: Enable. When cable is disconnected(Link Down), the analog part will power

down itself (PHY Tx part & part of twister) automatically except PHY Rx part and

part of twister to monitor SD signal in case that cable is re-connected and Link should

be established again.

Bit1: LANWake signal Enable/Disable

Set to 1: Enable LANWake signal.

Set to 0: Disable LANWake signal.

Bit0: PME_Status bit property

Set to 1: The PME_Status bit can be reset by PCI reset or by software if

D3cold_support_PME is 0. If D3cold_support_PME=1, the PME_Status bit is a

sticky bit.

Set to 0: The PME_Status bit is always a sticky bit and can only be reset by software.

Reserved. Do not change this field without Realtek approval.

Twister Parameter U for RTL8139C. Operational registers of the RTL8139C(L)+ are

7Ch-7Fh.

Reserved. Do not change this field without Realtek approval.

Twister Parameter T for RTL8139C. Operational registers of the RTL8139C(L)+ are

7Ch-7Fh.

20h-23h

24h-27h

28h-2Bh

2Ch

TW_PARM_U

TW_PARM_T

PHY1_PARM_T Reserved. Do not change this field without Realtek approval.

PHY Parameter 1-T for RTL8139C. Operational registers of the RTL8139C(L)+ are

from 78h to 7Bh.

PHY2_PARM_T Reserved. Do not change this field without Realtek approval.

PHY Parameter 2-T for RTL8139C. Operational register of the RTL8139C(L)+ is 80h.

2Dh-2Fh

30h-31h

-

Reserved.

CISPointer

Reserved. Do not change this field without Realtek approval.

CIS Pointer.

32h-33h

CheckSum

Reserved. Do not change this field without Realtek approval.

Checksum of the EEPROM content.

34h-3Eh

3Fh

-

Reserved. Do not change this field without Realtek approval.

PXE ROM code parameter.

PXE_Para

40h-7Fh

80h-FFh

VPD_Data

CIS_Data

VPD data field. Offset 40h is the start address of the VPD data.

CIS data field. Offset 80h is the start address of the CIS data. (93C56 only).

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RTL8139C(L)+

7.1 Summary of EEPROM Registers

Offset

Name

Type

Bit7

Bit6

Bit5

Bit4

Bit3

Bit2

Bit1

Bit0

00h-05h IDR0 – IDR5 R/W*

51h

52h

58h

63H

59h

CONFIG0

CONFIG1

R

-

BS2

-

BS1

-

VPD

BS0

-

PMEN

*

-

W

R

LEDS1

TxFCE

LEDS0 DVRLOAD LWACT MEMMAP IOMAP

LEDS0 DVRLOAD LWACT

RxFCE

*

-

W

R

-

*

W

R

MSRBMCR

CONFIG3

-

Spd_Set

Magic

ANE

-

FUDUP

*

W

R

GNTDel PARM_EN

LinkUp CardB_En CLKRU FuncReg FBtBEn

N_En

-

LWPTN

En

-

*

-

PARM_EN

-

Magic

-

LinkUp

LWPME

-

W

5Ah

CONFIG4

* RxFIFO

R/W

AutoClr

78h-7Bh PHY1_PARM R/W^**

7Ch-7Fh TW1_PARM R/W^**

TW2_PARM

32 bit Read Write

8 bit Read Write

80h

PHY2_PARM R/W^**

D8h

CONFIG5

*

-

LDPS LANWa PME_ST

R/W

ke

-

S

-

E0h

C+CR

R/W

DAC

-

*

The registers marked with type = W can be written only if bits EEM1=EEM0=1.

** The registers marked with type = W can be written only if bits EEM1=EEM0=1 and CONFIG3<PARM_EN> = 0.

*

**

7.2 Summary of EEPROM Power Management Registers

Configuration Name Type

Space offset

Bit7

Bit6

Bit5

Bit4

Bit3

Bit2

Bit1

Bit0

52h

53h

PMC

R

Aux_I_b1 Aux_I_b0

DSI

Reserved PMECLK

Version

D1

PME_D3_coldPME_D3_hotPME_D2 PME_D1 PME_D0

D2

Aux_I_b2

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2001/12/06

Rev.1.5

RTL8139C(L)+

8. PCI Configuration Space Registers

8.1 PCI Bus Interface

The RTL8139C(L)+ implements the PCI bus interface as defined in the PCI Local Bus Specifications Rev. 2.2. When internal

registers are being accessed, the RTL8139C(L)+ acts as a PCI target (slave mode). When accessing host memory for descriptor

or packet data transfer, the RTL8139C(L)+ acts as a PCI bus master.

All of the required pins and functions are implemented in the RTL8139C(L)+ as well as the optional pin, INTAB for support of

interrupt requests is implemented as well. For more information, refer to the PCI Local Bus Specifications Rev. 2.2, December

18, 1998.

8.1.1 Byte Ordering

The RTL8139C(L)+ is permanently configured to order the bytes of data on the AD[31:0] bus to conform to little-endian

ordering. Byte ordering affects bus mastered packet data transfers in 32-bit mode. Register information remains bit aligned (i.e.

AD[31] maps to bit 31 in any register space, AD[0] maps to bit 0, etc.) when registers are accessed with 32-bit operations. Bus

mastered transfers of buffer descriptor information also remain bit aligned.

Byte orientation for receive and transmit data and descriptors in system memory are done as follows:

31

24 23

16 15

8 7

0

Byte 3

Byte 2

Byte 1

Byte 0

C/BE[3]

(MSB)

C/BE[2]

C/BE[1]

C/BE[0]

(LSB)

Little-Endian Byte Ordering

8.1.2 Interrupt Control

Interrupts are performed by asynchronously asserting the INTAB pin. This pin is an open drain output. The source of the

interrupt can be determined by reading the Interrupt Status Register (ISR). One or more bits in the ISR will be set, denoting all

currently pending interrupts. Masking of specific interrupts can be accomplished by using the Interrupt Mask Register (IMR).

This allows the system to defer interrupt processing as needed.

8.1.3 Latency Timer

The PCI Latency Timer described in MXLAT defines the maximum number of bus clocks that the device will hold the bus. Once

the device gains control of the bus and issues FRAMEB, the Latency Timer will begin counting down. If GNTB is deasserted

before the RTL8139C(L)+ has finished with the bus, the device will maintain ownership of the bus until the timer reaches zero

(or has finished the bus transfer).

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2001/12/06

Rev.1.5

RTL8139C(L)+

8.1.4 32-Bit Data Operation

The RTL8139C(L)+ supports only 32-bit data access.

8.1.5 64-Bit Addressing

The RTL8139C(L)+ supports 64-bit addressing (Dual Address Cycle) as a bus master for transferring descriptor and packet data

information. This mode can be enabled or disabled through software.

8.2 Bus Operation

8.2.1 Target Read

A Target Read operation starts with the system generating FRAMEB, Address, and either an IO read (0010b) or Memory Read

(0110b) command. If the 32-bit address on the address bus matches the IO address range specified in IOAR (for I/O reads) or the

memory address range specified in MEM (for memory reads), the RTL8139C(L)+ will generate DEVSELB 2 clock cycles later

(medium speed). The system must tri-state the Address bus, and convert the C/BE bus to byte enables, after the address cycle. On

the 2nd cycle after the assertion of DEVSELB, all 32-bits of data and TRDYB will become valid. If IRDYB is asserted at that

time, TRDYB will be forced HIGH on the next clock for 1 cycle, and then tri-stated.

If FRAMEB is asserted beyond the assertion of IRDYB, the RTL8139C(L)+ will still make data available as described above,

but will also issue a Disconnect. That is, it will assert the STOPB signal with TRDYB. STOPB will remain asserted until

FRAMEB is detected as deasserted.

Target Read Operation

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2001/12/06

Rev.1.5

RTL8139C(L)+

8.2.2 Target Write

A Target Write operation starts with the system generating FRAMEB, Address, and Command (0011b or 0111b). If the upper 24

bits on the address bus match IOAR (for I/O reads) or MEM (for memory reads), the RTL8139C(L)+ will generate DEVSELB

2 clock cycles later. On the 2nd cycle after the assertion of DEVSELB, the device will monitor the IRDYB signal. If IRDYB is

asserted at that time, the RTL8139C(L)+ will assert TRDYB. On the next clock the 32-bit double word will be latched in, and

TRDYB will be forced HIGH for 1 cycle and then tri-stated. Target write operations must be 32-bits wide.

If FRAMEB is asserted beyond the assertion of IRDYB, the RTL8139C(L)+ will still latch the first double word as described

above, but will also issue a Disconnect. That is, it will assert the STOPB signal with TRDYB. STOPB will remain asserted until

FRAMEB is detected as deasserted.

Target Write Operation

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2001/12/06

Rev.1.5

RTL8139C(L)+

8.2.3 Master Read

A Master Read operation starts with the RTL8139C(L)+ asserting REQB. If GNTB is asserted within 2 clock cycles, FRAMEB,

Address, and Command will be generated 2 clocks after REQB (Address and FRAMEB for 1 cycle only). If GNTB is asserted 3

cycles or later, FRAMEB, Address, and Command will be generated on the clock following GNTB.

The device will wait for 8 cycles for the assertion of DEVSELB. If DEVSELB is not asserted within 8 clocks, the device will

issue a master abort by asserting FRAMEB HIGH for 1 cycle, and IRDYB will be forced HIGH on the following cycle. Both

signals will become tri-state on the cycle following their deassertion.

On the clock edge after the generation of Address and Command, the address bus will become tri-state, and the C/BE bus will

contain valid byte enables. On the clock edge after FRAMEB was asserted, IRDYB will be asserted (and FRAMEB will be

deasserted if this is to be a single read operation). On the clock where both TRDYB and DEVSELB are detected as asserted, data

will be latched in (and the byte enables will change if necessary). This will continue until the cycle following the deassertion of

FRAMEB.

On the clock where the second to last read cycle occurs, FRAMEB will be forced HIGH (it will be tri-stated 1 cycle later). On the

next clock edge that the device detects TRDYB asserted, it will force IRDYB HIGH. It, too, will be tri-stated 1 cycle later. This

will conclude the read operation. The RTL8139C(L)+ will never force a wait state during a read operation.

Master Read Operation

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2001/12/06

Rev.1.5

RTL8139C(L)+

8.2.4 Master Write

A Master Write operation starts with the RTL8139C(L)+ asserting REQB. If GNTB is asserted within 2 clock cycles, FRAMEB,

Address, and Command will be generated 2 clocks after REQB (Address and FRAMEB for 1 cycle only). If GNTB is asserted 3

cycles or later, FRAMEB, Address, and Command will be generated on the clock following GNTB.

The device will wait for 8 cycles for the assertion of DEVSELB. If DEVSELB is not asserted within 8 clocks, the device will

issue a Master Abort by asserting FRAMEB HIGH for 1 cycle. IRDYB will be forced HIGH on the following cycle. Both signals

will become tri-state on the cycle following their deassertion.

On the clock edge after the generation of Address and Command, the data bus will become valid, and the C/BE bus will contain

valid byte enables. On the clock edge after FRAMEB was asserted, IRDYB will be asserted (and FRAMEB will be deasserted if

this is to be a single read operation). On the clock where both TRDYB and DEVSELB are detected as asserted, valid data for the

next cycle will become available (and the byte enables will change if necessary). This will continue until the cycle following the

deassertion of FRAMEB.

On the clock where the second to last write cycle occurs, FRAMEB will be forced HIGH (it will be tri-stated 1 cycle later). On

the next clock edge that the device detects TRDYB asserted, it will force IRDYB HIGH. It, too, will be tri-stated 1 cycle later.

This will conclude the write operation. The RTL8139C(L)+ will never force a wait state during a write operation.

Master Write Operation

8.2.5 Configuration Access

Configuration register accesses are similar to target reads and writes in that they are single data word transfers and are initiated

by the system. For the system to initiate a Configuration access, it must also generate IDSEL as well as the correct Command

(1010b or 1011b) during the Address phase. The RTL8139C(L)+ will respond as it does during Target operations. Configuration

reads must be 32-bits wide, but writes may access individual bytes.

8.3 Packet Buffering

The RTL8139C(L)+ incorporates two independent FIFOs for transferring data to/from the system interface and from/to the

network. The FIFOs, providing temporary storage of data freeing the host system from the real-time demands of the network.

The way in which the FIFOs are emptied and filled is controlled by the FIFO threshold values in the Transmit Configuration and

Receive Configuration registers. These values determine how full or empty the FIFOs must be before the device requests the

bus. Additionally, there is a threshold value that determines how full the transmit FIFO must be before beginning transmission.

Once the RTL8139C(L)+ requests the bus, it will attempt to empty or fill the FIFOs as allowed by the respective MXDMA

settings in the Transmit Configuration and Receive Configuration registers.

The RTL8139C(L)+ uses two different modes of buffer management for transmission and reception of data. These two modes

are C and C+.

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2001/12/06

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RTL8139C(L)+

8.3.1 Transmit Buffer Manager

C Mode:

The host CPU initiates a transmit by storing an entire packet of data in one of the descriptors in the main memory, and those

descriptors should be double-word alignment. When the entire packet has been transferred to the Tx buffer, the RTL8139C(L)+

is instructed to move the data from the Tx buffer to the internal transmit FIFO in PCI bus master mode. When the transmit FIFO

contains a complete packet or is filled to the programmed threshold level, the RTL8139C(L)+ begins packet transmission. Please

refer to the Realtek RTL8139 series programming guide for detailed information.

C+ Mode:

The buffer management scheme used on the RTL8139C(L)+ allows quick, simple and efficient use of the frame buffer memory.

The buffer management scheme uses separate buffers and descriptors for packet information. This allows effective transfers of

data to the transmit buffer manager by simply transferring the descriptor information to the transmit queue.

The Tx Buffer Manager DMAs packet data from PCI memory space and places it in the 2KB transmit FIFO, and pulls data from

the FIFO to send to the Tx MAC. Multiple packets may be present in the FIFO, allowing packets to be transmitted with minimum

interframe gap. The way in which the FIFO is emptied and filled is controlled by the ETTH (Early Transmit Threshold) and

RXFTH (Rx FIFO Threshold) values. Additionally, once the RTL8139C(L)+ requests the bus, it will attempt to fill the FIFO as

allowed by the MXDMA setting.

The Tx Buffer Manager process also supports priority queuing of transmit packets. It handles this by drawing from four separate

descriptor lists to fill the internal FIFO. If packets are available in the higher priority queues, they will be loaded into the FIFO

before those of lower priority.

8.3.2 Receive Buffer Manager

C Mode:

The incoming packet is placed in the Rx FIFO of the RTL8139C(L)+. Concurrently, the RTL8139C(L)+ performs address

filtering of multicast packets according to its hash algorithms. When the amount of data in the Rx FIFO reaches the level defined

in the Receive Configuration Register (RCR), the RTL8139C(L)+ requests the PCI bus to begin transferring the data to the Rx

buffer in PCI bus master mode. The Rx buffer should be pre-allocated and indicated in RCR before packet reception. All

received packets stored in Rx buffer, including Rx header and 4-byte CRC, are double-word alignment. I.e., each received

packet is placed at next available double-word alignment address after the last received packet in Rx buffer. Please refer to the

Realtek RTL8139 series programming guide for detailed information.

C+ Mode:

The Rx Buffer Manager uses the same buffer management scheme as used for transmits. The Rx Buffer Manager retrieves

packet data from the Rx MAC and places it in the 2KB receive data FIFO, and pulls data from the FIFO for DMA to PCI memory

space. Similar to the transmit FIFO, the receive FIFO is controlled by the FIFO threshold value in RXFTH. This value

determines the number of long words written into the FIFO from the MAC unit before a DMA request for system memory

occurs. Once the RTL8139C(L)+ gets the bus, it will continue to transfer the long words from the FIFO until the data in the FIFO

is less than one long word, or has reached the end of the packet, or the max DMA burst size is reached , as set in MXDMA.

8.3.3 Packet Recognition

The Rx packet filter and recognition logic allows software to control which packets are accepted, based on destination address

and packet type. Address recognition logic includes support for broadcast, multicast hash, and unicast addresses. The packet

recognition logic includes support for WOL, Pause, and programmable pattern recognition.

52

2001/12/06

Rev.1.5

RTL8139C(L)+

8.4 PCI Configuration Space Table

No.

00h

01h

02h

03h

Name

Type

R

Bit7

Bit6

Bit5

Bit4

VID4

VID12

DID4

DID12

MWIEN

0

Bit3

Bit2

VID2

VID10

DID2

DID10

Bit1

VID1

VID9

DID1

DID9

Bit0

VID0

VID8

DID0

DID8

IOEN

VID

VID7

VID6

VID5

VID3

R

VID15

VID14

VID13

VID11

DID

R

DID7

DID6

DID5

DID3

R

DID15

DID14

DID13

DID11

04h Command

05h

R

0

PERRSP

0

-

0

BMEN MEMEN

W

-

PERRSP

-

R

0

-

0

FBTBEN SERREN

W

-

0

SERREN

06h

07h

Status

R

FBBC

0

NewCap

0

R

DPERR

SSERR

RMABT RTABT

STABT

DST1

DST0

DPD

W

DPERR

SSERR

STABT

-

DPD

08h Revision ID

R

0

09h

0Ah

0Bh

0Ch

0Dh

PIFR

SCR

BCR

CLS

LTR

R

0

R

0

R

0

1

0

R/W

R

0

LTR0

0

LTR7

LTR6

LTR5

LTR4

LTR3

LTP2

LTR1

W

LTR7

LTR6

LTR5

LTR4

LTR3

LTP2

LTR1

0Eh

0Fh

10h

HTR

BIST

IOAR

R

0

-

0

-

0

-

0

-

0

R

0

R

0

-

IOIN

-

W

-

11h

12h

13h

R/W

R

IOAR15

IOAR23

IOAR31

0

IOAR14

IOAR22

IOAR30

0

IOAR13 IOAR12 IOAR11 IOAR10

IOAR9

IOAR8

IOAR21 IOAR20 IOAR19 IOAR18 IOAR17 IOAR16

IOAR29 IOAR28 IOAR27 IOAR26 IOAR25 IOAR24

14h MEMAR

0

-

0

-

0

-

0

-

0

-

MEMIN

-

MEM8

W

-

15h

16h

R/W

MEM15

MEM23

MEM31

MEM14

MEM22

MEM30

MEM13 MEM12 MEM11 MEM10

MEM9

MEM21 MEM20 MEM19 MEM18 MEM17 MEM16

MEM29 MEM28 MEM27 MEM26 MEM25 MEM24

RESERVED

17h

18h-27h

28h-2Bh

2Ch

2Dh

2Eh

2Fh

30h

CISPtr

SVID

Cardbus CIS Pointer

SVID5

R

SVID7

SVID15

SMID7

SMID15

0

SVID6

SVID14

SMID6

SMID14

0

SVID4

SVID3

SVID2

SVID1

SVID0

SVID8

SMID0

SMID8

BROMEN

0

SVID13 SVID12 SVID11 SVID10

SMID5 SMID4 SMID3 SMID2

SVID9

SMID

R

SMID1

R

SMID13 SMID12 SMID11 SMID10

SMID9

BMAR

R

0

-

0

-

0

-

0

-

0

-

0

-

0

-

W

R

-

31h

BMAR15 BMAR14 BMAR13 BMAR12 BMAR11

W

-

32h

33h

34h

R/W BMAR23 BMAR22 BMAR21 BMAR20 BMAR19 BMAR18 BMAR17 BMAR16

R/W BMAR31 BMAR30 BMAR29 BMAR28 BMAR27 BMAR26 BMAR25 BMAR24

Cap_Ptr

R

0

1

0

1

0

53

2001/12/06

Rev.1.5

RTL8139C(L)+

35h-3Bh

3Ch

RESERVED

ILR5 ILR4

ILR

IPR

R/W

R

IRL7

ILR6

ILR3

ILR2

ILR1

ILR0

3Dh

0

1

0

3Eh MNGNT

R

1

0

3Fh

MXLAT

R

40h–4Fh

RESERVED

50h

51h

52h

53h

54h

PMID

NextPtr

PMC

R

0

DSI

0

1

0

R

Aux_I_b1 Aux_I_b0

Reserved PMECLK

Version

D1

R

PME_D3_coldPME_D3_hotPME_D2 PME_D1 PME_D0

D2

0

-

Aux_I_b2

PMCSR

R

0

-

0

-

0

-

0

-

0

-

Power State

-

W

R

55h

PME_Status

PME_En

W

56h–5Fh

60h

RESERVED

0

VPDID

NextPtr

R

0

1

0

1

0

61h

62h Flag VPD R/W VPDADDR VPDADDR VPDADD VPDADD VPDADD VPDADD VPDADD VPDADD

Address

7

Flag

6

R5

R4

R3

R2

R1

R0

63h

R/W

VPDADDR VPDADD VPDADD VPDADD VPDADD VPDADD VPDADD

14

R13

Data5

R12

Data4

R11

Data3

Data11

Data19

Data27

R10

Data2

Data10

Data18

Data26

R9

R8

64h VPD Data R/W

Data7

Data15

Data23

Data31

Data6

Data14

Data22

Data30

Data1

Data9

Data17

Data25

Data0

Data8

Data16

Data24

65h

66h

R/W

Data13

Data21

Data29

Data12

Data20

Data28

67h

68h-FFh

RESERVED

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2001/12/06

Rev.1.5

RTL8139C(L)+

8.5 PCI Configuration Space Functions

The PCI configuration space is intended for configuration, initialization, and catastrophic error handling functions. The

functions of the configuration space for the RTL8139C(L)+ are described below.

VID:

Vendor ID. This field will be set to a value corresponding to PCI Vendor ID in the external EEPROM. If there is no

EEPROM, this field will default to a value of 10ECh which is Realtek Semiconductor's PCI Vendor ID.

DID:

Device ID. This field will be set to a value corresponding to PCI Device ID in the external EEPROM. If there is no

EEPROM, this field will default to a value of 8129h.

Command: The command register is a 16-bit register used to provide coarse control over a device's ability to generate and

respond to PCI cycles.

Bit

15-10

9

Symbol

-

Description

Reserved

FBTBEN

Fast Back-To-Back Enable: Config3<FBtBEn>=0:Read as 0. Write operation has no effect. The

RTL8139C(L)+ will not generate Fast Back-to-back cycles. When Config3<FbtBEn>=1, This read/write

bit controls whether or not a master can do fast back-to-back transactions to different devices.

Initialization software will set the bit if all targets are fast back-to-back capable. A value of 1 means the

master is allowed to generate fast back-to-back transaction to different agents. A value of 0 means fast

back-to-back transactions are only allowed to the same agent. This bit’s state after RST# is 0.

System Error Enable: When set to 1, the RTL8139C(L)+ asserts the SERRB pin when it detects a

parity error on the address phase (AD<31:0> and CBEB<3:0> ).

8

7

6

SERREN

ADSTEP

PERRSP

Address/Data Stepping: Read as 0, write operation has no effect. The RTL8139C(L)+ never make

address/data stepping.

Parity Error Response: When set to 1, the RTL8139C(L)+ will assert the PERRB pin on the

detection of a data parity error when acting as the target, and will sample the PERRB pin as the master.

When set to 0, any detected parity error is ignored and the RTL8139C(L)+ continues normal

operation.

Parity checking is disabled after hardware reset (RSTB).

VGA palette SNOOP: Read as 0, write operation has no effect.

5

4

VGASNOOP

MWIEN

Memory Write and Invalidate Cycle Enable: This is an enable bit for using Memory Write and

Invalidate command. When this bit is 1, the RTL8139C(L)+ as a master may generate the command.

When this bit is 0, the RTL8139C(L)+ may generate Memory Write command instead. State after PCI

RSTB is 0.

3

2

SCYCEN

BMEN

Special Cycle Enable: Read as 0, write operation has no effect. The RTL8139C(L)+ ignores all

special cycle operations.

Bus Master Enable: When set to 1, the RTL8139C(L)+ is capable of acting as a bus master. When set

to 0, it is prohibited from acting as a PCI bus master.

For normal operations, this bit must be set by the system BIOS.

1

0

MEMEN

IOEN

Memory Space Access: When set to 1, the RTL8139C(L)+ responds to memory space accesses.

When set to 0, the RTL8139C(L)+ ignores memory space accesses.

I/O Space Access: When set to 1, the RTL8139C(L)+ responds to IO space access. When set to 0, the

RTL8139C(L)+ ignores I/O space accesses.

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Status: The status register is a 16-bit register used to record status information for PCI bus related events. Reads to this register

behave normally. Writes are slightly different in that bits can be reset, but not set.

Bit

Symbol

Description

15

DPERR

Detected Parity Error: When set indicates that the RTL8139C(L)+ detected a parity error, even if

parity error handling is disabled in command register PERRSP bit.

14

13

SSERR

RMABT

RTABT

STABT

DST1-0

DPD

Signaled System Error: When set indicates that the RTL8139C(L)+ asserted the system error pin,

SERRB. Writing a 1 clears this bit to 0.

Received Master Abort: When set indicates that the RTL8139C(L)+ terminated a master transaction

with master abort. Writing a 1 clears this bit to 0.

12

Received Target Abort: When set indicates that the RTL8139C(L)+ master transaction was terminated

due to a target abort. Writing a 1 clears this bit to 0.

11

Signaled Target Abort: Set to 1 whenever the RTL8139C(L)+ terminates a transaction with target

abort. Writing a 1 clears this bit to 0.

10-9

8

Device Select Timing: These bits encode the timing of DEVSELB. They are set to 01b (medium),

indicating the RTL8139C(L)+ will assert DEVSELB two clocks after FRAMEB is asserted.

Data Parity error Detected: This bit sets when the following conditions are met:

• The RTL8139C(L)+ asserts parity error(PERRB pin) or it senses the assertion of PERRB pin by

another device.

• The RTL8139C(L)+ operates as a bus master for the operation that caused the error.

• The Command register PERRSP bit is set.

Writing a 1 clears this bit to 0.

7

6

FBBC

UDF

Fast Back-To-Back Capable: Config3<FbtBEn>=0, Read as 0, write operation has no effect.

Config3<FbtBEn>=1, Read as 1.

User Definable Features Supported: Read as 0, write operation has no effect. The RTL8139C(L)+

does not support UDF.

5

66MHz

NewCap

-

66 MHz Capable: Read as 0, write operation has no effect. The RTL8139C(L)+ has no 66MHz

capability.

4

New Capability: Config3<PMEn>=0, Read as 0, write operation has no effect. Config3<PMEn>=1,

Read as 1.

Reserved

0-3

RID: Revision ID Register: An 8-bit register that specifies the RTL8139C(L)+ controller revision number.

PIFR: Programming Interface Register. An 8-bit register that identifies the programming interface of the RTL8139C(L)+

controller. The PCI specifications, revision 2.1, do not define any other specific values for network devices. So PIFR = 00h.

SCR: Sub-Class Register. An 8-bit register that identifies the function of the RTL8139C(L)+. SCR = 00h indicates that the

RTL8139C(L)+ is an Ethernet controller.

BCR: Base-Class Register. An 8-bit register that broadly classifies the function of the RTL8139C(L)+. BCR = 02h indicates

that the RTL8139C(L)+ is a network controller.

CLS: Cache Line Size. Specifies, in units of 32-bit words (double-words), the system cache line size. The RTL8139C(L)+

supports cache line size of 8, and 16 longwords (DWORDs). The RTL8139C(L)+ uses Cache Line Size for PCI

commands

that

are

cache

oriented,

such

as memory-read-line, memory-read-multiple, and

memory-write-and-invalidate.

LTR: Latency Timer Register. Specifies, in units of PCI bus clocks, the value of the latency timer of the RTL8139C(L)+.

When the RTL8139C(L)+ asserts FRAMEB, it enables its latency timer to count. If the RTL8139C(L)+ deasserts

FRAMEB prior to count expiration, the content of the latency timer is ignored. Otherwise, after the count expires, the

RTL8139C(L)+ initiates transaction termination as soon as its GNTB is deasserted. Software is able to read or write,

and the default value is 00H.

HTR: Header Type Register. Reads will return a 0, writes are ignored.

BIST: Built-in Self Test. Reads will return a 0, writes are ignored.

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IOAR: This register specifies the BASE IO address which is required to build an address map during configuration. It also

specifies the number of bytes required as well as an indication that it can be mapped into IO space.

Bit

Symbol

Description

31-8 IOAR31-8

BASE IO Address: This is set by software to the Base IO address for the operational register map.

7-2

IOSIZE

Size Indication: Read back as 0. This allows the PCI bridge to determine that the RTL8139C(L)+

requires 256 bytes of IO space.

Reserved

1

0

-

IOIN

IO Space Indicator: Read only. Set to 1 by the RTL8139C(L)+ to indicate that it is capable of being

mapped into IO space.

MEMAR: This register specifies the base memory address for memory accesses to the RTL8139C(L)+ operational registers.

This register must be initialized prior to accessing any of the RTL8139C(L)+'s registers with memory access.

Bit

31-8

7-4

Symbol

MEM31-8

MEMSIZE

Description

Base Memory Address: This is set by software to the base address for the operational register map.

Memory Size: These bits return 0, which indicates that the RTL8139C(L)+ requires 256 bytes of

Memory Space.

3

2-1

MEMPF

MEMLOC

Memory Prefetchable: Read only. Set to 0 by the RTL8139C(L)+.

Memory Location Select: Read only. Set to 0 by the RTL8139C(L)+. This indicates that the base

register is 32-bit wide and can be placed anywhere in the 32-bit memory space.

Memory Space Indicator: Read only. Set to 0 by the RTL8139C(L)+ to indicate that it is capable of

being mapped into memory space.

0

MEMIN

CISPtr: CardBus CIS Pointer. This field is valid only when CardB_En (bit3, Config3) = 1. The value of this register is

auto-loaded from 93C46 or 93C56 (from offset 30h-31h).

-

Bit 2-0: Address Space Indicator

Bit2-0

0

Meaning

Not supported. (CIS begins in device-dependent configuration space.)

The CIS begins in the memory address governed by one of the six Base

Address Registers. Ex., if the value is 2, then the CIS begins in the memory

address space governed by Base Address Register 2.

The CIS begins in the Expansion ROM space.

1-6

7

-

Bit27-3: Address Space Offset

Bit31-28: ROM Image number

Bit2-0

Space Type

Configuration space

Memory space

Address Space Offset Values

0

Not supported.

X; 1≤X≤6

0h≤value≤FFFF FFF8h. This is the offset into the memory address space

governed by Base Address Register X. Adding this value to the value in the

Base Address Register gives the location of the start of the CIS. For

RTL8139C(L)+, the value is 100h.

7

Expansion ROM

0≤image number≤Fh, 0h≤value≤0FFF FFF8h. This is the offset into the

expansion ROM address space governed by the Expansion ROM Base

Register. The image number is in the uppermost nibble of the CISPtr

register. The value consists of the remaining bytes. For RTL8139C(L)+,

the image number is 0h.

This read-only register points to where the CIS begins, in one of the following spaces:

i.

Memory space --- The CIS may be in any of the memory spaces from offset 100h and up after being

auto-loaded from 93C56. The CIS is stored in 93C56 EEPROM physically from offset 80h-FFh.

Expansion ROM space --- The CIS is stored in expansion ROM physically within the 128KB max.

ii.

SVID: Subsystem Vendor ID. This field will be set to a value corresponding to PCI Subsystem Vendor ID in the external

EEPROM. If there is no EEPROM, this field will default to a value of 10ECh which is Realtek Semiconductor's PCI

Subsystem Vendor ID.

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SMID: Subsystem ID. This field will be set to value corresponding to PCI Subsystem ID in the external EEPROM. If there is

no EEPROM, this field will default to a value of 8129h.

BMAR: This register specifies the base memory address for memory accesses to the RTL8139C(L)+ operational registers.

This register must be initialized prior to accessing any RTL8139C(L)+'s register with memory access.

Bit

Symbol

Description

31-18 BMAR31-18 Boot ROM Base Address

17-11

ROMSIZE

These bits indicate how many Boot ROM spaces to be supported.

The Relationship between Config 0 <BS2:0> and BMAR17-11 is as follows:

BS2 BS1 BS0 Description

0

1

0

1

0

1

0

1

0

1

0

1

0

1

No Boot ROM, BROMEN=0 (R)

8K Boot ROM, BROMEN (R/W), BMAR12-11 = 0 (R), BMAR17-13 (R/W)

16K Boot ROM, BROMEN (R/W), BMAR13-11 = 0 (R), BMAR17-14 (R/W)

32K Boot ROM, BROMEN (R/W), BMAR14-11 = 0 (R), BMAR17-15 (R/W)

64K Boot ROM, BROMEN (R/W), BMAR15-11 = 0 (R), BMAR17-16 (R/W)

128K Boot ROM, BROMEN(R/W), BMAR16-11=0 (R), BMAR17 (R/W)

unused

10-1

0

-

Reserved (read back 0)

BROMEN

Boot ROM Enable: This is used by the PCI BIOS to enable accesses to Boot ROM.

ILR:

Interrupt Line Register. An 8-bit register used to communicate with the routing of the interrupt. It is written by the

POST software to set interrupt line for the RTL8139C(L)+.

IPR:

Interrupt Pin Register. An 8-bit register indicating the interrupt pin used by the RTL8139C(L)+. The

RTL8139C(L)+ uses INTA interrupt pin. Read only. IPR = 01H.

MNGNT: Minimum Grant Timer: Read only. Specifies how long a burst period the RTL8139C(L)+ needs at 33 MHz clock

rate in units of 1/4 microsecond. This field will be set to a value from the external EEPROM. If there is no EEPROM,

this field will default to a value of 20h.

MXLAT: Maximum Latency Timer: Read only. Specifies how often the RTL8139C(L)+ needs to gain access to the PCI bus in

unit of 1/4 microsecond. This field will be set to a value from the external EEPROM. If there is no EEPROM, this

field will default to a value of 20h.

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8.6 The Default Value After Power-on (RSTB asserted)

PCI Configuration Space Table

No.

00h

01h

02h

03h

04h

Name

Type

R

Bit7

Bit6

Bit5

Bit4

Bit3

Bit2

Bit1

Bit0

VID

1

0

1

0

-

0

-

0

1

0

1

0

R

0

1

0

DID

R

0

1

R

1

0

Command

R

0

W

-

PERRSP

MWIEN

-

BMEN MEMEN IOEN

05h

R

0

-

0

W

-

NewCap

0

-

SERREN

06h

07h

Status

R

0

R

0

1

W

DPERR

SSERR RMABT RTABT

STABT

-

DPD

08h

09h

0Ah

0Bh

0Ch

0Dh

Revision ID

PIFR

R

0

1

0

R

0

SCR

R

0

BCR

R

0

1

0

CLS

R/W

R

0

LTR

0

W

LTR7

LTR6

LTR5

LTR4

LTR3

LTP2

LTR1

LTR0

0Eh

0Fh

10h

11h

12h

13h

14h

15h

16h

17h

18h

|

HTR

BIST

IOAR

R

0

1

0

R

R/W

R

MEMAR

R/W

RESERVED(ALL 0)

-

27h

28h

29h

2Ah

2Bh

2Ch

2Dh

2Eh

2Fh

30h

R

0

1

0

1

0

-

0

1

0

-

0

1

0

1

0

-

0

1

0

-

0

1

0

1

0

-

0

1

0

-

0

-

0

CISPtr

0

R

0

R

0

SVID

SMID

BMAR

R

0

R

0

R

1

R

1

R

0

W

R

BROMEN

31h

0

-

0

-

0

-

0

W

R/W

BMAR15 BMAR14 BMAR13 BMAR12 BMAR11

32h

33h

0

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RTL8139C(L)+

34h

35h

|

Cap-Ptr

-

R

Ptr7

Ptr6

Ptr5

Ptr4

Ptr3

Ptr2

Ptr1

Ptr0

RESERVED(ALL 0)

3Bh

3Ch

3Dh

3Eh

3Fh

40h

|

ILR

IPR

R/W

R

0

1

0

1

0

MNGNT

MXLAT

R

0

R

RESERVED(ALL 0)

-

FFh

8.7 PCI Power Management Functions

The RTL8139C(L)+ is compliant to ACPI (V1.0, V2.0), PCI Power Management (Rev 1.1), and Device Class Power

Management Reference Specification (V1.0a), such as to support OS Directed Power Management (OSPM) environment. To

support this, the RTL8139C(L)+ provides the following capabilities:

ꢂ

The RTL8139C(L)+ can monitor the network for a Wakeup Frame, a Magic Packet, or a Link Change, and notify the

system via PME# when such a packet or event arrives. Then, the whole system can restore to working state to process

the incoming jobs.

ꢂ

The RTL8139C(L)+ can be isolated from the PCI bus automatically with the auxiliary power circuit when the PCI bus is in

B3 state, i.e. the power on the PCI bus is removed. When the motherboard includes a built-in RTL8139C(L)+ single-chip

fast Ethernet controller, the RTL8139C(L)+ can be disabled when needed by pulling the isolate pin low to 0V.

When the RTL8139C(L)+ is in power down mode (D1 ~ D3),

♦

The Rx state machine is stopped, and the RTL8139C(L)+ keeps monitoring the network for wakeup events such Magic

Packet, Wakeup Frame, and/or Link Change, in order to wake up the system. When in power down mode, the

RTL8139C(L)+ will not reflect the status of any incoming packets in the ISR register and will not receive any packets

into the Rx FIFO.

♦

The FIFO status and the packets which are already received into Rx FIFO before entering into power down mode, are

kept by the RTL8139C(L)+ during power down mode

♦

The transmission is stopped. The action of PCI bus master mode is stopped, as well. The Tx FIFO is kept.

After restoration to a D0 state, the PCI bus master mode continues to transfer the data, which is not yet moved into the

Tx FIFO from the last break. The packet that was not transmitted completely last time is transmitted again.

D3cold_support_PME bit(bit15, PMC register) & Aux_I_b2:0 (bit8:6, PMC register) in PCI configuration space .

If EEPROM D3cold_support_PME bit(bit15, PMC) = 1, the above 4 bits depend on the existence of Aux power.

If EEPROM D3cold_support_PME bit(bit15, PMC) = 0, the above 4 bits are all 0's.

Examples:

1. If EEPROM D3c_support_PME = 1,

ꢂ

If Aux. power exists, then PMC in PCI config space is the same as EEPROM PMC, i.e. if EEPROM

PMC = C2 F7, then PCI PMC = C2 F7.

ꢂ

If Aux. power is absent, then PMC in PCI config space is the same as EEPROM PMC except the above

4 bits are all 0’s. I.e. if EEPROM PMC = C2 F7, the PCI PMC = 02 76.

ꢄ

In this case, if wakeup support is desired when the main power is off, it is suggested that the

EEPROM PMC bet set to C2 F7 (RT EEPROM default value).

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2. If EEPROM D3c_support_PME = 0,

ꢂ

If Aux. power exists, then PMC in PCI config space is the same as EEPROM PMC. I.e. if EEPROM

PMC = C2 77, then PCI PMC = C2 77.

ꢂ

If Aux. power is absent, then PMC in PCI config space is the same as EEPROM PMC except the above

4 bits are all 0’s. I.e. if EEPROM PMC = C2 77, the PCI PMC = 02 76.

ꢄ

In this case, if wakeup support is not desired when the main power is off, it is suggested that the

EEPROM PMC be set to 02 76.

Link Wakeup occurs only when the following conditions are met:

♦

The LinkUp bit (CONFIG3#4) is set to 1, the PMEn bit (CONFIG1#0) is set to 1, and the RTL8139C(L)+ is in an

isolation state, or the PME# can be asserted in current power state.

♦

The Link status is re-established.

Magic Packet Wakeup occurs only when the following conditions are met:

♦

The destination address of the received Magic Packet matches.

The received Magic Packet does not contain a CRC error.

The Magic bit (CONFIG3#5) is set to 1, the PMEn bit (CONFIG1#0) is set to 1, and the RTL8139C(L)+ is in isolation

state, or the PME# can be asserted in current power state.

♦

The Magic Packet pattern matches, i.e. 6 * FFh + MISC(can be none)+ 16 * DID(Destination ID) in any part of a valid

(Fast) Ethernet packet.

Wakeup Frame event occurs only when the following conditions are met:

♦

ꢅ

The destination address of the received Wakeup Frame matches.

The received Wakeup Frame does not contain a CRC error.

The PMEn bit (CONFIG1#0) is set to 1.

The 8-bit CRC* (or 16-bit CRC) of the received Wakeup Frame matches with the 8-bit CRC* (or 16-bit CRC) of the

sample Wakeup Frame pattern received from the local machine’s OS.

ꢅ

The last masked byte** of the received Wakeup Frame matches with the last masked byte** of the sample Wakeup

Frame pattern provided by the local machine’s OS. (In Long Wakeup Frame mode, the last masked byte field is replaced

with the high byte of the 16-bit CRC.)

* 8-bit CRC:

This 8-bit CRC logic is used to generate an 8-bit CRC from the masked bytes of the received Wakeup Frame packet

within offset 12 to 75. Software should calculate the 8-bit Power Management CRC for each specific sample wakeup

frame and store the calculated CRC in the corresponding CRC register for the RTL8139C(L)+ to check if there is

Wakeup Frame packet coming in.

* 16-bit CRC: (Long Wakeup Frame mode, the mask bytes cover from offset 0 to 127)

Long Wakeup Frame: The RTL8139C(L)+ also supports 3 long Wakeup Frames. If the range of mask bytes of the

sample Wakeup Frame, passed down by the OS to the driver, exceeds the range from offset 12 to 75, the related

registers of wakeup frame 2 and 3 can be merged to support one long wakeup frame by setting the LongWF (bit0,

CONFIG4). Thus, the range of effective mask bytes extends from offset 0 to 127. The low byte and high byte of

calculated 16-bit CRC should be stored into register CRC2 and LSBCRC2 respectively. The mask bytes (16 bytes)

should be stored to register Wakeup2 and Wakeup3. The CRC3 and LSBCRC3 have no meaning in this case and

should be reset to 0. So as the long Wakeup Frame pairs, wakeup frame 4 and 5, wakeup frame 6 and 7 each make up

one wakeup frame. The CRC5, CRC7, LSBCRC5, and LSBCRC7 have no meaning in this case and should be reset

to 0, if the RTL8139C(L)+ is set to support long Wakeup Frame. In this case, the RTL8139C(L)+ support 5 wakeup

frames, that are 2 normal wakeup frames and 3 long wakeup frames.

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** Last masked byte:

The last byte of the masked bytes of the received Wakeup Frame packet within offset 12 to 75 (in 8-bit CRC

mode) should matches with the last byte of the masked bytes of the sample Wakeup Frame provided by the

local machine’s OS.

The PME# signal is asserted only when the following are met:

ꢅ

The PMEn bit (bit0, CONFIG1) is set to 1.

The PME_En bit (bit8, PMCSR) in PCI Configuration Space is set to 1.

The RTL8139C(L)+ may assert PME# in current power state, or the RTL8139C(L)+ is in isolation¹state. Refer to

PME_Support(bit15-11) of the PMC register in PCI Configuration Space.

ꢅ

Magic Packet, LinkUp, or Wakeup Frame has occurred.

Note: Writing a 1 to the PME_Status (bit15) of PMCSR register in the PCI Configuration Space will clear this bit and

cause the RTL8139C(L)+ to stop asserting a PME# (if enabled).

When the RTL8139C(L)+ is in power down mode, ex. D1-D3, the IO, MEM, and Boot ROM space are all disabled. After RST#

asserted, the power state must be changed to D0 if the original power state is D3_cold. There is no hardware enforced delays at

RTL8139C(L)+’s power state. When in ACPI mode, the RTL8139C(L)+ does not support PME from D0, due to the setting of

PMC register. This setting comes from EEPROM.

The RTL8139C(L)+ also supports LAN WAKE-UP function. The LWAKE pin is used to notify the motherboard to execute

wake-up process whenever the RTL8139C(L)+ receives a wakeup event, such as Magic Packet.

The LWAKE signal is asserted according the following setting.

ꢅ

LWPME bit (bit4, CONFIG4):

0: The LWAKE is asserted whenever there is wakeup event occurs.

1: The LWAKE can only be asserted when the PMEB is asserted and the ISOLATEB is low.

Bit1 of DELAY byte(offset 1Fh, EEPROM):

0: LWAKE signal is disabled.

ꢅ

1: LWAKE signal is enabled

8.8 Vital Product Data (VPD)

Bit 31 of the VPD is used to issue VPD read/write command and is also a flag used to indicate whether the

transfer of data between the VPD data register and the 93C46/93C56 is completed or not.

1. Write VPD register: (write data to 93C46/93C56) Write the flag bit to a one (at the same time the VPD address is written).

When the flag bit is set to zero by the RTL8139C(L)+, the VPD data (all 4 bytes) has been transferred from the VPD data

register to 93C46/93C56.

2. Read VPD register: (read data from 93C46/93C56) Write the flag bit to a zero at the same time the VPD address is written).

When the flag bit is set to one by the RTL8139C(L)+, the VPD data (all 4 bytes) has been transferred from 93C46/93C56 to

the VPD data register.

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9. Functional Description

9.1 Transmit & Receive Operations in C mode

9.1.1 Transmit

The host CPU initiates a transmit by storing an entire packet of data in one of the descriptors in the main memory. Those

descriptors should be aligned in double-word format. When the entire packet has been transferred to the Tx buffer, the

RTL8139C(L)+ is instructed to move the data from the Tx buffer to the internal transmit FIFO in PCI bus master mode. When

the transmit FIFO contains a complete packet or is filled to the programmed threshold level, the RTL8139C(L)+ begins packet

transmission. Please refer to the Realtek RTL8139 series programming guide for detailed information.

9.1.2 Receive

The incoming packet is placed in the RTL8139C(L)+'s Rx FIFO. Concurrently, the RTL8139C(L)+ performs address filtering of

multicast packets according to its hash algorithms. When the amount of data in the Rx FIFO reaches the level defined in the

Receive Configuration Register (RCR), the RTL8139C(L)+ requests the PCI bus to begin transferring the data to the Rx buffer

in PCI bus master mode. The Rx buffer should be pre-allocated and indicated in RCR before packet reception. All received

packets stored in Rx buffer, including Rx header and 4-byte CRC, are double-word alignment. I.e., each received packet is

placed at next available double-word alignment address after the last received packet in Rx buffer. Please refer to Realtek

RTL8139 series programming guide for detailed information.

9.2 Transmit & Receive Operations in C+ mode

In C+ mode, the RTL8139C(L)+ supports a new descriptor-based buffer management that will significantly lower host CPU

utilization and is more suitable for server applications. The new buffer management algorithm provides capabilities of Microsoft

Large-Send offload, IP checksum offload, TCP checksum offload, UDP checksum offload, and IEEE802.1P, 802.1Q VLAN

tagging. The RTL8139C(L)+ supports up to 64 consecutive descriptors in memory for transmit and receive separately, which

means there can be 3 descriptor rings, one is a high priority transmit descriptor ring, another is a normal priority transmit

descriptor ring, and the other is a receive descriptor ring. Each descriptor ring may consist of up to 64 4-double-word

consecutive descriptors. Each descriptor consists of 4 consecutive double words. The start address of each descriptor group

should be 256-byte alignment. Software must pre-allocate enough buffers and configure all descriptor rings before transmitting

and/or receiving packets. Descriptors can be chained to form a packet, in both Tx and Rx. Please refer to the Realtek

RTL8139C(L)+ programming guide for detailed information. Any Tx buffer pointed to by one of Tx descriptors should be at

least 4 bytes.

Padding: The RTL8139C+ will automatically pad any packet less than 64 bytes (including 4 bytes CRC) to 64-bytes in length

(including 4-byte CRC) before transmitting that packet onto network medium, when the PAD bit is set to 1 in the C+CR (offset

E0h) C+ command register.

If a packet consists of 2 or more descriptors, then the descriptors in command mode should have the same configuration, except

EOR, FS, LS bits.

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9.2.1 Transmit

The following information describes what the Tx descriptor may look like, depending on different settings in each Tx

descriptor.

Large-Send Task Offload Tx Descriptor Format (Before transmitting, OWN=1,

LGSEN=1, Tx command mode 0)

bit 31 30 29 28 27 26

16 15

8

7

6

5

4

3

2

1

0

O E F L L Large-Send MSS value

W O S S G (11 bits)

Offset 0

Frame_Length

N R

=

S

E

N

=

1

T R

VLAN_TAG

Offset 4

Offset 8

RSVD

A S

G V

C D

VIDL

PRIO C VIDH

FI

TX_BUFFER_ADDRESS_LOW

TX_BUFFER_ADDRESS_HIGH

Offset 12

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Offset#

Bit#

Symbol

Description

0

31

OWN

Ownership: When set, indicates that the descriptor is owned by the NIC, and the data

relative to this descriptor is ready to be transmitted. When cleared, indicates that the

descriptor is owned by the host system. The NIC clears this bit when the relative buffer data

is transmitted. In this case, OWN=1.

End of descriptor Ring: When set, indicates that this is the last descriptor in the descriptor

ring. When the internal transmit pointer of the NIC reaches here, the pointer will return to

the first descriptor of the descriptor ring after transmitting the data relative to this

descriptor.

0

30

EOR

0

29

28

FS

LS

First Segment Descriptor: When set, indicates that this is the first descriptor of a Tx

packet, and this descriptor is pointing to the first segment of the packet.

Last Segment Descriptor: When set, indicates that this is the last descriptor of a Tx packet,

and this descriptor is pointing to the last segment of the packet.

TCP/IP Large Send Operation Enable: A command bit. The driver sets this bit to ask the

NIC to offload the Large send operation. In this case, LGSEN=1.

Maximum Segmentation Size: This is a command field, 11-bits long. The driver passes

large send MSS to the NIC through this field.

27

LGSEN

MSS

26-16

15-0

Frame_Le

ngth

RSVD

Transmit Frame Length: This field indicates the length in the Tx buffer, in bytes, to be

transmitted.

Reserved

4

31-18

17

TAGC

VLAN Tag Control Bit: 1: Enable. 0: Disable.

1: Add TAG. 0x8100 (Ethernet encoded tag protocol ID, indicating that this is a IEEE

802.1Q VLAN packet) is inserted after source address, and 2 bytes are inserted after tag

protocol ID from VLAN_TAG field in transmit descriptor.

0: Packet remains unchanged when transmitting. I.e., the packet transmitted is the same

as it was passed down by upper layer.

4

16

15-0

RSVD

VLAN_TAG

Reserved

The 2-byte VLAN_TAG contains information, from upper layer, of user priority, canonical

format indicator, and VLAN ID. Please refer to IEEE 802.1Q for more VLAN tag

information.

VIDH: The high 4 bits of a 12-bit VLAN ID.

VIDL: The low 8 bits of a 12-bit VLAN ID.

PRIO: 3-bit 8-level priority.

CFI: Canonical Format Indicator.

8

12

31-0

TxBuffL

TxBuffH

Low 32-bit Address of Transmit Buffer

High 32-bit Address of Transmit Buffer

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Normal (including IP, TCP, UDP Checksum Task Offloads) Tx Descriptor Format

(before transmitting, OWN=1, LGSEN=0, Tx command mode 1)

bit 31 30 29 28 27 26

16 15

8

7

6

5

4

3

2

1

0

O E F L L R R R R R R R R I U T

W O S S G S S S S S S S S P D C

Offset 0

Frame_Length

N R

=

S V V V V V V V V C P P

E D D D D D D D D S C C

1

N

=

0

S S

T R

A S

G V

C D

VLAN_TAG

Offset 4

Offset 8

Offset 12

RSVD

VIDL

PRIO C

FI

VIDH

TX_BUFFER_ADDRESS_LOW

TX_BUFFER_ADDRESS_HIGH

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Offset#

Bit#

Symbol

Description

0

31

OWN

Ownership: When set, indicates that the descriptor is owned by the NIC, and the data

relative to this descriptor is ready to be transmitted. When cleared, indicates that the

descriptor is owned by the host system. The NIC clears this bit when the relative buffer data

is transmitted. In this case, OWN=1.

End of Descriptor Ring: When set, indicates that this is the last descriptor in the descriptor

ring. When the internal transmit pointer of the NIC reaches here, the pointer will return to

the first descriptor of the descriptor ring after transmitting the data relative to this

descriptor.

First Segment Descriptor: When set, indicates that this is the first descriptor of a Tx

packet, and this descriptor is pointing to the first segment of the packet.

Last segment descriptor: When set, indicates that this is the last descriptor of a Tx packet,

and this descriptor is pointing to the last segment of the packet.

A Command Bit: TCP/IP Large send operation enable. Driver sets this bit to ask NIC to

offload Large send operation. In this case, LGSEN=0.

Reserved

0

30

EOR

0

29

28

27

FS

LS

LGSEN

0

26-19

18

RSVD

IPCS

IP Checksum Offload: A command bit. Driver sets this bit to ask NIC to offload IP

checksum.

0

17

16

UDPCS

TCPCS

UDP Checksum Offload: A command bit. Driver sets this bit to ask NIC to offload UDP

checksum.

TCP checksum offload enable: A command bit. The driver sets this bit to ask the NIC to

offload the TCP checksum.

15-0

Frame_Le

ngth

RSEV

Transmit Frame Length: This field indicates the length in the Tx buffer, in bytes, to be

transmitted

Reserved

4

31-18

17

TAGC

VLAN Tag Control Bit: 1: Enable. 0: Disable.

1: Add TAG. 0x8100 (Ethernet encoded tag protocol ID, indicating that this is a IEEE

802.1Q VLAN packet) is inserted after source address, and 2 bytes are inserted after tag

protocol ID from VLAN_TAG field in transmit descriptor.

0: Packet remains unchanged when transmitting. I.e., the packet transmitted is the same

as it was passed down by upper layer.

4

16

15-0

RSEV

VLAN_TAG

Reserved

The 2-byte VLAN_TAG contains information, from upper layer, of user priority, canonical

format indicator, and VLAN ID. Please refer to IEEE 802.1Q for more VLAN tag

information.

VIDH: The high 4 bits of a 12-bit VLAN ID.

VIDL: The low 8 bits of a 12-bit VLAN ID.

PRIO: 3-bit 8-level priority.

CFI: Canonical Format Indicator.

8

12

31-0

TxBuffL

TxBuffH

Low 32-bit Address of Transmit Buffer

High 32-bit Address of Transmit Buffer

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Tx Status Descriptor (After transmitting, OWN=0, Tx status mode)

After having transmitted, the Tx descriptor turns into a Tx status descriptor.

bit 31 30 29 28 27 26

16 15

8

7

6

5

4

3

2

1

0

O E F L R R U R T O L E CC3-0

W O S S S S N S E W N X

Offset 0

Offset 4

Offset 8

Offset 12

Frame_Length

N R

=

V V F V S C K C

D D

D

F

0

T R

VLAN_TAG

RSVD

A S

G V

C D

VIDL

PRIO C

FI

VIDH

TX_BUFFER_ADDRESS_LOW

TX_BUFFER_ADDRESS_HIGH

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Offset#

Bit#

Symbol

Description

0

31

OWN

Ownership: When set, indicates that the descriptor is owned by the NIC. When cleared,

indicates that the descriptor is owned by the host system. The NIC clears this bit when the

relative buffer data is already transmitted. In this case, OWN=0.

End of Descriptor Ring: When set, indicates that this is the last descriptor in the descriptor

ring. When the internal transmit pointer of the NIC reaches here, the pointer will return to

the first descriptor of the descriptor ring after transmitting the data relative to this

descriptor.

0

30

EOR

0

29

28

FS

LS

First Segment Descriptor: When set, indicates that this is the first descriptor of a Tx

packet, and this descriptor is pointing to the first segment of the packet.

Last Segment Descriptor: When set, indicates that this is the last descriptor of a Tx packet,

and this descriptor is pointing to the last segment of the packet.

0

27-26

25

RSVD

UNF

Reserved

FIFO Underrun: A status bit. NIC sets this bit to inform driver that FIFO underrun had

ever occurred before this packet transmitted.

0

24

23

RSVD

TES

Reserved

Transmit Error Summary: When set, indicates that at least one of the following errors

has occurred: OWC, EXC, LNKF. This bit is valid only when the LS (Last segment) bit is

set.

0

22

OWC

Out of Window Collision: A status bit. When set, it means an “out-of-window” collision is

encountered during transmission of a packet.

0

21

20

LNKF

EXC

Link Failure: A status bit. The NIC sets this bit to inform the driver of a link failure.

Excessive Collision: When set, indicates that the transmission was aborted due to 16

consecutive collisions.

0

19-16

15-0

CC3-0

Collision Counter: When Own bit =0, this is a status field. A 4-bit collision counter,

showing the total collision times before the packet was transmitted.

Frame_Le

ngth

RSEV

Transmit Frame Length: This field indicates the length of the Tx buffer, in bytes, to be

transmitted

Reserved

4

31-18

17

TAGC

VLAN Tag Control Bit: 1: Enable. 0: Disable.

1: Add TAG. 0x8100 (Ethernet encoded tag protocol ID, indicating that this is a IEEE

802.1Q VLAN packet) is inserted after source address, and 2 bytes are inserted after tag

protocol ID from VLAN_TAG field in transmit descriptor.

0: Packet remains unchanged when transmitting. I.e., the packet transmitted is the same

as it was passed down by upper layer.

4

16

15-0

RSEV

VLAN_TAG

Reserved

The 2-byte VLAN_TAG contains information, from upper layer, of user priority, canonical

format indicator, and VLAN ID. Please refer to IEEE 802.1Q for more VLAN tag

information.

VIDH: The high 4 bits of a 12-bit VLAN ID.

VIDL: The low 8 bits of a 12-bit VLAN ID.

PRIO: 3-bit 8-level priority.

CFI: Canonical Format Indicator.

8

12

31-0

TxBuffL

TxBuffH

Low 32-bit Address of Transmit Buffer

High 32-bit Address of Transmit Buffer

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9.2.2 Receive

The following information describes what the Rx descriptor may look like, depending on different states in each Rx descriptor.

Any Rx buffer, which is pointed to by one of the Rx descriptors, should be at least 4 bytes.

Rx Command Descriptor (OWN=1)

The driver should pre-allocate Rx buffers and configure Rx descriptors before packet reception. The following describes what a

Rx descriptor may look like before packet reception.

bit 31 30 29 28

19 18 17 16 15

13 12

8

7

6

5

4

3

2

1

0

O E

W O

N R

=

Offset 0

Offset 4

Offset 8

Offset 12

RSVD

Buffer_Size

1

T

VLAN_TAG

PRIO

RSVD

A

V

A

VIDL

C

VIDH

FI

RX_BUFFER_ADDRESS_LOW

RX_BUFFER_ADDRESS_HIGH

Offset#

Bit#

Symbol

Description

0

31

OWN

Ownership: When set, indicates that the descriptor is owned by the NIC, and is ready to

receive a packet. The OWN bit is set by the driver after having pre-allocated a buffer at

initialization, or the host has released the buffer to the driver. In this case, OWN=1.

End of Rx descriptor Ring: Set to 1 indicates that this descriptor is the last descriptor of

the Rx descriptor ring. Once the internal receive descriptor pointer of the NIC reaches here,

it will return to the first descriptor of the Rx descriptor ring after this descriptor is used by

packet reception.

0

30

EOR

0

29-13

12-0

RSVD

Buffer_Size

Reserved

Buffer Size: This field indicates the receive buffer size in bytes. Although the maximum

buffer size is 8K bytes/buffer, the RTL8139C(L)+ purges all data after 4K bytes if the

packet is larger than 4K-bytes long.

4

31-17

16

RSEV

TAVA

Reserved

Tag Available: When set, the received packet is an IEEE802.1Q VLAN TAG (0x8100)

available packet.

VLAN_TAG

4

15-0

If the TAG of the packet is 0x8100, The MAC of the RTL8139C(L)+ extracts four bytes

from the after source ID, sets the TAVA bit to1, and moves the TAG value to this field in

the Rx descriptor.

VIDH: The high 4 bits of a 12-bit VLAN ID.

VIDL: The low 8 bits of a 12-bit VLAN ID.

PRIO: 3-bit 8-level priority.

CFI: Canonical Format Indicator.

8

12

31-0

RxBuffL

Low 32-bit Address of Receive Buffer

RxBuffH High 32-bit address of receive buffer.

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Rx Status Descriptor (OWN=0)

When a packet is received, the Rx command descriptor turns into a Rx status descriptor.

bit 31 30 29 28 27 26

16 15

13 12

8

7

6

5

4

3 2 1 0

O E F L F M P B B F R R R C PI PI

U T

Frame_Length

Offset 0

Offset 4

W O S S A A A A O O W E U R D D IP D C

N R

=

E R M R V V T S N C 1 0 F P P

F F F F

T

0

T

VLAN_TAG

PRIO

A

V

A

RSVD

VIDL

C

VIDH

FI

Offset 8

RX_BUFFER_ADDRESS_LOW

Offset 12

RX_BUFFER_ADDRESS_HIGH

Offset#

Bit#

Symbol

Description

0

31

OWN

Ownership: When set, indicates that the descriptor is owned by the NIC. When cleared,

indicates that the descriptor is owned by the host system. The NIC clears this bit when it has

filled up this Rx buffer with a packet or part of a packet. In this case, OWN=0.

End of Rx Descriptor Ring: Set to 1 indicates that this descriptor is the last descriptor of

the Rx descriptor ring. When the internal receive descriptor pointer of the NIC reaches here,

it will return to the first descriptor of the Rx descriptor ring after this descriptor is used by

packet reception.

First Segment Descriptor: When set, indicates that this is the first descriptor of a received

packet, and that this descriptor is pointing to the first segment of the packet.

Last Segment Descriptor: When set, indicates that this is the last descriptor of a received

packet, and this descriptor is pointing to the last segment of the packet.

Frame Alignment Error: When set, indicates a frame alignment error has occurred on the

received packet. FAE packets can be received only when RCR_AER is set.

Multicast Address Packet Received: When set, indicates that a multicast packet has been received.

0

30

EOR

0

29

28

27

FS

LS

FAE

0

26

25

MAR

PAM

Physical Address Matched: When set, indicates that the destination address of this Rx

packet matches the value in the ID registers of the RTL8139C(L)+.

0

24

BAR

Broadcast Address Received: When set, indicates that a broadcast packet has been

received. BAR and MAR will not be set simultaneously.

0

23

22

21

BOVF

FOVF

RWT

Buffer Overflow: When set, indicates that receive buffer has been exhausted before this packet was received.

FIFO Overflow: When set, indicates that a FIFO overflow has occurred before this packet was received.

Receive Watchdog Timer Expired: When set, indicates that the received packet length

exceeds 4096 bytes. The receive watchdog timer will expire and stop the receiving engine.

(Same as the Long Bit definition in 8139a)

Receive Error Summary: When set, indicates that at least one of the following errors has

occurred: CRC, RUNT, RWT, FAE. This bit is valid only when the LS (Last Segment) bit is set.

0

20

RES

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0

19

18

RUNT

CRC

Runt Packet: When set, indicates that the received packet length is smaller than 64 bytes.

RUNT packets can be received only when RCR_AR is set.

CRC Error: When set, indicates that a CRC error has occurred on the received packet.

CRC packets can be received only when RCR_AER is set.

17, 16

PID1,

PID0

Protocol ID1, Protocol ID0: These 2 bits indicate the protocol type of the packet received.

PID1

PID0

Non-IP

TCP/IP

UDP/IP

IP

0

1

0

1

0

1

0

4

15

14

13

12-0

31-17

IPF

When set, indicates IP checksum failure.

UDPF When set, indicates UDP checksum failure.

TCPF When set, indicates TCP checksum failure.

Frame_Length

When OWN=0 and LS =1, it indicates the received packet length including CRC, in bytes.

Reserved

RSVD

TAVA

16

Tag Available: When set, the received packet is an IEEE802.1Q VLAN TAG (0x8100)

available packet.

15-0

VLAN_T If the packet ‘s TAG is 0x8100, The RTL8139C(L)+’s MAC extracts four bytes from after

AG

source ID, sets TAVA bit to1, and moves the TAG value to this field in Rx descriptor.

VIDH: The high 4 bits of a 12-bit VLAN ID.

VIDL: The low 8 bits of a 12-bit VLAN ID.

PRIO: 3-bit 8-level priority.

CFI: Canonical Format Indicator.

Low 32-bit Address of Receive Buffer

High 32-bit Address of Receive Buffer

8

12

31-0

RxBuffL

RxBuffH

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9.3 Line Quality Monitor

The line quality monitor function is available in 100Base-TX mode. It is possible to determine the amount of Equalization being used

by accessing certain test registers. This provides a crude indication of connected cable length. This function allows for a quick and

simple verification of the line quality in that any significant deviation from an expected register value (based on a known cable length)

would indicate that the signal quality has deviated from the expected nominal case.

9.4 Clock Recovery Module

The Clock Recovery Module (CRM) is supported in both 10Base-T and 100Base-TX mode. The CRM accepts 125Mb/s MLT3

data from the equalizer. The DPLL locks onto the 125Mb/s data stream and extracts a 125MHz recovered clock. The extracted

and synchronized clock and data are used as required by the synchronous receive operations.

9.5 Loopback Operation

Loopback mode is normally used to verify that the logic operations up to the Ethernet cable function correctly. In loopback mode

for 100Mbps, the RTL8139C(L)+ takes frames from the transmit descriptor and transmits them up to internal Twister logic. The

loopback function does not apply to external PHYceiver.

9.6 Tx Encapsulation with the Internal PHYceiver

While operating in 100Base-Tx mode, the RTL8139C(L)+ encapsulates the frames that it transmits according to the 4B/5B

code-groups table. The changes of the original packet data are listed as follows:

1. The first byte of the preamble in the MAC frame is replaced with the JK symbol pair.

2. After the CRC, the TR symbol pair is inserted.

9.7 Collision

If the RTL8139C(L)+ is not in the full-duplex mode, a collision event occurs when the receive input is not idle while the

RTL8139C(L)+ transmits. If the collision was detected during the preamble transmission, the jam pattern is transmitted after

completing the preamble (including the JK symbol pair).

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9.8 Rx Decapsulation with the Internal PHYceiver

The RTL8139C(L)+ continuously monitors the network when reception is enabled. When activity is recognized it starts to

process the incoming data.

After detecting receive activity on the line, the RTL8139C(L)+ starts to process the preamble bytes based on the mode of

operation.

While operating in 100Base-Tx mode, the RTL8139C(L)+ expects the frame to start with the symbol pair JK in the first bye of

the 8-byte preamble.

The RTL8139C(L)+ checks the CRC bytes and checks if the packet data ends with the TR symbol pair, if not, the

RTL8139C(L)+ reports an CRC error RSR.

The RTL8139C(L)+ reports a RSR<CRC> error in the following case:

In 100Base-Tx mode, one of the following occurs:

a. An invalid symbol (4B/5B Table) is received in the middle of the frame.

The RSR<ISE> bit also sets.

b. The frame does not end with the TR symbol pair.

9.9 Flow Control

The RTL8139C(L)+ supports IEEE802.3X flow control to improve performance in full-duplex mode. It detects PAUSE packets

to achieve flow control tasks.

9.9.1. Control Frame Transmission

When the RTL8139C(L)+, configured in C mode, detects that its free receive buffer less than 3K bytes, it sends a PAUSE packet

with pause_time(=FFFFh) to inform the source station to stop transmission for the specified period of time. After the driver has

processed the packets in the receive buffer and updated the boundary pointer, the RTL8139C(L)+ sends the another PAUSE

packet with pause_time(=0000h) to wake up the source station to restart transmission.

When the RTL8139C(L)+ is configured in C+ mode with Tx Flow Control enabled, it sends out a PAUSE packet with pause

time = FFFFh, whenever there are no free Rx descriptors available.

9.9.2. Control Frame Reception

The RTL8139C(L)+ enters a backoff state for a specified period of time when it receives a valid PAUSE packet with pause_time

(=n). If the PAUSE packet is received while the RTL8139C(L)+ is transmitting, the RTL8139C(L)+ starts to backoff after the

current transmission completes. The RTL8139C(L)+ is free to transmit the next packet when it receives a valid PAUSE packet

with pause_time(=0000h) or the backoff timer(=n*512 bit time) elapses.

Note: The PAUSE operation cannot be used to inhibit transmission of MAC Control frames (e.g. a PAUSE packet). The N-way

flow control capability can be disabled, please refer to Section 7, “EEPROM (93C46 or 93C56) Contents” for a detailed

description.

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9.10 Medium Auto-Detect

(UTP or MII, no Boot ROM interface)

The following diagram describes the process the RTL8139C(L)+ uses to detect the medium used.

Start

Yes

UTP link OK

No

Medium = UTP

Medium = MII

Yes

MII link OK

No

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9.11 Cable Connection Status

♦

For medium status from an external PHYceiver (MII application enabled, no Boot ROM) to be reported correctly, the

MLINK (pin 102) and MFDUP (pin 103) pins should be connected to relative pins of the external PHYceiver.

The status of Link Speed and Duplex mode are reflected to the relative registers when the current medium is either

UTP or MII (MII application enabled).

Link change from current LinkOk medium generates an interrupt (LinkChg, bit5, ISR) to notify the drivers of link

change event.

Force Link Speed function is effective only to RTL8139C(L)+’s internal PHYceiver. The RTL8139C(L)+ does not

support hardware access to external PHYceiver’s MII registers in MII application. The only way to force link speed

of external PHYceiver, is to use software generated MII timing through MII register (Offset FCh, when medium

select is set to Auto-Detect or MII mode).

1. UTP: Same as the RTL8139 series.

2. MII:

The information reflects the medium status from external PHYceiver, provided that the MLINK and MFDUP are

both connected to the relative pins of the external PHYceiver.

Link: by MLINK pin 102

If MLinkP (bit3, BMCR, offset 63h) = 1, then MLink=high means MII link OK

If MLinkP (bit3, BMCR, offset 63h) = 0, then MLink=low means MII link OK

MLinkP can be auto-loaded from EEPROM.

Duplex: by MFDUP pin 101

If MDupP (bit2, BMCR, offset 63h) = 1, then MFDup=high means MII Duplex=Full

If MDupP (bit2, BMCR, offset 63h) = 0, then MFDup=low means MII Duplex=Full

MDupP can be auto-loaded from EEPROM.

Speed: by MTXC

If MTXC = 2.5MHz, then Speed=10Mbps. If MTXC = 25MHz, Speed=100Mbps.

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9.12 MII Redundant Link

The following diagram shows the process used by the RTL8139C(L)+ to implement the MII redundant link feature. This feature

is valid only in MII applications only.

Internal PHY

RJ-45

RTL8139C(L)+

MII

External

PHYceiver

MLINK

MFDUP

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9.13 Memory Functions

9.13.1 Memory Read Line (MRL)

The Memory Read Line command reads information from a longword (DWORD) up to cache line boundary in size into a

prefetchable address space. The Memory Read Line command is semantically identical to the Memory Read command except

that it additionally indicates that the master intends to fetch a complete cache line. This command is intended to be used with

bulk sequential data transfers where the memory system and the requesting master might gain some performance advantage by

reading up to a cache line boundary in response to the request, rather than a single memory cycle. As with the Memory Read

command, pre-fetched buffers must be invalidated before any synchronization events are passed through this access path.

The RTL8139C(L)+ performs the MRL process according to the following rules:

i. Read accesses that reach the cache line boundary use the Memory Read Line (MRL) command,

instead of Memory Read command.

ii. Read accesses that do not reach the cache line boundary use the Memory Read (MR) command.

iii. The Memory Read Line (MRL) command operates in conjunction with the Memory Read Multiple

(MRM) command.

iv. The RTL8139C(L)+ will terminate the read transaction on to the cache line boundary when it is out

of resources on the transmit DMA. For example, when the transmit FIFO is almost full.

9.13.2 Memory Read Multiple (MRM)

The Memory Read Multiple command is semantically identical to the Memory Read command except that it additionally

indicates that the master may intend to fetch more than one cache line before disconnecting. The memory controller should

continue pipelining memory requests as long as FRAMEB is asserted. This command is intended to be used with bulk sequential

data transfers where the memory system and the requesting master might gain some performance advantage by sequentially

reading ahead one or more additional cache line(s) when a software transparent buffer is available for temporary storage.

The RTL8139C(L)+ performs the MRM process according to the following rules:

i. When the RTL8139C(L)+ reads full cache lines, it will use the Memory Read Multiple command.

ii. If the memory buffer is not cache-aligned, the RTL8139C(L)+ will use Memory Read Line

command to reach the cache line boundary first.

Example:

Assume the packet length = 1514 byte, cache line size = 16 longwords (DWORDs), and Tx buffer start address = 64m+4 (m > 0).

;Step1: Memory Read Line (MRL)

;Data: (0-3) => (4-7) => (8-11) =>………... => (56-59)

;From Address: <64m+4>, <64m+8>, ………., <64m+60>

;Step2. Memory Read Multiple (MRM)

(byte offset of the Tx packet)

(reach cache line boundary)

;Data: (60-63) => (64-67) => (68-71) => ……………………….….. => (1454-1467)

;From Address: <64m+64>, <64m+68>, ……………….…., <64m+64+(16*4)*21+(16-1)*4>

;Step3. Memory Read(MR)

;Data: (1468-1471) => (1472-1475) => ……………………………, => (1510-1513)

;From Address:<64m+64+(16*4)*22>,<64m+64+(16*4)*22+4>,..,<64m+64+(16*4)*22+42>

Step1: Memory Read Multiple (MRM)

Data: (0-3) => (4-7) => (8-11) =>………….. => (1454-1467)

From Address: <64m+4>, <64m+8>, ………., <64m+64+(16*4)*21+(16-1)*4>

Step2. Memory Read(MRL)

Data: (1468-1471) => (1472-1475) => ……………………………, => (1510-1513)

From Address:<64m+64+(16*4)*22>,<64m+64+(16*4)*22+4>,..,<64m+64+(16*4)*22+42>

78

2001/12/06

Rev.1.5

RTL8139C(L)+

9.13.3 Memory Write and Invalidate (MWI)

The Memory Write and Invalidate command is semantically identical to the Memory Write command except that it additionally

guarantees a minimum transfer of one complete cache line. For example, the master intends to write all bytes within the

addressed cache line in a single PCI transaction unless interrupted by the target. Note that all byte enables must be asserted

during each data phase for this command.

The master may allow the transaction to cross a cache line boundary only if it intends to transfer the entire next line as well. This

command requires implementation of a configuration register in the master indicating the cache line size and may only be used

with Linear Burst Ordering. It allows a memory performance optimization by invalidating a "dirty" line in a write-back cache

without requiring the actual write-back cycle, thus shortening access time. The RTL8139C(L)+ uses the MWI command while

writing full cache lines, and the Memory Write command while writing partial cache lines.

When the following requirements are met, the RTL8139C(L)+ issues the MWI command instead of the MW command on Rx

DMA:

i. The Cache Line Size written in the offset 0Ch of the PCI configuration space is 8 or 16

longwords (DWORDs).

ii. The accessed address is cache line aligned.

iii. The RTL8139C(L)+ has at least 8/16 longwords (DWORDs) of data in its RX FIFO.

iv. The MWI (bit 4) in the PCI configuration command register should be set to 1.

The RTL8139C(L)+ uses the Memory Write (MW) command instead of MWI whenever any one of the above listed

requirements fails. The RTL8139C(L)+ terminates the WMI cycle at the end of the cache line when a WMI cycle has started and

at least one of the requirements are no longer valid.

Example:

Assume Rx packet length = 1514 byte, cache line size = 16 DWORDs (longwords), and Rx buffer start address = 64m+4 (m > 0).

Step1: Memory Write (MW)

Data: (0-3) => (4-7) => (8-11) => ………... => (56-59)

To Address: <64m+4>, <64m+8>, …………., <64m+60>

Step2. Memory Write and Invalidate (MWI)

(byte offset of the Rx packet)

(reach cache line boundary)

Data: (60-63) => (64-67) => (68-71) => ……………………..….... => (1454-1457)

To Address: <64m+64>, <64m+68>, ………………..….., <64m+64+(16*4)*21+(16-1)*4>

Step3. Memory Write(MW)

Data: (1458-1461) => (1462-1465) => ……………………..……... => (1512-1513)

To Address: <64m+64+(16*4)*22>, <64m+64+(16*4)*22+4>, , <64m+64+(16*4)*22+42>

9.13.4 Dual Address Cycle (DAC)

The Dual Address Cycle (DAC) command is used to transfer a 64-bit address to devices that support 64-bit addressing when the

address is not in the low 4 GB address space. The RTL8139C(L)+ is capable of performing DAC, such that it is very competent

as a network server card in a heavy-duty server with the possibility of allocating a memory buffer above the 4GB memory

address space.

79

2001/12/06

Rev.1.5

RTL8139C(L)+

9.14 LED Functions

9.14.1 10/100 Mbps Link Monitor

The Link Monitor senses the link integrity or if a station is down.

9.14.2 LED_RX

In 10/100 Mbps mode, the LED function is like that of the RTL8129.

Power On

LED = Low

No

Receiving Packet?

Yes

LED = High for (100 +- 10) ms

LED = Low for (12 +- 2) ms

80

2001/12/06

Rev.1.5

RTL8139C(L)+

9.14.3 LED_TX

Power On

LED = Low

No

Transmitting Packet

Yes

LED = High for (100 +- 10) ms

LED = Low for (12 +- 2) ms

9.14.4 LED_TX+LED_RX

Power On

LED = Low

No

Tx or Rx Packet?

Yes

LED = High for (100 +- 10) ms

LED = Low for (12 +- 2) ms

81

2001/12/06

Rev.1.5

RTL8139C(L)+

9.15 Physical Layer Interfaces

The RTL8139C(L)+ supports standard media independent MII for 10Mbps and 100Mbps applications. In addition, a

management interface is defined for MII.

9.15.1 Media Independent Interface (MII)

The RTL8139C(L)+ supports 10Mbps and 100Mbps physical layer devices through the MII as defined in the IEEE 802.3 (clause

22) specifications. The MII consists of a transmit data interface (TxEN, TxER, TXD[3:0], and TxCLK), a receive data interface

(RxDV, RxER, RXD[3:0], and RxCLK), 2 status signals (CRS and COL) and a management interface (MDC and MDIO). In

this mode of operation, both Transmit and Receive clocks are supplied by the PHY.

9.15.2 MII Management Interface

The MII management interface utilizes a communication protocol similar to a serial EEPROM. Signaling occurs on two signals:

clock (MDC) and data (MDIO). This protocol provides capability for addressing up to 32 individual Physical Media Dependent

(PMD) devices which share the same serial interface, and for addressing up to 32 16-bit read/write registers within each PMD.

The MII management protocol utilizes the following frame format: start bits (SB), opcode (OP), PMD address (PA), register

address (RA), line turnaround (LT) and data, as shown below.

SB

OP

PA

RA

LT

2

Data

2 bits 2 bits

5 bits

16 bits

bits

MII Management Frame Format

i. Start bits are defined as <01>.

ii. Opcode bits are defined as <01> for a Write access and <10> for a Read access.

iii. PMD address is the device address.

iv. Register address is address of the register within that device.

v. Line turnaround bits will be <10> for Write accesses and will be <xx> for Read accesses. This allows time for the MII

lines to “turn around”.

vi. Data is the 16 bits of data that will be written to or read from the PMD device.

A reset frame, defined as 32 consecutive 1s (FFFF FFFFh), is also provided. After power up, all MII PMD devices must wait for

a reset frame to be received prior to participating in MII management communication. Additionally, a reset frame may be issued

at any time to allow all connected PMDs to re-synchronize to the data traffic.

82

2001/12/06

Rev.1.5

RTL8139C(L)+

10. Application Diagram

EEPROM

LED

CLK

DATA

Magnetics

Boot

ROM/

FLASH*

RJ45

RTL8139C(L)+

Address

External PHY

& Magnetics*

Auxiliary Power (3.3V/5V)

Auxiliary Power (5V)

PCI INTERFACE

* Boot ROM/FLASH and External PHY can not be implemented at the same time.

83

2001/12/06

Rev.1.5

RTL8139C(L)+

11. Electrical Characteristics

11.1 Temperature Limit Ratings

Parameter

Storage temperature

Operating temperature

Minimum

Maximum

+125

Units

°C

-55

0

70

11.2 DC Characteristics

11.2.1 Supply Voltage

Vcc = 3.0V min. to 3.6V max.

Symbol

Parameter

Conditions

OH= -8mA

Minimum Maximum Units

V

Minimum High Level Output

Voltage

I

0.9 * Vcc

Vcc

V

OH

V

Maximum Low Level Output

Voltage

I

0.1 * Vcc

Vcc+0.5

0.3 * Vcc

1.0

V

OL

OL= 8mA

V

Minimum High Level Input

Voltage

0.5 * Vcc

-0.5

V

IH

V

Maximum Low Level Input

Voltage

V

IL

I

Input Current

V

-1.0

uA

IN

IN= CC or

GND

I

Tri-State Output Leakage

Current

V

-10

10

uA

OZ

CC

OUT= CC or

GND

Average Operating Supply

I

0mA,

330

mA

OUT=

Current

84

2001/12/06

Rev.1.5

RTL8139C(L)+

11.3 AC Characteristics

11.3.1 FLASH/BOOT ROM Timing

MA17-0

TRC

ROMCSB

OEB

TWRBR

TOES

TCE

TOOLZ

WEB

TOHZ

TOH

TCOLZ

MD7-0

TACC

FLASH/BOOT ROM - Read

Symbol

TRC

TCE

TACC

TOES

TCOLZ

TOOLZ

TOHZ

TOH

Description

Minimum

Typical

Maximum

Units

ns

Read Cycle

135

-

200

60

-

40

0

Chip Enable Access Time

Address Access Time

Output Enable Access Time

Chip Enable to Output in Low Z

-

ns

-

ns

0

ns

Output Enable to Output in Low Z

Output Disable to Output in High Z

Output Hold from Address, ROMCSB, or

OEB

0

-

ns

0

ns

TWRBR

Write Recovery time Before Read

6

-

us

FLASH/BOOT ROM – Read Table

85

2001/12/06

Rev.1.5

RTL8139C(L)+

SETUPMPROGRAM

COMMAND

PROGRAM COMMAND

STANDBY/VCC

POWER-DOWN

PROGRAM

VERIFY

VCC POWER-UP

& STANDBY

LATCH ADDRESS

& DATA

PROGRAMMING

VERIFICATION

COMMAND

MA17-0

ROMCSB

OEB

tWC

tAS

tRC

tAH

tCH

tAH

tCS

tCH

tCS

tWHWH1

tWHGL

tWPH

tGHWL

tDF

tWP

tDS

tWP

tDS

tOH

tOE

WEB

tDS

tDH

tOOLZ

tCE

VALID

DATA

IN

DATAOUT

=40H

DATAOUT

=C0H

DATAO

MD7-0

tCOLZ

FLASH MEMORY – Write

Symbol

Description

Write Cycle Time

Minimum

Typical

Maximum Units

TWC

TAS

135

0

60

50

10

6

-

ns

us

Address Set-up Time

Address Hold Time

Data Set-up Time

Data Hold Time

Write Recovery Time before

Read

TAH

TDS

TDH

TWHGL

TGHWL

TCS

Read Recovery Time before

Write

0

-

us

ns

Chip Enable Set-up Time

before

20

Write

TCH

TWP

Chip Enable Hold Time

Write Pulse Width

Write Pulse Width High

Duration of Programming

Operation

0

-

us

ns

us

50

20

10

TWPH

-

TWHWH1

25

FLASH MEMORY – Write Table

86

2001/12/06

Rev.1.5

RTL8139C(L)+

11.3.2 PCI Bus Operation Timing

1

2

3

4

5

6

7

CLK

FRAMEB

AD31-0

ADDRESS

DATA

CBE3-0

BUS CMD

CBE3-0

TRDYB

IRDYB

DEVSELB

Target Read

1

2

3

4

5

6

7

CLK

FRAMEB

AD31-0

ADDRESS

BUS CMD

DATA

CBE3-0

TRDYB

IRDYB

DEVSELB

Target Write

87

2001/12/06

Rev.1.5

RTL8139C(L)+

CLK

1

2

3

4

5

6

7

FRAMEB

IDSEL

AD31-0

CBE3-0

ADDRESS

DATA

BUS CMD

CBE3-0

TRDYB

IRDYB

DEVSELB

Configuration Read

5

CLK

1

2

3

4

6

7

FRAMEB

IDSEL

AD31-0

CBE3-0

ADDRESS

BUS CMD

DATA

CBE3-0

TRDYB

IRDYB

DEVSELB

Configuration Write

88

2001/12/06

Rev.1.5

RTL8139C(L)+

CLK

1

2

3

4

5

6

7

REQB

GNTB

FRAMEB

AD31-0

ADDRESS

DATA

BUS Arbitration

CLK

1

2

3

4

5

6

7

8

FRAMEB

ADDRESS

BUS CMD

DATA1

DATA2

DATA3

DATA4

AD31-0

CBE3-0

TRDYB

IRDYB

DEVSELB

Memory Read

89

2001/12/06

Rev.1.5

RTL8139C(L)+

CLK

1

2

3

4

5

6

7

8

FRAMEB

DATA1

DATA2

DATA3

DATA4

AD31-0

ADDRESS

BUS CMD

CBE3-0

TRDYB

IRDYB

DEVSELB

Memory Write

CLK

1

2

3

4

5

6

7

8

FRAMEB

LO-ADDR HI-ADDR

DUAL AD BUS CMD

DATA1

DATA2

AD31-0

CBE3-0

IRDYB

TRDYB

DEVSELB

Fast

Medium Slow

DAC Memory Read

90

2001/12/06

Rev.1.5

RTL8139C(L)+

CLK

1

2

3

4

5

6

7

8

FRAMEB

LO-ADDR HI-ADDR

DUAL AD BUS CMD

DATA1

DATA2

AD31-0

CBE3-0

IRDYB

TRDYB

DEVSELB

Fast

Medium Slow

DAC Memory Write

CLK

1

2

3

4

5

6

7

FRAMEB

AD31-0

ADDRESS

DATA1

DATA2

IRDYB

TRDYB

STOPB

DEVSELB

Target Initiated Termination - Retry

91

2001/12/06

Rev.1.5

RTL8139C(L)+

CLK

1

2

3

4

5

6

7

FRAMEB

IRDYB

TRDYB

STOPB

DEVSELB

Target Initiated Termination - Disconnect

1

2

3

4

5

6

7

CLK

FRAMEB

IRDYB

TRDYB

STOPB

DEVSELB

Target Initiated Termination - Abort

92

2001/12/06

Rev.1.5

RTL8139C(L)+

1

2

3

4

5

6

7

8

CLK

FRAMEB

IRDYB

DEVSELB

FAST

MED

SLOW

SUB

Master Initiated Termination - Abort

CLK

1

2

3

4

5

6

7

8

FRAMEB

AD31-0

CBE3-0

PAR

ADDRESS

DATA1

DATA2

DATA3

BUS CMD

CBE[3:0]="1000”

Addr par

DATA1-par DATA2-par

DATA3-par

SERRB

PERRB

Parity Operation - One Example

93

2001/12/06

Rev.1.5

RTL8139C(L)+

11.3.3 MII Timing

TxCC

TxckR

TxckF

TxckL

TxckH

TxDS

TxDH

MTXC

MTXE

TxRD

TxRH

MTXD[3:0]

MII Port – Transmit

Symbol

TxCC

TxckR

TxckF

TxckH

TxckL

TxDS

Description

Minimum

Typical

Maximum Units

MTXC cycle

-

14

-

10

-

40

8

-

ns

Ns

MTXC rise time

MTXC fall time

MTXC high time

MTXC low time

MTXD setup

-

26

10

TxDH

TxRD

MTXD hold

MTXC rise to MTXE valid

time or MTXC rise to

MTXD[3:0] valid time

MTXD hold

-

12

-

TxRH

5

Ns

MII Port – Transmit Table

94

2001/12/06

Rev.1.5

RTL8139C(L)+

TrCC

TrckR

TxckF

TrckL

TrckH

TrDS

TrDH

MRXC

TrDS

TrDH

MRXDV

MRXD[3:0]

MII Port – Receive

Symbol

TrCC

TrckR

TrckF

TrckH

TrckL

TrDS

Description

Minimum

Typical

Maximum Units

MRXC cycle

-

40

8

-

ns

MRXC rise time

MRXC fall time

-

MRXC high time

14

10

26

-

MRXC low time

-

MRXD[3:0] setup to MRXC

rise time or MRXDV setup to

MRXC rise time

TrDH

MRXDV hold to after

MRXC rise time or

MRXD[3:0] hold to after

MRXC rise time

10

ns

MII Port – Transmit Table

95

2001/12/06

Rev.1.5

RTL8139C(L)+

TrSF

MRXC

TrHF

MRXER

MII PORT - Receive Error

MTXC

MCOL

TcSF

TcHF

MII PORT - Carrier Sense and Collision

Symbol

Description

Minimum

Typical

Maximum Units

TrSF/TcSF

MRXER (MCOL) setup to

MRXC (MTXC) fall time

MRXER (MCOL) hold to

MRXC (MTXC) fall time

10

-

20

ns

TrHF/TcHF

10

-

18

ns

MII PORT - Carrier Sense and Collision Table

96

2001/12/06

Rev.1.5

RTL8139C(L)+

TmCC

TmckH

TmckL

MDC

TmDI

TmDH

TmDS

TmHZ

TmLZ

TmDIH

READ

WRITE

READ

MDIO

MII Management Port

Symbol

Description

Minimum

Typical

Maximum Units

TmCC

TmckH

TmckL

TmDS

TmDH

TmLZ

MDC cycle time

MDC high time

MDC low time

50

25

10

5

-

ns

MDIO set up (as output pin)

MDIO hold (as output pin)

MDC rising clock to MDIO

(as input pin) Low Impedance

MDC rising clock to MDIO

(as input pin) High

-

40

20

TmHZ

-

ns

Impedance

TmDI

MDIO (as input pin) Valid

from MDC rising edge

MDIO (as input pin) hold

from MDC rising edge

-

40

ns

TmDIH

5

MII Management Port Table

97

2001/12/06

Rev.1.5

RTL8139C(L)+

12. Mechanical Dimensions

Notes:

1. Dimension D & E do not include interlead flash.

2. Dimension b does not include dambar protrusion/intrusion.

3. Controlling dimension: Millimeter

Symbol Dimension in inch

Min Typical Max

Dimension in mm

Min Typical Max

-

0.134

-

3.40

0.91

3.10

0.32

0.25

14.25

20.25

0.75

17.50

23.50

1.08

1.85

0.10

12°

A

A1

A2

b

0.004 0.010 0.036 0.10

0.102 0.112 0.122 2.60

0.005 0.009 0.013 0.12

0.002 0.006 0.010 0.05

0.541 0.551 0.561 13.75

0.778 0.787 0.797 19.75

0.010 0.020 0.030 0.25

0.665 0.677 0.689 16.90

0.902 0.913 0.925 22.90

0.027 0.035 0.043 0.68

0.053 0.063 0.073 1.35

4. General appearance spec. should be based on final visual

inspection spec.

0.25

2.85

0.22

0.15

14.00

20.00

0.5

c

D

TITLE: 128 QFP (14x20 mm ) PACKAGE OUTLINE

-CU L/F, FOOTPRINT 3.2 mm

E

e

LEADFRAME MATERIAL:

APPROVE

DOC. NO.

VERSION

PAGE

530-ASS-P004

HD

HE

L

L1

y

17.20

23.20

0.88

1.60

-

1

OF

CHECK

DWG NO.

DATE

Q128 - 1

Nov. 4 1999

-

0.004

-

0°

-

REALTEK SEMI-CONDUCTOR CO., LTD

θ

0°

12°

98

2001/12/06

Rev.1.5

RTL8139C(L)+

Notes:

1.Dimension b does not include dambar protrusion/intrusion.

2.Controlling dimension: Millimeter

Symbol Dimension in inch

Dimension in mm

Min Typical Max Min Typical Max

-

0.067

-

1.70

0.25

1.50

0.29

0.20

14.25

20.25

BSC

16.30

23.30

0.75

REF

9°

3.General appearance spec. should be based on final visual

inspection spec.

A

A1

A2

b

0.000 0.004 0.008 0.00

0.051 0.055 0.059 1.30

0.006 0.009 0.011 0.15

1.40

0.22

-

0.004

-

0.006 0.09

TITLE: 128LD

APPROVE

CHECK

c

LQFP

( 14x20x1.4 mm*2 ) PACKAGE OUTLINE

-CU L/F, FOOTPRINT 2.0 mm

LEADFRAME MATERIAL:

0.541 0.551 0.561 13.75

0.778 0.787 0.797 19.75

0.020 BSC

D

14.00

20.00

0.50

16.00

22.00

0.60

1.00

3.5°

E

e

DOC. NO.

VERSION

PAGE

530-ASS-P004

0.620 0.630 0.640 15.90

0.855 0.866 0.877 21.70

0.016 0.024 0.031 0.45

0.039 REF

1

HD

HE

L

L1

θ

OF

LQ128 - 1

Nov. 4.1999

DWG NO.

DATE

REALTEK SEMI-CONDUCTOR CO., LTD

0°

3.5°

9°

0°

99

2001/12/06

Rev.1.5

RTL8139C(L)+

Realtek Semiconductor Corp.

Headquarters

1F, No. 2, Industry East Road IX, Science-based

Industrial Park, Hsinchu, 300, Taiwan, R.O.C.

Tel : 886-3-5780211 Fax : 886-3-5776047

WWW: www.realtek.com.tw

100

2001/12/06

Rev.1.5


型号：	RTL8139C_PLUS
厂家：	ETC
描述：	RTL8139C_Plus Specification RTL8139C_Plus规格\n
文件：	总100页 (文件大小：871K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

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