RTL8211 [ETC]
; - 12号的铝制车身绘（ RAL 7032 ）
| 型号： | RTL8211 |
| 厂家： | 
ETC |
| 描述： |
|
| 文件： | 总56页 (文件大小：1740K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
RTL8211C-GR
RTL8211CL-GR
INTEGRATED 10/100/1000 GIGABIT
ETHERNET TRANSCEIVER
DATASHEET
(CONFIDENTIAL: Development Partners Only)
Rev. 1.3
02 September 2008
Track ID: JATR-1076-21
Realtek Semiconductor Corp.
No. 2, Innovation Road II, Hsinchu Science Park, Hsinchu 300, Taiwan
Tel.: +886-3-578-0211 Fax: +886-3-577-6047
www.realtek.com
RTL8211C & RTL8211CL
Datasheet
COPYRIGHT
©2008 Realtek Semiconductor Corp. All rights reserved. No part of this document may be reproduced,
transmitted, transcribed, stored in a retrieval system, or translated into any language in any form or by any
means without the written permission of Realtek Semiconductor Corp.
DISCLAIMER
Realtek provides this document “as is”, without warranty of any kind, neither expressed nor implied,
including, but not limited to, the particular purpose. Realtek may make improvements and/or changes in
this document or in the product described in this document at any time. This document could include
technical inaccuracies or typographical errors.
TRADEMARKS
Realtek is a trademark of Realtek Semiconductor Corporation. Other names mentioned in this document are
trademarks/registered trademarks of their respective owners.
USING THIS DOCUMENT
This document is intended for the software engineer’s reference and provides detailed programming
information.
Though every effort has been made to ensure that this document is current and accurate, more information
may have become available subsequent to the production of this guide. In that event, please contact your
Realtek representative for additional information that may help in the development process.
REVISION HISTORY
Revision
Release Date
2007/09/05
2008/01/11
Summary
1.0
First release.
1.1
Revised RTL8211CL pin 38 (Table 3, page 6).
Revised RTL8211CL pin 34 (Table 6, page 7).
Added section 6.8 LED Configuration, page 19.
Removed MII timing diagram.
Changed AVDD12/DVDD12 1.2V supply voltage to 1.0V.
Revised Table 20, page 22.
Revised Table 21, page 23.
Added 100Base-T4 support (Table 25, page 26).
Added Table 39, page 33.
1.2
1.3
2008/05/26
2008/09/02
Removed MII function.
Revised section 4 Pin Assignments, page 3.
Revised section 5 Pin Descriptions, page 5.
Revised section 8.1 PCB Layout, page 34.
Revised section 8.4 Typical Switching Regulator PCB Layout, page 40.
Added section 8.5 Efficiency Measurement, page 41.
Revised Figure 3, page 11.
Revised Table 38 LEDCR (LED Control Register, Address 0x18), page 33.
Revised Table 33, page 31.
Added 2.5V RGMII data to section 10 Characteristics, page 43.
Revised Table 42, page 43.
Integrated 10/100/1000 Gigabit Ethernet Transceiver
ii
Track ID: JATR-1076-21 Rev. 1.3
RTL8211C & RTL8211CL
Datasheet
Table of Contents
1.
2.
3.
4.
GENERAL DESCRIPTION..............................................................................................................................................1
FEATURES.........................................................................................................................................................................2
SYSTEM APPLICATIONS...............................................................................................................................................2
PIN ASSIGNMENTS .........................................................................................................................................................3
4.1.
RTL8211C PIN ASSIGNMENTS (64-PIN QFN) .............................................................................................................3
PACKAGE IDENTIFICATION...........................................................................................................................................3
RTL8211CL PIN ASSIGNMENTS (48-PIN LQFP) .........................................................................................................4
PACKAGE IDENTIFICATION...........................................................................................................................................4
4.2.
4.3.
4.4.
5.
PIN DESCRIPTIONS ........................................................................................................................................................5
5.1.
TRANSCEIVER INTERFACE............................................................................................................................................5
CLOCK .........................................................................................................................................................................5
RGMII.........................................................................................................................................................................6
MANAGEMENT INTERFACE...........................................................................................................................................6
RESET ..........................................................................................................................................................................6
MODE SELECTION ........................................................................................................................................................7
LED INDICATION .........................................................................................................................................................7
REGULATOR AND REFERENCE......................................................................................................................................7
POWER AND GROUND ..................................................................................................................................................8
NOT CONNECTED .........................................................................................................................................................8
5.2.
5.3.
5.4.
5.5.
5.6.
5.7.
5.8.
5.9.
5.10.
6.
FUNCTION DESCRIPTION ............................................................................................................................................9
6.1.
TRANSMITTER..............................................................................................................................................................9
6.1.1. RGMII (1000Mbps) Mode......................................................................................................................................9
6.1.2. RGMII (100Mbps) Mode........................................................................................................................................9
6.1.3. RGMII (10Mbps) Mode..........................................................................................................................................9
6.2.
RECEIVER.....................................................................................................................................................................9
6.2.1. RGMII (1000Mbps) Mode......................................................................................................................................9
6.2.2. RGMII (100Mbps) Mode......................................................................................................................................10
6.2.3. RGMII (10Mbps) Mode........................................................................................................................................10
6.3.
6.4.
6.5.
HARDWARE CONFIGURATION ....................................................................................................................................10
LED AND PHY ADDRESS CONFIGURATION ...............................................................................................................11
MAC/PHY INTERFACE..............................................................................................................................................12
6.5.1. RGMII...................................................................................................................................................................12
6.5.2. Management Interface..........................................................................................................................................12
6.6.
AUTO-NEGOTIATION..................................................................................................................................................13
6.6.1. Auto-Negotiation Priority Resolution...................................................................................................................16
6.6.2. Auto-Negotiation Master/Slave Resolution ..........................................................................................................16
6.6.3. Auto-Negotiation PAUSE/ASYMMETRIC PAUSE Resolution ............................................................................17
6.7.
6.8.
6.9.
6.10.
CROSSOVER DETECTION AND AUTO-CORRECTION ....................................................................................................18
LED CONFIGURATION................................................................................................................................................19
POLARITY CORRECTION.............................................................................................................................................21
POWER .......................................................................................................................................................................21
7.
REGISTER DESCRIPTIONS.........................................................................................................................................22
7.1.
7.2.
REGISTER MAPPING AND DEFINITIONS.......................................................................................................................22
REGISTER TABLE .......................................................................................................................................................23
7.2.1. BMCR (Basic Mode Control Register, Address 0x00) .........................................................................................23
Integrated 10/100/1000 Gigabit Ethernet Transceiver iii Track ID: JATR-1076-21 Rev. 1.3
RTL8211C & RTL8211CL
Datasheet
7.2.2. BMSR (Basic Mode Status Register, Address 0x01).............................................................................................24
7.2.3. PHYID1 (PHY Identifier Register 1, Address 0x02) ............................................................................................25
7.2.4. PHYID2 (PHY Identifier Register 2, Address 0x03) ............................................................................................26
7.2.5. ANAR (Auto-Negotiation Advertising Register, Address 0x04) ...........................................................................26
7.2.6. ANLPAR (Auto-Negotiation Link Partner Ability Register, Address 0x05) .........................................................27
7.2.7. ANER (Auto-Negotiation Expansion Register, Address 0x06).............................................................................27
7.2.8. ANNPTR (Auto-Negotiation Next Page Transmit Register, Address 0x07).........................................................28
7.2.9. ANNPRR (Auto-Negotiation Next Page Receive Register, Address 0x08)...........................................................28
7.3.
GBCR (1000BASE-T CONTROL REGISTER, ADDRESS 0X09) .....................................................................................29
7.3.1. GBSR (1000Base-T Status Register, Address 0x0A) ............................................................................................30
7.3.2. GBESR (1000Base-T Extended Status Register, Address 0x0F)..........................................................................30
7.3.3. PHYCR (PHY Specific Control Register, Address 0x10) .....................................................................................31
7.3.4. PHYSR (PHY Specific Status Register, Address 0x11).........................................................................................31
7.3.5. INER (Interrupt Enable Register, Address 0x12).................................................................................................32
7.3.6. INSR (Interrupt Status Register, Address 0x13)...................................................................................................32
7.3.7. RXERC (Receive Error Counter, Address 0x15)..................................................................................................33
7.3.8. LEDCR (LED Control Register, Address 0x18)...................................................................................................33
7.3.9. PAGSEL (Page Select Register, Address 0x1F)...................................................................................................33
8.
SWITCHING REGULATOR..........................................................................................................................................34
8.1.
PCB LAYOUT.............................................................................................................................................................34
INDUCTOR AND CAPACITOR PARTS LIST....................................................................................................................35
MEASUREMENT CRITERIA..........................................................................................................................................36
TYPICAL SWITCHING REGULATOR PCB LAYOUT.......................................................................................................40
EFFICIENCY MEASUREMENT ......................................................................................................................................41
POWER SEQUENCE .....................................................................................................................................................42
8.2.
8.3.
8.4.
8.5.
8.6.
9.
APPLICATION DIAGRAM ...........................................................................................................................................42
CHARACTERISTICS.................................................................................................................................................43
10.
10.1.
ABSOLUTE MAXIMUM RATINGS.................................................................................................................................43
RECOMMENDED OPERATING CONDITIONS .................................................................................................................43
CRYSTAL REQUIREMENTS..........................................................................................................................................43
DC CHARACTERISTICS...............................................................................................................................................44
AC CHARACTERISTICS...............................................................................................................................................44
10.2.
10.3.
10.4.
10.5.
10.5.1.
10.5.2.
MDC/MDIO Timing ........................................................................................................................................44
RGMII Timing Modes......................................................................................................................................45
11.
MECHANICAL DIMENSIONS.................................................................................................................................47
11.1.
11.2.
11.3.
RTL8211C 64-PIN QFN MECHANICAL DIMENSIONS.................................................................................................47
RTL8211CL 48-PIN LQFP MECHANICAL DIMENSIONS ............................................................................................48
RTL8211CL 48-PIN LQFP MECHANICAL DIMENSIONS NOTES.................................................................................49
12.
ORDERING INFORMATION...................................................................................................................................50
Integrated 10/100/1000 Gigabit Ethernet Transceiver
iv
Track ID: JATR-1076-21 Rev. 1.3
RTL8211C & RTL8211CL
Datasheet
List of Tables
TABLE 1. TRANSCEIVER INTERFACE .............................................................................................................................................5
TABLE 2. CLOCK...........................................................................................................................................................................5
TABLE 3. RGMII ..........................................................................................................................................................................6
TABLE 4. MANAGEMENT INTERFACE............................................................................................................................................6
TABLE 5. RESET............................................................................................................................................................................6
TABLE 6. MODE SELECTION..........................................................................................................................................................7
TABLE 7. LED INDICATION...........................................................................................................................................................7
TABLE 8. REGULATOR AND REFERENCE .......................................................................................................................................7
TABLE 9. POWER AND GROUND....................................................................................................................................................8
TABLE 10. NOT CONNECTED...........................................................................................................................................................8
TABLE 11. CONFIG PINS VS. CONFIGURATION REGISTER............................................................................................................10
TABLE 12. CONFIGURATION REGISTER DEFINITION ......................................................................................................................10
TABLE 13. TYPICAL MDIO FRAME FORMAT.................................................................................................................................12
TABLE 14. 1000BASE-T BASE AND NEXT PAGES BIT ASSIGNMENTS............................................................................................14
TABLE 15. LED CONFIGURATION (RTL8211C)............................................................................................................................19
TABLE 16. LED DEFAULT DEFINITIONS (RTL8211CL)................................................................................................................20
TABLE 17. LED INDICATION.........................................................................................................................................................20
TABLE 18. LED REGISTER TABLE (RTL8211CL).........................................................................................................................20
TABLE 19. LED CONFIGURATION TABLE (RTL8211CL)..............................................................................................................20
TABLE 20. REGISTER MAPPING AND DEFINITIONS ........................................................................................................................22
TABLE 21. BMCR (BASIC MODE CONTROL REGISTER, ADDRESS 0X00) ......................................................................................23
TABLE 22. BMSR (BASIC MODE STATUS REGISTER, ADDRESS 0X01)..........................................................................................24
TABLE 23. PHYID1 (PHY IDENTIFIER REGISTER 1, ADDRESS 0X02) ...........................................................................................25
TABLE 24. PHYID2 (PHY IDENTIFIER REGISTER 2, ADDRESS 0X03) ...........................................................................................26
TABLE 25. ANAR (AUTO-NEGOTIATION ADVERTISING REGISTER, ADDRESS 0X04)....................................................................26
TABLE 26. ANLPAR (AUTO-NEGOTIATION LINK PARTNER ABILITY REGISTER, ADDRESS 0X05) ...............................................27
TABLE 27. ANER (AUTO-NEGOTIATION EXPANSION REGISTER, ADDRESS 0X06)........................................................................27
TABLE 28. ANNPTR (AUTO-NEGOTIATION NEXT PAGE TRANSMIT REGISTER, ADDRESS 0X07).................................................28
TABLE 29. ANNPRR (AUTO-NEGOTIATION NEXT PAGE RECEIVE REGISTER, ADDRESS 0X08) ...................................................28
TABLE 30. GBCR (1000BASE-T CONTROL REGISTER, ADDRESS 0X09) .......................................................................................29
TABLE 31. GBSR (1000BASE-T STATUS REGISTER, ADDRESS 0X0A)..........................................................................................30
TABLE 32. GBESR (1000BASE-T EXTENDED STATUS REGISTER, ADDRESS 0X0F)......................................................................30
TABLE 33. PHYCR (PHY SPECIFIC CONTROL REGISTER, ADDRESS 0X10) ..................................................................................31
TABLE 34. PHYSR (PHY SPECIFIC STATUS REGISTER, ADDRESS 0X11)......................................................................................31
TABLE 35. INER (INTERRUPT ENABLE REGISTER, ADDRESS 0X12)..............................................................................................32
TABLE 36. INSR (INTERRUPT STATUS REGISTER, ADDRESS 0X13)...............................................................................................32
TABLE 37. RXERC (RECEIVE ERROR COUNTER, ADDRESS 0X15)................................................................................................33
TABLE 38. LEDCR (LED CONTROL REGISTER, ADDRESS 0X18)..................................................................................................33
TABLE 39. PAGSEL (PAGE SELECT REGISTER, ADDRESS 0X1F)..................................................................................................33
TABLE 40. INDUCTOR AND CAPACITOR PARTS LIST......................................................................................................................35
TABLE 41. POWER SEQUENCE PARAMETER ...................................................................................................................................42
TABLE 42. ABSOLUTE MAXIMUM RATINGS ..................................................................................................................................43
TABLE 43. RECOMMENDED OPERATING CONDITIONS ...................................................................................................................43
TABLE 44. CRYSTAL REQUIREMENTS............................................................................................................................................43
TABLE 45. DC CHARACTERISTICS.................................................................................................................................................44
TABLE 46. MDC/MDIO MANAGEMENT TIMING PARAMETERS ....................................................................................................45
TABLE 47. RGMII TIMING PARAMETERS......................................................................................................................................46
TABLE 48. ORDERING INFORMATION ............................................................................................................................................50
Integrated 10/100/1000 Gigabit Ethernet Transceiver
v
Track ID: JATR-1076-21 Rev. 1.3
RTL8211C & RTL8211CL
Datasheet
List of Figures
FIGURE 1. RTL8211C PIN ASSIGNMENTS (64-PIN QFN)...............................................................................................................3
FIGURE 2. RTL8211CL PIN ASSIGNMENTS (48-PIN LQFP) ..........................................................................................................4
FIGURE 3. LED AND PHY ADDRESS CONFIGURATION ................................................................................................................11
FIGURE 4. TYPICAL MDC/MDIO READ TIMING..........................................................................................................................12
FIGURE 5. TYPICAL MDC/MDIO WRITE TIMING........................................................................................................................13
FIGURE 6. SWITCHING REGULATOR APPLICATION.......................................................................................................................34
FIGURE 7. INPUT VOLTAGE OVERSHOOT <4V (GOOD)................................................................................................................36
FIGURE 8. INPUT VOLTAGE OVERSHOOT >4V (BAD)...................................................................................................................36
FIGURE 9. CERAMIC 22µF 1210(X5R) (GOOD)............................................................................................................................37
FIGURE 10. CERAMIC 22µF 0805(Y5V) (BAD)..............................................................................................................................37
FIGURE 11. ELECTROLYTIC 100µF (RIPPLE TOO HIGH).................................................................................................................38
FIGURE 12. 4R7GTSD32 (GOOD).................................................................................................................................................39
FIGURE 13. 1µH BEAD (BAD)........................................................................................................................................................39
FIGURE 14. 64-PIN TYPICAL SWITCHING REGULATOR PCB LAYOUT (TOP LAYER)......................................................................40
FIGURE 15. 64-PIN TYPICAL SWITCHING REGULATOR PCB LAYOUT (BOTTOM LAYER) ..............................................................40
FIGURE 16. SWITCHING REGULATOR EFFICIENCY MEASUREMENT CHECKPOINT ..........................................................................41
FIGURE 17. POWER SEQUENCE......................................................................................................................................................42
FIGURE 18. APPLICATION DIAGRAM .............................................................................................................................................42
FIGURE 19. MDC/MDIO MANAGEMENT TIMING PARAMETERS ...................................................................................................44
FIGURE 20. RGMII TIMING MODES ..............................................................................................................................................46
Integrated 10/100/1000 Gigabit Ethernet Transceiver
vi
Track ID: JATR-1076-21 Rev. 1.3
RTL8211C & RTL8211CL
Datasheet
1. General Description
The Realtek RTL8211C(L) is a highly integrated Ethernet transceiver that complies with 10Base-T,
100Base-TX, and 1000Base-T IEEE 802.3 standards. It provides all the necessary physical layer functions
to transmit and receive Ethernet packets over CAT 5 UTP cable or CAT 3 UTP (10Mbps only) cable.
The RTL8211C(L) uses state-of-the-art DSP technology and an Analog Front End (AFE) to enable
high-speed data transmission and reception over UTP cable. Functions such as Crossover Detection &
Auto-Correction, polarity correction, adaptive equalization, cross-talk cancellation, echo cancellation,
timing recovery, and error correction are implemented in the RTL8211C(L) to provide robust transmission
and reception capabilities at 10Mbps, 100Mbps, or 1000Mbps.
Data transfer between MAC and PHY is via the Reduced Gigabit Media Independent Interface (RGMII) for
1000Base-T, 10Base-T, and 100Base-TX.
Integrated 10/100/1000 Gigabit Ethernet Transceiver
1
Track ID: JATR-1076-21 Rev. 1.3
RTL8211C & RTL8211CL
Datasheet
2. Features
1000Base-T IEEE 802.3ab Compliant
100Base-TX IEEE 802.3u Compliant
10Base-T IEEE 802.3 Compliant
IEEE 802.3 Compliant RGMII
Supports Auto-Negotiation
Transmission rate up to 1Gbps over industry
standard CAT.5 UTP cable with BER less than
10-10 in 1000Base-T
The design transceiver capability target is up
to 120m for CAT.5 cable in 1000Base-T
Supports 3.3V or 2.5V signaling for RGMII
Supports 25MHz external crystal or OSC
Provides 125MHz clock source for MAC
Provides 6 network status LEDs (RTL8211C)
Supports Parallel Detection
Crossover Detection & Auto-Correction
Automatic polarity correction
Transmit wave-shaping
Provides 3 network status LEDs
(RTL8211CL)
DSP processing
Supports Link Down power saving
Built-in Switching regulator
64-pin QFN (RTL8211C)
Internal hybrids for 1000Base-T
Baseline Wander Correction
Supports half/full duplex operation
48-pin LQFP (RTL8211CL)
0.11µm process with very low power
consumption
3. System Applications
Network Interface Adapter, MAU (Media Access Unit), CNR (Communication and Network Riser), ACR
(Advanced Communication Riser), Ethernet hub, and Ethernet switch.
In addition, it can be used in any embedded system with an Ethernet MAC that needs a UTP physical
connection.
Integrated 10/100/1000 Gigabit Ethernet Transceiver
2
Track ID: JATR-1076-21 Rev. 1.3
RTL8211C & RTL8211CL
Datasheet
4. Pin Assignments
4.1. RTL8211C Pin Assignments (64-Pin QFN)
Figure 1. RTL8211C Pin Assignments (64-Pin QFN)
4.2. Package Identification
Green package is indicated by a ‘G’ in the location marked ‘T’ in Figure 1.
Integrated 10/100/1000 Gigabit Ethernet Transceiver
3
Track ID: JATR-1076-21 Rev. 1.3
RTL8211C & RTL8211CL
Datasheet
4.3. RTL8211CL Pin Assignments (48-Pin LQFP)
Figure 2. RTL8211CL Pin Assignments (48-Pin LQFP)
4.4. Package Identification
‘Green’ package is indicated by a ‘G’ in the location marked ‘T’ in Figure 2.
Integrated 10/100/1000 Gigabit Ethernet Transceiver
4
Track ID: JATR-1076-21 Rev. 1.3
RTL8211C & RTL8211CL
Datasheet
5. Pin Descriptions
Note that some pins have multiple functions. Refer to the Pin Assignment figures on page 3 (RTL8211C)
and on page 4 (RTL8211CL) for a graphical representation.
5.1. Transceiver Interface
Table 1. Transceiver Interface
Pin No.
(64-pin)
Pin No.
(48-pin)
Pin Name
MDI[0]+
MDI[0]−
MDI[1]+
MDI[1]−
Type Description
3
4
6
7
1
2
4
5
IO
IO
IO
IO
In MDI mode, this is the first pair in 1000Base-T, i.e., the BI_DA+/- pair,
and is the transmit pair in 10Base-T and 100Base-TX.
In MDI crossover mode, this pair acts as the BI_DB+/- pair, and is the
receive pair in 10Base-T and 100Base-TX.
In MDI mode, this is the second pair in 1000Base-T, i.e., the BI_DB+/-
pair, and is the receive pair in 10Base-T and 100Base-TX.
In MDI crossover mode, this pair acts as the BI_DA+/- pair, and is the
transmit pair in 10Base-T and 100Base-TX.
11
12
14
15
8
9
MDI[2]+
MDI[2]−
MDI[3]+
MDI[3]−
IO
IO
IO
IO
In MDI mode, this is the third pair in 1000Base-T, i.e., the BI_DC+/- pair.
In MDI crossover mode, this pair acts as the BI_DD+/- pair.
11
12
In MDI mode, this is the fourth pair in 1000Base-T, i.e., the BI_DD+/-
pair.
In MDI crossover mode, this pair acts as the BI_DC+/- pair.
5.2. Clock
Table 2. Clock
Pin No.
Pin No.
Pin Name
Type Description
(64-pin) (48-pin)
61
62
41
42
43
32
CKXTAL1
CKXTAL2
CLK125
I
Input/Output of 25MHz Clock Reference.
125MHz Reference Clock Generated from Internal PLL.
O
O
Integrated 10/100/1000 Gigabit Ethernet Transceiver
5
Track ID: JATR-1076-21 Rev. 1.3
RTL8211C & RTL8211CL
Datasheet
5.3. RGMII
Table 3. RGMII
Type Description
Pin No.
(64-pin)
Pin No.
(48-pin)
Pin Name
24
22
TXC
I
The transmit reference clock will be 125MHz, 25MHz, or 2.5MHz
±50ppm depending on speed.
25
26
27
28
29
22
23
24
25
26
27
19
TXD[0]
TXD[1]
TXD[2]
TXD[3]
TXCTL
RXC
I
I
Transmit Data.
Data is transmitted from MAC to PHY via TXD[3:0].
I
I
I
Receive Control Signal from the MAC.
O
The continuous receive reference clock will be 125MHz, 25MHz, or
2.5MHz ±50ppm. and is derived from the received data stream
17
19
20
21
16
19
14
16
17
18
13
16
RXD[0]
RXD[1]
RXD[2]
RXD[3]
RXCTL
TXDLY
O
O
O
O
O
I
Receive Data.
Data is transmitted from PHY to MAC via RXD[3:0].
Transmit Control Signal to the MAC.
RGMII Transmit Clock Timing Control.
1: Add 2 ns delay to TXC for TXD latching
RGMII Receiver Clock Timing Control.
1: Add 2ns delay to RXC for RXD latching
43
38
RXDLY
I
5.4. Management Interface
Table 4. Management Interface
Pin No.
(64-pin)
Pin No.
(48-pin)
Pin Name
Type Description
30
31
30
31
MDC
I
Management Data Clock.
MDIO
IO
Input/Output of Management Data.
5.5. Reset
Table 5. Reset
Pin No.
(64-pin)
Pin No.
(48-pin)
Pin Name
Type
Description
38
29
PHYRSTB
I
Hardware Reset. Active low.
Integrated 10/100/1000 Gigabit Ethernet Transceiver
6
Track ID: JATR-1076-21 Rev. 1.3
RTL8211C & RTL8211CL
Datasheet
5.6. Mode Selection
Table 6. Mode Selection
Pin No.
(64-pin)
Pin No.
(48-pin)
Pin Name
Type Description
50
44
20
21
34
35
17
18
PHY_AD0
PHY_AD1
AN0
I
I
I
I
PHY Configuration.
AN1
Note: See section 6.3 Hardware Configuration, page 10 for details.
5.7. LED Indication
Table 7. LED Indication
Type Description
Pin No.
Pin No.
Pin Name
(64-pin) (48-pin)
43
48
44
50
39
40
34
-
LED_Duplex/LED0
LED_100
O
O
O
O
O
O
LED Duplex (RTL8211C), LED0 (RTL8211CL)
LED 100
35
38
-
LED_1000/LED1
LED_10/LED2
LED_TX
LED1000 (RTL8211C), LED1 (RTL8211CL)
LED10 (RTL8211C), LED2 (RTL8211CL)
LED TX
LED RX
-
LED_RX
Note: See section 6.8 LED Configuration, page 19 for details.
5.8. Regulator and Reference
Table 8. Regulator and Reference
Type Description
Pin No.
(64-pin)
Pin No.
(48-pin)
Pin Name
64
46
RSET
I
Reference.
External Resistor Reference.
63
1
44, 45
48
VDDREG
REG_OUT
Power 3.3V Power Supply for Switching Regulator.
O
Switching Regulator 1.0V Output.
Connect to a 4.7µH inductor.
5
3
FB10
I
I
Feedback Pin for Switching Regulator.
3.3V: Enable switching regulator.
0V: Disable switching regulator.
58
39
ENSWREG
Integrated 10/100/1000 Gigabit Ethernet Transceiver
7
Track ID: JATR-1076-21 Rev. 1.3
RTL8211C & RTL8211CL
Datasheet
5.9. Power and Ground
Table 9. Power and Ground
Pin No.
(64-pin)
Pin No.
(48-pin)
Pin Name
Type
Description
18, 23, 49
18, 23
36, 45
8, 60
15, 21, 37
15, 21
DVDD33
DVDD33
DVDD10
AVDD33
AVDD10
GND
Power
Power
Power
Power
Power
Ground
Digital Power. 3.3V.
RGMII Power Pins, For 3.3 or 2.5V RGMII I/O.
Digital Power. 1.05V.
28, 36
6, 41
Analog Power. 3.3V.
13, 59
E-Pad
10, 40
Analog Power. 1.05V.
7, 20, 33, 47
Ground.
Exposed Pad (E-Pad) (64-pin package only) is Analog and
Digital Ground (see section 11.1 RTL8211C 64-Pin QFN
Mechanical Dimensions, page 47).
5.10. Not Connected
Table 10. Not Connected
Pin No. (64-pin)
Pin No.
Pin Name
Type Description
(48-pin)
2, 9, 10, 32, 33, 34, 35, 37, 42, 46,
47, 51, 52, 53, 54, 55, 56, 57
NULL
NC
NC Not Connected.
Integrated 10/100/1000 Gigabit Ethernet Transceiver
8
Track ID: JATR-1076-21 Rev. 1.3
RTL8211C & RTL8211CL
Datasheet
6. Function Description
6.1. Transmitter
Based on state-of-the-art DSP technology and mixed-mode signal processing technology, the
RTL8211C(L) is capable of operating at 10/100/1000Mbps link speed over standard CAT.5 UTP cable and
CAT.3 UTP cable (10Mbps).
6.1.1. RGMII (1000Mbps) Mode
The RTL8211C(L)’s PCS layer receives data bytes from the MAC through the RGMII interface and
performs the generation of continuous code-groups through 4D-PAM5 coding technology. Then those code
groups are passed through a waveform-shaping filter to minimize EMI effect, and are transmitted onto the
4-pair CAT5 cable at 125MBaud/s through a D/A converter.
6.1.2. RGMII (100Mbps) Mode
The transmitted 4-bit nibbles (TXD[3:0]) from the MAC, clocked at 25MHz (TXC), are converted into 5B
symbol code through 4B/5B coding technology, then through scrambling and serializing, are converted to
125MHz NRZ and NRZI signals. After that, the NRZI signal are passed to the MLT3 encoder, then to the
D/A converter and transmitted onto the media.
6.1.3. RGMII (10Mbps) Mode
The transmit 4-bit nibbles (TXD[3:0]) from the MAC, clocked at 2.5MHz (TXC), are serialized into
10Mbps serial data. Then the 10Mbps serial data is converted into a Manchester-encoded data stream and is
transmitted onto the media by the D/A converter.
6.2. Receiver
6.2.1. RGMII (1000Mbps) Mode
Input signals from the media first pass through the on-chip sophisticated hybrid circuit to subtract the
transmitted signal from the input signal for effective reduction of near-end echo. Afterwards, the received
signal is processed with state-of-the-art technology, such as adaptive equalization, BLW (Baseline
Wander) correction, cross-talk cancellation, echo cancellation, timing recovery, error correction, and
4D-PAM5 decoding. Then, the 8-bit-wide data is recovered and is sent to the RGMII interface at a clock
speed of 125MHz. The Rx MAC retrieves the packet data from the receive RGMII interface and sends it to
the Rx Buffer Manager.
Integrated 10/100/1000 Gigabit Ethernet Transceiver
9
Track ID: JATR-1076-21 Rev. 1.3
RTL8211C & RTL8211CL
Datasheet
6.2.2. RGMII (100Mbps) Mode
The MLT3 signal is processed with an ADC, equalizer, BLW (Baseline Wander) correction, timing
recovery, MLT3 and NRZI decoder, descrambler, 4B/5B decoder, and is then presented to the RGMII
interface in 4-bit-wide nibbles at a clock speed of 25MHz.
6.2.3. RGMII (10Mbps) Mode
The received differential signal is converted into a Manchester-encoded stream first. Next, the stream is
processed with a Manchester decoder, and is de-serialized into 4-bit-wide nibbles. The 4-bit nibbles are
presented to the RGMII interface at a clock speed of 2.5MHz.
6.3. Hardware Configuration
The operation speed, interface mode, and PHY address can be set by the CONFIG pins. The respective
value mapping of CONFIG with the configurable vector is listed in Table 11. To set the CONFIG pins, an
external pull-high or pull-low via resister is required.
Table 11. CONFIG Pins vs. Configuration Register
RTL8211C Pin
LED Link 10
LED Link 1000
RXD2
RTL8211CL Pin
LED0
Pin Name
PHYAD[0]
PHYAD[1]
AN[0]
LED1
RXD2
RXD3
RXD3
AN[1]
Table 12. Configuration Register Definition
Configuration Description
PHYAD[1:0]
PHY Address.
PHYAD sets the PHY address for the device.
Note: PHYAD[:]=0 can support all PHYaddresses. It can automatically remember the first MAC address.
Auto-Negotiation (NWay) Configuration.
AN[1:0]
AN[1:0] controls the setting of Auto-Negotiation enable/disable, speed, and duplex setting.
00: 10Base-T Full Duplex
01: 100base-Tx Half Duplex
10: 100base-Tx Full Duplex
11: NWay. Advertise all capabilities
Integrated 10/100/1000 Gigabit Ethernet Transceiver
10
Track ID: JATR-1076-21 Rev. 1.3
RTL8211C & RTL8211CL
Datasheet
6.4. LED and PHY Address Configuration
In order to reduce the pin count on the RTL8211C(L), the LED pins are duplex with the PHY address pins.
Because the PHYAD strap options share the LED output pins, the external combinations required for
strapping and LED usage must be considered in order to avoid contention. Specifically, when the LED
outputs are used to drive LEDs directly, the active state of each output driver is dependent on the logic level
sampled by the corresponding PHYAD input upon power-up/reset. For example, as Figure 3 (left-side)
shows, if a given PHYAD input is resistively pulled high then the corresponding output will be configured
as an active low driver. On the right side, we can see that if a given PHYAD input is resistively pulled low
then the corresponding output will be configured as an active high driver. The PHY address configuration
pins should not be connected to GND or VCC directly, but must be pulled high or low through a resistor (ex
4.7KΩ). If no LED indications are needed, the components of the LED path (LED+510Ω) can be removed.
PHY Address[:]=Logical 1
RXDLY=Logical 1
PHY Address[:]=Logical 0
RXDLY=Logical 0
LED Indication=Active low
LED Indication=Active High
Figure 3. LED and PHY Address Configuration
Integrated 10/100/1000 Gigabit Ethernet Transceiver
11
Track ID: JATR-1076-21 Rev. 1.3
RTL8211C & RTL8211CL
Datasheet
6.5. MAC/PHY Interface
The RTL8211C(L) supports industry standard and is suitable for most off-the-shelf MACs with a RGMII
interface.
6.5.1. RGMII
In 1000Base-T mode (RGMII interface is selected), TXC and RXC sources are 125MHz. TXC will always
be generated by the MAC and RXC will always be generated by the PHY. TXD[3:0] and RXD[3:0] signals
are used for date transitions on rising edge and on falling edge of clock.
6.5.2. Management Interface
The management interface provides access to the internal registers through the MDC and MDIO pins as
described in IEEE 802.3u section 22. The MDC signal, provided by the MAC, is the management data
clock reference to the MDIO signal. The MDIO is the management data input/output and is a bi-directional
signal that runs synchronously to MDC. The MDIO pin needs a 10k Ohm pull-up resistor to maintain the
MDIO high during idle and turnaround.
Preamble suppression is the default setting of the RTL8211C(L) after power-on. However, there still must
be at least one idle bit between operations.
Up to 32 RTL8211C(L)s can share the same MDIO line. In switch/router applications, each port should be
assigned a unique address during the hardware reset sequence, and it can only be addressed via that unique
PHY address. For detailed information on the RTL8211C(L) management registers, see section 7 Register
Descriptions, page 22.
Table 13. Typical MDIO Frame Format
<idle><start><op code><PHY addr.><reg. addr.><turnaround><data><idle>
<idle><01><10><AAAAA><RRRRR><Z0><xxxx xxxx xxxx xxxx><idle>
<idle><01><01><AAAAA><RRRRR><10><xxxx xxxx xxxx xxxx><idle>
Management Serial Protocol
Read
Write
MDC
z
z
MDIO(MAC)
z
MDIO(PHY)
z
z
z
1 1 1
0 0 0 0 0 0 0 0 0 0 0 0 0 0
0
1
1
0
0
0
0
0
1
0
0
0
0
0
Read
(OP
Code)
Idle Start
PHY Address
0x01
Reg. Address
0x00 (BMCR)
Turn
Around
Reg. Data
0x1140
Idle
Figure 4. Typical MDC/MDIO Read Timing
Integrated 10/100/1000 Gigabit Ethernet Transceiver
12
Track ID: JATR-1076-21 Rev. 1.3
RTL8211C & RTL8211CL
Datasheet
MDC
z
z
MDIO(MAC)
z
z
0 0 0 0 0 0
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
Write
(OP
Code)
PHY Address
0x01
Reg. Address
0x00 (BMCR)
Turn
Around
Reg. Data
0x1340
Idle
Start
Idle
Figure 5. Typical MDC/MDIO Write Timing
6.6. Auto-Negotiation
Auto-Negotiation is a mechanism to determine the fastest connection between two link partners. For copper
media applications, it was introduced in IEEE 802.3u for Ethernet and Fast Ethernet, and then in
IEEE 802.3ab to address extended functions for Gigabit Ethernet. It performs the following:
• Auto-Negotiation Priority Resolution
• Auto-Negotiation Master/Slave Resolution
• Auto-Negotiation PAUSE/ASYMMETRIC PAUSE Resolution
• Crossover Detection & Auto-Correction Resolution
Upon de-assertion of a hardware reset, the RTL8211C(L) can be configured to have auto-negotiation
enabled, or be forced to operate in 10Base-T, 100Base-TX, or 1000Base-T mode via the CONFIG pins (see
section 6.3 Hardware Configuration, page 10). If the RTL8211C(L) is configured to operate only in
1000Base-T mode, then auto-negotiation is still enabled with only 1000Base-T mode advertised.
The auto-negotiation process is initiated automatically upon any of the following:
• Power-up
• Hardware reset
• Software reset (register 0.15)
• Restart auto-negotiation (register 0.9)
• Transition from power down to power up (register 0.11)
• Entering the link fail state
Integrated 10/100/1000 Gigabit Ethernet Transceiver
13
Track ID: JATR-1076-21 Rev. 1.3
RTL8211C & RTL8211CL
Datasheet
Table 14. 1000Base-T Base and Next Pages Bit Assignments
Name Bit Description
Bit
Register Location
Base Page
D15
NP
Next Page.
-
1: Indicates that Next Pages follow
0: Indicates that no Next Pages follow
Acknowledge.
D14
D13
Ack
RF
-
-
1: Indicates that a device has successfully received its link
partner’s Link Code Word (LCW)
Remote Fault.
1: Indicates to its link partner that a device has encountered a
fault condition
D[12:5]
D[4:0]
A[7:0] Technology Ability Field.
Indicates to its link partner the supported technologies specific to
Register 4.[12:5]
Table 25, page 26.
the selector field value.
S[4:0]
Selector Field.
Register 4.[4:0]
Always 00001.
Table 25, page 26.
Indicates to its link partner that it is an IEEE Std 802.3 device.
PAGE 0 (Message Next Page)
Next Page.
M15
NP
-
1: Indicates that Next Pages follow
0: Indicates that no Next Pages follow
Acknowledge.
M14
M13
Ack
MP
Ack2
T
-
-
-
-
-
1: Indicates that a device has successfully received its link
partner’s Link Code Word (LCW)
Message Page.
1: Indicates to its link partner that this is a message page, not an
unformatted page.
M12
Acknowledge 2.
1: Indicates to its link partner that a device has the ability to
comply with the message.
M11
Toggle.
Used by the NWay arbitration function to ensure
synchronization with its link partner during Next Page exchange.
M[10:0]
-
1000Base-T Message Code.
Always 8.
PAGE 1 (Unformatted Next Page)
Next Page.
U15
NP
-
1: Indicates that Next Pages follow
0: Indicates that no Next Pages follow
Acknowledge.
U14
U13
Ack
MP
-
-
1: Indicates that a device has successfully received its link
partner’s Link Code Word (LCW)
Message Page.
1: Indicates to its link partner that this is a message page, not an
unformatted page.
Integrated 10/100/1000 Gigabit Ethernet Transceiver
14
Track ID: JATR-1076-21 Rev. 1.3
RTL8211C & RTL8211CL
Datasheet
Bit
Name Bit Description
Register Location
U12
Ack2
Acknowledge 2.
-
1: Indicates to its link partner that a device has the ability to
comply with the message.
U11
T
Toggle.
-
Used by the NWay arbitration function to ensure
synchronization with its link partner during Next Page exchange.
U[10:5]
U4
-
-
Reserved. Transmit as 0
-
1000Base-T Half Duplex.
1: Half duplex
RGMII register 9.8 (GBCR)
Table 30, page 29.
0: No half duplex
U3
U2
U1
-
-
-
1000Base-T Full Duplex.
1: Full duplex
RGMII register 9.8 (GBCR)
Table 30, page 29.
0: No full duplex
1000Base-T Port Type Bit.
1: Multi-port device
RGMII register 9.8 (GBCR)
Table 30, page 29.
0: Single-port device
1000Base-T Master-Slave Manual Configuration Value.
1: Master
RGMII register 9.8 (GBCR)
Table 30, page 29.
0: Salve
This bit is ignored if bit 9.12=0
1000Base-T Master-Slave Manual Configuration Enable.
1: Manual Configuration Enable
U0
-
RGMII register 9.8 (GBCR)
Table 30, page 29.
This bit is intended to be used for manual selection in
Master-Slave mode, and is to be used in conjunction with bit
9.11
PAGE 2 (Unformatted Next Page)
Next Page.
U15
NP
-
1: Indicates that Next Pages follow
0: Indicates that no Next Pages follow
Acknowledge.
U14
U13
Ack
MP
Ack2
T
-
-
-
-
1: Indicates that a device has successfully received its link
partner’s Link Code Word (LCW)
Message Page.
1: Indicates to its link partner that this is a message page, not an
unformatted page.
U12
Acknowledge 2.
1: Indicates to its link partner that a device has the ability to
comply with the message.
U11
Toggle.
Used by the NWay arbitration function to ensure
synchronization with its link partner during Next Page exchange.
U[10:0]
-
1000Base-T Master-Slave Seed Bit[10:0]
Master-Slave
Seed Value SB[10:0]
Integrated 10/100/1000 Gigabit Ethernet Transceiver
15
Track ID: JATR-1076-21 Rev. 1.3
RTL8211C & RTL8211CL
Datasheet
6.6.1. Auto-Negotiation Priority Resolution
Upon the start of auto-negotiation, to advertise its capabilities each station transmits a 16-bit packet called
a Link Code Word (LCW), within a burst of 17 to 33 Fast Link Pulses (FLP). A device capable of
auto-negotiation transmits and receives the FLPs. The receiver must identify three identical LCWs before
the information is authenticated and used in the arbitration process. The devices decode the base LCW and
select capabilities with the highest common denominator supported by both devices.
To advertise 1000Base-T capability, both link partners, sharing the same link medium, should engage in
Next Page (1000Base-T Message Page, Unformatted Page 1, and Unformatted Page 2) exchange.
Auto-negotiation ensures that the highest priority protocol will be selected as the link speed based on the
following priorities advertised through the Link Code Word (LCW) exchange. Refer to IEEE 802.3 Clause
28 for detailed information.
1. 1000Base-T Full Duplex (highest priority)
2. 1000Base-T Half Duplex
3. 100Base-Tx Full Duplex
4. 100Base-Tx Half Duplex
5. 10Base-T Full Duplex
6. 10Base-T Half Duplex (lowest priority)
6.6.2. Auto-Negotiation Master/Slave Resolution
To establish a valid 1000Base-T link, the Master/Slave mode of both link partners should be resolved
through the auto-negotiation process:
Master Priority:
Multi-port > Single port
Manual > Non-manual
Determination of Master/Slave configuration from LCW:
Manual_MASTER=U0*U1
Manual_SLAVE=U0*!U1
Single-port device=!U0*!U2
Integrated 10/100/1000 Gigabit Ethernet Transceiver
16
Track ID: JATR-1076-21 Rev. 1.3
RTL8211C & RTL8211CL
Datasheet
Multi-port device=!U0*U2
Where: U0 is bit 0 of the Unformatted Page 1
U1 is bit 1 of the Unformatted Page 1
U2 is bit 2 of the Unformatted Page 1
Where there are two stations with the same configuration, the one with higher Master-Slave seed
SB[10:0] in the unformatted page 2 shall become Master.
Master-Slave configuration process resolution:
Successful: Bit 10.15 Master-Slave Configuration Fault is set to logical 0, and bit 10.14 is set to
logical 1 for Master resolution, or set to logical 0 for Slave resolution.
Unsuccessful: Auto-Negotiation restarts.
Fault detect: Bit 10.15 is set to logical 1 to indicate that a configuration fault has been detected.
Auto-Negotiation restarts automatically. This happens when both stations are set to manual Master
mode or manual Slave mode, or after seven attempts to configure the Master-Slave relationship
through the seed method has failed.
6.6.3. Auto-Negotiation PAUSE/ASYMMETRIC PAUSE Resolution
Auto-negotiation is also used to determine the flow control capability between link partners. Flow control
is a mechanism that can force a busy transmitting link partner to stop transmitting in a full duplex
environment by sending special MAC control frames. In IEEE 802.3u, a PAUSE control frame had already
been defined. However, in IEEE 802.3ab, a new ASY-PAUSE control frame was defined; if the MAC can
only generate PAUSE frames but is not able to respond to PAUSE frames generated by the link partner,
then it is called Asymmetric PAUSE.
PAUSE/ASYMMETRIC PAUSE capability can be configured by setting the ANAR bits 10 and 11 (Table
25, page 26). Link partner PAUSE capabilities can be determined from ANLPAR bits 10 and 11 (Table 26,
page 27). A PHY layer device such as the RTL8211C(L) is not directly involved in PAUSE resolution, but
simply advertises and reports PAUSE capabilities during the Auto-Negotiation process. The MAC is
responsible for final PAUSE/ASYMMETRIC PAUSE resolution after a link is established, and is
responsible for correct flow control actions thereafter.
Integrated 10/100/1000 Gigabit Ethernet Transceiver
17
Track ID: JATR-1076-21 Rev. 1.3
RTL8211C & RTL8211CL
Datasheet
6.7. Crossover Detection and Auto-Correction
Ethernet needs a crossover mechanism between both link partners to cross the transmit signal to the
receiver when the medium is twisted-pair cable (e.g., CAT.3 or CAT.5 UTP). Crossover Detection &
Auto-Correction Configuration eliminates the need for crossover cables between devices, such as two PC’s
connected to each other with a CAT.3 or CAT.5 Ethernet cable. The basic concept is to assume the initial
default setting is MDI mode, and then check the link status. If no link is established after a certain time,
change to MDI Crossover mode and repeat the process until a link is established. An 11-bit pseudo-random
timer is applied to decide the mode change time interval.
Crossover Detection & Auto-Correction is not a part of the Auto-Negotiation process, but it utilizes the
process to exchange the MDI/MDI Crossover configuration. If the RTL8211C(L) is configured to only
operate in 100Base-TX or only in 10Base-T mode, then Auto-Negotiation is disabled only if the Crossover
Detection & Auto-Correction function is also disabled. If Crossover Detection & Auto-Correction are
enabled, then Auto-Negotiation is enabled and the RTL8211C(L) advertises only 100Base-TX mode or
10Base-T mode. If the speed of operation is configured manually and Auto-Negotiation is still enabled
because the Crossover Detection & Auto-Correction function is enabled, then the duplex advertised is as
follows:
1. If CONFIG is set to half duplex, then only half duplex is advertised.
2. If CONFIG is set to full duplex, then both full and half duplex are advertised.
If the user wishes to advertise only full duplex at a particular speed with the Crossover Detection &
Auto-Correction function enabled, then Auto-Negotiation should be enabled (register 0.12) with the
appropriate advertising capabilities set in registers 4 or 9. The Crossover Detection & Auto-Correction
function may be enabled/disabled by setting (register 16.6) manually.
After initial configuration following a hardware reset, Auto-Negotiation can be enabled and disabled via
register 0.12, speed via registers 0.13, 0.6, and duplex via register 0.8. The abilities that are advertised can
be changed via registers 4 and 9. Changes to registers 0.12, 0.13, 0.6, and 0.8 do not take effect unless at
least one of the following events occurs:
• Software reset (register 0.15)
• Restart of Auto-Negotiation (register 0.9)
• Transition from power-down to power-up (register 0.11)
Registers 4 and 9 are internally latched once each time Auto-Negotiation enters the ABILITY DETECT
state in the arbitration state machine (IEEE 802.3). Hence a write into register 4 or 9 has no effect once the
RTL8211C(L) begins to transmit Fast Link Pulses.
Integrated 10/100/1000 Gigabit Ethernet Transceiver
18
Track ID: JATR-1076-21 Rev. 1.3
RTL8211C & RTL8211CL
Datasheet
Register 7 is treated in a similar manner as 4 and 9 during additional Next Page exchanges. Once the
RTL8211C(L) completes Auto-Negotiation, it updates the various statuses in registers 1, 5, 6, and 10. The
speed, duplex, page received, and Auto-Negotiation completed statuses are also available in registers 17
and 19.
6.8. LED Configuration
The RTL8211C supports six LED pins, suitable for multiple types of applications that can directly drive the
LEDs. These pins are LED10, LED100, LED1000, LEDDUP, LEDRX, and LEDTX. The output of these
pins is determined by setting the corresponding bits in register 24. The functionality of the LEDs is shown
in Table 15.
Table 15. LED Configuration (RTL8211C)
Pin
Register 24
Control Bit
Register 24 Control Bit=0 (default)
Register 24 Control Bit=1
LED_LINK10
24.3
Low=10 Link Up
LED10, LED100:
High=10 Link Down
Low, Low=1000Mbps
High, Low=100Mbps
Low, High=10Mbps
LED_LINK100
24.3
Low=100 Link Up
High=100 Link Down
High, High=Link Down
Low=Link Up (Any speed)
High=Link Down (Any speed)
Low=Full Duplex
LED_LINK1000
LED_DUPLEX
24.3
24.2
Low=1000 Link Up
High=1000 Link Down
Low=Full Duplex
High=Half Duplex
Blink=Collision
High=Half Duplex
LED_RX
LED_TX
24.1
24.0
Low=Receiving
Low=Link Up
High=Not Receiving
High=Link Down
Blinking=Receiving
Low=Link Up
Low=Transmitting
High=Not Transmitting
High=Link Down
Blinking=Transmitting or Receiving
The RTL8211CL supports three LED pins, suitable for multiple types of applications that can directly drive
the LEDs. The output of these pins is determined by setting the corresponding bits in Page2 register 26. To
change the register page, see note 2 (below) and Table 18, page 20. The functionality of the RTL8211CL
LEDs is shown in Table 16.
Note 1: LED0, LED1, and LED2 are for RTL8211CL use. LED 1000, LED100, LED10, LEDTX, LEDRX,
and LED DUPLEX are for RTL8211C use.
Note 2: To switch to Page2, Register 26, set Register 31 Data=0002. After setting, switch to PHY`s Page0
(Register 31 Data=0000).
Integrated 10/100/1000 Gigabit Ethernet Transceiver
19
Track ID: JATR-1076-21 Rev. 1.3
RTL8211C & RTL8211CL
Datasheet
Table 16. LED Default Definitions (RTL8211CL)
Description
Pin
LED0
LED1
Blinking=Transmitting or Receiving
Low=Link Up (Any speed)
High=Link Down (Any speed)
Note: High/Low active depends on hardware config setting.
N/A
LED2
Note: Default Register: Page2 Reg.26=0078 (RTL8211CL only)
Table 17. LED Indication
Type Description
Pin No.
(64-pin)
Pin No. Pin Name
(48-pin)
43
48
44
50
39
40
34
-
LED_Duplex/LED0
O
O
O
O
O
O
LED Duplex (RTL8211C), LED0 (RTL8211CL)
LED100
LED 100
35
38
-
LED1000/LED1
LED10/LED2
LED_TX
LED 1000 (RTL8211C), LED1 (RTL8211CL)
LED10 (RTL8211C), LED2 (RTL8211CL)
LED TX
LED RX
-
LED_RX
The functionality of the RTL8211CL LED pins can be customized from Page2 register26 (see Table 18).
There are sixteen configuration types (see Table 19).
Table 18. LED Register Table (RTL8211CL)
LINK Speed
100Mbps
Active (Tx/Rx)
10Mbps
Reg26 Bit0
Reg26 Bit4
Reg26 Bit8
1000Mbps
Reg26 Bit2
Reg26 Bit6
Reg26 Bit10
LED0
LED1
LED2
Reg26 Bit1
Reg26 Bit5
Reg26 Bit9
Reg26 Bit3
Reg26 Bit7
Reg26 Bit11
Table 19. LED Configuration Table (RTL8211CL)
Pin
LINK Bit
Active (Tx/Rx) Bit
Description
10
0
0
0
0
0
0
0
0
1
1
100
0
1000
LED
0
0
1
1
0
0
1
1
0
0
0
1
0
1
0
1
0
1
0
1
N/A
Active
0
0
Link 1000
0
Link 1000+Active
Link 100
1
1
Link 100+Active
Link 100/1000
Link 100/1000+Active
Link 10
1
1
0
0
Link 10+Active
Integrated 10/100/1000 Gigabit Ethernet Transceiver
20
Track ID: JATR-1076-21 Rev. 1.3
RTL8211C & RTL8211CL
Datasheet
Pin
LINK Bit
Active (Tx/Rx) Bit
Description
10
1
100
0
1000
1
1
0
0
1
1
0
1
0
1
0
1
Link 10/1000
Link 10/1000+Active
Link 10/100
1
0
1
1
1
1
Link 10/100+Active
Link 10/100/1000
Link (10/10/1000)+Active
1
1
1
1
6.9. Polarity Correction
The RTL8211C(L) automatically corrects polarity errors on the receive pairs in 1000Base-T and 10Base-T
modes. In 100Base-TX mode polarity is irrelevant. In 1000Base-T mode, receive polarity errors are
automatically corrected based on the sequence of idle symbols. Once the descrambler is locked, the polarity
is also locked on all pairs. The polarity becomes unlocked only when the receiver loses lock. In 10Base-T
mode, polarity errors are corrected based on the detection of validly spaced link pulses. The detection
begins during the MDI crossover detection phase and locks when the 10Base-T link is up. The polarity
becomes unlocked when the link is down.
6.10. Power
The RTL8211C(L) implements a voltage regulator to generate operating power. The system vendor needs
to supply a 3.3V, 1A steady power source. The RTL8211C(L) converts the 3.3V steady power source to
1.05V via a switching regulator.
Another possible implementation is to use an external regulator to generate 1.0V. Be sure that the regulator
meets the required current rate.
The RTL8211C(L) implements an option for the RGMII power pins. The standard I/O voltage of the
RGMII interface is 3.3V, with support for 2.5V to lower EMI. The 2.5V power source for RGMII is from an
external regulator.
Integrated 10/100/1000 Gigabit Ethernet Transceiver
21
Track ID: JATR-1076-21 Rev. 1.3
RTL8211C & RTL8211CL
Datasheet
7. Register Descriptions
7.1. Register Mapping and Definitions
Table 20. Register Mapping and Definitions
Offset
Access
RW
RO
Name
Description
0
BMCR
BMSR
Basic Mode Control Register.
Basic Mode Status Register.
PHY Identifier Register 1.
PHY Identifier Register 2.
Auto-Negotiation Advertising Register.
Auto-Negotiation Link Partner Ability Register.
Auto-Negotiation Expansion Register.
Auto-Negotiation Next Page Transmit Register.
Auto-Negotiation Next Page Receive Register.
1000Base-T Control Register.
1000Base-T Status Register.
Reserved.
1
2
RO
PHYID1
PHYID2
ANAR
ANLPAR
ANER
3
RO
4
RW
RW
RW
RW
RW
RW
RO
5
6
7
ANNPTR
ANNPRR
GBCR
8
9
10
GBSR
11~14
15
RO
RSVD
RO
GBESR
PHYCR
PHYSR
INER
1000Base-T Extended Status Register.
PHY Specific Control Register.
PHY Specific Status Register.
Interrupt Enable Register.
Interrupt Status Register.
16
RW
RO
17
18
RW
RO
19
INSR
21
RO
RXERC
LEDCR
RSVD
Receive Error Counter.
24
RW
RO
LED Control Register.
25
Reserved.
27~30
31
RO
RSVD
Reserved.
RW
RW
PAGSEL
LEDCR
Page Select Register.
26/Page2
LED Control Register.
Note: To switch to Page2, Register 26, set Register 31 Data=0002. After setting, switch to the PHY`s Page0 (Register 31
Data=0000).
Integrated 10/100/1000 Gigabit Ethernet Transceiver
22
Track ID: JATR-1076-21 Rev. 1.3
RTL8211C & RTL8211CL
Datasheet
7.2. Register Table
7.2.1. BMCR (Basic Mode Control Register, Address 0x00)
Table 21. BMCR (Basic Mode Control Register, Address 0x00)
Bit
Name
RW
RW, SC1
Default Description
0.15
Reset
0
Reset.
1: PHY reset
0: Normal operation
Loopback Mode for 10M &100M.
1: Enable loopback mode
0: Disable loopback mode
0.14
0.13
Loopback
Speed[0]
RW
RW
0
The loopback function enables RGMII transmit data to be routed to the
RGMII receive data path.
0
Speed Select bit 0.
In forced mode, i.e. when Auto-Negotiation is disabled, bits 6 and 13
determine device speed selection.
Speed[1]
Speed[0]
Speed Enabled
Reserved
1
1
0
0
1
0
1
0
1000Mbps
100Mbps
10Mbps
0.12
0.11
0.10
ANE
RW
RW
RW
1
0
0
Auto-Negotiation Enable.
1: Enable Auto-Negotiation
0: Disable Auto-Negotiation
Power Down.
PWD
Isolate
1: Power down (only Management Interface and logic active, link is down)
0: Normal operation
Isolate.
1: RGMII interface is isolated; the serial management interface (MDC,
MDIO) is still active. When this bit is asserted, the RTL8211C(L) ignores
TXD[3:0], and TXCLT inputs, and presents a high impedance on TXC,
RXC, RXCLT, RXD[3:0].
0: Normal operation
0.9
0.8
Restart_AN
Duplex
RW, SC
RW
0
1
Restart Auto-Negotiation.
1: Restart Auto-Negotiation
0: Normal operation
Duplex Mode.
1: Full Duplex operation
0: Half Duplex operation
This bit is valid only in force mode, i.e., NWay is disabled.
Integrated 10/100/1000 Gigabit Ethernet Transceiver
23
Track ID: JATR-1076-21 Rev. 1.3
RTL8211C & RTL8211CL
Datasheet
Bit
Name
RW
Default Description
0.7
Collision test
RW
0
Collision Test.
1: Collision test enabled
0: Normal operation
When set, this bit will cause the COL signal to be asserted in response to
the assertion of TXEN within 512-bit times. The COL signal will be
de-asserted within 4-bit times in response to the de-assertion of TXEN.
0.6
Speed[1]
RSVD
RW
RO
1
Speed Select bit 1.
Refer to bit 0.13.
0.5:0
000000 Reserved.
Note 1: SC: Self-cleared
Note 2: The power-on duplex, speed, and ANE values take on the values set by external pins AN[3:0] on hardware reset
only. A write to these registers has no effect unless any one of the following also occurs: Software reset (0.15) is asserted,
Restart_AN (0.9) is asserted, or PWD (0.11) transitions from power down to normal operation.
Note 3: When the RTL8211C(L) is switched from power down to normal operation, software reset and restart
auto-negotiation are performed even if bits Reset (0.15) and Restart_AN (0.9) are not set by the user.
Note 4: Auto-Negotiation is enabled when speed is set to 1000Base-T. Crossover Detection & Auto-Correction takes
precedence over Auto-Negotiation disable (0.12=0). If ANE is disabled, speed and duplex capabilities are advertised by
0.13, 0.6, and 0.8. Otherwise, register 4.8:5 and 9.9:8 take effect.
Note 5: Auto-Negotiation automatically restarts after hardware or software reset regardless of whether or not the restart bit
(0.9) is set.
7.2.2. BMSR (Basic Mode Status Register, Address 0x01)
Table 22. BMSR (Basic Mode Status Register, Address 0x01)
Bit
Name
RW
Default Description
1.15
100Base-T4
RO
0
1
100Base-T4 Capability.
The RTL8211C(L) does not support 100Base-T4 mode. This bit
should always be 0.
1.14
1.13
1.12
1.11
1.10
100Base-TX (full)
100Base-TX (half)
10Base-T (full)
RO
RO
RO
RO
RO
100Base-TX Full Duplex Capability.
1: Device is able to perform 100Base-TX in full duplex mode
0: Device is not able to perform 100Base-TX in full duplex mode
100Base-TX Half Duplex Capability.
1
1
1
0
1: Device is able to perform 100Base-TX in half duplex mode
0: Device is not able to perform 100Base-TX in half duplex mode
10Base-T Full Duplex Capability.
1: Device is able to perform 10Base-T in full duplex mode.
0: Device is not able to perform 10Base-T in full duplex mode.
10Base-T Half Duplex Capability.
10Base-T (half)
100Base-T2 (full)
1: Device is able to perform 10Base-T in half duplex mode
0: Device is not able to perform 10Base-T in half duplex mode
100Base-T2 Full Duplex Capability.
The RTL8211C(L) does not support 100Base-T2 mode and this bit
should always be 0.
Integrated 10/100/1000 Gigabit Ethernet Transceiver
24
Track ID: JATR-1076-21 Rev. 1.3
RTL8211C & RTL8211CL
Datasheet
Bit
Name
RW
Default Description
1.9
100Base-T2 (half)
RO
0
100Base-T2 Half Duplex Capability.
The RTL8211C(L) does not support 100Base-T2 mode. This bit
should always be 0.
1.8
1000Base-T Extended
status
RO
1
1000Base-T Extended Status Register.
1: Device supports Extended Status Register 0x0F (15)
0: Device does not support Extended Status Register 0x0F
This register is read-only and is always set to 1.
Reserved.
1.7
1.6
RSVD
RO
RO
0
1
Preamble Suppression
Preamble Suppression Capability (Permanently On).
The RTL8211C(L) always accepts transactions with preamble
suppressed.
1.5
1.4
Auto-Negotiation
Complete
RO
0
0
Auto-Negotiation Complete.
1: Auto-Negotiation process complete, and contents of registers
5, 6, 8, and 10 are valid
0: Auto-Negotiation process not complete
Remote Fault.
Remote Fault
RC*
1: Remote fault condition detected (cleared on read or by reset).
Indication or notification of remote fault from Link Partner
0: No remote fault condition detected
Auto Configured Link.
1.3
1.2
Auto-Negotiation
Ability
RO
RO
1
0
1: Device is able to perform Auto-Negotiation
0: Device is not able to perform Auto-Negotiation
Link Status.
Link Status
1: Linked
0: Not Linked
This register indicates whether the link was lost since the last read.
For the current link status, either read this register twice or read
register bit 17.10 Link Real Time.
1.1
1.0
Jabber Detect
RC
RO
0
1
Jabber Detect.
1: Jabber condition detected
0: No Jabber occurred
Extended Capability
1: Extended register capabilities, always 1
Note: RC: Read-cleared after read.
7.2.3. PHYID1 (PHY Identifier Register 1, Address 0x02)
Table 23. PHYID1 (PHY Identifier Register 1, Address 0x02)
Bit
Name
RW
Default
Description
2.15:0 OUI_MSB
RO
0000000000011100
Organizationally Unique Identifier Bit 3:18.
Always 0000000000011100.
Note: Realtek OUI is 0x000732.
Integrated 10/100/1000 Gigabit Ethernet Transceiver
25
Track ID: JATR-1076-21 Rev. 1.3
RTL8211C & RTL8211CL
Datasheet
7.2.4. PHYID2 (PHY Identifier Register 2, Address 0x03)
Table 24. PHYID2 (PHY Identifier Register 2, Address 0x03)
Bit
Name
RW
Default
Description
3.15:10 OUI_LSB
RO
110010
Organizationally Unique Identifier Bit 19:24.
Always 110010.
3.9:4
3.3:0
Model Number
Revision Number
RO
RO
010001
0010
Always 010001.
Revision Number
7.2.5. ANAR (Auto-Negotiation Advertising Register, Address 0x04)
Table 25. ANAR (Auto-Negotiation Advertising Register, Address 0x04)
Bit
Name
RW
Default
Description
4.15
NextPage
RW
0
1: Additional next pages exchange desired
0: No additional next pages exchange desired
Reserved.
4.14
4.13
RSVD
RO
0
0
Remote fault
RW
1: Set Remote Fault bit
0: No remote fault detected
4.12
4.11
RSVD
RO
0
0
Reserved.
Asymmetric
PAUSE
RW
1: Advertise support of asymmetric pause
0: No support of asymmetric pause
1: Advertise support of pause frames
0: No support of pause frames
1: 100Base-T4 support
4.10
4.9
PAUSE
RW
RO
RW
RW
RW
RW
RO
0
100Base-T4
1
0: 100Base-T4 not supported
1: Advertise support of 100Base-TX full-duplex mode
0: Not advertised
4.8
100Base-TX(full)
100Base-TX(half)
10Base-T(full)
10Base-T(half)
Selector field
1
4.7
1
1: Advertise support of 100Base-TX half-duplex mode
0: Not advertised
4.6
1
1
1: Advertise support of 10Base-TX full-duplex mode
0: Not advertised
4.5
1: Advertise support of 10Base-TX full-duplex mode
0: Not advertised
4.4:0
00001
Indicates the RTL8211C(L) supports IEEE 802.3
Note 1: The setting of Register 4 has no effect unless NWay is restarted or the link goes down.
Note 2: If 1000Base-T is advertised, then the required next pages are automatically transmitted. Register 4.15 should be set
to 0 if no additional next pages are needed.
Integrated 10/100/1000 Gigabit Ethernet Transceiver
26
Track ID: JATR-1076-21 Rev. 1.3
RTL8211C & RTL8211CL
Datasheet
7.2.6. ANLPAR (Auto-Negotiation Link Partner Ability Register,
Address 0x05)
Table 26. ANLPAR (Auto-Negotiation Link Partner Ability Register, Address 0x05)
Bit
Name
RW
Default Description
5.15
Next Page
RO
0
0
0
Next Page Indication.
Received Code Word Bit 15.
Acknowledge.
5.14
5.13
ACK
RO
RO
Received Code Word Bit 14.
Remote Fault indicated by Link Partner.
Received Code Word Bit 13.
Remote Fault
5.12:5 Technology Ability Field
5.4:0 Selector Field
RO
RO
00000000 Received Code Word Bit 12:5.
00000 Received Code Word Bit 4:0.
Note: Register 5 is not valid until the Auto-Negotiation complete bit 1.5 indicates completed.
7.2.7. ANER (Auto-Negotiation Expansion Register, Address 0x06)
Table 27. ANER (Auto-Negotiation Expansion Register, Address 0x06)
Bit
Name
RW Default Description
RO 0x000 Reserved.
Parallel Detection Fault RC
6.15:5 RSVD
6.4
6.3
6.2
6.1
6.0
0
0
1
0
0
1: A fault has been detected via the Parallel Detection function
0: A fault has not been detected via the Parallel Detection function
1: Link Partner supports Next Page exchange
0: Link Partner does not support Next Page exchange
1: Local Device is able to send Next Page
Always 1.
Link Partner Next
Pageable
RO
RO
RC
RO
Local Next Pageable
Page Received
1: A New Page (new LCW) has been received
0: A New Page has not been received
Link Partner
Auto-Negotiation
capable
1: Link Partner supports Auto-Negotiation
0: Link Partner does not support Auto-Negotiation
Note: Register 6 is not valid until the Auto-Negotiation complete bit 1.5 indicates completed.
Integrated 10/100/1000 Gigabit Ethernet Transceiver
27
Track ID: JATR-1076-21 Rev. 1.3
RTL8211C & RTL8211CL
Datasheet
7.2.8. ANNPTR (Auto-Negotiation Next Page Transmit Register,
Address 0x07)
Table 28. ANNPTR (Auto-Negotiation Next Page Transmit Register, Address 0x07)
Bit
Name
RW
Default
Description
7.15
Next Page
RW
0
Next Page Indication.
0: No more next pages to send
1: More next pages to send
Transmit Code Word Bit 15.
Transmit Code Word Bit 14.
Message Page.
7.14
7.13
RSVD
RO
0
1
Message Page
RW
0: Unformatted Page
1: Message Page
Transmit Code Word Bit 13.
Acknowledge2.
7.12
Acknowledge 2
RW
0
0: Local device has no ability to comply with the message received
1: Local device has the ability to comply with the message received
Transmit Code Word Bit 12.
Toggle bit.
7.11
Toggle
RO
0
Transmit Code Word Bit 11.
Content of Message/Unformatted Page.
Transmit Code Word Bit 10:0.
7.10:0 Message/
Unformatted Field
RW
0x001
7.2.9. ANNPRR (Auto-Negotiation Next Page Receive Register,
Address 0x08)
Table 29. ANNPRR (Auto-Negotiation Next Page Receive Register, Address 0x08)
Bit
8.15
8.14
8.13
8.12
8.11
Name
RW
RO
RO
RO
RO
RO
RO
Default Description
Next Page
Acknowledge
Message Page
Acknowledge 2
Toggle
0
Received Link Code Word Bit 15.
0
0
Received Link Code Word Bit 14.
Received Link Code Word Bit 13.
Received Link Code Word Bit 12.
Received Link Code Word Bit 11.
Received Link Code Word Bit 10:0.
0
0
8.10:0 Message/ Unformatted Field
0x00
Note: Register 8 is not valid until the Auto-Negotiation complete bit 1.5 indicates completed.
Integrated 10/100/1000 Gigabit Ethernet Transceiver
28
Track ID: JATR-1076-21 Rev. 1.3
RTL8211C & RTL8211CL
Datasheet
7.3. GBCR (1000Base-T Control Register, Address 0x09)
Table 30. GBCR (1000Base-T Control Register, Address 0x09)
Bit
Name
RW
Default Description
Test Mode Select.
9.15:13 Test Mode
RW
0
000: Normal Mode
001: Test Mode 1 - Transmit Jitter Test
010: Test Mode 2 - Transmit Jitter Test (MASTER mode)
011: Test Mode 3 - Transmit Jitter Test (SLAVE mode)
100: Test Mode 4 - Transmit Distortion Test
101, 110, 111: Reserved
9.12
9.11
9.10
9.9
MASTER/SLAVE Manual
Configuration Enable
RW
RW
RW
RW
RW
RO
AN[3:0] Enable Manual Master/Slave Configuration.
1: Manual MASTER/SLAVE configuration
0: Automatic MASTER/SLAVE
MASTER/SLAVE
Configuration Value
AN[3:0] Advertise Master/Slave Configuration Value.
1: Manual configure as MASTER
0: Manual configure as SLAVE
Port Type
AN[3:0] Advertise Device Type Preference.
1: Prefer multi-port device (MASTER)
0: Prefer single port device (SLAVE)
AN[3:0] Advertise 1000Base-T Full-Duplex Capability.
1: Advertise
1000Base-T Full Duplex
1000Base-T Half Duplex
RSVD
0: Do not advertise
9.8
AN[3:0] Advertise 1000Base-T Half-Duplex Capability.
1: Advertise
0: Do not advertise
9.7:0
0
Reserved.
Note 1: Values set in register 9.12:8 have no effect unless Auto-Negotiation is restarted (Reg0.9) or the link goes down.
Note 2: Bits 9.11 and 9.10 are ignored when bit 9.12=0.
Integrated 10/100/1000 Gigabit Ethernet Transceiver
29
Track ID: JATR-1076-21 Rev. 1.3
RTL8211C & RTL8211CL
Datasheet
7.3.1. GBSR (1000Base-T Status Register, Address 0x0A)
Table 31. GBSR (1000Base-T Status Register, Address 0x0A)
Bit
Name
RW
Default Description
10.15 MASTER/SLAVE
Configuration Fault
RO, RC
0
0
0
0
0
0
Master/Slave Manual Configuration Fault Detected.
1: MASTER/SLAVE configuration fault detected
0: No MASTER/SLAVE configuration fault detected
Master/Slave Configuration Result.
10.14 MASTER/SLAVE
Configuration Resolution
RO
RO
RO
RO
RO
1: Local PHY configuration resolved to MASTER
0: Local PHY configuration resolved to SLAVE
Local Receiver Status.
10.13 Local Receiver Status
10.12 Remote Receiver Status
1: Local Receiver OK
0: Local Receiver Not OK
Remote Receiver Status.
1: Remote Receiver OK
0: Remote Receiver Not OK
10.11 Link Partner 1000Base-T
Full Duplex Capability
Link Partner 1000Base-T Full Duplex Capability.
1: Link Partner is capable of 1000Base-T full duplex
0: Link Partner is not capable of 1000Base-T full duplex
Link Partner 1000Base-T Half Duplex Capability.
1: Link Partner is capable of 1000Base-T half duplex
0: Link Partner is not capable of 1000Base-T half duplex
Reserved.
10.10 Link Partner 1000Base-T
Half Duplex Capability
10.9:8 RSVD
RO
00
10.7:0 Idle Error Count
RO, RC
0x00
MSB of Idle Error Counter.
The counter stops automatically when it reaches 0xff.
Note 1: Values set in register 10.11:10 are not valid until register 6.1 is set to 1.
Note 2: Register 10 is not valid until the Auto-Negotiation complete bit 1.5 indicates completed.
7.3.2. GBESR (1000Base-T Extended Status Register, Address 0x0F)
Table 32. GBESR (1000Base-T Extended Status Register, Address 0x0F)
Bit
Name
RW
RO
RO
RO
RO
RO
Default
Description
15.15 1000Base-X FD
15.14 1000Base-X HD
15.13 1000Base-T FD
15.12 1000Base-T HD
15.11:0 RSVD
0
0: Not 1000Base-X full duplex capable
0: Not 1000Base-X half duplex capable
1: 1000Base-T full duplex capable
1: 1000Base-T half duplex capable
Reserved.
0
1
1
0x000
Integrated 10/100/1000 Gigabit Ethernet Transceiver
30
Track ID: JATR-1076-21 Rev. 1.3
RTL8211C & RTL8211CL
Datasheet
7.3.3. PHYCR (PHY Specific Control Register, Address 0x10)
Table 33. PHYCR (PHY Specific Control Register, Address 0x10)
Bit
Name
RW Default Description
16.15:12 RSVD
RW
RW
0000 Reserved.
16.11 Assert CRS on Transmit
0
1: Assert CRS on transmit
0: Never assert CRS on transmit
16.10 Force Link Good
16.9:7 RSVD
RW
RW
RW
0
1: Force link good
0: Normal operation
011
11
Reserved.
16.6:5 MDI Crossover Mode
01: Manual MDI configuration
00: Manual MDI Crossover configuration
Note: Before setting the register, address 0xE bit10 need set to 1.
After setting the register, a PHY reset is required.
16.4
Disable CLK125
RW
0
The CLK125 I/O pin (RTL8211C=pin 41, and RTL8211CL=pin
32) function is disabled by default. Please contact Realtek FAE
(nicfae@realtek.com) for enabling instructions. After enabling
I/O pin (pin41/pin32), functions are as shown below:
1: CLK125 remains at logic Low
0: CLK125 Toggling Enabled
16.3:1 RSVD
16.0 Disable Jabber
RW
RW
111
0
Reserved.
1: Disable jabber function
0: Enable jabber function
7.3.4. PHYSR (PHY Specific Status Register, Address 0x11)
Table 34. PHYSR (PHY Specific Status Register, Address 0x11)
Bit
Name
RW Default Description
17.15:14 Speed
RO
01
Link Speed.
11: Reserved
01: 100Mbps
10: 1000Mbps
00: 10Mbps
17.13 Duplex
RO
RC
RO
RO
0
0
0
0
Full/Half Duplex Mode.
1: Full duplex
New Page Received.
1: Page received
Speed and Duplex Mode Resolved.
1: Resolved
0: Half duplex
17.12 Page received
0: Page not received
0: Not resolved
0: Link not OK
17.11 Speed and duplex
resolved
17.10 Link (real time)
Real Time Link Status.
1: Link OK
17.9:7 RSVD
RO
RO
000
0
Reserved.
17.6
MDI crossover status
MDI/MDI Crossover Status.
1: MDI Crossover
0: Low active
0: MDI
1: High active
17.5
17.4
LED Control
LED Definition
RW
RW
0
1
0: N/A
1: Link and Speed Indication by combination of LEDs (Only for
RTL8211CL)
17.3
ALDPS
RW
1
0: Disable Advance link down power saving
1: Enable Advance link down power saving
Reserved.
17.2:1 RSVD
17.0 Jabber (real time)
RW
RO
10
0
Real Time Jabber Indication.
1: Jabber Indication
0: No jabber Indication
Integrated 10/100/1000 Gigabit Ethernet Transceiver
31
Track ID: JATR-1076-21 Rev. 1.3
RTL8211C & RTL8211CL
Datasheet
7.3.5. INER (Interrupt Enable Register, Address 0x12)
Table 35. INER (Interrupt Enable Register, Address 0x12)
Bit
Name
RW
RW
RW
RW
RW
RW
Default Description
18.15 Auto-Negotiation Error Interrupt
18.14 Speed Change Interrupt
0
0
0
0
0
1: Interrupt enable
0: Interrupt disable
0: Interrupt disable
0: Interrupt disable
0: Interrupt disable
0: Interrupt disable
1: Interrupt enable
1: Interrupt enable
1: Interrupt enable
1: Interrupt enable
18.13 Duplex Mode Change Interrupt
18.12 Page Received Interrupt
18.11 Auto-Negotiation Completed
Interrupt
18.10 Link Status Change Interrupt
RW
RW
RW
RW
RW
RW
RW
RW
0
0
0
0
0
0
0
0
1: Interrupt enable
1: Interrupt enable
1: Interrupt enable
Reserved.
0: Interrupt disable
0: Interrupt disable
0: Interrupt disable
18.9
18.8
18.7
18.6
Symbol Error Interrupt
False Carrier Interrupt
RSVD
MDI Crossover Change Interrupt
1: Interrupt enable
Reserved.
0: Interrupt disable
18.5:2 RSVD
18.1
18.0
Polarity Change Interrupt
Jabber Interrupt
1: Interrupt enable
1: Interrupt enable
0: Interrupt disable
0: Interrupt disable
7.3.6. INSR (Interrupt Status Register, Address 0x13)
Table 36. INSR (Interrupt Status Register, Address 0x13)
Bit
Name
RW Default Description
19.15 Auto-Negotiation Error
19.14 Speed Change
RC
RC
RC
RC
0
0
0
0
1: Auto-Negotiation Error
1: Link speed changed
0: No Auto-Negotiation Error
0: Link speed not changed
0: Duplex mode not changed
19.13 Duplex Mode Change
19.12 Page Received
1: Duplex mode changed
1: Page (a new LCW) received
0: Page not received
19.11 Auto-Negotiation Completed
19.10 Link Status Change
RC
0
1: Auto-Negotiation completed
0: Auto-Negotiation not completed
RC
RC
RC
RC
RC
0
0
0
0
0
1: Link status changed
1: Symbol error detected
1: False carrier
0: Link status not changed
19.9
19.8
19.7
19.6
Symbol Error
False Carrier
0: No symbol error detected
0: No false carrier detected
RSVD
Reserved.
MDI Crossover Change
1: Crossover status changed
0: Crossover status not changed
19.5:2 RSVD
RC
RC
0000 Reserved.
19.1
Polarity Change
0
1: Polarity Changed
0: Polarity not changed
Note: This bit is valid only when 1000Base-T is enabled.
19.0
Jabber
RC
0
1: Jabber detected
0: No jabber detected
Integrated 10/100/1000 Gigabit Ethernet Transceiver
32
Track ID: JATR-1076-21 Rev. 1.3
RTL8211C & RTL8211CL
Datasheet
7.3.7. RXERC (Receive Error Counter, Address 0x15)
Table 37. RXERC (Receive Error Counter, Address 0x15)
Bit
Name
RW
Default
Description
21.15:0 Receive Error Count
RC
0x0000
Receive Error Count.
Note: The RXERC register is read-cleared after a read.
7.3.8. LEDCR (LED Control Register, Address 0x18)
Table 38. LEDCR (LED Control Register, Address 0x18)
Bit
Name
RW
Default
Description
24.15 Disable LED
RW
0
0: Enable
1: Disable
24.14:12 LED Pulse Stretch
Duration
RW
010
000: No pulse stretching
010: 42ms to 84ms
100: 170ms to 340ms
110: 670ms to 1.3s
Reserved.
001: 21ms to 42ms
011: 84ms to 170ms
101: 340ms to 670ms
111: 1.3s to 2.7s
24.11 RSVD
24.10:8 RSVD
24.7:4 RSVD
RW
RW
RW
RW
0
111
0100
0
Reserved.
Reserved.
24.3
LEDLINK Control
1: Link and Speed Indication by combination of LEDs
0: Link and Speed Indication by specific LED
Refer to section 6.8 LED Configuration (only for RTL8211C).
1: Full Duplex Indication
24.2
24.1
24.0
LEDDUP Control
LEDRX Control
LEDTX Control
RW
RW
RW
0
0
0
0: Full Duplex/Collision Indication
1: Rx Activity/Link Indication
0: Rx Activity Indication only
1: Tx or Rx Activity/Link Indication
0: Tx Activity Indication only
7.3.9. PAGSEL (Page Select Register, Address 0x1F)
Table 39. PAGSEL (Page Select Register, Address 0x1F)
Bit
Name
RW
RW
RW
Default
0
Description
31.15:3 RSVD
31.2:0 Pagesel
Reserved.
000
Page Select Signal.
000: Page 0 (default page)
010: Page 2
001: Page 1
011: Page 3
100: Page 4
Integrated 10/100/1000 Gigabit Ethernet Transceiver
33
Track ID: JATR-1076-21 Rev. 1.3
RTL8211C & RTL8211CL
Datasheet
8. Switching Regulator
The RTL8211C(L)-GR incorporates a state-of-the-art switching regulator that requires a well-designed
PCB layout in order to achieve good power efficiency and lower the output voltage ripple and input
overshoot.
8.1. PCB Layout
• The input 3.3V power trace connected to VDDREG should be wider than 40mils.
• The bulk de-coupling capacitors (C82 and C83) should be placed within 200mils (0.5cm) of VDDREG
to prevent input voltage overshoot.
• The output power trace out of REG_OUT should be wider than 60mils.
• Keep L1 (4.7µH) within 200mils (0.5cm) of REG_OUT.
• Keep C18 and C19 within 200mils (0.5cm) of L1 to ensure stable output power and better power
efficiency.
• Both C18 and C82 are strongly recommended to be ceramic capacitors.
Note: Violation of the above rules will damage the IC.
Figure 6. Switching Regulator Application
Note: RTL8211C Pin1=REG_OUT/Pin63=VDDREG
RTL8211CL Pin48=REG_OUT/Pin44 and Pin45=VDDREG (Two pins for VDDRGE)
Integrated 10/100/1000 Gigabit Ethernet Transceiver
34
Track ID: JATR-1076-21 Rev. 1.3
RTL8211C & RTL8211CL
Datasheet
8.2. Inductor and Capacitor Parts List
Table 40. Inductor and Capacitor Parts List
Inductor Type
4R7GTSD32
6R8GTSD32
6R8GTSD53
Inductance
5.1µH
Q at 500KHz
57.15
ESR at 500KHz (MΩ)
Max I (mA) Output Ripple (mV)
281
313
375
1100
900
12.6
12
6.7µH
67.35
7.1µH
59.7
1510
10.4
Note 1: The ESR is equivalent to RDC or DCR. Lower ESR inductor values will promote a higher efficiency switching
regulator.
Note 2: The power inductor used by the switching regulator should be able to withstand 600mA of current.
Note 3: Typically, if the power inductor’s ESR at 1MHz is below 0.8Ω, the switching regulator efficiency will be above
75%. However the actual switching regulator efficiency must be measured according to the method described in section 8.5
Efficiency Measurement, page 41.
Capacitor Type
22µF 1210 TDK
22µF 1210 X5R
Capacitance
21.5µF
ESR at 500KHz (MΩ)
Output Ripple (mV) Load Transient (mV)
24.25
24.90
9.6
81.0
73.0
22.15µF
10.4
Note: Capacitors (C18 and C82) are suggested to be ceramic due to their low ESR value. Lower ESR values will yield lower
output voltage ripple.
Integrated 10/100/1000 Gigabit Ethernet Transceiver
35
Track ID: JATR-1076-21 Rev. 1.3
RTL8211C & RTL8211CL
Datasheet
8.3. Measurement Criteria
In order for the switching regulator to operate properly, the input and output voltage measurement criteria
must be met. From the input side, the voltage overshoot cannot exceed 4V; otherwise the chip may be
damaged. Note that the voltage signal must be measured directly at VDDREG, not at the capacitor. In order
to reduce the input voltage overshoot, the C82 and C83 must be placed close to VDDREG. The following
figures show what a good input voltage and a bad one look like.
Figure 7. Input Voltage Overshoot <4V (Good)
Figure 8. Input Voltage Overshoot >4V (Bad)
Integrated 10/100/1000 Gigabit Ethernet Transceiver 36 Track ID: JATR-1076-21 Rev. 1.3
RTL8211C & RTL8211CL
Datasheet
From the output side measured at REG_OUT, the voltage ripple must be within 100mV. Choosing different
types and values of output capacitor (C18, C19) and power inductor (L1) will seriously affect the efficiency
and output voltage ripple of switching regulators. The following figures show the effects of different types
of capacitors on the switching regulator’s output voltage.
The blue square wave signal (top row) is measured at the output of REG_OUT before the power inductor
(L1). The yellow signal (second row) is measured after the power inductor (L1), and shows there is a
voltage ripple. The green signal (lower row) is the current. Data in the following figures was measured at
gigabit speed.
Figure 9. Ceramic 22µF 1210(X5R) (Good)
Figure 10. Ceramic 22µF 0805(Y5V) (Bad)
Integrated 10/100/1000 Gigabit Ethernet Transceiver 37
Track ID: JATR-1076-21 Rev. 1.3
RTL8211C & RTL8211CL
Datasheet
A ceramic 22µF (X5R) will have a lower voltage ripple compared to the electrolytic 100µF. The key to
choosing a proper output capacitor is to choose the lowest ESR to reduce the output voltage ripple.
Choosing a ceramic 22µF 0805 (Y5V) in this case will cause malfunction of the switching regulator.
Placing several Electrolytic capacitors in parallel will help lower the output voltage ripple.
Figure 11. Electrolytic 100µF (Ripple Too High)
Integrated 10/100/1000 Gigabit Ethernet Transceiver
38
Track ID: JATR-1076-21 Rev. 1.3
RTL8211C & RTL8211CL
Datasheet
The following figures show how different inductors affect the REG_OUT output waveform. The typical
waveform should look like Figure 12, which has a square waveform with a dip at the falling edge and the
rising edge. If the inductor is not carefully chosen, the waveform may look like Figure 13, where the
waveform looks like a distorted square. This will cause insufficient current supply and will undermine the
stability of the system at gigabit speed. Data in the following figures was measured at gigabit speed.
Figure 12. 4R7GTSD32 (Good)
Figure 13. 1µH Bead (Bad)
Integrated 10/100/1000 Gigabit Ethernet Transceiver 39
Track ID: JATR-1076-21 Rev. 1.3
RTL8211C & RTL8211CL
Datasheet
8.4. Typical Switching Regulator PCB Layout
The typical layout of Figure 14 and Figure 15 are similar. The trace from RSET should pass through a via to
the lower layer, and the trace should be protected by a ground trace. The width of the ground trace should be
more than 5 mils.
Figure 14. 64-Pin Typical Switching Regulator PCB Layout (Top Layer)
Figure 15. 64-Pin Typical Switching Regulator PCB Layout (Bottom Layer)
Integrated 10/100/1000 Gigabit Ethernet Transceiver 40 Track ID: JATR-1076-21 Rev. 1.3
RTL8211C & RTL8211CL
Datasheet
8.5. Efficiency Measurement
The efficiency of the switching regulator is designed to be above 75% in gigabit traffic mode. It is very
important to choose a suitable inductor before Gerber certification, as the Inductor ESR value will affect the
efficiency of the switching regulator. An inductor with a lower ESR value will result in a higher efficiency
switching regulator.
The efficiency of the switching regulator is easily measured using the following method.
Figure 16 shows two checkpoints, checkpoint A (CP_A) and checkpoint B (CP_B). The switching
regulator input current (Icpa) should be measured at CP_A, and the switching regulator output current (Icpb)
should be measured at CP_B.
To determine efficiency, apply the following formula:
Efficiency = Vcpb*Icpb / Vcpa*Icpa
Where Vcpb is 1.05V; Vcpa is 3.3V. The measurements should be performed in gigabit traffic mode.
For example: The inductor used in the evaluation board is a GOTREND GTSD32-4R7M:
• The ESR value @ 1MHz is approximately 0.712ohm
• The measured Icpa is 160mA at CP_A
• The measured Icpb is 400mA at CP_B
These values are measured in gigabit traffic mode, so the efficiency of the GOTREND GTSD32-4R7M can
be calculated as follows:
Efficiency = (1.05V*400mA) / (3.3V*160mA) = 0.80 = 80%.
We strongly recommend that when choosing an inductor for the switching regulator, the efficiency should
be measured, and that the inductor should yield an efficiency rating higher than 75%. If the efficiency does
not meet this requirement, there may be risk to the switching regulator reliability in the long run.
CP_A
CP_B
Figure 16. Switching Regulator Efficiency Measurement Checkpoint
Integrated 10/100/1000 Gigabit Ethernet Transceiver
41
Track ID: JATR-1076-21 Rev. 1.3
RTL8211C & RTL8211CL
Datasheet
8.6. Power Sequence
Figure 17. Power Sequence
Table 41. Power Sequence parameter
Symbol
Rt1
Description
Min
Typical
Max
100
100
Units
ms
3.3V Rise Time
1
-
-
Rt1
2.5V RGMII Rise Time
-
ms
Note: The RTL8211C(L) does not support fast 3.3V rising. The 3.3V rise time must be controlled over 1ms. If the rise time is
too short, it will induce a peak voltage in VDDREG which may cause permanent damage to the switching regulator.
9. Application Diagram
Switching
Regulator
Power 3.3V, 1.05V
Main/Aux. Power
25 MHz
Clock
1.05V
LED
Power 3.3V,
Power
LED
RGMII
MAC
RTL8211C(L)
125 MHz Clock
MDC
MDIO
Figure 18. Application Diagram
Integrated 10/100/1000 Gigabit Ethernet Transceiver
42
Track ID: JATR-1076-21 Rev. 1.3
RTL8211C & RTL8211CL
Datasheet
10. Characteristics
10.1. Absolute Maximum Ratings
Table 42. Absolute Maximum Ratings
Minimum
Symbol
Description
Maximum
Unit
V
VDD33, AVDD33
AVDD10, DVDD10
Supply Voltage 3.3V
Supply Voltage 1.05V
-0.4
-0.1
-0.2
-0.5
-0.3
-55
+0.4
+0.1
V
VDD25 (RGMII 2.5V) Supply Voltage 2.5V
+0.3
V
DCinput
DCoutput
NA
Input Voltage
Corresponding Supply Voltage + 0.5
Corresponding Supply Voltage + 0.5
+125
V
Output Voltage
Storage Temperature
V
°C
Note:Refer to the most updated schematic circuit for correct configuration.
WARNING: Absolute maximum ratings are limits beyond which permanent damage may be caused to the
device, or device reliability will be affected. All voltages are specified reference to GND unless otherwise
specified.
10.2. Recommended Operating Conditions
Table 43. Recommended Operating Conditions
Description
Pins
Minimum
Typical
Maximum
3.63
Unit
V
Supply Voltage VDD
DVDD33, AVDD33
2.97
0.95
2.37
0
3.3
1.05
2.5
-
AVDD10, DVDD10
1.09
V
2.5V RGMII
2.62
V
Ambient Operating Temperature TA
Maximum Junction Temperature
-
-
70
°C
°C
-
-
125
10.3. Crystal Requirements
Table 44. Crystal Requirements
Minimum Typical
Symbol
Description/Condition
Maximum
Unit
Fref
Parallel resonant crystal reference frequency,
fundamental mode, AT-cut type.
-
25
-
MHz
Fref Stability
Parallel resonant crystal frequency stability,
fundamental mode, AT-cut type. Ta=0°C~70°C.
Parallel resonant crystal frequency tolerance,
-30
-50
-
+30
+50
ppm
ppm
Fref Tolerance
-
fundamental mode, AT-cut type. Ta=25°C.
Fref Duty Cycle Reference clock input duty cycle.
40
-
-
-
-
60
30
%
Ω
ESR
DL
Equivalent Series Resistance.
Drive Level.
-
0.5
mW
Integrated 10/100/1000 Gigabit Ethernet Transceiver
43
Track ID: JATR-1076-21 Rev. 1.3
RTL8211C & RTL8211CL
Datasheet
10.4. DC Characteristics
Table 45. DC Characteristics
Symbol
Parameter
Conditions
Minimum
Typical
3.3
Maximum
3.63
Units
V
VDD33,
AVDD33
3.3V Supply Voltage
-
-
-
2.97
RGMII I/O 2.5V RGMII Supply Voltage
2.37
2.5
2.62
V
DVDD10,
1.05V Supply Voltage
AVDD10
0.95
1.05
1.09
V
Voh (3.3V) Minimum High Level Output Voltage
Voh (2.5V) Minimum High Level Output Voltage
-
-
-
-
-
-
0.9*VDD33
-
-
-
-
-
-
VDD33
VDD25
0.1*VDD33
0.1*VDD25
-
V
V
V
V
V
V
0.9*VDD25
Vol (3.3V)
Vol (2.5V)
Vih
Maximum Low Level Output Voltage
Maximum Low Level Output Voltage
Minimum High Level Input Voltage
Maximum Low Level Input Voltage
0
0
1.8
-
Vil
0.9
Vin=VDD33
or GND
Iin
Input Current
0
-
0.5
µA
10.5. AC Characteristics
10.5.1. MDC/MDIO Timing
MDC/MDIO Timing – Management Port
tMCC
tMCH
Vih(min)
Vil(max)
MDC
tMCL
tMSU
tMRV
tMHT
Vih(min)
Vil(max)
MDIO
Figure 19. MDC/MDIO Management Timing Parameters
Integrated 10/100/1000 Gigabit Ethernet Transceiver
44
Track ID: JATR-1076-21 Rev. 1.3
RTL8211C & RTL8211CL
Datasheet
Table 46. MDC/MDIO Management Timing Parameters
Symbol
tMCC
tMCH
tMCL
tMSU
tMHT
tMRV
Description
Min
80
30
30
10
10
-
Max
Units
ns
MDC Cycle Time
MDC High Time
-
-
ns
MDC Low Time
-
ns
MDIO Setup Time
MDIO Hold Time
MDC Clock Rise to MDIO Valid
-
ns
-
ns
40
ns
10.5.2. RGMII Timing Modes
TXC
TXDLY=1
TXD[3:0], TXCLT
Tsetup
Thold
Integrated 10/100/1000 Gigabit Ethernet Transceiver
45
Track ID: JATR-1076-21 Rev. 1.3
RTL8211C & RTL8211CL
Datasheet
Figure 20. RGMII Timing Modes
Table 47. RGMII Timing Parameters
Symbol
TXC/RXC
tGCC
Description
Min
Typical
Max
Units
TXC, RXC Frequency
125-100ppm
125
8
-
125+100ppm MHz
TXC, RXC Cycle Time
-
-
-
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
tR
RXC Rise Time (20%~80%)
0.75
tF
RXC Fall Time (20%~80%)
-
-
0.75
TsetupT
TholdT
Tsetup
Thold
TXD, TXCLT Setup to TXC
1
2
2
-
-
-
TXD, TXCLT Hold from TXC
TXDLY=1; TXD, TXCLT Setup to TXC
TXDLY=1; TXD, TXCLT Hold from TXC
Data to Clock Output Skew
0.8
-0.9
2.7
-0.5
1.2
1
-
-
-
Tskew
TsetupR
TholdR
0
2
2
0.5
-
RXDLY=1; RXD, RXCLT Setup to RXC
RXDLY=1; RXD, RXCLT Hold from RXC
-
Integrated 10/100/1000 Gigabit Ethernet Transceiver
46
Track ID: JATR-1076-21 Rev. 1.3
RTL8211C & RTL8211CL
Datasheet
11. Mechanical Dimensions
11.1. RTL8211C 64-Pin QFN Mechanical Dimensions
Note: For RTL8211C-GR specific information refer to line 3.
Note: Exposed Pad is Analog and Digital Ground.
Integrated 10/100/1000 Gigabit Ethernet Transceiver
47
Track ID: JATR-1076-21 Rev. 1.3
RTL8211C & RTL8211CL
Datasheet
11.2. RTL8211CL 48-Pin LQFP Mechanical Dimensions
Integrated 10/100/1000 Gigabit Ethernet Transceiver
48
Track ID: JATR-1076-21 Rev. 1.3
RTL8211C & RTL8211CL
Datasheet
11.3. RTL8211CL 48-Pin LQFP Mechanical Dimensions Notes
Notes:
1. To be determined at seating plane -c-
2. Dimensions D1 and E1 do not include mold protrusion.
Symbol Dimension in
Inchs
Dimension in
Millimeters
D1 and E1 are maximum plastic body size dimensions
including mold mismatch.
Min
-
Nom
Max
Min
-
Nom
Max
1.70
0.20
1.50
0.29
0.25
0.16
3. Dimension b does not include dambar protrusion.
Dambar cannot be located on the lower radius of the foot.
4. Exact shape of each corner is optional.
A
A1
A2
b
-
0.067
-
0.000 0.004 0.008
0.051 0.055 0.059
0.006 0.009 0.011
0.006 0.008 0.010
0.00
1.30
15
0.1
1.40
5. These dimensions apply to the flat section of the lead
between 0.10 mm and 0.25 mm from the lead tip.
6. A1 is defined as the distance from the seating plane to the
lowest point of the package body.
0.22
b1
c1
D
0.15
0.09
0.20
0.004
-
0.006
-
0.354 BSC
0.276 BSC
0.354 BSC
0.276 BSC
0.020 BSC
9.00 BSC
7.00 BSC
9.00 BSC
7.00 BSC
0.50 BSC
7. Controlling dimension: millimeter.
D1
E
8. Reference document: JEDEC MS-026, BBC
TITLE: 48LD LQFP (7x7x1.4mm)
E1
PACKAGE OUTLINE DRAWING, FOOTPRINT 2.0mm
LEADFRAME MATERIAL:
e
L
L1
θ
0.016 0.024 0.031
0.039 REF
0.40
0.60
1.00 REF
3.5°
0.80
APPROVE
DOC. NO.
VERSION
PAGE
1
OF
0°
0°
3.5°
-
9°
-
0°
0°
9°
-
-
CHECK
DWG NO.
DATE
SS048 - P1
θ1
θ2
θ3
12° TYP
12° TYP
12° TYP
12° TYP
REALTEK SEMICONDUCTOR CORP.
Integrated 10/100/1000 Gigabit Ethernet Transceiver
49
Track ID: JATR-1076-21 Rev. 1.3
RTL8211C & RTL8211CL
Datasheet
12. Ordering Information
Table 48. Ordering Information
Part Number
RTL8211C-GR
RTL8211CL-GR
Package
Status
64-Pin QFN with Green Package
48-Pin LQFP with Green Package
Production
Production
Note: See page 3 (RTL8211C-GR) and page 4 (RTL8211CL-GR) for package identification.
Realtek Semiconductor Corp.
Headquarters
No. 2, Innovation Road II
Hsinchu Science Park, Hsinchu 300, Taiwan
Tel.: +886-3-578-0211 Fax: +886-3-577-6047
www.realtek.com
Integrated 10/100/1000 Gigabit Ethernet Transceiver
50
Track ID: JATR-1076-21 Rev. 1.3
相关型号：
©2020 ICPDF网 联系我们和版权申明