S1D19105 [ETC]
S1D19105d01b000;
| 型号： | S1D19105 |
| 厂家： | 
ETC |
| 描述： | S1D19105d01b000 |
| 文件： | 总122页 (文件大小：1015K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
S1D19105 Series
Rev.1.1
NOTICE
No part of this material may be reproduced or duplicated in any form or by any means without the written
permission of Seiko Epson. Seiko Epson reserves the right to make changes to this material without notice.
Seiko Epson does not assume any liability of any kind arising out of any inaccuracies contained in this material
or due to its application or use in any product or circuit and, further, there is no representation that this material
is applicable to products requiring high level reliability, such as, medical products. Moreover, no license to
any intellectual property rights is granted by implication or otherwise, and there is no representation or warranty
that anything made in accordance with this material will be free from any patent or copyright infringement of a
third party. This material or portions thereof may contain technology or the subject relating to strategic
products under the control of the Foreign Exchange and Foreign Trade Law of Japan and may require an export
license from the Ministry of International Trade and Industry or other approval from another government
agency.
All other product names mentioned herein are trademarks and/or registered trademarks of their respective
companies.
©SEIKO EPSON CORPORATION 2005, All rights reserved.
Configuration of product number
ꢀDSE1VICESD
19105 D 00B0
00
Packing specifications
Specifications
Shape (D: Chip, T:TCP, F : QFP)
Model number
Model name (D : LCD Driver)
Product classification
(S1:Semiconductors)
CONTENTS
1. DESCRIPTION....................................................................................................................................1
2. FEATURES .........................................................................................................................................2
3. BLOCK DIAGRAM .............................................................................................................................3
4. PIN ASSIGNMENT..............................................................................................................................4
4.1 S1D19105 Specifications of Chip...............................................................................................4
4.2 Bump Center Coordinates..........................................................................................................6
5. PIN DESCRIPTION...........................................................................................................................10
5.1 External Power Pins.................................................................................................................10
5.2 Built-in Power Pins ...................................................................................................................10
5.3 1st Booster Pins .......................................................................................................................11
5.4 The 2nd Booster Pins...............................................................................................................11
5.5 The 3rd Booster Pins................................................................................................................12
5.6 The 4th Booster Pins................................................................................................................12
5.7 VCOM Generation Pins..............................................................................................................13
5.8 Control Pins..............................................................................................................................14
5.9 γ Reference Output Pin ............................................................................................................15
5.10 RGB Interface Signal Pins........................................................................................................16
5.11 LCD Output Pins.......................................................................................................................16
5.12 Test Pins ...................................................................................................................................17
5.13 Dummy Output Pins .................................................................................................................17
6. FUNCTIONAL DESCRIPTION .........................................................................................................18
6.1 MPU Interface...........................................................................................................................18
6.1.1 MPU Interface Selection.............................................................................................18
6.1.2 Parallel MPU Interface................................................................................................18
6.1.3 Serial Interface............................................................................................................19
6.1.4 Internal Data Bus Expansion of Display Data ............................................................21
6.1.5 Access to Display Data RAM and Internal Register via MPU Interface.....................23
6.1.6 VSYNC Interface ........................................................................................................24
6.2 RGB Interface...........................................................................................................................25
6.2.1 RGB Interface Selection.............................................................................................25
6.2.2 RGB Interface Operation Modes................................................................................26
6.2.3 Internal Data Bus of RGB Interface............................................................................29
6.2.4 Access to Display Data RAM via RGB Interface........................................................30
6.3 Write Speed to Display Data RAM ...........................................................................................32
6.4 Display Data RAM ....................................................................................................................34
6.4.1 Display Data RAM ......................................................................................................34
6.4.2 Source Line Drive Output Pins and RAM Data..........................................................34
6.4.3 Row Address Circuit/Column Address Circuit............................................................35
6.4.4 Area Scrolling .............................................................................................................36
6.4.5 Partial Display.............................................................................................................37
6.4.6 AC Operation Drive ....................................................................................................38
6.5 Oscillation Circuit......................................................................................................................39
6.6 Setting Gate Line Scan Mode ..................................................................................................40
6.7 How to Connect to the External Power Supply........................................................................42
Rev.1.1
EPSON
i
6.8 Description of Operation of Built-in Power Supply...................................................................45
6.9 Power Supply for LCD and Main Specifications for Power Supply..........................................46
6.9.1 Basic Configuration Diagram of Built-in Power Supply..............................................47
6.9.2 The 1st Booster Circuit...............................................................................................48
6.9.3 The 2nd Booster Circuit..............................................................................................49
6.9.4 The 3rd Booster Circuit...............................................................................................50
6.9.5 The 4th Booster Circuit...............................................................................................51
6.9.6
VCOM Generation Circuit.............................................................................................53
6.10 Connection Diagram of External Parts.....................................................................................54
6.11 Gray scale Voltage Generation Circuit.....................................................................................58
6.11.1 Adjusting Gray Scale Voltage.....................................................................................59
6.11.2 Amplitude Adjustment.................................................................................................59
6.11.3 Tilt Adjustment ............................................................................................................59
6.11.4 Fine Adjustment of Gray Scale Voltage......................................................................59
6.12 Calculation of Gray Scale Voltage............................................................................................60
6.13 Resetting...................................................................................................................................64
7. COMMANDS.....................................................................................................................................65
7.1 Command List ..........................................................................................................................66
7.2 Initial Values of a Single-Byte Command.................................................................................67
7.3 Parameter Initial Value List.......................................................................................................68
7.4 Explanation of Commands .......................................................................................................70
7.5 Instruction Setup Example (Reference) ...................................................................................99
7.5.1 Initial Setup to Display-ON (VCORE forceful ON, VCORE forceful OFF) ......................99
7.5.2 Initial Setup to Display-ON (Normal use of VCORE)..................................................100
7.5.3 Power OFF Sequence..............................................................................................101
7.5.4 Initial Setup to Display-ON (Normal use of , VDC4 is less than 2.3V).....................102
7.5.5 Power OFF sequence...............................................................................................103
8. ABSOLUTE MAXIMUM RATINGS.................................................................................................104
9. RECOMMENDED OPERATING CONDITIONS .............................................................................105
10. DC CHARACTERISTICS................................................................................................................106
11. AC CHARACTERISTICS................................................................................................................107
11.1 Oscillation Frequency.............................................................................................................107
11.2 Parallel Interface.....................................................................................................................107
11.2.1 The 80-Series MPUs ................................................................................................107
11.2.2 The 68-Series MPUs ................................................................................................109
11.3 Serial Interface ....................................................................................................................... 111
11.4 Resetting.................................................................................................................................112
11.5 Source Output ........................................................................................................................112
11.6 RGB Interface.........................................................................................................................113
12. NOTES ............................................................................................................................................114
ii
EPSON
Rev.1.1
1. DESCRIPTION
1. DESCRIPTION
The S1D19105 series is a 1-chip driver for driving amorphous Si-TFT with built-in data RAM that contains 176
RGB × 220 dots, supporting 262k-color display. Since this series contains all power circuits necessary for the
220-output gate driver, 176-RGB output source driver, and the display, the TFT color panel module of a
maximum of 176 RGB × 220 dots can be constructed with a minimum of components.
The S1D19105 incorporates 8/9/16/18-bit parallel interface that can be directly attached to the micro computer
(hereafter referred to as MPU) bus. The 3-line serial interface can also be used. The S1D19105 series receives
parallel or serial display data from the microprocessor, stores it in the display data RAM, and outputs resource
line drive signals, gate driver drive signals, and AC operation timing signals independent from MPU operations.
Also, for movie display, 6/16/18-bit RGB interface and VSYNC synchronization function are provided.
The S1D19105 series has the low current consumption, source line drive circuit (including reference voltage
adjustment resistor and bias circuit for reference voltage circuit), high-efficiency power circuit and the CR
oscillation circuit for fully-built-in display clock that does not require external parts. In addition, power can be
controlled more finely using command control, as this series supports 8-color display mode and partial display
mode. The S1D19105 series provides
a high-performance but handy display system with a minimum of
components in the minimum power consumption.
S1D19105 Series (Rev.1.1)
EPSON
1
2. FEATURES
2. FEATURES
ꢀ
ꢀ
ꢀ
Supports 176 RGB × 220 dots and 262,144 colors amorphous Si-TFT color panel.
RAM capacity 176 × 3 × 220 × 6 = 696,960 bits
Display function
Display of 262k-color at a time
Area scrolling
Partial display
8-color display mode
ꢀ
Interface function
Selection from 8/9/16/18-bit parallel MPU interface.
Direct attachment to either of 80- and 68-series MPUs.
262k-color display via 16-bit interface by selecting 2+16 and 16+2 modes.
___
Serial interface 3 signal lines (CS, SCL, and SI signals)
Selection from 6/16/18-bit RGB interface specifically for moving picture display, etc.
VSYNC synchronization function provides flicker-free moving picture display.
ꢀ
ꢀ
176 × 3 source line drive output A 6-bit D/A converter is included.
A 110 output each is placed on the right and left sides of the 220 gate line drive output chip. Also,
supports interlace drive.
ꢀ
ꢀ
CR oscillation circuit (External clocks can also be used.)
Common electrode drive signal outputs (VCOM signals)
Allows 1-frame/3-line interlace/n-line reverse driving.
ꢀ
Low supply voltage operation
DDI- VSSSS= 2.3 to 3.1V (power supply for internal logic power supply)
V
V
- V = 1.65 to 3.3V (interface I/O power supply)
VDD - V = 2.3 to 3.1V (power supply for built-in power circuits)
VDDDDC2 ORES-SVSS = 2.3 to 3.1V (internal logic power supply)
Source voltage = Max.5.5V
Gate voltage = Max.30V
ꢀ
ꢀ
BUMP layout appropriate for COG assembly
Package models available: Au bump chip and COF
2
EPSON
S1D19105 Series (Rev.1.1)
3. BLOCK DIAGRAM
3. BLOCK DIAGRAM
GD1 to 4
Gate driver
Gate driver
4
V
V
V
OUT
DC1
LD0
V
V
V
V
V
V
V
V
V
V
V
DD
Source driver
DDI
C11N
C11P
DD2
Display data latch circuit
VDC2
SS
C12N
C12P
REG
DDHS
ONREG
OFREG
CORE
OSC
LDO
VOUTM
VDC3
Display data RAM
C31N
C31P
C33N
C32N
C32P
176
U3
U220U6
VEE
Column address
Control logic
VDC4
VDC5
C41N
C41P
VDDHG
OSCI
VCOM
VSWIN
OSCO
CWN
CWP
COMW
FBW
V
VCOMH
FBH
V
V
V
COMH2
COML
DDRH
DDRL
TEST1 to 5
RGB interface
System interface
5
V
8
3
18
Fig.1 S1D19105 Series Block Diagram
S1D19105 Series (Rev.1.1)
EPSON
3
4. PIN ASSIGNMENT
4. PIN ASSIGNMENT
4.1 S1D19105 Specifications of Chip
Table 1 Specifications of Chip
Dimensions
Parameter
Unit
X
Y
Chip size
19.56
2.49
mm
µm
µm
µm
µm
µm
Chip thickness
Bump pitch
Bump size
400
Min.50
No.1 to 205
No.206 to 978
54
24
100
105
Bump height
Typ.15
Note: These values are given for reference only.
Table 2 Bump Assignment Drawing
(0,0)
REV **
The alignment mark is put on two locations.
25
30
40
150
50
30
25
40
25
30
30
25
50
150
Unit: µm
Fig.2 Alignment Mark
4
EPSON
S1D19105 Series (Rev.1.1)
4. PIN ASSIGNMENT
(-7060.0, -152.6)
REV **
(-7220.0, -200.6)
Unit: µm
Fig.3 Revision Coordinate Mark
105
S1 to S528
25
40
50
G1 to G220
105
24 26 24
Area = 2520µ
m2
54
I/O Pins
100
(for different potentials)
Min.80
Area = 5400
µ
m2
Unit: µm
Fig.4 Bump Size and Assignment Drawing
S1D19105 Series (Rev.1.1)
EPSON
5
4. PIN ASSIGNMENT
4.2 Bump Center Coordinates
Table 3 Bump Center Coordinates
Unit: µm
Y
BUMP No. Signal name
X
Y
BUMP No. Signal name
X
1
2
3
4
5
6
7
8
ADUMMY
BDUMMY
DUMMY
-9429.2
-9349.2
-9269.2
-9189.2
-9109.2
-9029.2
-8949.2
-8869.2
-8789.2
-8709.2
-8629.2
-8549.2
-8469.2
-8389.2
-8309.2
-8229.2
-8149.2
-8039.2
-7929.2
-7819.2
-7739.2
-7649.2
-7569.2
-7435.5
-7355.5
-7275.5
-7195.5
-7115.5
-7025.5
-6945.5
-6865.5
-6785.5
-6705.5
-6571.8
-6491.8
-1098.6
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
V
V
V
V
V
V
V
V
V
V
C86
IF1
CORE
CORE
CORE
CORE
-6411.8
-6331.8
-6251.8
-6171.8
-6091.8
-6011.8
-5931.8
-5851.8
-5771.8
-5691.8
-5611.8
-5531.8
-5451.8
-5371.8
-5291.8
-5211.8
-5131.8
-5051.8
-4971.8
-4891.8
-4811.8
-4731.8
-4651.8
-4571.8
-4491.8
-4411.8
-4331.8
-4251.8
-4171.8
-4091.8
-4011.8
-3931.8
-3851.8
-3771.8
-3691.8
-1098.6
V
V
COM
COM
DDI
DUMMY
DDI
V
V
DDHG
SS
SS
SS
SS
DDHG
9
DUMMY
C41P
C41P
DUMMY
C41N
C41N
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
IF2
IF3
DUMMY
DUMMY
V
ONREG
V63
V
V
DC4
DC5
V
V
8
7
6
5
4
3
2
1
0
V
V
V
OFREG
DC3
OUTDM
V
V
V
V
V
V
V
C32P
C32P
C32N
C32N
DUMMY
DUMMY
____
V
EE
RES
V
EE
DUMMY
___
C33N
C33N
DUMMY
C31N
C31N
C31P
CS
DUMMY
A0
DUMMY
___
WR
DUMMY
___
C31P
RD
6
EPSON
S1D19105 Series (Rev.1.1)
4. PIN ASSIGNMENT
Unit: µm
Y
BUMP No. Signal name
X
Y
BUMP No. Signal name
X
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
DUMMY
D0
-3611.8
-3531.8
-3371.8
-3211.8
-3051.8
-2891.8
-2731.8
-2571.8
-2411.8
-2251.8
-2091.8
-1931.8
-1771.8
-1611.8
-1451.8
-1291.8
-1131.8
-971.8
-811.8
-651.8
-491.8
-331.8
-171.8
-91.8
-1098.6
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
SD
868.2
-1098.6
EECK
EEDA
EECS
1028.2
1188.2
1348.2
1508.2
1668.2
1748.2
1828.2
1908.2
1988.2
2068.2
2148.2
2228.2
2308.2
2388.2
2468.2
2548.2
2628.2
2708.2
2798.2
2908.2
2998.2
3088.2
3168.2
3248.2
3328.2
3408.2
3488.2
3568.2
3648.2
3728.2
3808.2
3888.2
3968.2
4048.2
D1
D2
D3
D4
D5
D6
D7
D8
D9
D10
D11
D12
D13
D14
D15
D16
VEP
TEST1
DUMMY
TEST2
DUMMY
TEST3
DUMMY
TEST4
DUMMY
TEST5
DUMMY
TRI
OSCO
OSCI
D17
V
OSC
DDRL
DDRH
REG
DUMMY
VSYNCO2
VSYNCO
VSYNCI
DUMMY
HSYNC
DUMMY
DCK
DUMMY
ENABLE
DUMMY
DUMMY
DUMMY
DUMMY
SCL
V
V
V
V
V
SS
SS
SS
SS
SS
SS
SS
SS
-11.8
68.2
148.2
228.2
308.2
388.2
468.2
548.2
V
V
V
V
V
V
VDDI
VDDI
VDDI
VDDI
628.2
708.2
788.2
DUMMY
VCORE
S1D19105 Series (Rev.1.1)
EPSON
7
4. PIN ASSIGNMENT
Unit: µm
Y
BUMP No. Signal name
X
Y
BUMP No. Signal name
X
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
V
V
V
V
V
V
V
CORE
CORE
CORE
CORE
CORE
CORE
CORE
4128.2
4208.2
4288.2
4368.2
4448.2
4528.2
4608.2
4688.2
4768.2
4848.2
4928.2
5008.2
5088.2
5168.2
5248.2
5328.2
5408.2
5488.2
5568.2
5648.2
5728.2
5808.2
5888.2
5968.2
6048.2
6128.2
6208.2
6288.2
6368.2
6448.2
6528.2
6608.2
6688.2
6768.2
6848.2
-1098.6
176
177
178
179
180
181
182
183
184
185
186
187
188
189
190
191
192
193
194
195
196
197
198
199
200
201
202
203
204
205
V
V
V
V
OUT
OUT
OUT
OUT
6928.2
7008.2
7088.2
7168.2
7248.2
7328.2
7408.2
7488.2
7578.2
7658.2
7791.9
7871.9
7961.9
8041.9
8121.9
8201.9
8335.6
8415.6
8495.6
8575.6
8655.6
8735.6
8815.6
8895.6
8975.6
9109.3
9189.3
9269.3
9349.3
9429.3
-1098.6
V
V
DDHS
DDHS
V
V
C21P
C21P
C21N
C21N
DC2
DC2
V
DD
DD
DD
DD
DD
DD
DD
DD
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
C11N
C11N
C11N
C11N
C11P
C11P
C11P
C11P
V
OUTM
OUTM
COML
COML
V
V
V
DD2
DD2
DD2
DD2
DD2
DD2
DD2
DD2
DC1
DC1
LDO
LDO
V
COMH2
FBH
V
REG
V
COMH
FBW
V
COMW
CWP
CWN
V
SWIN
V
V
COM
COM
DUMMY
CDUMMY
DDUMMY
8
EPSON
S1D19105 Series (Rev.1.1)
4. PIN ASSIGNMENT
Unit: µm
Y
BUMP No. Signal name
X
Y
BUMP No. Signal name
X
206
207
208
209
210
211
212
213
214
215
216
217
218
219
220
221
222
DUMMY
DUMMY
9650
9625
9600
9575
9550
9525
9500
9475
9450
9425
9400
9375
9350
9325
9300
9275
9250
ꢁ
958.8
1103.8
958.8
1103.8
958.8
1103.8
958.8
1103.8
958.8
1103.8
958.8
1103.8
958.8
1103.8
958.8
1103.8
958.8
ꢁ
333
334
335
336
337
S6
S7
S8
S9
S10
ꢁ
6475
6450
6425
6400
6375
ꢁ
1103.8
958.8
1103.8
958.8
1103.8
ꢁ
V
V
COM
COM
DDUMMY
CDUMMY
GD1
G1
ꢁ
ꢁ
ꢁ
ꢁ
ꢁ
ꢁ
G2
G3
G4
G5
G6
G7
G8
G9
853
854
855
856
857
858
859
860
861
862
863
864
S526
S527
S528
DUMMY
DUMMY
DUMMY
DUMMY
DUMMY
GD3
G111
G112
G113
ꢁ
-6525
-6550
-6575
-6600
-6625
-6650
-6675
-6700
-6725
-6750
-6775
-6800
ꢁ
1103.8
958.8
1103.8
958.8
1103.8
958.8
1103.8
958.8
1103.8
958.8
1103.8
958.8
ꢁ
G10
ꢁ
ꢁ
ꢁ
ꢁ
ꢁ
ꢁ
ꢁ
321
322
323
324
325
326
327
328
329
330
331
332
G109
G110
GD2
DUMMY
DUMMY
DUMMY
DUMMY
S1
6775
6750
6725
6700
6675
6650
6625
6600
6575
6550
6525
6500
1103.8
958.8
1103.8
958.8
1103.8
958.8
1103.8
958.8
1103.8
958.8
1103.8
958.8
ꢁ
ꢁ
ꢁ
ꢁ
ꢁ
ꢁ
970
971
972
973
974
975
976
977
978
G219
G220
GD4
BDUMMY
ADUMMY
-9450
-9475
-9500
-9525
-9550
-9575
-9600
-9625
-9650
958.8
1103.8
958.8
1103.8
958.8
1103.8
958.8
1103.8
958.8
S2
S3
S4
S5
VCOM
VCOM
DUMMY
DUMMY
X coordinates of Gm pin (m = 1 to 110): (110-m) × 25 + 6750
µ
m
Y coordinates: m = 1103.8
X coordinates of Sm pin (m=1 to 528): (528-m) × 25 -6575
Y coordinates: m = 1103.8 m for odd number m = 958.8
X coordinates of Gm pin (m=111 to 220): (220-m) × 25 -9475
Y coordinates: m = 1103.8 m for odd number m = 958.8 m for even number
µ
m for odd number m = 958.8
µ
m for even number
µm
µ
µm for even number
µ
m
µ
µ
S1D19105 Series (Rev.1.1)
EPSON
9
5. PIN DESCRIPTION
5. PIN DESCRIPTION
5.1 External Power Pins
Table 4 External Power Pins
Connected
To
External
power
Number of
Pin Name
V
I/O
Description
pins
DD2
Power supply
I
Power pins for built-in power circuits.
Used for built-in power supply.
8
Used as the reference power supply for the 1st booster.
Supply external power.
See section 6.7 How to Connect to External Power Supply.
Power pins for VCORE generation built-in power circuits.
V
DD
Power supply
I
External
power
8
6
It is common to the VDD2
.
Supply external power.
See section 6.7 How to Connect to External Power Supply.
Power pins dedicated to interface.
Power supply for interface pins.
Supply external power.
V
DDI
Power supply
I
External
power
See section 6.7 How to Connect to External Power Supply.
They are ground pins.
The 0V pin connected to the system ground.
Used as the IC board potential.
V
SS
Power supply
I
External
power
12
5.2 Built-in Power Pins
Table 5 Built-in Power Pins
Connected
To
Capacity
External
power
Number of
Pins
Pin Name
I/O
Description
V
CORE
I/O
Logic and RAM power supplies.
12
Generated by a built-in power supply or connected to an
external power. Connect it to external power basically.
See section 6.7 How to Connect to External Power Supply.
Reference voltage for built-in power supply.
V
REG
O
O
O
Capacity
Capacity
Capacity
2
2
1
V
V
DDHS
Voltage for generating source driver drive voltage.
Voltage for adjusting VDDHG.
Connect it to capacity if it used.
Set it to open if it is not used.
ONREG
V
DC4
Open
V
OFREG
O
Capacity
Voltage for adjusting VEE
.
1
V
DC3
Connect it to capacity if it used.
Open
Open
Set it to open if it is not used.
V
V
OSC
LDO
O
O
Voltage for CR oscillation circuit
Used as the reference voltage for the 1st booster.
Used to control the 1st booster voltage. Fixed it to open
basically.
1
2
Capacity
Open
V
V
DDRH
DDRL
O
O
Capacity
Capacity
Reference voltage for V
0
generation for γ correction resistor.
1
1
Reference voltage for V63 generation for γ correction
resistor.
10
EPSON
S1D19105 Series (Rev.1.1)
5. PIN DESCRIPTION
5.3 1st Booster Pins
Table 6 1st Booster Pins
Connected
To
Capacity
Number of
Pin Name
I/O
Description
The 1st booster voltage.
Pins
V
OUT
O
4
Outputs double VDC1 voltage for built-in power
circuits.
The 1st booster reference voltage input pin.
V
DC1
I
V
DD2
LDO
2
V
Connect either VDD2 or VLDO
.
Connect it to VDD2
basically.
C11N
C11P
I/O
I/O
Capacity
Capacity
Flying capacitor for generating VOUT output
Connecting pins on the negative side
Flying capacitor for generating VOUT output
Connecting pins on the positive side
4
4
5.4 The 2nd Booster Pins
Table 7 The 2nd Booster Pins
Connected
To
Number of
Pin Name
I/O
Description
Pins
V
DC2
I
V
DD2
The 2nd booster reference voltage input pin.
Connect either VDD2 or VOUT.
2
V
OUT
C21P
C21N
I/O
I/O
O
Capacity
Capacity
Capacity
Flying capacitor for generating VOUTM output
Connecting pins on the positive side
Flying capacitor for generating VOUTM output
Connecting pins on the negative side
Voltage for generating VCOML
2
2
2
V
OUTM
Outputs the voltage obtained by multiplying VDD2 or VOUT
by a factor of (-1).
S1D19105 Series (Rev.1.1)
EPSON
11
5. PIN DESCRIPTION
5.5 The 3rd Booster Pins
Table 8 The 3rd Booster Pins
Connected
To
Number of
Pin Name
I/O
Description
Pins
V
DC3
I
V
DD2
OUTDM
OFREG
DC3
The 3rd booster reference voltage input pin.
Connect it to either VOUTDM or VOFREG.
1
V
V
Connect it to VOFREG at the time of –3 times boosting.
Outputs VOUT
Used to input VOUT to VDC3
V
OUTDM
O
O
V
.
1
2
2
2
2
2
2
Open
.
C31P
C31N
C33N
C32P
C32N
Capacity
1 Flying capacitor for generating VEE output
Connecting pins on the positive side
I/O
I/O
I/O
I/O
O
Capacity
Capacity
Capacity
Capacity
Capacity
1 Flying capacitor for generating VEE output
Connecting pins on the negative side
3 Flying capacitor for generating VEE output
Connecting pins on the negative side
2 Flying capacitor for generating VEE output
Connecting pins on the positive side
2 Flying capacitor for generating VEE output
Connecting pins on the negative side
V
EE
VEE output pin
Gate off voltage
Outputs the voltage obtained by multiplying VDD2 or VOUT by
a factor of (-1 to -3).
5.6 The 4th Booster Pins
Table 9 The 4th Booster Pins
Number of
Pin Name
I/O
Connected To
Description
Pins
V
DC4
I
V
DD2
SS
ONREG
DD2
SS
ONREG
The 4th booster reference voltage input pin.
1
V
Connect it to VDD2, VSS or VONREG. It should be connected
to VSS. Because It is for discharge pin of the VDDHG.
The 4th booster reference voltage input pin.
V
V
DC5
I
V
V
1
Connect it to VDD2, VSS or VONREG.
V
C41P
C41N
I/O
I/O
O
Capacity
Capacity
Capacity
Flying capacitor connecting pins on the positive side for
generating VEE output
Flying capacitor connecting pins on the negative side for
generating VEE output
2
2
2
V
DDHG
V
DDHG output pin. Gate on voltage
Outputs double boosted voltage between VDC4 and VEE to
V
DC5.
12
EPSON
S1D19105 Series (Rev.1.1)
5. PIN DESCRIPTION
5.7 VCOM Generation Pins
Table 10 VCOM Generation Pins
Connected
Number of
Pin Name
I/O
Description
To
Pins
V
SWIN
O
I/O
I/O
O
I
O
Open
Open
Open
Open
Open
Capacity
Resistor
This pin. Fix it to open.
This pin. Fix it to open.
This pin. Fix it to open.
This pin. Fix it to open.
This pin. Fix it to open.
1
1
1
1
1
CWN
CWP
V
COMW
FBW
V
COMH
Voltage output pin on the side of high voltage level of the VCOM
signal.
2
The twice of voltage inputted into the FBH pin are outputted. It is
possible to adjust VCOMH voltage, maintaining VCOM amplitude
by connecting variable resistance between VREG to VSS and
inputting arbitrary voltage into FBH pin. Adjustment by the built-in
electronic control is also possible.
FBH
I
VCOMH2 It is an adjustment voltage input pin in the case of adjusting
1
Resistor
Capacity
VCOMH voltage.
When adjusting by external resistance, it is possible to adjust
VCOMH voltage, maintaining VCOM amplitude by connecting
variable resistance between VREG to VSS and inputting arbitrary
voltage into FBH pin. The twice as many voltage inputted into the
FBH pin as this is outputted to VCOMH. To adjust it using the
built-in electronic control, connect it to the VCOMH2 pin.
Connect capacity about it between VSS to decrease the influence
of the noise.
V
COMH2
O
O
FBH
Open
Capacity
This pin is used for connecting to FBH to adjust the VCOMH voltage
with the built-in electronic control.
Voltage output pin on the side of low voltage level of the VCOM
signal.
1
2
V
COML
V
COML=VCOMH – VCA × 2
Outputs voltage by the above equation.
VCA is the value of the built-in electronic control used for
determining the amplitude of VCOM
.
S1D19105 Series (Rev.1.1)
EPSON
13
5. PIN DESCRIPTION
5.8 Control Pins
Table 11 Control Pins
Connected
To
Number of
Pin Name
I/O
Description
Pins
___
CS
I
MPU
Chip Select pin.
1
___
When CS= LOW, the pin is active and data or command input is
___
enabled. In the test mode, clock input from the CS pin is
enabled.
A0
I
MPU
Data/command identification pin
1
When using the parallel interface, usually the least significant bit of
the MPU address bus is connected to identify the data or
command.
When using the 9-bit serial interface, fix it for LOW or HIGH.
A0= HIGH : The display data or command parameters are
entered in the Data Bus pins.
A0= LOW : The commands are entered in the Data Bus pins.
Read pin. (If connected to the 80-series MPU)
___
RD
I
I
MPU
MPU
1
1
(E)
While this signal is kept LOW, the data bus is output enabled at the
___
RD signal pin of 80-series MPU.
Enable clock pin. (If connected to the 68-series MPU)
This is the Enable Clock input pin of the 68-series MPU.
When the serial interface is selected, fix VDDI or VSS for the level.
___
WR
__
Write pin. (If connected to the 80-series MPU)
___
(R/W)
Used for connecting 80-series MPU’s WR signal. A signal on the
___
data bus is latched at the rising edge of the WR signal.
Read or write pin. (If connected to the 68-series MPU)
This is the Read/Write signal input pin of the 68-series MPU.
__
R/W = HIGH: Read
__
R/W = LOW: Write
When the serial interface is selected, fix VDDI or VSS for the level.
Data bus pin.
D0 to D17
I/O
MPU
18
Controller 18-bit bi-directional data bus. Used as data bus for both parallel
MUP interface and RGB interface.
When the parallel MPU interface is selected and the Chip Select is
in the non-active state, operations of all pins stop, disabling both
input and output. The following signal pins are used for each
mode. Unused pins can be set open.
8-bit mode D17 to D10
9-bit mode D17 to D9
16-bit mode D17 to D2
18-bit mode D17 to D0
Input pins used when the RGB interface is selected.
The following signal pins are used for each mode. Unused pins can
be set open.
6-bit mode D17 to D12
16-bit mode D17 to D2
18-bit mode D17 to D0
14
EPSON
S1D19105 Series (Rev.1.1)
5. PIN DESCRIPTION
Connected
To
Number of
Pin Name
I/O
Description
Pins
SCL
I
MPU
Serial clock pin.
1
Serial clock input pins used when the serial interface is selected.
When not choosing a serial interface, it is possible to make it to
open.
SD
I/O
MPU
Serial data input/output pin.
1
Serial data input/output pin used when the serial interface is
selected.
When not choosing a serial interface, it is possible to make it to
open.
MPU interface switching pin.
C86= HIGH : The 68-series MPU interface
C86= LOW : The 80-series MPU interface
MPU interface switching pin.
C86
I
I
V
V
SS
/
1
3
DDI
IF1, IF2
IF3
V
V
SS
/
DDI
IF3
IF2
IF1
Interface
16-bit parallel
18-bit parallel
8-bit parallel
9-bit parallel
9-bit serial
LOW LOW LOW
LOW LOW HIGH
LOW HIGH LOW
LOW HIGH HIGH
HIGH HIGH HIGH
____
RES
I
I
MPU
Reset pin.
Resets if set to LOW.
Clock input pin.
Test pin. Connect it to either VSS or VDDI
When the built-in oscillation circuit is used, set (P17 data set
command is “0”) and connect it to VSS or VDDI When the built-in
1
1
OSCI
V
V
SS
/
DDI
.
.
oscillation circuit is used, set (P17 data set command is “1”) and
enter an external clock.
Clock output pin.
Test pin. Set open.
OSCO
O
Open
1
Outputs oscillation clocks when the built-in oscillator circuit is
used.
Verifies the oscillation out when testing.
5.9 γ Reference Output Pin
Table 12 γ Reference Output Pin
Connected
Number of
Pin Name
I/O
Description
To
Pins
V
0
O
O
O
Capacity
Capacity
Open
MSB of the gray scale voltage
LSB voltage of the gray scale voltage
Test pin. Set open.
1
1
1
V
63
V8 to V1
S1D19105 Series (Rev.1.1)
EPSON
15
5. PIN DESCRIPTION
5.10 RGB Interface Signal Pins
Table 13 RGB Interface Signal Pins
Connected
To
Number of
Pin Name
I/O
Description
Vertical synchronization input pins.
Pins
VSYNCI
I
MPU
1
Enters the vertical synchronization signal when set for the VSYNC
interface, RGB transfer 2 or 3 using the Set Display Data Interface
command.
If it is not set, no entry operation takes place. So it is possible to
set it open.
Vertical synchronization output pins.
Outputs the vertical synchronization signal.
Vertical synchronization output pins.
VSYNCO
O
O
MPU
1
1
VSYNCO2
Open
Outputs the vertical synchronization divided into 1/2.
As it is a test pin, set it open.
Horizontal synchronization pins.
HSYNC
I
MPU
1
Enters the horizontal synchronization signal when set for the RGB
transfer 3 using the Set Display Data Interface command.
If it is not set, no entry operation takes place. So it is possible to
set it open.
DOTCLK
I
MPU
RGB interface dot clock pin.
1
Enters the dot clock when using the RGB interface.
At the rising edge or falling edge of this signal, the RGB data
entered in D0 to D17 is read.
When the RGB interface is not used, it is possible to set open.
When the RGB transfer 3 is set, it becomes the display reference
clock signal and the reference clock of a booster clock.
RGB Interface enable pin.
ENABLE
I
MPU
1
This is the data enable signal when using the RGB interface.
When the RGB interface is not used, it is possible to set open.
5.11 LCD Output Pins
Table 14 LCD Output Pins
Connected
To
Number of
Pins
Pin Name
I/O
Description
S1 to S528
O
LCD
Source line drive output pins.
528
Converts digital display data into analog form (D/A conversion) and
outputs it.
Gate line drive output pins.
Outputs gate line selection level: VDDHG and non-selection level:
G1 to 220
GD1 to 4
O
LCD
220
V
EE.
O
O
LCD
LCD
Dummy gate line drive output pins.
Continuously outputs VEE voltage level.
4
8
V
COM
V
COM signal output pin.
Used as the common electrode signal for the TFT panel.
16
EPSON
S1D19105 Series (Rev.1.1)
5. PIN DESCRIPTION
5.12 Test Pins
Table 15 Test Pins
Connected
To
Number of
Pin Name
I/O
Description
Pins
TEST1
I
GND
Test pin
1
The customer cannot use it. Be sure to enter LOW.
HIGH: Test mode (adjustment of oscillation frequency and VREG
LOW: Normal operation mode
)
TEST2
TEST3
I
I
GND
Test pin
1
1
The customer cannot use it. Be sure to enter LOW.
HIGH: Test mode (Built-in power output is not discharged.)
LOW: Normal operation mode. (Built-in power output is
discharged.)
V
DDI
VCORE disable pin
Set HIGH when supplying an external power supply to the VCORE
pin.
HIGH: Forcefully turns VCORE OFF. (Not discharged.)
LOW: Normal operation mode. (Discharge is carried out when
VCORE OFF.)
See section 6.7 How to Connect to External Power Supply.
Connect it to VDDI to connect with external power supply basically.
TEST4
TEST5
I
I
GND
GND
VCORE force enable pin
1
1
Used to not discharge VCORE in the sleep in state.
HIGH: Forcefully turns VCORE ON. (Not discharged.)
LOW: Normal operation mode. (Discharge is carried out when
VCORE OFF.)
See section 6.7 How to Connect to External Power Supply.
Connect it to GND to connect with external power supply basically.
Test pin
(The customer cannot use it. Be sure to enter LOW. )
HIGH: Test mode LOW: Normal operation mode
Test pin. Internal constant current adjustment pin. Fix it to open.
Test pin. Fix it to open.
TRI
O
O
O
O
O
Open
Open
Open
Open
Open
1
1
1
1
1
EECK
EEDA
EECS
VEP
Test pin. Fix it to open.
Test pin. Fix it to open.
Test pin. Fix it to open.
5.13 Dummy Output Pins
Table 16 Dummy Output Pins
Connected
Number of
Pins
Pin Name
I/O
Description
To
DUMMY
Open
Dummy pin
42
Do not connect the voltage to the DUMMY pin.
There are two pins that are connected by aluminum winding.
When it is used, connect it within VSS to VOUT
There are two pins that are connected by aluminum winding.
When it is used, connect it within VEE to VDDHG
There are two pins that are connected by aluminum winding.
When it is used, connect it within VEE to VDDHG
There are two pins that are connected by aluminum winding.
When it is used, connect it within VSS to VOUT
ADUMMY
BDUMMY
CDUMMY
DDUMMY
Open
Open
Open
Open
2
2
2
2
.
.
.
.
S1D19105 Series (Rev.1.1)
EPSON
17
6. FUNCTIONAL DESCRIPTION
6. FUNCTIONAL DESCRIPTION
6.1 MPU Interface
This IC is provided with 8/9/16/18-bit MPU interface and 9-bit serial interface for command and display data
transfer from the MPU. When you have selected the 16-bit MPU interface, you can select 2 + 16-bit or 16 + 2-bit
mode using the data set command. Also, for display data transfer, 6/16/18-bit RGB interface is provided. In
addition, with the VSYNC synchronization function newly provided, the system best suited to displaying both
still pictures and moving pictures simultaneously can be built.
6.1.1 MPU Interface Selection
The MPU interface can be used for transferring commands and display data, and can be selected with the MPU
interface select pins (IF3, IF2 and IF1) as shown in the table below.
Table 17 MPU Interface Selection
IF3
IF2
IF1
Interface
16-bit parallel
18-bit parallel
8-bit parallel
9-bit parallel
9-bit serial
RAM Write
Enable
Enable
Enable
Enable
RAM Read
Enable
Enable
Enable
Enable
LOW
LOW
LOW
LOW
HIGH
LOW
LOW
HIGH
HIGH
HIGH
LOW
HIGH
LOW
HIGH
HIGH
Disable
Disable
6.1.2 Parallel MPU Interface
Depending on the C86 pin setting, 80-series or 68-series MPU can be connected.
Table 18 C86 Test Pins
___
RD
___
C86
WR
__
HIGH: 68-series MPU bus
LOW: 80-series MPU bus
E
R/W
___
___
RD
WR
Signals on the parallel MPU interface are identified by combination with the data/command identification pin
(A0).
Table 19 MPU Interface Identification
68-Series MPU
80-Series MPU
__
___
___
A0
Function
R/W
E
RD
WR
LOW
HIGH
HIGH
LOW
HIGH
HIGH
LOW
LOW
HIGH
HIGH
HIGH
HIGH
LOW
LOW
HIGH
HIGH
HIGH
HIGH
LOW
LOW
Revision read
RAM data read
RAM data, command parameter write
Command write
D17 to D0, DR and DB are used as 8/9/16/18-bit width bus according to the setting of the MPU interface select
pins IF1, IF2 and IF3, and unused pins are set open. For commands and parameters, MSB 8 bits (D17 to D10) are
used.
18
EPSON
S1D19105 Series (Rev.1.1)
6. FUNCTIONAL DESCRIPTION
Table 20 MPU Parallel Interface (Except for Display Data)
Data type
Parallel MPU interface Dxx
Bus width
A0
17 16 15 14 13 12 11 10 9
Command
8
7
6
5
4
3
2
1
0
18-bit mode
Command
Parameter
Command
Parameter
Command
Parameter
Command
Parameter
Command
Parameter
Command
Parameter
0
1
0
1
0
1
0
1
0
1
0
1
Parameter
Command
Parameter
Command
Parameter
Command
Parameter
Command
16-bit mode
Z
Z
Z
Z
Z
Z
Z
Z
Z
Z
Z
Z
Z
Z
Z
Z
Z
Z
Z
Z
2+16-bit mode
*
16 + 2-bit mode
*
9-bit mode
Z
Z
Z
Z
Z
Z
Z
Z
Z
Z
Z
Z
Z
Z
Z
Z
Z
Z
Z
Z
Z
Z
Z
Z
Z
Z
Z
Z
Parameter
Command
Parameter
8-bit mode
Z
Z
* 2+16bit mode and 16+2bit mode are chosen by the data set command(BCh).
indicates invalid data.
Z indicates disable. Set the disabled pins open.
6.1.3 Serial Interface
___
The serial interface supports 9-bit mode. The 9-bit mode consists of three lines: chip select (CS), serial clock
(SCL), and serial data input (SI). When the serial interface is selected, data can be input/output by clocks while
___
the chip is active (CS=LOW). Data is transferred in the unit of 9 bits. At input, data is read in order from MSB at
the clock rising edge. MSB is the data/command identification data (D/C) equivalent to the A0 signal of the
parallel interface. It is the command when set to “0” and the parameter when set to “1”.
___
To prevent malfunction due to noise, it is recommended to set the CS signal to HIGH every 9 bits. (The serial
___
counter is reset at the falling edge of the CS signal.)
Table 21 9-bit Serial Interface (Except for Display Data)
Serial interface bit position
Data type
DC 17 16 15 14 13 12 11 10
Command
Parameter
0
1
Command
Parameter
D/C: Data/command identification bit
indicates invalid data.
Processing starts when the serial transfer clock D10 LSB is input. Writing to or reading from the display data
RAM is disabled. If any parameter exceeding the number of parameters defined for each command is entered, it
is invalid.
S1D19105 Series (Rev.1.1)
EPSON
19
6. FUNCTIONAL DESCRIPTION
The interface examples are given below. (The intermediate level of SD in the following diagram indicates the
state of high impedance.)
ꢂ When writing
CS
SCL
SD
D/C C17 C16 C15 C14 C13 C12 C11 C10 D/C P17 P16 P15 P14 P13 P12 P11 P10
D/C C17 C16 C15 C14 C13 C12 C11 C10
D/C: A0
Cn: Command Bit n
Pn: Parameter Bit n
___
The 9-bit serial data (1 packet) must be kept at the LOW level during transfer. When CS sets to LOW, SCL
___
should be in the state of LOW. If CS is set HIGH during 1-packet transfer, the packet in the process of
___
transfer is cancelled. Setting LOW for CS again brings the state of accepting retransfer of the packet.
CS
SCL
SD
D/C C17 C16 C15 C14 C13 C12 C11 C10 D/C C17 C16 C15 C14 C13 C12 C11 C10 D/C P17 P16 P15 P14 P13 P12 P11 P10
Ignore Input
D/C: A0
Cn: Command Bit n
Pn: Parameter Bit n
ꢂ When reading
___
When data is read using the status read and revision read commands, the following situation occurs. When CS
sets to LOW, SCL should be in the state of LOW. When transfer of read data up to final bit is completed, the
internal process exits the read state to the state of accepting commands.
CS
SCL
SD
D/C C17 C16 C15 C14 C13 C12 C11 C10 R7 R6 R5 R4 R3 R2 R1 R0 D/C C17 C16 C15 C14 C13
Read Command Input
D/C: A0
Read Data Output
Cn: Command Bit n
Command Input
Rn: Read Data Bit n
___
___
If CS is set HIGH during read data transfer, the read state is cancelled. Setting LOW for CS again brings the
state of accepting commands.
CS
SCL
SD
D/C C17 C16 C15 C14 C13 C12 C11 C10 R7 R6 R5 R4 R3 R2
D/C C17 C16 C15 C14 C13
Read Command Input
D/C: A0
Read Data Output
Cn: Command Bit n
Command Input
Rn: Read Data Bit n
SCL pin should be LOW state, when CS is changed to LOW.
20
EPSON
S1D19105 Series (Rev.1.1)
6. FUNCTIONAL DESCRIPTION
6.1.4 Internal Data Bus Expansion of Display Data
Display data read or written in the parallel MPU interface is expanded to 18-bit internal data bus and RGB data
as shown in the table below.
For display data transfer in 8-bit, 9-bit, 2 +1 6-bit or 16 + 2-bit mode, two accesses are needed for a single dot.
Write operation to the display RAM is executed when the second data has been transferred. Therefore, be sure
to transfer data twice at a time. Otherwise, the data last transferred is not written to the display RAM. The data
count is reset at RAM Write or RAM Read command identification.
Sequence of transfer from external data bus to internal data bus
MPU external bus
D17 D16 D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2
16 bits
ID17 ID16 ID15 ID14 ID13 ID12 ID11 ID10 ID9 ID8 ID7 ID6 ID5 ID4 ID3 ID2 ID1 ID0
RGB
Assignment
R5 R4 R3 R2 R1 R0 G5 G4 G3 G2 G1 G0 B5 B4 B3 B2 B1 B0
Fig.5 Parallel MPU Interface External Data Bus 16 bits
The 1st
The 2nd time
time
MPU external bus
2 + 16 bits
D3 D2 D17 D16 D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2
ID17 ID16 ID15 ID14 ID13 ID12 ID11 ID10 ID9 ID8 ID7 ID6 ID5 ID4 ID3 ID2 ID1 ID0
RGB
Assignment
R5 R4 R3 R2 R1 R0 G5 G4 G3 G2 G1 G0 B5 B4 B3 B2 B1 B0
Fig.6 Parallel MPU Interface External Data Bus 2 + 16 bits
The 2nd
The 1st time
time
MPU external bus
16 + 2 bits
D17 D16 D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D17 D16
ID17 ID16 ID15 ID14 ID13 ID12 ID11 ID10 ID9 ID8 ID7 ID6 ID5 ID4 ID3 ID2 ID1 ID0
RGB
Assignment
R5 R4 R3 R2 R1 R0 G5 G4 G3 G2 G1 G0 B5 B4 B3 B2 B1 B0
Fig.7 Parallel MPU Interface External Data Bus 16 + 2 bits
S1D19105 Series (Rev.1.1)
EPSON
21
6. FUNCTIONAL DESCRIPTION
MPU external bus
D17 D16 D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
18 bits
ID17 ID16 ID15 ID14 ID13 ID12 ID11 ID10 ID9 ID8 ID7 ID6 ID5 ID4 ID3 ID2 ID1 ID0
RGB
Assignment
R5 R4 R3 R2 R1 R0 G5 G4 G3 G2 G1 G0 B5 B4 B3 B2 B1 B0
Fig.8 Parallel MPU Interface External Data Bus 18 bits
1st time
2nd times
MPU external bus
8 bits
D17 D16 D15 D14 D13 D12 D11 D10
D17 D16 D15 D14 D13 D12 D11 D10
ID17 ID16 ID15 ID14 ID13 ID12 ID11 ID10 ID9 ID8 ID7 ID6 ID5 ID4 ID3 ID2 ID1 ID0
RGB
Assignment
R5 R4 R3 R2 R1 R0 G5 G4 G3 G2 G1 G0 B5 B4 B3 B2 B1 B0
Fig.9 Parallel MPU Interface External Data Bus 8 bits
1st time
2nd times
MPU external bus
9 bits
D17 D16 D15 D14 D13 D12 D11 D10 D9 D17 D16 D15 D14 D13 D12 D11 D10 D9
ID17 ID16 ID15 ID14 ID13 ID12 ID11 ID10 ID9 ID8 ID7 ID6 ID5 ID4 ID3 ID2 ID1 ID0
RGB
Assignment
R5 R4 R3 R2 R1 R0 G5 G4 G3 G2 G1 G0 B5 B4 B3 B2 B1 B0
Fig.10 Parallel MPU Interface External Data Bus 9 bits
22
EPSON
S1D19105 Series (Rev.1.1)
6. FUNCTIONAL DESCRIPTION
6.1.5 Access to Display Data RAM and Internal Register via MPU Interface
When data is transferred to or from the MPU, a kind of pipeline operation is performed, generating the internal
pulse for each access. Therefore, access from the MPU does not require the reference clock, providing low power
consumption. Also, an access succeeds if it ends within the cycle time. No weight is required and high-speed
data transfer can be realized.
For example, when the MPU writes data to the display data RAM, the data is temporarily held by the write bus
holder. Then, it is written to the internal RAM with the internal pulse (Write signal) by the time the next Write
Data cycle starts. Also, when the MPU reads display data in the internal RAM, the data is read in the first Read
data cycle (dummy) and is held by the read bus holder with the internal pulse (Read signal), then the data is read
in the system bus from the read bus holder in the next Read data cycle.
A single dummy read is always required after the Read command.
A0
__
WR
N+1
N+2
Write
command
N
DATA
command
N
N+2
N+1
Bus holder
Write signal
Fig.11 MPU Interface Write Operation Example
A0
___
WR
DUMMY read
last data
Data read
n
Data read
n+1
__
RD
Read
command
DATA
Read signal
increment N+1
n
N
N+2
Column address
Bus holder
last data
n+1
n+2
Fig.12 MPU Interface Read Operation Example
S1D19105 Series (Rev.1.1)
EPSON
23
6. FUNCTIONAL DESCRIPTION
6.1.6 VSYNC Interface
The VSYNC is included as the means of smoothly displaying moving pictures while using the MPU interface.
Moving pictures can be smoothly displayed without using the RGB interface.
In the VSYNC interface, the display timing is determined by the built-in oscillation clock and frame
synchronization signal (VSYNCI). If VSYNC is not entered, all the display timings are determined by the
built-in oscillation clock. Once VSYNCI is entered, however, the display timing synchronizes with VSYNCI
and it is set at the head (the first line of the back poaching) of a frame. The RAM address (column address and
row address) is also set to the start address.
To obtain smooth moving pictures on the moving picture display, relationship between the lower limit of the
RAM read speed and built-in oscillation clock must be considered.
To prevent display distortion, the display RAM write operation must be performed at the speed high enough not
to be passed by the relevant line data read operation speed at the display timing. See also section 6.3 Write
Speed to Display Data RAM.
1 frame
Wait
FP FP FP BP BP
1
2
219 220 FP FP FP
FP FP BP BP
1
2
Line number
VSYNCI
External signal 1 frame
Forcefully
synchronized
by the VSYNCI
rising edge.
Internal clock
FP
FP
BP
Line number
VSYNCI
Delay in synchronization =
2H clock
Fig.13 VSYNC Interface Example
24
EPSON
S1D19105 Series (Rev.1.1)
6. FUNCTIONAL DESCRIPTION
6.2 RGB Interface
This IC is provided with the RGB interface best suited to displaying moving pictures, in addition to the MPU
interface used to connect to the MPU. As with the MPU interface, the display RAM write address is a rectangle
area defined by the Set Start Address and Set End Address commands.
Only the display RAM write operation is enabled via the RGB interface Command input, display RAM read or
status read operations are disabled. Command access from the MPU interface can be accepted at any time.
However, those commands accessing the display RAM (RAM Write, RAM Read and Read Modify Write) cannot
be entered. Be sure to perform the operation after access via the RGB interface has been completed.
6.2.1 RGB Interface Selection
The RGB interface bus width can be selected according to the settings of the Set Display Data Interface
command parameter as shown below.
Table 22 RGB Interface Selection
P15
0
0
1
1
P14
0
1
0
1
RGB interface bus width
18-bit, transfer once
16-bit, transfer once
6-bit, transfer three times
Setting disabled
S1D19105 Series (Rev.1.1)
EPSON
25
6. FUNCTIONAL DESCRIPTION
6.2.2 RGB Interface Operation Modes
By setting the RGB interface status using the Set Display Interface command, the best suited interface to the
display status can be used for data transfer to the display RAM.
Table 23 RGB Interface Operation Modes
Display timing
Reference clock
Internal oscillation
Internal oscillation
DOTCLK
ENABLE
D17 to 0
Valid
Valid
Valid
Data transfer mode
DOTCLK
VSYNCI
VSYNCO
HSYNC
RGB transfer 1
RGB transfer 2
RGB transfer 3
Valid
Valid
Valid
Invalid
Valid
Valid
Valid
Valid
Valid
Invalid
Invalid
Valid
RGB transfer 1
To write data to the display RAM, access it using D17 to 0, ENABLE and DOTCLK.
As timing signals necessary for display operation, the signals generated inside the IC are used.
Since vertical synchronization signals generated in the internal timing are output from the VSYNCO,
flicker-free display is achieved by transferring the display data from the RGB interface synchronizing with
these signals.
RGB transfer 2
To write data to the display RAM, access it using D17 to 0, ENABLE and DOTCLK.
As timing signals necessary for display operation, internal signals of the IC are used. These signals are
forcedly synchronized with the frame top by VSYNCI entered externally. Set the RAM address to the start
address. VSINCI must be continuously supplied externally.
VSYNCI must be entered during the period of front poaching (FP).
RGB transfer 3
To write data to the display RAM, access it using D17 to 0, ENABLE and DOTCLK.
As timing signals necessary for display operation, all the external signals are used. VSYNCI, HSYNC and
DOTCLK must be continuously supplied externally. The RAM address is set to the start address by the
VSYNCI input.
If DOTCLK is faster than the clock frequency (1MHz) of the built-in oscillation circuit, it is recommended to set
to the value close to 1MHz by dividing DOTCLK by P2 of the display data interface set. Division is valid only
for the clock used for the display timing (to reduce current consumption). Write clock to RAM is not divided.
To switch from the MPU interface to RGB transfer 3, the following command must be set according to the
display timing externally entered.
Display set (command code: CAh)
P1 and P2 Number of clocks during 1H
It is set as the short number of clocks more than the number
of 1 clocks rather than the cycle of HSYNC.
(Used for calculation of frequency setting of the boosting
clock set at P4. If the cycle changes, set in the shortest
cycle. )
P7
Number of back poaching line (BP) Set the value longer than the timing at which write to RAM
starts.
Display timing set (command code: A1h)
P1 to P4, P6 and P7 Various timings
It is set as the number of clocks of DOTCLK within the
number of clocks of 1H set up by the display set. (When
dividing, the clock after dividing is reference clock.)
26
EPSON
S1D19105 Series (Rev.1.1)
6. FUNCTIONAL DESCRIPTION
ENABLE
(L = Enable 1)
DOTCLK
(Read at rising edge)
Don’t care
Don’t care
D0 to D17
Write to Write to Write to Write to Write to
RAM RAM RAM RAM RAM
Fig.14 Write to RAM (Common to RGB transfer 1 to 3)
Wait
1 frame
FP FP FP BP BP
1
2
219 220 FP FP FP
FP FP BP BP
1
2
Line number
VSYNCI
Forcefully
External signal 1 frame
synchronized
by the VSYNCI
rising edge.
Internal clock
FP
FP
BP
Line number
VSYNCI
Delay in synchronization
= 2H clock
Fig.15 Example of RGB Transfer 2 (VSYNC Synchronization)
74
75
1
2
3
4
5
6
DOTCLK
(Rising edge)
HSYNC
(L=ENABLE)
Fig.16 Example of RGB Transfer 3 HSYNC and DOTCLK timing
S1D19105 Series (Rev.1.1)
EPSON
27
6. FUNCTIONAL DESCRIPTION
Display interface set
Display data interface set
Switch to internal
VSYNC
Switch to external VSYNC
MPU
→
RGB
RGB → MPU
VSYNCO
External VSYNCI
IC internal vertical
synchronization
timing
To switch from RGB transfer
3 to MPU interface, enter at
least one VSYNCI after
command input.
External VSYNC waiting time
Fig.17 Example of Switching Display Timing between RGB Transfer 3 and MPU Interface
Period of overwriting the
moving picture display area
Period of overwriting the
still picture display area
Period of overwriting the
moving picture display
VSYNCI
HSYNC
DOTCLK
ENABLE
D17-0
Data
Data
Don’t Care
Data
Don’t Care
Serial
Interface
RAM write
command
RAM write command
Address set command
MPU data transfer mode
Address set command
RGB transfer 3 mode
Fig.18 Example of Overwriting the Still Picture Display Area
During Moving Picture Display Operations
28
EPSON
S1D19105 Series (Rev.1.1)
6. FUNCTIONAL DESCRIPTION
6.2.3 Internal Data Bus of RGB Interface
Data entered from the RGB interface data pin is read by DOTCLK as display data.
The display data is expanded into the 18-bit internal data bus as shown below. In 6/16-bit mode, set unused pins
to open.
RGB Interface
D17 D16 D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
External Data Bus
18 bits
ID17 ID16 ID15 ID14 ID13 ID12 ID11 ID10 ID9 ID8 ID7 ID6 ID5 ID4 ID3 ID2 ID1 ID0
RGB
R5 R4 R3 R2 R1 R0 G5 G4 G3 G2 G1 G0 B5 B4 B3 B2 B1 B0
Assignment
Fig.19 RGB Interface External Data Bus 18 bits
RGB Interface
External Data Bus
16 bits
D17 D16 D15 D14 D13
D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2
ID17 ID16 ID15 ID14 ID13 ID12 ID11 ID10 ID9 ID8 ID7 ID6 ID5 ID4 ID3 ID2 ID1 ID0
RGB
Assignment
R5 R4 R3 R2 R1 R0 G5 G4 G3 G2 G1 G0 B5 B4 B3 B2 B1 B0
Fig.20 RGB Interface External Data Bus 16 bits
MPU Interface
External Data
Bus 6 bits
1st
2nd
3rd
D17 D16 D15 D14 D13 D12 D17 D16 D15 D14 D13 D12 D17 D16 D15 D14 D13 D12
ID17 ID16 ID15 ID14 ID13 ID12 ID11 ID10 ID9 ID8 ID7 ID6 ID5 ID4 ID3 ID2 ID1 ID0
RGB
Assignment
R5 R4 R3 R2 R1 R0 G5 G4 G3 G2 G1 G0 B5 B4 B3 B2 B1 B0
Fig.21 RGB Interface External Data Bus 6 bits
S1D19105 Series (Rev.1.1)
EPSON
29
6. FUNCTIONAL DESCRIPTION
6.2.4 Access to Display Data RAM via RGB Interface
With the RGB interface, the display data is read and written to the built-in display RAM at the rising edge of
DOTCLK signal. DOTCLK and ENABLE are used for writing to the display RAM. In the 16/18-bit mode, a
single dot is read at a time. In the 6-bit mode, a single dot is read as the display data in three steps, in the order
of R, G and B. By combining with the wind address, display data in a rectangle area can be transferred. The
display RAM data and addresses are updated only while the ENABLE signal is LOW. When using the RGB
interface, scroll display function is available. But it does not recommend using. Because the reading order to
the internal RAM changes writing data is passed to the reading of the internal RAM and the image sometimes
scrambles.
ENABLE
DOTCLK
D17-0
N-1
N+1
N+2
N
Latched data
N-1
N
N+1
N+2
Write signal
HSYNC
DOTCLK
ENABLE
D17-0
Front Poaching
VSYNCI
HSYNC
ENABLE
Back poaching
Fig.22 Example of Writing Data into Display Data RAM
When using the RGB interface, back poaching starts after 2H from the falling edge of VSYNCI, and then display
operation is performed. After the display operation, front poaching is performed. Front poaching can be set to 1
to 4096. Back poaching can be set to 1 to 256.
In case of VSINCI is Low enable; raising edge sets RAM address. In case of VSINCI is High enable; falling
edge sets RAM address. Then RAM writing should start after it.
30
EPSON
S1D19105 Series (Rev.1.1)
6. FUNCTIONAL DESCRIPTION
Back poaching
Still picture display area
Moving picture
display area
Front poaching
HSYNC
DOTCLK
ENABLE
Fig.23 Moving Picture and Still Display Area
S1D19105 Series (Rev.1.1)
EPSON
31
6. FUNCTIONAL DESCRIPTION
6.3 Write Speed to Display Data RAM
In moving picture display via VSYNC interface, RGB transfer 1 or RGB transfer 2, the display RAM write
operation must be performed at a speed not to be caught up by the line data read operation speed at display timing
to prevent display distortion. When the back poaching is not specified, even if the RAM write operation is
performed at a high speed, it is caught up with by the display timing in the first line. Specify back poaching of
2 lines or more. Please pay attention because the following calculation is not able to apply in the case that the
scrolling function is used.
Example when passing of the display timing does not take place
RAM write
start
Back poaching
Display area
Line 220
Line 1
Line 110
RAM write
Display timing
Period of display
Period of back poaching
Fig.24 Write Speed to Display Data RAM
The display data must be written to RAM at the speed faster than that calculated from the relational expression
shown below.
Number of clocks in 1H =
(1 /((Number of display lines + back poaching + front poaching) × Number of frame
frequency / Oscillation frequency)
176 × Number of display lines
Minimum RAM
>
(Number of display lines + Back poaching) × Number of clocks in 1H
write speed
× 0.9 s - Start time of write operation from VSYNCO or VSYNCI
µ
An example of setting the RAM write speed based on the above relation expression is given below.
Number of display lines: 220 lines
Back poaching: 15 lines
Front poaching: 4 lines
Number of data in 1H: 176 (when using 16/18-bit bus)
Start time of write operation from VSYNCO or VSYNCI: 20µs
Oscillation frequency: 1MHz 10% (oscillation frequency 1µs 10%)
Frame frequency: 60Hz
Number of clocks in 1H =
(1 / ((220 +15 + 4) × 60Hz)) / 1µs = 69.7 So, it makes 70 clocks.
To make RAM write completion time < Display read completion time true.
176 × 220
Write speed
>
( 220 + 15 ) × 70 × 0.9µs - 20µs
2.62MHz
Therefore, for write operation at 2.62MHz or over, screen distortion can be eliminated.
32
EPSON
S1D19105 Series (Rev.1.1)
6. FUNCTIONAL DESCRIPTION
Oscillation frequency
+10% -10%
2.62MHz
RAM write speed
TBDMHz
Line220
Normal range of RAM write
TBDms
18.33ms
Back poaching
15.0ms
Fig.25 Write Speed to Display Data RAM
Start the writing to RAM after a back porch period start. Cautions, a start address is reset at the time of a front
porch and a back porch change.
S1D19105 Series (Rev.1.1)
EPSON
33
6. FUNCTIONAL DESCRIPTION
6.4 Display Data RAM
6.4.1 Display Data RAM
RAM that stores dot data for display. One dot consists of three dots (R, G and B), and one dot holds 6-bit
display data. 18 bits of the internal data bus correspond to R dots (R5, R4, R3, R2, R1 and R0), G dots (G5, G4,
G3, G2, G1 and G0) and B dots (B5, B4, B3, B2, B1 and B0). Maximum display size is 176 × 220 dots and the
RAM capacity is 696,960 bits (176 × 220 × 18). Correspondence between display data and gray scale are shown.
(000000): Gray scale 0 (0%, black) Normally white liquid crystal VCOM = LOW
(000001): Gray scale 1
:
(111110): Gray scale 62
(111111): Gray scale 63 (100%, RGB)
Table 24 Display Data Memory Map
Row Address
Dot
Line
Normal Reverse
R
R5
to
G
G5
to
B
B5
to
R
G
B
R
G
B
Address
0
1
219
218
0
1
R0
G0
B0
218
219
1
0
218
219
Column Normal
Address
0
175
1
174
175
0
Reverse
S1
S2
S3
S4
S5
S6
S526 S527 S528
The MPU and RGB interfaces access the display RAM in the unit of one dot. To the source output, at the
internal display timing independent of the MPU or RGB interface, display data read for each line specified with
line address for line cycle is sent.
Normal or reverse setup of row and column addresses are specified with the Set Data command parameters.
6.4.2 Source Line Drive Output Pins and RAM Data
The output destination of R, G and B dot data of display data RAM can be switched by the Set Data command
according to the LCD color filter layout.
Table 25 Source Line Drive Output Pins and RAM Data
Output pin
Normal
Reverse
S1
R
B
S2
G
G
S3
B
R
S4
R
B
S5
G
G
S6
B
R
ꢁꢁꢁ
ꢁꢁꢁ
ꢁꢁꢁ
S528
B
R
34
EPSON
S1D19105 Series (Rev.1.1)
6. FUNCTIONAL DESCRIPTION
6.4.3 Row Address Circuit/Column Address Circuit
An access area of the RAM is defined by a rectangle having the vertex identified by the start address and end
address. Assume that the start address has column address C1 and row address R1, and that the end address has
start address C2 and row address R2. The display data is written in address (C1, R1) and subsequent addresses,
and if the address is in the column direction, the column address is incremented by +1 automatically for each
Write or Read pulse. After the data has been written in column address C2, the row address is incremented by
+1 and the column address is returned to C1. After the end address of (C2, R2) has been written, it is returned
to the start address.
During the RAM access via the MPU interface, when a RAM Write command or RAM Read command is entered,
the column and row addresses are set to the start address automatically.
During the RAM access via the RGB interface, the column and row addresses are set to the start address
automatically at the beginning of the frame (VSYNC timing).
The address direction of a column or a row address and the address scan direction can be inverted by Set Data
command.
Table 26 Row /Column Display Sequence
Address
P10=0 Row address normal
P10=1 Row address reverse
transition
Display
start
position
C1,R1
P11=0
Column address
normal
P11=1
Column address
reverse
P11=0
Column address
normal
P11=1
Column address
reverse
Display
end
position
C2,R2
Line
Line
Line
Line
C1,R1
Addr
Addr
Addr
Addr
0
0
0
0
ꢁ
ꢁ
ꢁ
ꢁ
ꢁ
ꢁ
ꢁ
ꢁ
ꢁ
ꢁ
ꢁ
ꢁ
ꢁ
ꢁ
ꢁ
ꢁ
P13=0
Scan
direction
right and
left
ꢁ
ꢁ
ꢁ
ꢁ
C2,R2
219
219
219
219
S1ꢁ ꢁ ꢁ ꢁ ꢁ S528
S1ꢁ ꢁ ꢁ ꢁ ꢁ S528
S1ꢁ ꢁ ꢁ ꢁ ꢁ S528
S1ꢁ ꢁ ꢁ ꢁ ꢁ S528
Line
Line
Line
Addr
Addr
Addr
C2,R2
0
0
0
Line
ꢁ
ꢁ
ꢁ
Addr
ꢁ
ꢁ
ꢁ
ꢁ
ꢁ
ꢁ
ꢁ
ꢁ
ꢁ
0
P13=1
Scan direction
up and down
ꢁ
ꢁ
ꢁ
ꢁ
ꢁ
C1,R1
ꢁ
ꢁ
ꢁ
219
219
219
S1ꢁ ꢁ ꢁ ꢁ ꢁ S528
S1ꢁ ꢁ ꢁ ꢁ ꢁ S528
S1ꢁ ꢁ ꢁ ꢁ ꢁ S528
219
S1ꢁ ꢁ ꢁ ꢁ ꢁ S528
S1D19105 Series (Rev.1.1)
EPSON
35
6. FUNCTIONAL DESCRIPTION
6.4.4 Area Scrolling
The RAM can be divided into a maximum of three sections in the row direction and the fixed display and
scrolling areas can be created.
Center area scrolling
P1
Top area scrolling
Bottom area scrolling
P1
Entire screen scrolling
P1
0
P1
P2
P3
P3
P2
*
1
P2
P2
*
1
P1: Line start address to be assigned to the scroll area
P2: Line end address to be assigned to the scroll area
P3: Number of line to the bottom fixed area.
: Fix area
*
1: Number of display lines (P4 of the Set Display Command)
: Scroll area
Fig. 26 Area Scrolling
Concept of area scrolling display
Updating the display start line in a certain cycle can scroll the screen.
Fig.27 Concept of Area Scrolling Display
36
EPSON
S1D19105 Series (Rev.1.1)
6. FUNCTIONAL DESCRIPTION
6.4.5 Partial Display
When the RAM display area is specified by the Partial Display In command, partial display areas consisting of
any number of lines can be created in any position of the LCD screen. The source line drive waveforms of the
RAM data appear within the partial display area, while minimum voltage level (V , V63) output against the VCOM
0
signal or power supply voltage of VDDHS/VSS in the non-display area. In the non-display area, power
consumption can be reduced in proportion to the number of non-display lines to stop circuits that generates gray
scale voltage. By specifying the 8-color mode, power consumption can also be reduced. By selecting the
refresh rate of a non-display area the further low power is possible. It is possible to set the power supply control
of the term that does not do the refreshing of a non-display area in detail with a partial power control. By
setting an display area to 8 color modes and the reduction of the consumption power be possible.
Partial Display In
n frame
1 frame
Command input
VSYNCO
Non-display area
Non-display area
Non-display area
Source output
V
P63
V
N63
VN63
V
COM
Frame reverse drive example
Outputs the display area data.
Outputs the voltage of the non-display area color
Fig.28 Partial Display (refresh rate 1/1)
The driving method of front poaching period(FP) and back poaching period(BP) during partial display are as
follows. The front poaching becomes being the same as that of a non-displaying area. The back poaching
becomes being the same as that of display area.
S1D19105 Series (Rev.1.1)
EPSON
37
6. FUNCTIONAL DESCRIPTION
6.4.6 AC Operation Drive
With this IC, the following AC operation modes can be used.
(1) Frame reverse driving: Reverses the AC operation signals once for each frame.
(2) n-line reverse driving: Reverses the AC operation signals for every 1 to 16-line frame display.
(3) Interlace drive: Reverses the AC operation signals three times for each frame with 3-line interlace drive.
Display line
Frame
reverse
driving
1 frame
1 frame
Display line
n-line
reverse
driving
n=5
1 frame
1 frame
Display line
Interlace
drive
1 frame
Fig.30 AC Operation Drive
38
EPSON
S1D19105 Series (Rev.1.1)
6. FUNCTIONAL DESCRIPTION
6.5 Oscillation Circuit
This is a fully built-in CR-type oscillator to generate display clocks. The oscillation starts when the sleep state
is canceled by the Sleep Out command. The oscillation stops when the sleep state is set by the Sleep In
command.
When it is set by the Set Data command P17 that the built-in oscillator is not used, the oscillation circuit does not
function. In such a case, the OSCI pin functions as the input pin of external clocks.
S1D19105 Series (Rev.1.1)
EPSON
39
6. FUNCTIONAL DESCRIPTION
6.6 Setting Gate Line Scan Mode
You can select two-side driving or two-side up and down driving.
The drive mode is specified with the Set Gate Line Scan Mode command parameter. Set the gate driver scan
start and end lines. There is a gate line of a maximum of 220 lines. And the gate line of 110 lines is in right and
left. When using it by less than 220 lines, it assigns equally (right and left of the number of use lines) from G110
pin G111 pin most located in the middle. The number of lines on either side is surely made the same.
The value set up in Gate Line scan mode set is the output signal of a gate driver, and is the gate line number
which begins from G1. The gate line number at the very end of the use line continuously assigned from G110
pin G111 pin is set up. Please take care that this is not a line address. And the number of display set of
P5(number of dots) and the number of use lines need to be completely in agreement.
Setting example:
Conditions is P5 of display set (number of dots) = 208 line
The number of use lines of one side =208/2=104 lines
Scanning start line number =111-104=7
Scanning end line number =110+104=214
Regardless of interlace driving and Two-side up and down driving 1/2, it becomes like the above-mentioned
example of calculation.
Two-side interlace driving 1
TFT panel
Two-side interlace driving 2
TFT panel
S1D19105
S1D19105
Scan order
Normal direction
Reverse direction
G1
G111
→
→
G220
G110
→
→
G2
→
G219→ ꢁ ꢁ ꢁ →G110
→
G111
G112
→
G109→ ꢁ ꢁ ꢁ →G220
→
G1
220-line display example: Start line = 1, end line = 220
Scan order
G12 G209→ ꢁ ꢁ ꢁ G110
G112
Normal direction
Reverse direction
G11
G111
→
→
G210
G110
→
→
→
→
→
G111
G11
G109→ ꢁ ꢁ ꢁ G210
→
200-line display example: Start line = 11, end line = 210
40
EPSON
S1D19105 Series (Rev.1.1)
6. FUNCTIONAL DESCRIPTION
Two-side up and down driving 1
TFT panel
Two-side up and down driving 1
TFT panel
S1D19105
S1D19105
Scan order
Normal direction
Reverse direction
G1
G111
→
G110
→
G220
→
→
G111
G1
→
G220
→
G110
220-line display example: Start line = 1, end line = 220
Scan order
G110 G210
G210 G110
Normal direction
Reverse direction
G11
G111
→
→
→
→
→
→
G111
G11
200-line display example: Start line = 11, end line = 210
Two-side up and down driving 2
TFT panel
Two-side up and down driving 2
TFT panel
S1D19105
S1D19105
Scan order
Normal direction
Reverse direction
G220
G110
→
G111
→
G1
→
G220
G110
→
G1
→
G111
→
220-line display example: Start line = 1, end line = 220
Scan order
G111 G11
G11 G111→
Normal direction
Reverse direction
G210
G110
→
→
→
→
→
G210
G110
200-line display example: Start line = 11, end line = 210
Fig.31 Gate Line Scan Mode
S1D19105 Series (Rev.1.1)
EPSON
41
6. FUNCTIONAL DESCRIPTION
6.7 How to Connect to the External Power Supply
Case (1) Two power supplies (2.3V or more)
(Example AVDD = 2.8V, DVDD = 2.75V)
TEST3=H TEST4=L (VCORE is normally OFF) : This connection should be used basically.
V
V
DD2
DD
2.8V
2.75V
V
DDI
V
CORE
TEST3=L TEST4=H (VCORE is normally ON)
V
V
DD2
DD
2.8V
2.75V
V
DDI
V
CORE
V
SS
TEST3=L TEST4=L (VCORE automatic stop, automatic start)
V
V
DD2
DD
2.8V
2.75V
V
DDI
V
CORE
V
SS
Fig.32 How to Connect to the External Power Supply Case (1)
42
EPSON
S1D19105 Series (Rev.1.1)
6. FUNCTIONAL DESCRIPTION
Case (2) Two power supplies (One power supply is 1.65 to 2.3V.)
(Example AVDD = 2.8V, DVDD = 1.8V)
TEST3=H TEST4=L (VCORE is normally OFF) : This connection should be used basically.
V
V
DD2
DD
2.8V
1.8V
V
DDI
V
CORE
TEST3=L TEST4=H (VCORE is normally ON)
V
V
DD2
DD
2.8V
1.8V
V
DDI
V
CORE
V
SS
TEST3=L TEST4=L (VCORE automatic stop, automatic start)
V
V
DD2
DD
2.8V
1.8V
V
DDI
V
CORE
V
SS
Fig.33 How to Connect to the External Power Supply Case (2)
S1D19105 Series (Rev.1.1)
EPSON
43
6. FUNCTIONAL DESCRIPTION
Case (3) One power supply (2.3V or more is required)
(Example AVDD = 2.8V)
TEST3=H TEST4=L (VCORE is normally OFF) : This connection should be used basically.
V
V
DD2
DD
2.8V
V
DDI
V
CORE
TEST3=L TEST4=H (VCORE is normally ON)
V
V
DD2
DD
2.8V
V
DDI
V
CORE
V
SS
TEST3=L TEST4=L (VCORE automatic stop, automatic start)
V
V
DD2
DD
2.8V
V
DDI
V
CORE
V
SS
Fig.34 How to Connect to the External Power Supply Case (3)
44
EPSON
S1D19105 Series (Rev.1.1)
6. FUNCTIONAL DESCRIPTION
6.8 Description of Operation of Built-in Power Supply
All bias voltages required for liquid crystal drive can be generated by single power input. The following voltage
levels are generated.
Power supply for oscillation circuit: VOSC
Reference power supply for 1st-boosting: VLDO (It is not used and VDD2 is used usually)
Power supply: VOUT,RVEG
Reference voltage: V
Source driver voltage: VODUDTHMS, VDDRH, VDDRL and V
to V63
0
Voltage for opposed elDecDtHroGde:EVECOMH and VCOML
Gate driver voltage: V
, V , VONREG and VOFREG
The built-in electronic control function allows adjustment of each output voltage. The electronic control can be
controlled by commands. The built-in reference voltage circuit permits continuously stable LCD power supply
without depending on the system power supply. Built-in 1st, 2nd, 3rd, and 4th boosters provide high-precision
constant voltage.
V
DDHG
DDHG
V
(Note 1) [1st booster circuit]
DD2
V
OUT
V =
Max.6.2V
LDO
V
=2.5 to 3V
DDHS
V
=2.7 to 5.8V
=3.5V
× 2
V
DC3 (Note 3)
REG
COMH
V
V
DC1
V
V
DD
V
DC2 (Note 2)
V
DC5
DDRH
OFREG
V
ONREG
V
V
V
=2.7 to 5.8V
DDRL
=0 to 1.55V
V
CORE=2.5V
OSC=1.5V
(Note 5)
=2.5 to 5.1V
=0 to 6.2V
V
DC4
V
SS
COML
V
V
=0V
(Note 4)
× -1 to -3
× -1 to -3
OUTM
V
× 2
[2nd booster circuit]
Note 1: VDC1 is connected to VDD2 or VLDO
DC2 OUT DD2
.
.
V
EE
EE
×
V
=-18.6 to –10( -3)
Note 2: V
Note 3: VDC3 is connected to VOFREG or VOUT or VDD2
DC4 DD2 ONREG OUTDM
.
is connected to V
or V
.
[3rd booster circuit]
[4th booster circuit]
Note 4: V
Note 5: VDC5 is connected to VSS or VDD2 or VONREG or VOUTDM.
Note 6: Please use it not to exceed recommended operation conditions.
is connected to V
or V
or V
Fig.35 Voltage Relational Diagram
S1D19105 Series (Rev.1.1)
EPSON
45
6. FUNCTIONAL DESCRIPTION
6.9 Power Supply for LCD and Main Specifications for Power Supply
Table 27 S1D19105 Power Supply for LCD and Main Specifications for Power Supply
No.
1
2
Parameter
Number of source lines for TFT panel
Number of gate lines for TFT panel
Structure of TFT panel holding capacity
S1-S528
S1D19105
528 (176 RGB)
220
Cst structure
3
V0 to V63 (analog 64 gray scale)
G1-G220
Gate ON voltage: VDDHG
Gate OFF voltage: VEE
V
COM
Common HIGH voltage VCOMH
Adjustment with the electronic control or
external R
4
5
LCD output
Common LOW voltage VCOML
Automatic setting with VCOMH - VCA
× 2
Common amplitude: VCA
electronic control
× 2 Adjustment with
V
V
DDI
IO power supply
Input power supply
DD
Power supply for VCORE generation
Reference power supply for booster circuit
Reference power supply for 1st boosting
RAM and logic power supply.
V
DD2
V
LDO
V
CORE
V
V
OSC
OUT
Power supply for oscillation
Power supply for source and VCOM generation
VDD2 × double:
(1st booster
output)
V
REG
Reference voltage
V
DDHS
Source driver power supply
Maximum gray scale voltage
Minimum gray scale voltage
V
DDRH
V
DDRL
COMH
OFREG
ONREG
OUTM
V
VCOM signal HIGH power supply
Internal power
supply output
V
Reference voltage for VEE generation
Reference voltage for VDDHG generation
Power supply for VCOML generation
-1 time boosting
6
V
V
(2nd booster
output)
V
COML
VCOM signal LOW power supply
V
EE
Gate OFF voltage
-1 to 3 times boosting
(3rd booster
output)
V
DDHG
Gate ON voltage
Double boosting
(4th booster
output)
46
EPSON
S1D19105 Series (Rev.1.1)
6. FUNCTIONAL DESCRIPTION
6.9.1 Basic Configuration Diagram of Built-in Power Supply
The S1D19105 contains a power supply circuit for liquid crystal drive. Select the external circuit configuration
appropriate for your specifications by referring to the recommended basic circuits provided for stable use of
built-in power circuit.
V
0
V
OUT
DC1
V0 regulator
V
V
V
63 regulator
V
LDO
VDDRH
DDRH regulator
V
DDRL
DDHS
V
DDRL regulator
C11N
C11P
1st booster
circuit
V
ꢁ
V
V
DDHS regulator
ONREG regulator
V
ONREG
OFREG
V
DC2
V
V
OFREG regulator
V
SWIN
COM
V
OUT
V
C21P
C21N
2nd booster
circuit
ꢂ
V
OUTM
DC3
V
COM
ꢅ
V
REG
generation
circuit
V
V
COMH
V
OUT
FBH
V
COMH2
C31P
C31N
C33N
V
COML
3rd booster
circuit
V
CORE
ꢃ
V
V
CORE regulator
OSC regulator
C32P
V
OSC
LDO
V
EE
V
V
LDO regulator
V
DC4
V
DC5
V
ONREG
Power control
circuit
(register,
timer, etc.)
V
V
V
DD2
C41P
C41N
DD
SS
4th booster circuit
ꢄ
V
DDHG
Fig. 36 Basic Configuration Diagram of Built-in Power Circuits
S1D19105 Series (Rev.1.1)
EPSON
47
6. FUNCTIONAL DESCRIPTION
6.9.2 The 1st Booster Circuit
The 1st booster circuit, comprised of a charge pump type DC/DC converter, can be selected by external
connection switching of the boost reference power supply. The booster converts the selected input power
voltage (VDC1) to the power supply for the liquid crystal power circuit (VOUT) by doubling the voltage.
V
OUT = 2 × VDC1 [V]
The desired booster circuit is provided by changing the connection corresponding to 1 in the basic configuration
diagram of the internal power circuit.
V
V
V
DC1
DD2
LDO
V
OUT
V
OUT
DD2=VDC1
SS
V
C11N
V
SS
V
C11P
Double boosting (VDC1 = VDD2
)
V
V
V
DC1
DD2
LDO
OUT
V
V
OUT
LDO=VDC1
SS
V
C11N
V
SS
V
C11P
Double boosting (VDC1 = VLDO
)
Fig.37 The 1st Booster Circuit (Connection Example)
DDCC11should be selected VDD2 usually.
[V
Select Voltage]
V
48
EPSON
S1D19105 Series (Rev.1.1)
6. FUNCTIONAL DESCRIPTION
6.9.3 The 2nd Booster Circuit
The 2nd booster circuit, comprised of a charge pump type DC/DC converter, is a reverse booster circuit that can
be selected by external connection switching of the boost reference power supply. The booster converts the
multiplying the voltage by -1 time with refDeCre2nce to VSS
.
selected input power voltage (between V
and VSS) to the power voltage (VOUTM) for the VCOM circuit by
V
OUTM
=
-1 × VDC2 [V]
The desired circuit is provided by changing the connection corresponding to 2 in the basic configuration
diagram of the internal power circuit as shown below.
V
DC2
V
DC2
V
OUT=VDC2
V
DD2
V
DD2
V
V
V
DD2=VDC2
SS
V
OUT
V
OUT
V
V
SS
V
SS
VSS
C21P
C21N
OUTM
C21P
C21N
V
OUTM
V
OUTM
OUTM
Reverse boosting (VDC2 = VOUT
)
Reverse boosting (VDC2 = VDD2
)
Fig.38 The 2nd Booster Circuit (Connection Example)
[VDC2 Select Voltage]
For VDC2, VDD2 or VOUT can be freely selected.
S1D19105 Series (Rev.1.1)
EPSON
49
6. FUNCTIONAL DESCRIPTION
6.9.4 The 3rd Booster Circuit
The 3rd booster circuit, comprised of a charge pump type DC/DC converter, can be selected by external
connection switching of the boost reference power supply. The booster converts the selected input power
voltage (between VDC3 and VSS) to the gate driver negative power voltage (VEE) by -N times. Boosting by the
magnifying power of -1, -2 and -3 is available through external connection.
V
EE = N × VDC3 [V] : [N = -1, -2, -3]
The desired circuit is provided by changing the connection corresponding to 3 in the basic configuration
diagram of the internal power circuit as shown below.
V
DC3
DD2
OUTDM
OFREG
V
DC3
DD2
OUTDM
OFREG
V
V
V
V
V
V
V
OUTDM=VDC3
V
OFREG=VDC3
C31P
C31P
C31N
C31N
V
SS
VSS
C33N
C32P
C33N
C32P
V
EE
C32N
C32N
V
EE
V
EE
VEE
V
SS
VSS
- 1 time boosting (VDC3 = VOFREG
)
-2 boosting (VDC3 = VOUT)
V
DC3
DD2
OUTDM
OFFREG
V
V
It is also possible to connect VOUT instead of
VOUTDM. Because of VOUTDM and VOUT are
connected inside IC.
V
V
OFREG=VDC3
C31P
C31N
V
SS
C33N
C32P
C32N
V
EE
V
EE
V
SS
-3 boosting (VDC3 = VOFRE, only)
Fig.39 The 3rd Booster Circuit (Connection Example)
[VDC3 Select Voltage]
For V , select V , V
and V
so that VDDHG - VEE ≤ 30.0V can be satisfied in any magnifying
powerDoCf3 boosting.DD2–3 tOimUeTsDMboostingOFshRoEGuld be set
V
DC3 = VOFRE. Setting to V
= V
allows fine
adjustment of the VEE output voltage using the built-in regulator. The variable rangeOoFfRvEoGltage iDsCa3s follows.
V
OFREG output pin
2.0 to 5.1[V] (0.1 V step)
Built-in regulator output
50
EPSON
S1D19105 Series (Rev.1.1)
6. FUNCTIONAL DESCRIPTION
6.9.5 The 4th Booster Circuit
The 4th booster circuit, comprised of a charge pump type DC/DC converter, is a reverse booster circuit that can
be selected by external connection switching of the boost reference power supply. The booster converts the
selected input power voltage (between VDC4 and VEE) to the gate driver positive power voltage (VDDHG) by 1
time with reference to VDC5
.
V
DDHG = VDC5 + 1 × (VDC4-VEE) [V]
The desired circuit is provided by changing the connection corresponding to 4 in the basic configuration
diagram of the internal power circuit as shown below.
V
DC5
SS
V
V
DC5
SS
V
V
OUT
V
OUT
V
DDHG
V
ONREG
V
ONREG
V
DDHG
V
V
DD2
DC4
V
V
DD2
DC4
V
DC4 =VOUT
V
DC4 =VDD2
DC5=VSS
C41P
C41P
V
VDC5=VSS
C41N
C41N
V
DDHG
V
DDHG
V
EE
V
EE
V
Reverse boosting (VDC4 = VDD2), (VDC5 = VSS
)
Reverse boosting (VDC4 = VOUT), (VDC5 = VSS)
V
V
DC5
SS
V
V
DC5
SS
V
OUT
V
OUT
V
V
V
C41P
ONREG
VONREG
V
DDHG
V
DDHG
DD2
DC4
V
V
DD2
DC4
V
V
DC4=VONREG
DC5 =VSS
C41P
V
DC5 =VONREG
DC4=VONREG
V
V
C41N
V
C41N
SS
DDHG
V
DDHG
V
EE
V
EE
Reverse boosting (VDC4, VDC5 = VONREG
)
Reverse boosting (VDC4 = VONREG), (VDC5 = VSS
)
Fig.40 The 4th Booster Circuit (Connection Example)
S1D19105 Series (Rev.1.1)
EPSON
51
6. FUNCTIONAL DESCRIPTION
[VDC4 Select Voltage]
For VDC4, VDD2, VSS ,VONREG and VOUT can be freely selected. In doing so, select the voltage to satisfy
V
DDHG - VEE ≤ 30.0V. Using VONREG allows fine adjustment of the VDDHG voltage using the built-in regulator.
VDC4 pin should connect more than 2.3V. When VDC4 pin needs to be used less than 2.3V, please connect with
VONREG, set up VONREG more than 2.3V only at the time of boosting starting, and put in the processing
adjusted to the target voltage by the electronic volume command or the power control command after the 4th
boosting starting.
[VDC5 Select Voltage]
For VDC5, VDD2, VSS ,VONREG and VOUT can be freely selected. In doing so, select the voltage to satisfy
The variablEeErange of the voltage OisNaRsEfGollows.
V
DDHG - V ≤ 30.0V. Using V
allows fine adjustment of the VDDHG voltage using the built-in regulator.
V
ONREG output pin
0.0 to 6.2[V] (0.2 V step)
Built-in regulator output
52
EPSON
S1D19105 Series (Rev.1.1)
6. FUNCTIONAL DESCRIPTION
6.9.6 VCOM Generation Circuit
The VCOM generation circuit generates the voltage of VCOMH and VCOML needed for generating VCOM output
voltage. Setting of each voltage can be combined as follows.
V
V
COMH: Electronic control register setting using the built-in resistor
Adjustment of output voltage through external resistor
COML: VCOML = VCOMH - VCA × 2 [V]
V
V
COMH
REG
V
V
COMH
REG
FBH
FBH
V
COMH2
V
COMH2
V
COML
V
COML
V
SS
VSS
External resistor for adjusting VCOMH
Use of built-in resistor for adjusting VCOMH
Fig.41 VCOM Generation Circuit (Connection Example)
V
COMH output pin
2.0 to 5.975[V] (0.075 V step)
Built-in regulator output
S1D19105 Series (Rev.1.1)
EPSON
53
6. FUNCTIONAL DESCRIPTION
6.10 Connection Diagram of External Parts
External Circuit Connection Example 1
Specifications: 1st booster circuit [VDC1 select = VDD2
]
3rd booster circuit [V DC2select = V DD2, -double boosting mode]
2nd booster circuit [V
select = V
]
4th booster circuit [VDC3 select = VDODU2T, V
select = VSS]
V
COM generation circDuCit4[Specifications foDr Ce5xternal resistor for adjusting VCOMH
]
Example) Assuming that VDD2 = 2,85V, each voltage with no load is as follows.
= 2 × VDD2
=
=
=
=
5.7[V]
-2.85[V]
-11.4[V]
14.25[V]
VOUT
V
= -1 × V
VOUTM
= -2 × VODUD2T
VDEEDHG
= VDC5 + 1 × (VDC4 - VEE)
CB16
CB17
V
V
0
VOUT
V
0
regulator
63 regulator
DDRH regulator
DDRL regulator
CB1
63
VDC1
VLDO
V
VDD2
CB5
CB6
CB7
V
DDRH
V
V
DDRL
V
C11N
CP1
1st booster
C11P
VDDHS
circuit
V
DDHS regulator
VONREG
VONREG regulator
V
DC2
V
OFREG
V
DD2
VOFREG regulator
VOUT
CP2
CB2
C21P
C21N
2nd booster
circuit
VOUTM
V
COM generation
circuit
V
DC3
CB11
CB13
V
V
COMH
REG
VOUTDM
VOFREG
RB1
FBH
CB18
RA1
V
COMH2
C31P
C31N
C33N
CP3_1
CP3_2
CB12
V
COML
3rd booster
circuit
CB14
VCORE
C32P
C32N
V
CORE regulator
OSC regulator
V
OSC
V
V
EE
VLDO
CB3
VDD2
V
LDO regulator
VDC4
Power supply
control circuit
(register, timer,
etc.)
VDC5
V
SS
C41P
C41N
CP4
VDD2
4th booster circuit
VDD
VSS
V
DDHG
CB4
Fig.42 External Circuit Connection Example 1
54
EPSON
S1D19105 Series (Rev.1.1)
6. FUNCTIONAL DESCRIPTION
External Circuit Connection Example 2
Specifications: 1st booster circuit [VDC1 select = VLDO
]
3rd booster circuit [V DC2select = V OUT , -triple boosting mode]
2nd booster circuit [V
select = V
]
4th booster circuit [VDDCC34 select = VOFREG
VDC5 select = VSS]
V
COM generation circuit [SpecificatiOoNnsREfoGr, built-in resistor for adjusting VCOMH
]
Example) Assuming that VDD2 = 2.85V, each voltage with no load is as follows.
= 2.55V(Typ.)
= 4.0V
[Regulator output]
VLDO
V
[Regulator output (Electronic control setting)]
[Regulator output (Electronic control setting)]
VOFREG
= 3.0V
VONREG = 2 × VLDO
=
=
5.1[V]
VOUT
= -1 × V
-5.1[V]
VOUTM
VDEEDHG
= -3 × VOOUFRTEG
= -12.0[V]
= VONREG - VEE
=
15.0[V]
CB16
CB17
V0
VOUT
CB1
V0 regulator
V
63
VDC1
VLDO
V63 regulator
CB5
CB6
CB7
V
DDRH
V
DDRH regulator
VDDRL
V
DDRL regulator
C11N
CP1
1st booster
C11P
V
DDHS
circuit
VDDHS regulator
V
ONREG
CB8
CB9
V
ONREG regulator
V
DC2
V
OFREG
V
OFREG regulator
VOUT
C21P
C21N
CP2
CB2
2nd booster
circuit
V
OUTM
V
COM generation
CB13
VREG
VDC3
circuit
CB11
CB18
VOUTDM
VCOMH
FBH
V
OFREG
CP3_1
C31P
C31N
C33N
V
COMH2
CB12
CB14
V
COML
3rd booster
circuit
CP3_3
CP3_2
VCORE
C32P
C32N
V
CORE regulator
OSC regulator
V
OSC
V
CB15
V
EE
VLDO
CB3
V
LDO regulator
VDC4
V
ONREG
VDC5
Power supply
control circuit
(register, timer,
etc.)
VSS
C41P
C41N
CP4
V
DD2
4th booster circuit
VDD
CB4
VDDHG
V
SS
Fig.43 External Circuit Connection Example 2
S1D19105 Series (Rev.1.1)
EPSON
55
6. FUNCTIONAL DESCRIPTION
Table 28 Recommended Capacity Value
Capacitor Capacity value Maximum value of voltage biased to both
Circuit name
name
CP1
[µF]
1.0 to 2.2
1.0 to 2.2
1.0 to 2.2
1.0 to 2.2
1.0
ends of the capacitor
1st booster output
V
V
V
V
V
V
V
V
V
V
DD2, VLDO
CB1
CP2
CB2
CP3_1
CP3_2
CP3_3
CB3
CP4
CB4
CB18
CB11
CB12
CB13
CB5
CB6
CB7
CB8
CB9
DD2 2, VLDO×2
×
2nd booster output
3rd booster output
DD2, VOUT
DD2, VOUT
DD2, VOUT, VOFREG
1.0
1.0
1.0
DD2
OFREG
DD2
DC4 - VEE
DC5 + (VDC4 - VEE
×2, VOUT
×
2, VOFREG
×
2
3
×3
×2, VOUT
×2, VOFREG
×
4th booster output
0.1 to 1.0
0.1 to 1.0
0.01 to 0.1
1.0 to 2.2
1.0 to 2.2
0.1 to 1.0
1.0
)
V
COM generation circuit
FBH
V
V
V
V
V
V
V
V
V
V
V
V
COMH
COML
REG
Regulator
DDRH
DDRL
DDHS
ONREG
OFREG
CORE
LDO
0.1
1.0 to 2.2
0.1 to 1.0
0.1 to 1.0
1.0 to 2.2
1.0 to 2.2
0.1
Power supply
Gray scale
CB14
CB15
CB16
CB17
0
0.1
63
The maximum voltage can be set when using the built-in electronic control if VREG = 3.5V.
include variations.
VREG does not
The capacity of the capacitor is the recommended value. When selecting a capacitor, check the appearance
quality of indication with the actual equipment and set to the capacity value that makes the voltage of liquid
crystal drive stable.
Use the B characteristics for capacitor.
A tolerance voltage should be selected aiming at 70% of the standard.
56
EPSON
S1D19105 Series (Rev.1.1)
6. FUNCTIONAL DESCRIPTION
Table 30 Recommended Value for Wiring Resistor when Installing COG
Pin type
Pin name, etc.
Pin number
40, 41, 136 to 139
42 to 45, 128 to 135
36 to 39, 140 to 147
148 to 163
Resistor value
Power pins
V
V
V
V
DDI
10Ω
or less
SS
CORE
DD, VDD2
Booster series pins
1st booster pins
164 to 179
10
20
30
20
Ω
Ω
Ω
Ω
or less
or less
or less
or less
or less
2nd booster pins
182 to 189
3rd and 4th booster pins
7 to 35(Except DUMMY)
198 to 200
V
COM auxiliary pins, etc.
___ ___ ___
Other logic signal pins
WR, RD, CS
D0 to D17,VDD,VSS, etc.
Others
100Ω
The above values are recommended, however, it does not mean that the resistor does not function if they are not
satisfied.
Since the booster-series pins are effective for power conversion efficiency, the lower the value is, the better the
efficiency becomes.
Since impedance is high in wiring to the FBH pin, carry out wiring as short as possible to prevent the influence of
noise.
Also, prevent wiring from crossing other signals.
S1D19105 Series (Rev.1.1)
EPSON
57
6. FUNCTIONAL DESCRIPTION
6.11 Gray scale Voltage Generation Circuit
This circuit generates 64 levels by 2 series (positive and negative poles) of voltages according to the polarity
inversion for AC operation. The circuit incorporates a function to correct the gray scale voltage curve according
to the characteristics of panel to be connected. Setting can be changed using the Set Gamma Correction
Characteristics command. However, care should be taken, because power consumption is so high that can cause
departure from the default γ ratio. The reference voltage circuit (positive pole) configuration diagram is shown
below. Negative pole also serves as an equivalent composition figure.
With electronic control
Amplitude
Tilt adjust
register
Fine adjust register
3/
adjust register
5/
5/
4/
3/
3/
3/
3/
4/
3/
3/
3/
3/
V
DDRH
3/
V
0
V
RP0
16 to 1
8 to 1
Selector
P1
V
OP1
V
1
2
3
4
5
6
V
V
RP1
V
V
8 to 1
V
V
V
VOP2
VOP3
VOP4
VOP5
8 to 1
Selector
V
P2
8 to 1
Selector
V
P3
8 to 1
Selector
V
P4
8 to 1
Selector
V
P5
8 to 1
V
OP6
OP7
Selector
V
V
V
V
V
V
V
V
55
56
57
58
59
60
61
62
V
P6
V
8 to 1
Selector
P7
V
V
RP2
VOP8
8 to 1
8 to 1
Selector
P8
V
V
RP3
16 to 1
V
DDRL
V
63
Fig.44 Reference Voltage Circuit Configuration Diagram (Positive Pole)
58
EPSON
S1D19105 Series (Rev.1.1)
6. FUNCTIONAL DESCRIPTION
6.11.1 Adjusting Gray Scale Voltage
Adjustment of gray scale voltage and tilt as well as fine adjustment are available in accordance with
characteristics of liquid crystal panel or color creation.
On the positive pole/
negative pole side
On the positive pole/
negative pole side
V
DDRH
V
P1 to VP8
V
RP3 to VRP0
V
RN0 to VRN3
V
N1 to VN8
V
DDRL
Gray scale level
Fine adjustment
Gray scale level
Gray scale level
Tilt adjustment
Amplitude adjustment
Fig.45 Gray scale Voltage Slope Adjustment
6.11.2 Amplitude Adjustment
Determines with the electronic control command.
6.11.3 Tilt Adjustment
Adjusts the tilt of the gray scale voltage for four points of the gray scale level.
6.11.4 Fine Adjustment of Gray Scale Voltage
Fine-adjusts the gray scale voltage for eight points of the gray scale level. At each point, fine adjustment is
made by selecting one of 8 types (4 or 3 bits) of the voltage generated by the resistance string.
S1D19105 Series (Rev.1.1)
EPSON
59
6. FUNCTIONAL DESCRIPTION
6.12 Calculation of Gray Scale Voltage
Specifying the gray scale voltage involves three registers. The amplitude register determines the entire
difference of voltage, the tilt adjust register determines a tilt of gray scale curve by selecting internal fixed
resistor, and the voltage fine-adjust register for fine adjusting the gray scale voltage.
ꢃ Amplitude Adjustment
The Set Electronic Control commands allows adjustment of amplitude of VDDRH and VDDRL (5 bits: Specify a
value of 0 to 31). Therefore, the value to be changed is within VDDRH - VDDRL
.
DDDDRRLH : 0.00V to 1.55V
V
V
: 2.70V to 5.80V
ꢃ Tilt Adjust Register
Specify the resistor value using VRP0 (4 bits), VRP1 (3 bits), VRP2 (3 bits) and VRP3 (4 bits).
Table 30 Tilt Adjust Register Value and Resistor Value (Colored items indicate the standard value.)
Resistor
value
1R
Resistor
value
0R
Tilt adjust register
0000
Tilt adjust register
000
001
010
011
100
101
110
111
0001
0010
0011
0100
0101
0110
0111
1000
1001
1010
1011
1100
1101
1110
1111
000
3R
5R
7R
9R
4R
8R
12R
16R
20R
25R
30R
1R
3R
5R
7R
9R
12R
16R
21R
27R
34R
42R
52R
64R
78R
96R
120R
V
RP2<2:0>
12R
16R
21R
27R
34R
42R
52R
64R
78R
96R
120R
0R
4R
8R
12R
16R
20R
25R
30R
V
RP0<3:0>
0000
0001
0010
0011
0100
0101
0110
0111
1000
1001
1010
1011
1100
1101
1110
1111
V
RP3<3:0>
001
010
011
100
V
RP1<2:0>
101
110
111
60
EPSON
S1D19105 Series (Rev.1.1)
6. FUNCTIONAL DESCRIPTION
ꢃ Voltage Fine-Adjust Register
Select the reference voltage VOP1 to VOP8 to the gray scale amplifier with the fine-adjust register (3 bits). The
expression for calculation is shown below. SUMRP of the expression means the value of four variable resistors
for tilt adjustment with the basic R added.
Tilt adjust
resistor
Min.
Max.
Typ.
V
V
V
V
RP0
RP1
RP2
RP3
1R
0R
0R
1R
120R
30R
30R
5R
0R
0R
120R
7R
Basic R
126R
SUMRP = VRP0 + VRP1 + VRP2 + VRP3 + Basic R
Fine-adjust register Expression for calculation
V
DDRH
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
DDRH
000
001
010
011
100
101
110
111
000
001
010
011
100
101
110
111
000
001
010
011
100
101
110
111
000
001
010
011
100
101
110
111
DDRH-(VDDRH-VDDRL
DDRH-(VDDRH-VDDRL
DDRH-(VDDRH-VDDRL
DDRH-(VDDRH-VDDRL
DDRH-(VDDRH-VDDRL
DDRH-(VDDRH-VDDRL
DDRH-(VDDRH-VDDRL
DDRH-(VDDRH-VDDRL
DDRH-(VDDRH-VDDRL
DDRH-(VDDRH-VDDRL
DDRH-(VDDRH-VDDRL
DDRH-(VDDRH-VDDRL
DDRH-(VDDRH-VDDRL
DDRH-(VDDRH-VDDRL
DDRH-(VDDRH-VDDRL
DDRH-(VDDRH-VDDRL
DDRH-(VDDRH-VDDRL
DDRH-(VDDRH-VDDRL
DDRH-(VDDRH-VDDRL
DDRH-(VDDRH-VDDRL
DDRH-(VDDRH-VDDRL
DDRH-(VDDRH-VDDRL
DDRH-(VDDRH-VDDRL
DDRH-(VDDRH-VDDRL
DDRH-(VDDRH-VDDRL
DDRH-(VDDRH-VDDRL
DDRH-(VDDRH-VDDRL
DDRH-(VDDRH-VDDRL
DDRH-(VDDRH-VDDRL
DDRH-(VDDRH-VDDRL
DDRH-(VDDRH-VDDRL
DDRH-(VDDRH-VDDRL
)
)
)
)
)
)
)
)
)
)
)
)
)
)
)
)
)
)
)
)
)
)
)
)
)
)
)
)
)
)
)
)
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
(VRP0+0R)/SUMRP
(VRP0+2R)/SUMRP
(VRP0+4R)/SUMRP
(VRP0+6R)/SUMRP
(VRP0+8R)/SUMRP
(VRP0+10R)/SUMRP
(VRP0+12R)/SUMRP
(VRP0+14R)/SUMRP
V
OP1
OP2
OP3
OP4
V
V
V
V
P1<2:0>
P2<2:0>
P3<2:0>
P4<2:0>
(VRP0+16R+VRP1)/SUMRP
(VRP0+18R+VRP1)/SUMRP
(VRP0+20R+VRP1)/SUMRP
(VRP0+22R+VRP1)/SUMRP
(VRP0+24R+VRP1)/SUMRP
(VRP0+26R+VRP1)/SUMRP
(VRP0+28R+VRP1)/SUMRP
(VRP0+30R+VRP1)/SUMRP
(VRP0+32R+VRP1)/SUMRP
(VRP0+34R+VRP1)/SUMRP
(VRP0+36R+VRP1)/SUMRP
(VRP0+38R+VRP1)/SUMRP
(VRP0+40R+VRP1)/SUMRP
(VRP0+42R+VRP1)/SUMRP
(VRP0+44R+VRP1)/SUMRP
(VRP0+46R+VRP1)/SUMRP
(VRP0+48R+VRP1)/SUMRP
(VRP0+50R+VRP1)/SUMRP
(VRP0+52R+VRP1)/SUMRP
(VRP0+54R+VRP1)/SUMRP
(VRP0+56R+VRP1)/SUMRP
(VRP0+58R+VRP1)/SUMRP
(VRP0+60R+VRP1)/SUMRP
(VRP0+62R+VRP1)/SUMRP
V
V
V
S1D19105 Series (Rev.1.1)
EPSON
61
6. FUNCTIONAL DESCRIPTION
Fine-adjust register
000
001
010
011
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
OP5
OP6
OP7
OP8
V
V
V
V
P5<2:0>
P6<2:0>
P7<2:0>
P8<2:0>
100
101
110
111
000
001
010
011
100
101
110
111
000
001
010
011
100
101
110
111
000
001
010
011
100
101
110
111
V
V
V
V
V
V
V
V
V
DDRL
V
DDRL
62
EPSON
S1D19105 Series (Rev.1.1)
6. FUNCTIONAL DESCRIPTION
ꢃ Gray Scale Voltage
The expression for calculating the gray scale voltage is shown below.
Gray scale
voltage
Gray scale
voltage
Expression for calculation
Expression for calculation
V
V
V
V
V
V
0
1
2
3
4
5
V
V
DDRH
OP1
VOP5
V
V
V
V
V
V
V
V
V
V
V
V
36
37
38
39
40
41
42
43
44
45
46
47
V
V
V
V
V
V
V
V
V
V
OP6+(VOP5-VOP6
OP6+(VOP5-VOP6
OP6+(VOP5-VOP6
OP6+(VOP5-VOP6
OP6+(VOP5-VOP6
OP6+(VOP5-VOP6
OP6+(VOP5-VOP6
OP6+(VOP5-VOP6
OP6+(VOP5-VOP6
OP6+(VOP5-VOP6
)
)
)
)
)
)
)
)
)
)
*
*
*
*
*
*
*
*
*
*
(36/38)
(33/38)
(30/38)
(27/38)
(24/38)
(22/38)
(19/38)
(16/38)
(13/38)
(10/38)
V
V
V
OP2+(VOP1-VOP2
OP2+(VOP1-VOP2
OP2+(VOP1-VOP2
)
)
)
*
*
*
(27/38)
(19/38)
(12/38)
V
OP2+(VOP1-VOP2
)
*
(5/38)
V
OP2
V
V
V
V
6
7
8
9
V
V
V
V
V
OP3+(VOP2-VOP3
OP3+(VOP2-VOP3
OP3+(VOP2-VOP3
OP3+(VOP2-VOP3
OP3+(VOP2-VOP3
)
*
*
*
*
*
(37/38)
(31/38)
(24/38)
(19/38)
(13/38)
)
)
)
)
)
)
V
V
V
10
11
12
V
V
OP6+(VOP5-VOP6
OP6+(VOP5-VOP6
)
)
*
*
(6/38)
(3/38)
V
V
OP3+(VOP2-VOP3
OP3+(VOP2-VOP3
*
*
(8/38)
(3/38)
VOP6
V
OP3
V
V
V
V
V
V
V
V
V
V
48
49
50
51
52
53
54
55
56
57
V
V
V
V
V
V
V
V
OP7+(VOP6-VOP7
OP7+(VOP6-VOP7
OP7+(VOP6-VOP7
OP7+(VOP6-VOP7
OP7+(VOP6-VOP7
OP7+(VOP6-VOP7
OP7+(VOP6-VOP7
OP7+(VOP6-VOP7
)
*
*
*
*
*
*
*
*
(38/38)
(34/38)
(31/38)
(27/38)
(23/38)
(20/38)
(16/38)
(12/38)
V
V
V
V
V
V
V
V
V
V
13
14
15
16
17
18
19
20
21
22
V
V
V
V
V
V
V
V
V
V
OP4+(VOP3-VOP4
OP4+(VOP3-VOP4
OP4+(VOP3-VOP4
OP4+(VOP3-VOP4
OP4+(VOP3-VOP4
OP4+(VOP3-VOP4
OP4+(VOP3-VOP4
OP4+(VOP3-VOP4
OP4+(VOP3-VOP4
OP4+(VOP3-VOP4
)
*
*
*
*
*
*
*
*
*
*
(36/38)
(31/38)
(27/38)
(23/38)
(19/38)
(15/38)
(12/38)
(8/38)
(5/38)
(2/38)
)
)
)
)
)
)
)
)
)
)
)
)
)
)
)
)
V
V
OP7+(VOP6-VOP7
OP7+(VOP6-VOP7
)
)
*
*
(7/38)
(2/38)
VOP7
V
OP4
V
V
V
V
V
V
58
59
60
61
62
63
V
V
V
V
OP8+(VOP7-VOP8
OP8+(VOP7-VOP8
OP8+(VOP7-VOP8
OP8+(VOP7-VOP8
)
*
*
*
*
(35/38)
(28/38)
(21/38)
(12/38)
V
V
V
V
V
V
V
V
V
V
V
V
V
23
24
25
26
27
28
29
30
31
32
33
34
35
V
V
V
V
V
V
V
V
V
V
OP5+(VOP4-VOP5
OP5+(VOP4-VOP5
OP5+(VOP4-VOP5
OP5+(VOP4-VOP5
OP5+(VOP4-VOP5
OP5+(VOP4-VOP5
OP5+(VOP4-VOP5
OP5+(VOP4-VOP5
OP5+(VOP4-VOP5
OP5+(VOP4-VOP5
)
*
*
*
*
*
*
*
*
*
*
(37/38)
(34/38)
(31/38)
(28/38)
(24/38)
(21/38)
(18/38)
(16/38)
(13/38)
(10/38)
)
)
)
)
)
)
)
)
)
)
)
)
V
OP8
V
DDRL
The constant 38 in the expression for
calculation indicates the total number of
bits in the tilt register and fine-adjust
register.
V
V
V
OP5+(VOP4-VOP5
OP5+(VOP4-VOP5
OP5+(VOP4-VOP5
)
)
)
*
*
*
(7/38)
(4/38)
(1/38)
S1D19105 Series (Rev.1.1)
EPSON
63
6. FUNCTIONAL DESCRIPTION
6.13 Resetting
____
____
When the power is turned on, resetting by the RES pin is necessary. Following the rest by the RES pin, each
input pin must be normally controlled. For connection of the LOW pulse width for reset, continue 1
µs or more.
If it is 100ns or less, it is rejected.
For the default value of the command and parameter after reset, see
(1) 7.2 Initial Values of a Single-Byte Command
(2) 7.3 Parameter Initial Value List.
____
During reset (RES = LOW), no data is output even if revision read operation is performed. It becomes Hi-Z.
64
EPSON
S1D19105 Series (Rev.1.1)
7. COMMANDS
7. COMMANDS
___
___
__
The data bus signal is identified by combination of A0, RD (E) and WR (R/W) pins. All commands are
interpreted and executed independent from external clocks. When A0 is LOW, data existing on the data bus is
considered to be a command. When A0 is HIGH, data is considered to be a command parameter or the data of
display data RAM.
Each of commands and parameters is defined in a single byte (8 bits) long. Pins D0 to D9 are invalid for 16-bit or
18-bit parallel interfacing. Eight bits after the D/C are valid for serial interfacing.
There are two types of commands: multiple-byte commands having parameters, and single-byte commands
having no parameters. To issue a multiple-byte command, enter its single-byte command code and enter the
specified number of bytes of parameters. If there are two or more parameters, all parameters must be entered, in
principle. Another command can also be entered during parameter entry if A0 is set to LOW by accessing via
___
WR or E signal. However, it should be noted that for parameters to be executed in synchronization with
VSYNC, those parameters entered partway are not executed. The parameter to be executed in synchronization
with VSYNC is executed in synchronization with the first VSYNC after all the parameters have been entered.
The RAM Write and RAM Read commands have not restriction in the number of parameter bytes. The command
ends automatically when A0 is set to LOW and when the next command is entered.
___
The 80-series MPU interface starts reading when LOW signal is entered in the RD pin, and it starts writing
___
when LOW signal is entered in the WR pin. The 68-series MPU starts reading when HIGH signal is entered in
__
__
the R/W pin, and it starts writing when LOW signal is entered in the R/W pin. The HIGH signal must be
entered in the E pin.
For serial interfacing, data signals are processed as explained in Paragraph 6.1.3.
Any other code not described here must not be used.
S1D19105 Series (Rev.1.1)
EPSON
65
7. COMMANDS
7.1 Command List
Table 31 Command List
Command Instruction Command
No.
Command name
Display ON
Code
(Hex)
AF
length
execution
timing
Function
(Byte)
1
2
1
1
VSYNC Turns the LCD display ON.
Immediately Turns the LCD display OFF.
afterward
Display OFF
AE
3
Sets display
CA
10
VSYNC Number of clocks in 1H and number of
display lines
Normally white or normally black, etc.
VSYNC Sets the display timing.
Immediately RGB array, access direction,
afterward built-in oscillator, etc.
Immediately Sets the RAM access start address.
afterward Start Column Address, Start Row
Address
Immediately Sets the RAM access end address.
afterward End Column Address, End Row
Address
4
5
Set Display Timing
Set Data
A1
BC
8
2
6
7
Set Start Address
Set End Address
15
75
3
3
8
9
RAM Write
RAM Read
5C
5D
E0
Immediately Writes data into the RAM.
afterward
Immediately Reads data from the RAM.
afterward
Immediately Sets to the read-modify-write state.
afterward
10 Read-Modify-Write
11 Set Area Scrolling
12 Set Display Start Line
AA
AB
5
2
VSYNC Sets the area scroll state.
VSYNC Starts display of the scrolling area.
Set Line Address
13 Partial Display In
A8
4
VSYNC Sets the partial display state and starts
partial display.
14 Partial Display Out
A9
31
8B
6F
8C
20
1
3
5
4
3
8
VSYNC Cancels partial display.
VSYNC Sets the display data interface.
VSYNC Sets the display color state.
VSYNC Sets the gate line scan mode.
VSYNC Sets the AC operation drive state.
Immediately Sets the power supply.
afterward
15 Set Display Data Interface
16 Set Display Color Mode
17 Gate Line Scan Mode
18 Set AC Operation Drive
19 Set Electronic Control
20 Set
γ
Correction Characteristics
22
7
Immediately Sets the
afterward
γ correction value.
21 Set Power Control
22 Set Partial Power Control
21
23
14
8
VSYNC Controls the power circuit.
VSYNC Controls power supply in partial
non-display area.
23 Sleep In
95
94
1
1
Immediately Execute Automatic Off Sequence
afterward command
24 Sleep Out
VSYNC Execute Automatic On Sequence
command
66
EPSON
S1D19105 Series (Rev.1.1)
7. COMMANDS
Command Instruction Command
No.
Command name
Code
(Hex)
97
length
(Byte)
1
execution
timing
Function
25
V
OSC OFF
Immediately Stops VCORE and VOSC
afterward
.
26 Turns VOSC ON
27 Stops oscillation
28 Starts oscillation
29 Test
96
93
1
1
1
8
1
3
1
1
Immediately Starts up VCORE and VOSC
afterward
Immediately Stops the built-in oscillation circuit.
afterward
Immediately Starts the built-in oscillation circuit.
afterward
Immediately Command for testing
afterward
This is the no-operation command that
does not affect the system operation.
Immediately Reads the status.
afterward
Immediately Reads revision.
afterward
.
92
FF
0
30 NOP
31 Status Read
32 Revision Read
33 Soft Reset
E8
-(E9)
99
Immediately Soft Reset
afterward
7.2 Initial Values of a Single-Byte Command
Display OFF
Partial Display Out (Normal display)
Sleep In
High-Speed RAM Write Out
StOoSpCs oscillation.
V
OFF
S1D19105 Series (Rev.1.1)
EPSON
67
7. COMMANDS
7.3 Parameter Initial Value List
Table 32 Parameter Initial Value List
Code (Bin)
Deci
mal
0
No.
Command
Sets display
Parameter
Initial state
1H=74 clocks
D17 D16 D15 D14 D13 D12 D11 D10
3
P1
P2
P3
P4
P5
P6
P7
0
0
0
*
1
0
0
0
1
0
1
1
0
0
0
0
*
0
0
0
0
0
0
*
0
1
0
0
*
1
*
*
1
0
0
*
0
0
0
0
1
0
1
0
1
0
0
1
0
0
0
*
1
0
0
0
73 1H=74 clocks
Liquid crystal type, etc.
Boosting clock frequency
219 220-line display
0
2
All pins enabled.
Number of back poaching
lines 3
Number of front poaching
lines 2
All pins enabled.
Source output ON at the
1st clock
P8
0
0
0
0
0
0
0
1
1
P9
P1
*
0
*
0
*
0
*
0
*
0
0
0
0
0
0
0
0
0
4
Set Display Timing
P2
P3
P4
0
0
0
1
0
1
0
0
0
0
0
0
0
0
0
1
1
1
1
0
0
0
0
0
70 Source output OFF at 71st
clock
4
Gate output ON at the 5th
clock
68 Gate output OFF at the
69th clock
P5
P6
P7
P1
P1
P2
P1
P2
P1
P2
P3
P4
*
0
0
0
0
0
1
1
0
1
0
*
*
0
0
0
0
0
0
1
0
1
0
*
*
0
0
0
0
0
1
0
0
0
0
*
*
1
0
0
0
0
0
1
0
1
0
*
0
0
1
0
0
0
1
1
0
1
0
*
0
0
0
0
0
0
1
0
0
0
0
*
0
1
0
0
0
0
1
1
0
1
0
1
0
1
1
0
0
0
1
1
0
1
0
1
0
19
9
Drive mode switch
COM boost timing
Drive mode switch timing
Row address normal setup
Start Column Address
Start Row Address
V
5
6
Set Data
Set Start Address
0
0
7
Set End Address
175 End Column Address
219 End Row Address
11 Set Area Scrolling
0
Start address
219 End address
0
Number of scroll lines 0
The full-screen can be
scrolled.
12 Display Start Line
13 Partial Display In
P1
P1
P2
P3
P1
P2
P1
0
0
0
0
0
*
*
0
0
0
0
0
*
*
0
0
0
0
0
*
*
0
0
0
0
0
*
*
0
0
0
0
0
*
*
0
0
0
0
0
*
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Display Start Line 0
Area 1 Start Line 0
Area 1 End Line 0
Non-display refresh rate
MPU interface 18 bits
Division is not done.
Select voltage and display
color
15 Set Display Data
Interface
0
0
16 Set Display Color
Mode
P2
P3
P4
P1
*
*
*
*
0
1
1
*
0
0
0
*
1
0
0
*
*
*
*
0
0
1
1
*
0
0
0
0
1
0
0
0
Gray scale amplifier ability
Bias setting
Boosting clock frequency
Normal direction, interlace
drive
17 Set Gate Line
Scan Mode
P2
P3
0
1
0
1
0
0
0
1
0
1
0
0
0
1
0
1
0
Scan start line
219 Scan end line
68
EPSON
S1D19105 Series (Rev.1.1)
7. COMMANDS
Code (Bin)
Deci
mal
No.
Command
Parameter
Initial state
D17 D16 D15 D14 D13 D12 D11 D10
18 Set AC Operation
Drive
19 Set Electronic
P1
P2
P1
P2
P3
P4
P5
P6
P7
P8
P1
P2
P3
P4
P5
P6
P1
P2
P3
P4
P5
P6
P7
P8
*
*
*
*
*
*
*
*
*
*
0
*
*
*
*
*
0
0
*
0
0
0
*
0
*
*
*
*
*
*
*
*
*
*
0
0
1
1
1
1
0
0
*
0
0
0
1
0
*
*
*
0
*
*
*
*
*
*
1
0
0
0
0
0
0
0
*
*
0
0
0
0
*
*
*
0
0
0
0
0
0
0
0
*
0
*
*
*
*
*
0
0
0
0
0
*
*
0
*
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
0
0
0
0
0
*
0
0
0
0
0
0
0
0
0
0
1
0
0
0
0
0
0
0
0
0
0
*
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
0
0
0
*
n-line reverse
n-line set 1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
*
1
0
0
0
0
0
1
1
*
V
V
DDHS
Control
COMH
VCA
DDRH
V
V
V
V
V
V
V
V
V
V
V
DDRL
ONREG
OFREG
LDO
RP3
RP2
P2
20 Set
γ
Correction
V
V
RP0
RP1
Characteristics
V
V
V
V
P1
P3
P5
P7
P4
P6
P8
21 Set Power Control
Wait1, 2
Wait3, 4
Booster circuit
Regulator 1
Regulator 2
Regulator 3
0
0
*
0
0
1
0
0
0
0
0
Pre-buffer ability setting
Gray scale amplifier control
1
P9
PA
PB
*
0
*
*
0
*
*
0
*
*
0
*
*
0
*
*
0
*
0
0
0
0
0
0
0
0
0
Gray scale amplifier control
2
Gray scale amplifier output
Hz1
Gray scale amplifier output
Hz2
PC
PD
P1
P2
P3
P4
P5
P6
P7
P1
P2
*
*
*
*
*
0
0
*
*
*
*
0
1
*
1
*
0
0
0
1
*
*
0
0
*
0
*
0
0
0
0
0
*
1
0
0
0
0
*
*
1
0
0
*
*
*
*
*
0
0
*
*
*
0
0
0
1
0
1
0
0
*
0
1
0
0
0
0
0
0
0
0
*
0
0
0
0
1
0
1
0
0
0
*
1
0
0
0
Gray scale amplifier ability
Bias setting
22 Set Partial Power
Control
VCOM ability setting
Boosting clock frequency
Regulator 1
Regulator 2
Regulator 3
Gray scale amplifier ability
Bias setting
29 Test
VREG adjustment
Constant current
adjustment
P3
*
*
*
0
0
0
0
0
Oscillation frequency
adjustment
P4
P5
P6
P7
P1
*
0
*
0
0
0
0
*
0
0
0
*
0
0
0
*
0
0
0
0
1
0
0
0
0
1
0
0
0
0
0
0
0
0
0
1
Discharge control 1
Discharge control 2
Gate driver test
Detector test
00H
*
32 Revision Read
0
0
0
S1D19105 Series (Rev.1.1)
EPSON
69
7. COMMANDS
7.4 Explanation of Commands
(1) Display ON (Command code: AFh, Parameter: None)
This command converts the display data stored in the built-in RAM to the gray scale voltage and displays on the
LCD panel. The Sleep Out command be entered beforehand. The Display On is waited until it is ready for
starting display after Sleep Out. When it is ready, the command is executed.
D17 D16 D15 D14 D13 D12 D11 D10
Function
Command Display ON
1
0
1
0
1
1
1
1
(2) Display OFF (Command code: AEh, Parameter: None)
Turns the LCD display OFF. After receiving the command, display is canceled from the next frame at once.
D17 D16 D15 D14 D13 D12 D11 D10
Function
Command Display OFF
1
0
1
0
1
1
1
0
Enter Display OFF
command.
Source output
Gate scan
Frame
Data
1 frame
Discharge
After receiving the Display OFF command, source output and VCOM output produce an output of VSS and display
white (in case of normally white liquid crystal) while turning the gate line on for a period of 1 frame or more.
Then, they discharge the power circuits.
70
EPSON
S1D19105 Series (Rev.1.1)
7. COMMANDS
(3) Set Display (Command code: CAh, Parameter: 9 bytes)
This command sets the display conditions. P3 and P6 execute immediately. P1, P2, P4, P5, P7 and P8 execute
in synchronization with the first VSYNC after P9 was entered.
D17 D16
D15
0
P15
P25
*
D14
0
P14
P24
*
D13
1
*
P23
*
*
D12
0
*
P22
*
P42
D11
1
P11
P21
P31
P41
D10
Function
Set Command Display
1
1
0
P17 P16
P27 P26
P37 P36
P10 Parameter 1 (P1) Number of clocks in 1H (MSB)
P20 Parameter 2 (P2) Number of clocks in 1H (LSB)
P30 Parameter 3 (P3) Liquid crystal type
*
P46
P45
P44
P40 Parameter 4 (P4) Sets boosting clock frequency.
Parameter 5 (P5) Number of display dots Y
(number of display lines)
P57 P56
P55
P54
P53
P52
P51
P50
P67 P66
P77 P76
P87 P86
P65
P75
P85
*
P64
P74
P84
*
P63
P73
P83
*
P62
P72
P82
0
P61
P71
P81
0
P60 Parameter 6 (P6) Source output Hi-Z control
P70 Parameter 7 (P7) Back poaching line
P80 Parameter 8 (P8) Front poaching line
*
*
0
Parameter 9 (P9) Reserved parameter
Parameter 1 (P1): Sets MSB bits of the number of clocks in 1H and the number of display dots. Sets the
expansion MSB bits of front poaching.
P11 to P10: Sets MSB 2 bits of the number of clocks required during 1H (a single-line select period) subtracted
by 1.
P17 to P14: Sets MSB 4 bits of the front poaching. (The LSB 8 bits are set by P8).
Parameter 2 (P2): Sets LSB 8 bits of the number of clocks required during 1H (a single-line select period)
subtracted by 1. Notice change of the number of clocks of 1H about a relation with display
timing set. Please be sure to set up to become longer than the various timing set up by the
source timing set. When making a setting value small during display turn ON, it
recommends changing display timing set previously.
Example: If the frame frequency is 60Hz, the number of display lines is 220, back poaching is 3 lines, front
poaching is 2 lines and the single clock cycle is 1µs:
1 / 60 / (220+2+3) = 74µs (1H)
Set value = 74-1 = 73
P1=00H, P2=49H
Parameter 3 (P3): Sets the address location of RAM and liquid panel type.
P31 and P30: Sets the divided ratio of a built-in oscillation.
P31
0
0
P30
0
1
Divided ratio
Non divided (1MHz)
1/2 (0.5MHz)
1
1
0
1
1/4 (0.25MHz)
Setting disabled
P36: Automatically sets the RAM’s column address location linked with the P6 source output Hi-Z.
0: Manual No change of RAM address
1: Automatic Automatically changes the column address location of RAM.
P37: Sets the type of the LCD panel to be used.
0: Normally white
1: Normally black
Parameter 4 (P4): Sets frequency of the boosting clock of the 1st to 4th booster in displaying 262k-color display
of display area.
S1D19105 Series (Rev.1.1)
EPSON
71
7. COMMANDS
P42 to P40: Sets frequency of the boosting clock of the 1st and 2nd boosters in displaying 262k-color display.
P46 to P44: Sets frequency of the boosting clock of the 3rd and 4th boosters in displaying 262k-color display.
Determine while checking the display.
P42/P46
P41/P45
P40/P44
Frequency
= Stop (disable)
= Frequency in 1H
= Frequency in 1H
= Frequency in 1H
= Frequency in 1H
= Frequency in 1H / 2
= Frequency in 1H / 4
= Frequency in 1H / 8
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
×
×
×
×
8
4
2
1
Parameter 5 (P5): Sets the number of dots to be displayed in the direction of Y subtracted by 1. Odd lines
cannot be set up.
Example) To use a 176RGB × 220-dot LCD panel:
Set value = 220-1 = 219
Parameter 6 (P6): Sets source output not to be used to Hi-Z. Sets a maximum of 16 outputs to Hi-Z and allows
160-dot display.
P63
0
1
P62
*
0
P61
*
0
P60
*
0
Pins set to Hi-Z
All pins enabled
S1-S3
1
1
0
0
0
1
1
0
S1-S6
S1-S9
1
1
0
1
1
0
1
0
S1-S12
S1-S15
1
1
1
1
0
1
1
0
S1-S18
S1-S21
1
1
1
1
S1-S24
P67
0
1
P66
*
0
P65
*
0
P64
*
0
Pins set to Hi-Z
All pins enabled
S528-S526
1
1
0
0
0
1
1
0
S528-S523
S528-S520
1
1
0
1
1
0
1
0
S528-S517
S528-S514
1
1
1
1
0
1
1
0
S528-S511
S528-S508
1
1
1
1
S528-S505
Parameter 7 (P7): Sets the number of lines for back poaching subtracted by 1.
P77 to P70: Sets the number of lines for back poaching in the range from 1 to 256.
It recommends that is making a change of the number of lines before sleep out. When it changes
during display turn on, a display may be abnormal a moment. Since it may be VCOM is same
voltage potential 2-frame period. (Attention follows coincidence becomes abnormal. Odd lines to
even lines and even lines to odd lines. Odd lines to odd lines and even lines to even lines are not
happen)
Parameter 8 (P8): Sets the number of lines of front poaching subtracted by 1.
P87 to P80: Sets the number of lines for front poaching in the range from 2 to 4096 by combining with MSB 4
72
EPSON
S1D19105 Series (Rev.1.1)
7. COMMANDS
bits of P1. 1 line (00h) is prohibition of a setup.
Parameter 9 (P9): Test parameter Specify 000.
P92 to 90: Specifying 1 sets all source outputs to Hi-Z.
(4) Set Display Timing (Command code: A1h, Parameter: 7 bytes)
With the clock setting of the display timing, the output timing best-suited to the characteristics of the panel to be
connected can be obtained.
1H
BP
1 line
2 lines
3 lines
Source output
Gate output
Source output
OFF timing
Source output
ON timing
Gate output
OFF timing
Gate output
ON timing
Fig.46 Display Timing Control
Enable the source output (S1 to S528 pins) and set the timing of Hi-Z and ON/OFF timing of the LCD output of
the gate driver. Set the timing within the range of the number of clocks required during 1H (a single-line select
period) subtracted by 1, which was set by 0 - Set Display P1. Set the timing to be changed subtracted by 1.
It is the number of clocks of the oscillator when using the built-in oscillator for the display timing, or the number
of DOTCLKs when using the DOTCLK. It becomes the DOTCLK number that was divided in the case that it
divided with P2 of the display data interface set.
D17 D16 D15 D14 D13 D12 D11 D10
Function
Command Set Display Timing
1
0
1
0
0
0
0
1
P17 P16 P15 P14 P13 P12 P11 P10 Parameter 1 (P1) Source Output ON Timing
P27 P26 P25 P24 P23 P22 P21 P20 Parameter 2 (P2) Source Output OFF Timing
P37 P36 P35 P34 P33 P32 P31 P30 Parameter 3 (P3) Gate Signal “Select” Timing
P47 P46 P45 P44 P43 P42 P41 P40 Parameter 4 (P4) Gate Signal “Non-select” Timing
*
*
*
*
P53 P52 P51 P50 Parameter 5 (P5) Sets selection of drive mode
P67 P66 P65 P64 P63 P62 P61 P60 Parameter 6 (P6) COMH and VCOML boost timing
V
P77 P76 P75 P74 P73 P72 P71 P70 Parameter 7 (P7) Sets the switching timing of drive mode
Parameter 1 (P1): Sets the turn-ON (enabling) timing of source outputs (S1 to S528 pins) to the number of clocks
from the beginning of the line subtracted by 1.
Parameter 2 (P2): Sets the turn-OFF (Hi-Z) timing of source outputs (S1 to S528 pins) to the number of clocks
from the beginning of the line subtracted by 1.
It sets up so that it may surely become source on timing < source off timing. Moreover, it is
necessary to set up source of timing by the less than -2 CK number of 01h to 1H.
Parameter 3 (P2): Sets the turn-ON (VDDHG) timing of gate outputs (G1 to G220 pins) to the number of clocks
from the beginning of the line subtracted by 1.
S1D19105 Series (Rev.1.1)
EPSON
73
7. COMMANDS
Parameter 4 (P4): Sets the turn-OFF (VEE) timing of gate outputs (G1 to G220 pins) to the number of clocks from
the beginning of the line subtracted by 1.
It sets up so that it may surely become gate on timing < gate off timing. Moreover, it is
necessary to set up gate of timing by the less than -1 CK number of 01h to 1H.
Parameter 5 (P5): Selects the source drive mode, power down for the gray scale generation circuit after the source
output Hi-Z and the VCOMH and VCOML ability control.
P53: Selects whether or not to UP (boost) the ability of VCOMH and V
. The boosting timing is set by P6.
This command is valid when power control command of P56 setCsOtoML1.
0: Not boost
1: Boost
P52: Selects whether or not to enable power saving of the gray scale voltage generation circuit after the source
OFF timing.
0: Not enable power saving
1: Enable power saving
P52 generally uses not to power save. Power-save may be used to reduce power by decreasing the frame
frequency.
Carefully check the indication before using it.
P51 and P50: Select the source drive mode.
P51 P50
Switch mode
Switches between pre-buffer drive and
centralized DAC drive at the timing set
by P7.
Centralized DAC drive throughout the
period of source output enable. P7 is
ignored.
Pre-buffer drive throughout the period
of source output enable. P7 is
ignored.
0
0
1
1
0
1
0
1
Setting disabled
Parameter 6 (P6): With P67 to P60, sets the timing of bringing UP (boost) the ability of the regulator of the
built-in power supply to the number of clocks from the beginning of the line subtracted by 1.
If it is being boosted by the Power Control command, the above setting is invalid.
Parameter 7 (P7): With P77 to P70, sets the timing of switching between pre-buffer drive and centralized DAC
drive to the number of clocks from the beginning of the line subtracted by 1.
In pre-buffer + concentration DAC drive (P51, P50= 0,0), change timing is surely set as
source ON timing <P7< source OFF timing. Moreover, in any drive systems, 00h is
prohibition of a setup.
74
EPSON
S1D19105 Series (Rev.1.1)
7. COMMANDS
Setup Example
Source Output On Timing P1 = 3
Source Output Off Timing P2 = 71
Gate Signal Select Timing P3 = 4
Gate Signal Non-select Timing P4 = 70
Source Drive Mode, etc. P5 = 00
Drive Mode SCwOitMchLing Timing P7 = 6 (P51, P50 = 0, 0)
V
COMH and V
Boost Timing P6 = 19 (invalid)
Clock
1
2
3
4
5
6
7
68
69
70
71
72
73
Hi-Z
74
1
2
Source output
Gate output
Hi-Z
Enable
V
COM
Drive mode switching
(Internal signal)
Pre-buffer drive
DAC drive
S1D19105 Series (Rev.1.1)
EPSON
75
7. COMMANDS
(5) Set Data (Command code: BCh, Parameter: 1 byte)
Sets display data conditions. Change the display RAM address direction and the scan direction while the Display
OFF is set, and wait for 1ms or more after changing. When only parameters not related to the display RAM are
changed, the setting is immediately enabled. In this case, there is no need to wait.
D17 D16 D15 D14 D13 D12 D11 D10
Function
Command Set Data
1
0
1
1
1
1
0
0
P17 P16 P15 P14 P13 P12 P11 P10 Parameter 1 (P1) Controls
built-in oscillator
Parameter 1 (P1)
P10: Row address normal/reverse
0: Normal
1: Reverse
P11: Column address normal/reverse
0: Normal (S1 to 3: Address 0, S526 to S528: Address 175)
1: Reverse (S1 to 3: Address 175, S526 to S528: Address 0)
P12: Selects oscillation clock output built into the OSCO pin
Usually, it is used by Hi-Z. When making it output, It recommends connecting the capacitor of 1uF to
VOSC pin.
0: Hi-Z
1: Output
P13: Selects the address scan direction when display data is written into (or read from) the RAM from the
MPU interface. When the RGB interface is used, select “Incremented when written (or read) in the
column address direction”.
0: Incremented when written (or read) in the column address direction.
1: Incremented when written (or read) in the row address direction.
P14: Sets the assignment order of RGB corresponding to the order of S1, S2, S3….pins.
0: RGB (S1:R S2:G S3:B ꢁ ꢁ ꢁ S528:B)
1: BGR (S1:B S2:G S3:R ꢁ ꢁ ꢁ S528:R)
P15: Selects the number of bits of display data when display data is written into (or read from) the RAM when
the MPU interface is 16-bit parallel.
0: 16 bits × 1 time
1: 16 bits × 2 times
With P16:15, select each data format of the 1st and 2nd transfer when set to 16 bits × two times.
0: 1st transfer 2 bits, 2nd transfer 16 bits
1: 1st transfer 16 bits, 2nd transfer 2 bits
P17: Selects oscillator.
0: Uses the built-in oscillator.
1: Does not use the built-in oscillator (but enters external clocks via the OSCI pin. It is an object for a
test.)
76
EPSON
S1D19105 Series (Rev.1.1)
7. COMMANDS
(6) Set Start Address (Command code: 15h, Parameter: 2 bytes)
Sets the access start address of the display RAM.
D17 D16 D15 D14 D13 D12 D11 D10
Function
Command Set Start Address
0
0
0
1
0
1
0
1
P17 P16 P15 P14 P13 P12 P11 P10 Parameter 1 (P1) Column Address
P27 P26 P25 P24 P23 P22 P21 P20 Parameter 2 (P2) Row Address
P17 P16 P15 P14 P13 P12 P11 P10
Column address
0
0
0
0
0
0
0
0
0
0
0
0
:
0
0
0
0
0
0
0
0
1
0
1
0
00H
01H
02H
:
1
1
0
0
0
1
0
0
1
1
1
1
1
1
0
1
AEH
AFH
P27 P26 P25 P24 P23 P22 P21 P20
Row address
0
0
0
0
0
0
0
0
0
0
0
0
:
0
0
0
0
0
0
0
0
1
0
1
0
00H
01H
02H
:
1
1
0
1
1
0
0
1
1
1
1
0
1
1
0
1
DAH
DBH
(7) Set End Address (Command code: 75h, Parameter: 2 bytes)
Sets the access end address of the display RAM. After receiving the command, the setting is enabled
immediately.
D17 D16 D15 D14 D13 D12 D11 D10
Function
Command Set End Address
0
1
1
1
0
1
0
1
P17 P16 P15 P14 P13 P12 P11 P10 Parameter 1 (P1) Column Address
P27 P26 P25 P24 P23 P22 P21 P20 Parameter 2 (P2) Row Address
The setting range is the same as the start address. However, the start address < the end address must be true.
(8) RAM Write (Command code: 5Ch, Parameter: unlimited)
___
Automatically increments the address based on the WR signal after command input, and writes parameters as
the data into the display data RAM. When a command is entered, the column and row addresses are set to their
start address. Any number of bytes of parameters can be written until the next command is entered. When the
write address reaches the end address, it is returned to the start address.
The relationship between the parameter (display data) bit length and pins varies depending on the interface used
as described in 6.2.3.
D17 D16 D15 D14 D13 D12 D11 D10
Function
0
1
0
1
1
1
0
0
Command RAM Write
*
*
*
*
*
*
*
*
Parameter Specifies data to be written into the display RAM.
S1D19105 Series (Rev.1.1)
EPSON
77
7. COMMANDS
(9) RAM Read (Command code: 5Dh, Parameter: unlimited)
___
Automatically increments the address based on the RD signal after command input, and reads data from the
display RAM. When a command is entered, the column and row addresses are set to their start address. The data
reading is continued until the next command is entered. Any number of bytes of data can be read. When the read
address reaches the end address, it is returned to the start address.
The relationship between the parameter (display data) bit length and pins varies depending on the interface used
as described in 6.2.3.
D17 D16 D15 D14 D13 D12 D11 D10
Function
0
1
0
1
1
1
0
1
Command RAM Read
Parameter Specifies data to be read from the display RAM
*
*
*
*
*
*
*
*
(10) Read-Modify-Write (Command code: E0h, Parameter: unlimited)
This command makes both RAM Write and RAM Read executable and reduces the CPU load when the RAM
area data is repeated to change. If the memory is set to the Read-Modify-Write status by the
___
Read-Modify-Write command, the addresses are NOT incremented automatically by the read signal (RD for
___
80-series) until it is released. It is incremented only by the write signal (WR for 80-series). This state is
canceled when another command is entered. When the Read-Modify-Write status is released, control is returned
to the address specified by the Set Start Address command before status change.
D17 D16 D15 D14 D13 D12 D11 D10
Function
Command Read-Modify-Write
1
1
1
0
0
0
0
0
Set Start Address
Set End Address
Read-Modify-Write In
Dummy Read
Read Data
Write Data
NO
End the change?
YES
Next command
78
EPSON
S1D19105 Series (Rev.1.1)
7. COMMANDS
(11) Set Area Scrolling (Command code: AAh, Parameter: 4 bytes)
Makes settings for partially scrolling the screen in the row direction. With this command and the following 4
parameters, type of area scroll, fixed area and scroll area can be set.
D17 D16 D15 D14 D13 D12 D11 D10
Function
Command Set Area Scrolling
1
0
1
0
1
0
1
0
P17 P16 P15 P14 P13 P12 P11 P10 Parameter 1 (P1) Scroll Start Line Address
P27 P26 P25 P24 P23 P22 P21 P20 Parameter 2 (P2) Scroll End Line Address
P37 P36 P35 P34 P33 P32 P31 P30 Parameter 3 (P3) Number of Scroll Lines
*
*
*
*
*
*
P41 P40 Parameter 4 (P4) Scroll Mode
Parameter (P1): Specifies the scroll start line address of the RAM to be assigned to the scroll area. For top area
and the full-screen scrolling, set it to the 0 address. The display start line address is also set to
this scroll start line address until it is set with the Display Start Line command.
Parameter 2 (P2): Specifies the scroll end line address of the RAM to be assigned to the scroll area. For bottom
area and the full-screen scrolling, set it to the 219 addresses. Keep the scroll start line address
< scroll end line address true.
Parameter 3 (P3): Sets the value to the number of scroll lines.
Sets the value to the number of display lines (set by P3 of Set Display) subtracted by the
number of display lines in the bottom fixed area. For the bottom area and the full-screen
scrolling, set it to any value (the set value is ignored).
Parameter (P4): Selects an area scroll mode.
P41
0
0
1
1
P40
0
1
0
1
Area scroll type
The center area can be scrolled
The top area can be scrolled
The bottom area can be scrolled
The full-screen can be scrolled
An area can be scrolled only after the Set Area Scroll command has been issued and the display start address has
been set by the Display Start Line command.
[Area scroll setup example]
Conditions: Set the number of display lines to 220 and scroll the center window. Also, select 16 lines for the top
fixed area and 8 lines for the bottom fixed area.
D17 D16 D15 D14 D13 D12 D11 D10
Function
Set Area Scrolling
Scroll start address (16)
Scroll end address (219 - 8 = 211)
Number of scroll lines (219 - 8 = 211)
Scroll mode
1
0
1
1
*
0
0
1
1
*
1
0
1
0
*
0
1
0
0
*
1
0
1
0
*
0
0
1
1
*
1
0
1
1
0
0
0
1
1
0
S1D19105 Series (Rev.1.1)
EPSON
79
7. COMMANDS
(12) Set Display Start Line (Command code: ABh, Parameter: 1 byte)
Sets the display start line address of the display RAM. From the scroll area addresses specified by this
command, select the display start address. If this command is repeated in a certain cycle, the window can be
scrolled dynamically.
D17 D16 D15 D14 D13 D12 D11 D10
Function
Command Set Display Start Line
1
0
1
0
1
0
1
1
P17 P16 P15 P14 P13 P12 P11 P10 Parameter Display start line address
(13) Partial Display In (Command code: A8h, Parameter: 3 bytes)
Used to partially display the screen (by line division) to reduce the power consumption.
D17 D16 D15 D14 D13 D12 D11 D10
Function
Command Partial In
1
0
1
0
1
0
0
0
P17 P16 P15 P14 P13 P12 P11 P10 Parameter 1 (P1) Partial Display Start Line
P27 P26 P25 P24 P23 P22 P21 P20 Parameter 2 (P2) Partial Display End Line
P37 P36 P35 P34 P33 P32 P31 P30 Parameter 3 (P3) Frame frequency in the
non-display area
From the number of display lines specified by parameter P3 of the Set Display command, set the partial display
address using P1 and P2. (It is NOT the line address. It is the display line of the panel, beginning from line
number 0. See below.) P3 sets the number of off voltage write frames during the period of the partial non-display
and the partial type.
Line 1
Line 2
Line 3
Line 4
ꢁꢁꢁ
Line 219
Line 220
When the number of display lines is 220
Parameter 1 (P1): Specifies the partial display start line number subtracted by 1 of the above line.
Example: To start partial display at line 1, specify 0.
To start partial display at line 4, specify 3.
Parameter 2 (P2): Specifies the partial display end line number subtracted by 1 of the above line.
Example: To end partial display at line 15, specify 14.
Parameter 3 (P3): Sets the non-display area refresh rate and drive voltage at the time of refreshment.
P36 to 30: Sets the frame frequency that refreshes the partial non-display area to 1/N in the display area. For
both source and common, the drive voltage when not refreshed is set to Hi-Z state.
0000000 : 1
0000001 : 1/3
0000010 : 1/5
0000011 : 1/7
ꢁ
1111110 : 1/253
1111111 : Does not refresh
80
EPSON
S1D19105 Series (Rev.1.1)
7. COMMANDS
P37: Switches mode between VDDHS/VSS mode and V /V63 mode. Since no gray scale amplifier is used in
0 to6V3 62 gray scale voltage is stopped.
V
DDHS/VSS mode, power consumption is lowered.0 In V /V mode, display with less power used is also
possible, because the gray scale amplifier that generates V
1
D/DVH6S3 mSoSde.
0: Sets to V
1: Sets to V
/V mode.
0
(14) Partial Display Out (Command code: A9h, Parameter: None)
The Partial Out command cancels the partial display and returns to the normal display mode. After receiving the
command, the setting is enabled from the next frame.
D17 D16 D15 D14 D13 D12 D11 D10
Function
Command Partial Display Out
1
0
1
0
1
0
0
1
(15) Set Display Data Interface (Command code: 31h, Parameter: 1 byte)
Sets the operation state of the display interface. After receiving the command, the setting is enabled immediately.
D17 D16 D15 D14 D13 D12 D11 D10
Function
0
0
1
1
0
0
0
1
Command Set Display Data Interface
P17 P16 P15 P14 P13 P12 P11 P10 Parameter 1 (P1) Sets display interface
P22 P21 P20 Parameter 2 (P2) Dividing ratio of DOTCLK
*
*
*
*
*
Parameter 1 (P1): Sets the operation mode and bus width of the display interface.
P12 to P10:
P12
0
0
P11
0
0
P10
0
1
Data transfer mode
Normal MPU data transfer
0
1
1
1
1
0
0
1
1
0
1
1
VSYNC Interface
RGB transfer 1
RGB transfer 2
RGB transfer 3
Setting disabled
*
1
0
The period beyond 1H is required for the change of a display interface between the last
display line and VSYNCI.
P13 0: At the rising edge of the DOTCLK, data is read.
1: At the falling edge of the DOTCLK, data is read.
P15, P14:
P15
0
0
1
1
P14
0
1
0
1
RGB interface bus width
18 bits (1 dot transferred in 1 step)
16 bits (1 dot transferred in 1 step)
6 bits (1 dot transferred in 3 steps)
Setting disabled
P16: ENABLE
0: LOW enabled.
1: HIGH enabled.
P17: HSYNC, VSYNC
0: LOW enabled.
1: HIGH enabled.
S1D19105 Series (Rev.1.1)
EPSON
81
7. COMMANDS
Parameter 2 (P2): Determines the dividing ratio of DOTCLK.
If the display RAM is written at a high speed using DOTCLK as display clock, the display
timing may not be set properly. In this case, set the division ratio to specify an appropriate
value for the display timing. The clock to be set for each command parameter is a clock after
division. The count value of division is reset at the beginning of each line.
P22
0
0
P21
0
0
P20
0
1
Division ratio
Division is not done.
1/2 division
0
0
1
1
0
1
1/3 division
1/4 division
1
1
0
0
0
1
1/5 division
1/6 division
1
1
1
1
0
1
1/7 division
1/8 division
(16) Set Display Color Mode (Command code: 8Bh, Parameter: 4 bytes)
Sets the maximum number of display colors. After receiving the command, the setting is enabled from the next
frame.
Switching between 262K-color mode and 8-color mode is available using the Set Display Color Mode command
parameter. Only the MSB in the display RAM is used as the gray scale data used for display.
D17 D16 D15 D14 D13 D12 D11 D10
Function
1
*
*
*
*
0
0
0
1
*
*
*
*
0
1
1
Command Set Display Color Mode
*
*
*
P12 P11 P10 Parameter 1 (P1) Maximum number of display color
P22 P21 P20 Parameter 2 (P2) Sets gray scale amplifier ability
P32 P31 P30 Parameter 3 (P3) Sets bias circuit ability
P26 P25 P24
P36 P35 P34
P46 P45 P44
P42 P41 P40 Parameter 4 (P4) Sets the boosting frequency.
Parameter 1 (P1):
P11, 10: Switches mode between VDDHS/VSS mode and V /V mode. Since no gray scale amplifier is used
also DpoDsHsSible, because the gray scale amplifier that generates 0V to V62 gray scale voltage is stopped.
in V
/VSS mode, power consumption is lowered.0 I6n3V /V63 mode, display with less power used is
D/DVHS mSoSde when P11 is set to 1. It is invalid when P11 is set to 0.
P10: 0 Specifies 8-color V
/V mode when P11 is set to 11. It is invalid when P11 is set to 0.
P11:0 Sets the maximum num6b3er of display colors to 262K colors.
P10: 1 Specifies 8-color V
0
P11:1 Sets the maximum number of display colors to 8 colors.
P12: Sets whether or not to boost VCOMH and V
in the 8-color-display area similarly to P53 (boosting
of VCOMH and VCOML) of Set Display TimiCnOg.ML
0: Not boost
1: Boost
Parameter 2 (P2) to Parameter 3 (P3): Sets power control of the 8-color display. It is valid only when P11 = 1.
Parameter 2 (P2): See PC of power control.
Parameter 3 (P3): See PD of power control.
Parameter 4 (P4): Sets frequency of the boosting clock of the 1st - 4th booster in 8-color display area.
P42 to P40: Sets frequency of the boosting clock of the 1st and 2nd boosters in the 8-color display area.
P46 to P44: Sets frequency of the boosting clock of the 3rd and 4th boosters in the 8-color display area.
Determine while checking the display.
P42, P46 P41, P45 P40, P44
Frequency
82
EPSON
S1D19105 Series (Rev.1.1)
7. COMMANDS
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
= Stop (disable)
= Frequency in 1H
= Frequency in 1H
= Frequency in 1H
= Frequency in 1H
= Frequency in 1H / 2
= Frequency in 1H / 4
= Frequency in 1H / 8
×
×
×
×
8
4
2
1
(17) Set Gate Line Scan Mode (Command code: 6Fh, Parameter: 3 bytes)
Sets the line scan mode of the gate driver.
Be sure to enter before the Sleep Out command.
D17 D16 D15 D14 D13 D12 D11 D10
Function
Command Set Gate Line Scan Mode
P11 P10 Parameter 1 (P1) Scan Mode
0
*
1
*
1
*
0
*
1
P13
1
*
1
1
P27 P26 P25 P24 P23 P22 P21 P20 Parameter 2 (P2) Number of Scan Start Line
P37 P36 P35 P34 P33 P32 P31 P30 Parameter 3 (P2) Number of Scan End Line
Parameter 1 (P1): Sets the gate line scan mode.
P11
0
0
1
1
P10
0
1
0
1
Mode
Interlace drive
Up and down drive 1
Up and down drive 2
Setting disabled
P13: 0 Normal direction scan
1 Reverse direction scan
Parameter 2 (P2): Sets the gate scan start line subtracted by 1.
Parameter 3 (P3): Sets the gate scan end line subtracted by 1.
S1D19105 Series (Rev.1.1)
EPSON
83
7. COMMANDS
G1
G110
G220
G1
P2
Middle
point
G110
G220
P3
Interlace drive
(normal direction)
Up and down drive
(normal direction)
It needs to be completely in agreement with P5 (the number of display dots) of display set command. It cannot
respond to the panel of odd lines. Refer to the 6.6th clause for the details about the setting method.
(18) Set AC Operation Drive (Command code: 8Ch, Parameter: 2 bytes)
Sets the AC operation drive state. After receiving the command, the setting is enabled from the next frame.
D17 D16 D15 D14 D13 D12 D11 D10
Function
1
*
*
0
*
*
0
*
*
0
*
*
1
1
0
0
Command Set AC Operation Drive
*
*
P11 P10 Parameter 1 (P1) AC operation mode
P23 P22 P21 P20 Parameter 2 (P2) n-line reverse
Parameter 1 (P1): Sets the AC operation mode.
P11
0
0
P10
0
1
AC operation mode
n-line reverse driving
Frame reverse driving
Interlace drive
1
0
1
1
Setting disabled
Parameter 2 (P2): Sets the number of lines for n-line reverse driving subtracted by 1.
84
EPSON
S1D19105 Series (Rev.1.1)
7. COMMANDS
(19) Set Electronic Control (Command code: 20h, Parameter: 7 bytes)
Determines the output voltage of each voltage regulator of the built-in power circuit.
D17 D16 D15 D14 D13 D12 D11 D10
Function
Command Set Electronic Control
0
*
*
*
*
*
*
*
*
0
*
*
*
*
*
*
*
*
1
0
0
0
0
0
*
P14 P13 P12 P11 P10 Parameter 1 (P1)
V
V
DDHS
P25 P24 P23 P22 P21 P20 Parameter 2 (P2)
COMH
*
*
*
*
*
*
P34 P33 P32 P31 P30 Parameter 3 (P3) VCA, VCOMW
P44 P43 P42 P41 P40 Parameter 4 (P4)
P54 P53 P52 P51 P50 Parameter 5 (P5)
P64 P63 P62 P61 P60 Parameter 6 (P6)
P74 P73 P72 P71 P70 Parameter 7 (P7)
VONREG
VOFREG
VDDRH
VDDRL
VLDO
*
*
P82 P81 P80 Parameter 7 (P8)
Parameter 1 (P1) to Parameter 7 (P8): Sets the output voltage of each voltage reagulator
.
EVR
0
V
COMH
V
DDHS
V
DDRH
V
OFREG
V
COMW
VCA
1.5
V
ONREG
V
DDRL
V
LDO
EVR
32(20h)
V
COMH
2
2.7
2.7
2
3.0
0.0
0
3
4.4
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
2.075
2.15
2.225
2.8
2.9
3
2.8
2.9
3
2.1
2.2
2.3
2.4
2.5
2.6
2.7
2.8
2.9
3
3.1
3.2
3.3
3.4
3.5
3.6
3.7
3.8
3.9
4
4.1
4.2
4.3
4.4
4.5
4.6
4.7
4.8
4.9
5
3.1
3.2
3.3
1.55
1.6
1.65
1.7
1.75
1.8
1.85
1.9
1.95
2
2.05
2.1
2.15
2.2
2.25
2.3
2.35
2.4
2.45
2.5
2.55
2.6
2.65
2.7
2.75
2.8
2.85
2.9
2.95
3
3.05
0.2
0.4
0.05
0.1
2.95
2.9
33(21h) 4.475
34(22h) 4.55
35(23h) 4.625
36(24h) 4.7
37(25h) 4.775
38(26h) 4.85
39(27h) 4.925
40(28h)
0.6
0.8
1.0
1.2
1.4
1.6
1.8
2.0
2.2
2.4
2.6
2.8
3.0
3.2
3.4
3.6
3.8
4.0
4.2
4.4
4.6
4.8
5.0
5.2
5.4
5.6
5.8
6.0
6.2
0.15
0.2
0.25
0.3
0.35
0.4
0.45
0.5
0.55
0.6
0.65
0.7
0.75
0.8
0.85
0.9
0.95
1
1.05
1.1
1.15
1.2
1.25
1.3
1.35
1.4
1.45
1.5
2.8
2.7
2.6
2.55
2.5
2.3
2.375
2.45
2.525
2.6
2.675
2.75
2.825
2.9
2.975
3.05
3.125
3.2
3.275
3.35
3.425
3.5
3.575
3.65
3.725
3.8
3.875
3.95
4.025
4.1
3.1
3.2
3.3
3.4
3.5
3.6
3.7
3.8
3.9
4
4.1
4.2
4.3
4.4
4.5
4.6
4.7
4.8
4.9
5
5.1
5.2
5.3
5.4
5.5
5.6
5.7
5.8
3.1
3.2
3.3
3.4
3.5
3.6
3.7
3.8
3.9
4
4.1
4.2
4.3
4.4
4.5
4.6
4.7
4.8
4.9
5
5.1
5.2
5.3
5.4
5.5
5.6
5.7
5.8
3.4
3.5
3.6
3.7
3.8
3.9
4.0
4.1
4.2
4.3
4.4
4.5
4.6
4.7
4.8
4.9
5.0
5.1
5.2
5.3
5.4
5.5
5.6
5.7
5.8
5.9
6.0
6.1
5
41(29h) 5.075
42(2Ah) 5.15
43(2Bh) 5.225
44(2Ch)
5.3
45(2Dh) 5.375
46(2Eh) 5.45
47(2Fh) 5.525
48(30h)
49(31h) 5.675
50(32h) 5.75
51(33h) 5.825
52(34h) 5.9
5.6
53(35h) 5.975
54(36h) 5.975
55(37h) 5.975
56(38h) 5.975
57(39h) 5.975
58(3Ah) 5.975
59(3Bh) 5.975
60(3Ch) 5.975
61(3Dh) 5.975
62(3Eh) 5.975
63(3Fh) 5.975
4.175
4.25
4.325
5.1
1.55
The above values are calculated values only and no guarantee on them is offered. In reality, since computations
are performed based on VREG and output to the regulator, variations in V
and regulators are included.
For VCOMH, the output voltage can be adjusted with the external resistoRr.EG There is connection way that can be
half voltage of VCOMW.
S1D19105 Series (Rev.1.1)
EPSON
85
7. COMMANDS
(20) Set γ Correction Characteristics (Command code: 22h, Parameter: 12 bytes)
Sets gray scale voltage according to the γ characteristics of the LCD panel.
D17 D16 D15 D14 D13 D12 D11 D10
Function
γ Correction Characteristics
0
0
1
0
0
0
1
0
Command Set
P17 P16 P15 P14 P13 P12 P11 P10 Parameter 1 (P1)
V
V
V
V
V
V
RP3
RP2
P2
V
V
RP0
*
*
*
*
*
P26 P25 P24
P36 P35 P34
P46 P45 P44
P56 P55 P54
P66 P65 P64
*
*
*
*
*
P22 P21 P20 Parameter 2 (P2)
P32 P31 P30 Parameter 3 (P3)
P42 P41 P40 Parameter 4 (P4)
P52 P51 P50 Parameter 5 (P5)
P62 P61 P60 Parameter 6 (P6)
RP1
V
V
V
V
P1
P3
P5
P7
P4
P6
P8
Parameter 1 (P1): Positive polarity side tilt adjustment register VRP3 and VRP0
Parameter 2 (P2): Positive polarity side tilt adjustment register VRP2 and VRP1
Parameter 3 (P3): Positive polarity side fine adjustment selector VP2 and VP1
Parameter 4 (P4): Positive polarity side fine adjustment selector VP4 and VP3
Parameter 5 (P5): Positive polarity side fine adjustment selector VP6 and VP5
Parameter 6 (P6): Positive polarity side fine adjustment selector VP8 and VP7
Setting the positive polarity automatically sets the negative polarity to be symmetrical.
For details on how to set, see section 6.11 “Gray scale Voltage Generation Circuit”.
86
EPSON
S1D19105 Series (Rev.1.1)
7. COMMANDS
(21) Set Power Control (Command code: 21h, Parameter: 13 bytes)
Sets ON or OFF of a function and ability of power circuit. The setup is performed automatically and sequentially
with the Sleep Out command in accordance with the setting of this command.
D17 D16 D15 D14 D13 D12 D11 D10
Function
Command Set Power Control
0
0
1
0
0
0
0
1
P17 P16 P15 P14 P13 P12 P11 P10 Parameter 1 (P1) Wait 1 and 2 (Sleep Out)
P27 P26 P25 P24 P23 P22 P21 P20 Parameter 2 (P2) Wait 3 and 4 (Sleep Out)
*
*
*
*
*
P33 P32 P31 P30 Parameter 3 (P3) Booster circuit control, etc.
P47 P46
P44 P43 P42 P41 P40 Parameter 4 (P4) Regulator circuit control 1
P57 P56 P55 P54 P53 P52 P51 P50 Parameter 5 (P5) Regulator circuit control 2
P67 P66 P65
*
*
*
*
*
*
Parameter 6 (P6) Regulator circuit control 3
*
P76 P75 P74
P72 P71 P70 Parameter 7 (P7) Sets pre-buffer ability
P87 P86 P85 P84 P83 P82 P81 P80 Parameter 8 (P8) Gray scale amplifier control 1
P91 P90 Parameter 9 (P9) Gray scale amplifier control 2
PA7 PA6 PA5 PA4 PA3 PA2 PA1 PA0 Parameter A (PA) Gray scale amplifier output Hz1
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
PB1 PB0 Parameter B (PB) Gray scale amplifier output Hz2
PC6 PC5 PC4
PD6 PD5 PD4
PC2 PC1 PC0 Parameter C (PC) Sets gray scale amplifier ability
PD2 PD1 PD0 Parameter D (PD) Sets bias circuit ability
Parameter 1 (P1): Sets Wait 1 or 2 during Sleep Out
Parameter 2 (P2): Sets Wait 3 or 4 during Sleep Out
P10 to P13: Wait 1
P14 to P17: Wait 2
P20 to P23: Wait 3
P24 to P27: Wait 4
0000: No wait
0001: 1 frame
0010: 2 frames
ꢁ
1111: 15 frames
Parameter 3 (P3): P33 to P30 booster circuit VLDO ON/OFF control
P30: 0
: 1
V
LDO OFF
V
LDO ON
0: Booster circuit OFF
1: Booster circuit ON
P31: 1st and 2nd booster circuit
P32: 3rd booster circuit
P33: 4th booster circuit
Parameter 4 (P4): Regulator circuit ON/OFF control 1
0: Regulator OFF
1: Regulator ON (Cancels discharge and turns the regulator ON.)
P41: VDDHS
P40: V
P42: VOFREG
P43: VONREG
P44: VDDDDRRLH
S1D19105 Series (Rev.1.1)
EPSON
87
7. COMMANDS
P47, P46: Sets the reference voltage. Sets to VREG1
.
P47
0
0
1
1
P46
0
1
0
1
Reference voltage
V
REG Voltage
Setting
Valid
Setting disabled
Setting disabled
Setting disabled
V
V
V
REG1
REG2
REG3
3.5V
3.5V
3.5V
-
Setting disabled
Parameter 5 (P5): Regulator circuit ON/OFF control 2
0: Regulator OFF
1: Regulator ON (Cancels discharge and turns the regulator ON.)
P50: VCOMH
P51: Set to 0.
P53: VCCOOMML
P52: V
For testing.
P54: Fixes at 0 (Resistor built into VCOMH is ON.)
COMH and VCOML ability adjustment (for testing) Specify 0. For testing.
V
P55: 1 CCUT2 With no guaranteed phase capacityC(OVMCHOMH only)
P56: 0 BST2 Normal
P55: 0 CCUT2 With guaranteed phase capacity (V
only)
P56: 1 BST2 Ability UP
P57: 0 LPOW2 Normal
P57: 1 LPOW2 Low power
Parameter 6 (P6): Regulator circuit ability control 3
V
ONREG and VOFREG ability adjustment (for testing) Set to 0. For testing.
P65: 0 CCUT1 With guaranteed phase capacity
P65: 1 CCUT1 With guaranteed phase capacity
P66: 0 BST1 Normal
P66: 1 BST1 Ability UP
P67: 0 LPOW1 Normal
P67: 1 LPOW1 Low power
Parameter 7 (P7): Sets the pre-buffer ability of each source output pin. Specify 100.
P72 to P70: P bias
P76 to P74: N bias
P72/P76 P71/P75 P70/P74 Pre-buffer current consumption ratio
0
0
0
0
0
1
0
1
0
3
2.5
2
0
1
1
1
1
1
0
0
1
1
1
0
1
0
1
1.5
1
0.75
0.5
0.25
88
EPSON
S1D19105 Series (Rev.1.1)
7. COMMANDS
Parameter 8 (P8): Gray scale amplifier control 1
Enables 10 gray scale amplifiers by combining with the parameter A.
Specify 1 for all.
P87
V
P86
V
P85
V
P84
V
P83
V
P82
V
P81
V
P80
VOP1
OP8
OP7
OP6
OP5
OP4
OP3
OP2
Parameter 9 (P9): Gray scale amplifier control 2
Enables 10 gray scale amplifiers by combining with the parameter B.
Specify 1 for all.
P91
P90
VOPH
V
OPL
Parameter A (PA): Gray scale amplifier output Hz control 1
Enables 10 gray scale amplifiers by combining with the parameter 8.
Specify 1 for all.
PA7
PA6
PA5
PA4
PA3
PA2
PA1
PA0
VOP1
V
OP8
V
OP7
V
OP6
V
OP5
V
OP4
V
OP3
V
OP2
Parameter B (PB): Gray scale amplifier output Hz control 2
Enables 10 gray scale amplifiers by combining with the parameter 9.
Specify 1 for all.
PB1
PB0
VOPH
V
OPL
Parameter C (PC): Set gray scale amplifier ability
Sets the ability of the gray scale amplifier.
Specify 001.
PC2 to PC0: Auxiliary
PC6 to PC4: Main
PC2/PC6 PC1/PC5 PC0/PC4 Gray scale amplifier current consumption ratio
0
0
0
0
1
1
1
0
0
1
1
0
0
1
0
1
0
1
0
1
1
0.0 (Stop)
1
1
2
0.5
1.5
2.5
Parameter D (PD): Set bias circuit ability
Sets the bias ability given to the gray scale amplifier.
Please set it to follows. PD2 to PD0 : 100, PD6 to PD4: 100
S1D19105 Series (Rev.1.1)
EPSON
89
7. COMMANDS
PD2 to PD0 : for VREFN
PD2
PD1
0
PD0
0
Gray scale amplifier current consumption ratio
0
0.0 (Stop)
0
0
0
1
1
0
4
2
0
1
1
0
1
0
1.33
1
1
1
1
0
1
1
1
0
1
0.8
0.67
0.57
PD6 to PD4 : for VREFP
PD6
0
PD5
0
PD4
0
Gray scale amplifier current consumption ratio
0.0 (Stop)
0
0
0
1
1
0
4
2
0
1
1
0
1
0
1.33
1
1
1
1
0
1
1
1
0
1
0.8
0.67
0.57
(22) Set Partial Power Control (Command code: 23h, Parameter: 7 bytes)
Power supply setup of the non-display area at the time of partial display is performed. P1 to P5 can set the state
of the power supply circuit of the period for which non-display area is not refreshed etc. P6 and P7 can set the
state of the power supply circuit of the refreshment period of non-display area etc.
D17 D16 D15 D14 D13 D12 D11 D10
Function
0
*
*
*
0
1
0
0
*
*
0
1
1
Command Partial Power control
*
*
P14
P12 P11 P10 Parameter 1 (P2) Sets VCOM ability
P22 P21 P20 Parameter 2 (P2) Sets the boosting cycle
P26 P25 P24
*
*
P34 P33 P32 P31 P30 Parameter 3 (P3) Regulator circuit control 1
*
*
Parameter 1 (P1): Sets the recovery time and partial mode.
P12 to P10: Specifies the time at which power control returns, i.e., how many hours before driving the display
line.
000: 0H
001: 1H
010: 2H
ꢁ
111: 7H
P14: Sets whether or not to boost VCOMH and VCOML in the non-display area similarly to P53 (boosting of
V
COMH and VCOML) of Set Display Timing.
0: Not boost
1: Boost
Parameter 2 (P2): Sets frequency of the boosting clock of the 1st - 4th booster in the non-display area.
P22 to P20: Sets frequency of the boosting clock of the 1st and 2nd boosters in the non-display area.
P26 to P24: Sets frequency of the boosting clock of the 3rd and 4th boosters in the non-display area.
90
EPSON
S1D19105 Series (Rev.1.1)
7. COMMANDS
Determine while checking the display.
P22/P26
P21/P25
P20/P24
Frequency
= Stop
= Frequency in 1H
= Frequency in 1H
= Frequency in 1H
= Frequency in 1H
= Frequency in 1H / 2
= Frequency in 1H / 4
= Frequency in 1H / 8
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
×
×
×
×
8
4
2
1
Parameter 3 (P3) to Parameter 7 (P7): Sets power control of non-display area.
Discharge is not carried out even if it is set to OFF.
Parameter 3 (P3): See P4 of power control. However, VREG of P47 and P46 cannot be selected.
Parameter 4 (P4): See P5 of power control. However, VCOMH built-in resistor On of P54 cannot be selected.
same VCOM sCigOnMaHl as a display area is genCeOraMted.
When P40(V
) P42(VCOML) P43 (V
) is set to 1, also in a non-displaying area, the
A non-displaying area is set to Hi-Z when P43 (VCOM) is set to 0.
Parameter 5 (P5): See P6 of power control.
Parameter 6 (P6): See PC of power control.
Parameter 7 (P7): See PD of power control.
S1D19105 Series (Rev.1.1)
EPSON
91
7. COMMANDS
(23) Sleep In (Command code: 95h, Parameter: none)
Automatic command that executes multiple commands. Turns the display off, discharges power supply after
displaying white, stops oscillation and puts into sleep state. After receiving the command, execution takes place
immediately.
D17 D16 D15 D14 D13 D12 D11 D10
Function
Command: Sleep In command
1
0
0
1
0
1
0
1
Sleep In
Display OFF
Discharge
White display (in case of normally white)
1 Frame
Stops the built-in power circuit and resets
the Discharge Power Control Register.
Oscillation stops
After this, in the state of VOSC stop
V
OSC STOP
Fig.47 Sleep In Time Chart
Sleep In
VSYNCO
Frame
S1 to S528
V
SS
SS
V
SS
SS
VCOM
V
V
G1 to G220
VSS 0V
VOSC
OSC
In VSYNC interface, RGB transfer 2 and RGB transfer 3, no Sleep In takes place with no external clock entered.
Be sure to enter the external clock. Change the MPU interface mode to cause Sleep In.
92
EPSON
S1D19105 Series (Rev.1.1)
7. COMMANDS
(24) Sleep Out (Command code: 94h, Parameter: none)
Automatic command that executes multiple commands. Starts VOSC and sequentially executes the Start
Oscillation and Power Control command. When the Display ON command is received following startup of the
built-in power supply. Displays starts from the beginning of the frame. If the Display ON command is received
before the built-in power supply starts, wait is set automatically and the frame is displayed from the beginning
after the built-in power supply is started. The boosting clock at the time of boost starting starts by 33h
irrespective of the setting value (P4) of the display set. Before Wait4 end, it changes into the setting value of a
display set automatically.
D17 D16 D15 D14 D13 D12 D11 D10
Function
Command: Sleep Out command
1
0
0
1
0
1
0
0
Sleep Out
V
OSC ON
V
OSC starts
Oscillation starts.
Power Control 1
Power Control 2
Power Control 3
Oscillation starts
Wait1
(Oscillation circuit
stabilization time)
The 1st and 2nd booster operation starts.
Wait2
(Booster circuit
stabilization time)
The operation of the VREG ON
and regulator starts.
Wait3
(Regulator circuit
stabilization time)
The operation of the 3rd and 4th booster starts.
Wait4
(Booster circuit
stabilization time)
When the Display On command is received, the
state of displaying from the beginning of a frame
is resulted from synchronization with the internal
frame.
State of display enabled
Set Start Address
Set End Address
RAM Write
Other setting
Display ON
Displays RAM data.
Once the Display ON command is issued, the display appears.
However, if the Display ON command is issued during the startup, the display appears after the startup of the
power supply (following the state of display enabled). If the Display On command is not issued, the state of
display enabled continues.
In VSYNC interface, RGB transfer 2 and RGB transfer 3, Sleep Out does not take place with no external clock
entered. To execute Sleep Out, it is recommended to start in MPU interface mode and switch to other mode
after Wait4.
S1D19105 Series (Rev.1.1)
EPSON
93
7. COMMANDS
1
Power
2
Power
Sleep Out
(standby)
Oscillation start
3
Power
Display ON
Wait2
Wait3
Wait4
S1 to S528
VCOM
G1 to G220
VSS
VOSC
OSC
VDDHS
VOUT
VOUM
VOUT /VOUM
VDDHG
VDDHG /VEE
VEE
Fig.48 Sleep Out Time Chart
94
EPSON
S1D19105 Series (Rev.1.1)
7. COMMANDS
(25) V
OFF (Command code: 97h, Parameter: none)
Stop VOCSOCRE regulator, VOSC and VREG1 to V
. To set standby with the IC powered, enter this command to
place in the state of low consumption. To RcEhGa3nge from the state of low consumption to the state of normal
operation, enter the VOSC On command.
D17 D16 D15 D14 D13 D12 D11 D10
Function
Command: VOSC OFF command
1
0
0
1
0
1
1
1
TEST3,4=HIGH, LOW: VCORE is normally OFF(VCORE is outside input)
the halt of VOCSOCRaEnd VREG1 to VREG3
.
Constantly V
is OFF then it does not do the control of VCORE. It does only
TEST3,4=LOW, LOW: VCORE automatic control(VCORE is inside generation)
It does the halt of VCORE, VOSC and VREG1 to VREG3
.
TEST3,4=LOW, HIGH: VCORE is normally ON (V
is inside generation)
the halt of VOCSOCRaEnd VREG1 to VREG3
.
Constantly V
is ON thenCitOdRoEes not do the control of VCORE. It does only
(26) VOSC ON (Command code: 96h, Parameter: none)
entereCdOfRoEr 10ms after entering the command.
Set V
to the state of normal operation and start VOSC and VREG1 to VREG3
.
Other commands cannot be
D17 D16 D15 D14 D13 D12 D11 D10
Function
Command: VOSC ON command
1
0
0
1
0
1
1
0
TEST3,4=HIGH, LOW: VCORE is normally OFF(VCORE is outside input)
the halt of VOCSOCRaEnd VREG1 to VREG3
.
Constantly V
is OFF then it does not do the control of VCORE. It does only
TEST3,4=LOW, LOW: VCORE automatic control(VCORE is inside generation)
VOCOSCRE is operating, it does only VOSC ON.
V
and VREG1 to VREG3 are ON in the command input when VCORE stop. In case of
TEST3,4=LOW, HIGH: VCORE is normally ON (V
is inside generation)
the halt of VOCSOCRaEnd VREG1 to VREG3
.
Constantly V
is ON thenCitOdRoEes not do the control of VCORE. It does only
(27) Stop Oscillation (Command code: 93h, Parameter: none)
Stops oscillation of the built-in oscillation circuit.
D17 D16 D15 D14 D13 D12 D11 D10
Function
Command : Stop Oscillation
1
0
0
1
0
0
1
1
(28) Start Oscillation (Command code: 92h, Parameter: none)
Starts oscillation of the built-in oscillation circuit.
D17 D16 D15 D14 D13 D12 D11 D10
Function
Command : Start Oscillation
1
0
0
1
0
0
1
0
S1D19105 Series (Rev.1.1)
EPSON
95
7. COMMANDS
(29) Test (Command code: FFh, Parameter: 7 bytes)
Sets the function test mode. This is used for testing at shipping. The customer cannot use this command.
P1 to P3 are enabled when the TEST 1 pin is set to HIGH.
D17 D16 D15 D14 D13 D12 D11 D10
Function
1
*
*
*
*
1
*
*
*
1
1
1
1
1
1
Command Test
P15 P14 P13 P12 P11 P10 Parameter 1 (P1) For VREG adjustment (TEST 1)
*
*
*
P23 P22 P21 P20 Parameter 1 (P2) Constant current adjustment (TEST 1)
P34 P33 P32 P31 P30 Parameter 3 (P3) Oscillation frequency adjustment (TEST 1)
P46 P45 P44 P43 P42 P41 P40 Parameter 4 (P4) Discharge control 1
P57 P56 P55 P54 P53 P52 P51 P50 Parameter 5 (P5) Discharge control 2
*
P77
*
*
P65 P64 P63 P62 P61 P60 Parameter 6 (P6) Gate driver test
P73 P72 P71 P70 Parameter 7 (P7) Detector test
*
*
Parameter 1 (P1): For VREG adjustment (When TEST 1 pin = LOW, this is disabled.)
Parameter 2 (P2): For internal constant current adjustment (When TEST 1 pin = LOW, this is disabled.)
Parameter 3 (P3): For oscillation frequency adjustment (When TEST 1 pin = LOW, this is disabled.)
Parameter 4 (P4): Individual control of discharge function
0: Discharge
1: No discharge
P40: VLDO
P41: 1st and 2nd boosters
P42: 3rd booster
P43: 4th booster
P45: VOSC
P44: V
P46: VRCOEGRE
Parameter 5 (P5): Individual control of discharge function
0: Discharge
1: No discharge
P51: VDDHS
P50: V
P52: VOFREG
P53: VONREG
P54: VDDRH
P55: VDDRL
P56: VCOMH
P57: VCCOOMML
Parameter 6 (P6) Test function of gate driver (The customer cannot use this pin.)
P60: All-pin HIGH
P61: Test 1
0: Normal operation 1: All-pin VDDHG (with time difference)
0: Normal operation 1: 1, 5, 9 …pin VDDHG
P63: Test 3
0: Normal operation 1: 3, 7, 11 …pin VDDHG
0: Normal operation 1: 2, 6, 10 …pin V
P62: Test 2
P64: Test 4
0: Normal operation 1: 4, 8, 12 …pin VDDDDHHGG
0: Normal operation 1: Full-output logic reverse
P65: Reverse
Parameter 7 (P7): Test function of detector and VSYNC synchronization cancellation function (The customer
cannot use this pin.)
P70: VDD2-series detector power saving
0: OFF
1: Normal operation
96
EPSON
S1D19105 Series (Rev.1.1)
7. COMMANDS
P71: VDD2-series detector power saving
0: Power-up
1: Normal operation
1: Normal operation
1: Normal operation
P72: VDD2-series detector power saving
0: OFF
P73: VDDI-series detector power-up
0: Power-up
P77: Cancels the function execution in synchronization with VSYNC of all commands.
0: Synchronized with VSYNC 1: Exectes immediately.
(30) NOP (Command code: 00h, Parameter: 0 byte)
This is a non-operation command. This command does not affect the system operation at all.
D17 D16 D15 D14 D13 D12 D11 D10
Function
Command: Non Operation command
0
0
0
0
0
0
0
0
(31) Status Read (Command code: E8h, Parameter: 3 bytes)
The internal state of the IC can be read.
D17 D16 D15 D14 D13 D12 D11 D10
Function
Command: Status Read
1
1
1
0
1
0
0
0
P17 P16 P15 P14 P13 P12 P11 P10 Status 1 (P1)
P27 P26 P25 P24 P23 P22 P21 P20 Status 2 (P2)
*
P36 P35 P34 P33 P32 P31 P30 Status 3 (P3)
Parameter 1 (P1):
P10: 1: Turns the display ON.
0: Turns the display OFF.
P11: 1: Sleep Out
0: Sleep In
P12: 1: Partial In
0: Partial Out
P13: 1: High-speed RAM write mode
0: Normal RAM Write
P14: 1: 8-color display mode
0: 262k-color display mode
P15: 1: Scans in row direction.
0: Scans in column direction.
P16: Area scroll mode P40
P17: Area scroll mode P41
Parameter 2 (P2):
P20 to 27: RAM line address
Parameter 3 (P3):
S1D19105 Series (Rev.1.1)
EPSON
97
7. COMMANDS
P30: 1: Source ON
0: Source OFF
P31: 1: Pre-buffer drive.
0: DAC drive:
0: VCOM boost OFF
P32: 1: V
boost ON
P33: WaitC1OM
P34: Wait 2
P35: Wait 3
P36: Wait 4
(32) Revision Read (Command code: E9, Parameter: none)
The command code is valid only at the serial interface mode.
___
Revision of the IC can be read. For the parallel interface, revision can be read by setting A0 to LOW and RD
to LOW without setting the command code.
D17 D16 D15 D14 D13 D12 D11 D10
Function
Command: Revision Read
1
1
1
0
1
0
0
1
(33) Soft Reset (Command code: 99, Parameter: none)
The same reset as hard reset can be used with this command without hard resetting.
D17 D16 D15 D14 D13 D12 D11 D10
Function
Command : Soft Reset
1
0
0
1
1
0
0
1
98
EPSON
S1D19105 Series (Rev.1.1)
7. COMMANDS
7.5 Instruction Setup Example (Reference)
7.5.1 Initial Setup to Display-ON (VCORE forceful ON, VCORE forceful OFF, VDC4 is 2.3V or more)
___
Reset
Set the RES pin to LOW.
Power (VDD and VDD2) ON
Release reset
1ms or more
___
Set the RES pin to HIGH.
1µs or more
Starting,
V
and reference voltage
of VREG1 OVSRC
V
OSC ON
100µ s or more
Set Gate Line Scan Mode
Set Data
Set Display
Initial setup before
turning on power
Set Display Timing
Set Electronic Control
Set Power Control
Sleep Out
Set Start Address
Set End Address
RAM Write
Wait4 = 4 frame or
more *1
Other Setting
State of Display ON enabled
After the state of Display ON enabled, display is enabled at any time. If the Display ON command is received
before the state of display enabled, wait takes place automatically until the state of Display ON enabled is
reached.
*1: Wait 4 is for reference. This value depends on the LCD panel lode, it should be decided after evaluation.
S1D19105 Series (Rev.1.1)
EPSON
99
7. COMMANDS
7.5.2 Initial Setup to Display-ON (VCORE forceful ON, VCORE forceful OFF, VDC4 is less than 2.3V,
V
ONREG is used)
___
Set the RES pin to LOW.
Reset
Power (VDD and VDD2) ON
Release reset
1ms or more
___
Set the RES pin to HIGH.
1µs or more
Starting, VOSC and reference voltage
of VREG1 to VREG3
V
OSC ON
100µs or more
Set Gate In Scan Mode
Set Data
Initial setup
before turning
on power
Set Display
Set Display Timing
Set Electronic Control (VONREG ≥ 2.3V)
Set Power Control
Sleep Out
150ms or more
V
ONREG changes into the target voltage
Electronic Control
or
Power Control
after 3rd and 4th boosting (VDDHG and
VEE) stabilized. When making it 0V,
V
ONREG is turned off by the power control
command.
Wait4 = 4 frame or
more *1
Set Start Address
Set End Address
RAM Write
Other setup
State of Display ON enabled
It can display at any time after which can be display turned on state. It is necessary for the state which can be
display turned on to have set VCONREG as the target voltage by the electronic volume or power control command.
The display ON command should perform after changing into the target voltage of VCONREG. However, when the
time of a display ON command being executed is during the automatic wait period after sleep out, it waits
automatically until a wait period expires.
*1: Wait 4 is for reference. This value depends on the LCD panel lode, it should be decided after evaluation.
100
EPSON
S1D19105 Series (Rev.1.1)
7. COMMANDS
7.5.3 Initial Setup to Display-ON (Normal use of VCORE, VDC4 is 2.3V or more)
___
Set the RES pin to LOW.
Reset
Power (VDD and VDD2) ON
Release reset
1ms or more
___
Set the RES pin to HIGH.
1µs or more
V
OSC ON
Starting VOSC
100µs or more
1µs or more
Soft reset
Set Gate In Scan Mode
Set Data
Initial setup
before turning
on power
Set Display
Set Display Timing
Set Electronic Control
Set Power Control
Sleep Out
Other setup
Set Start Address
Set End Address
RAM Write
Wait4 = 4 frame or
more *1
State of Display ON enabled
After the state of Display ON enabled, display is enabled at any time. If the Display ON command is received
before the state of display enabled, wait takes place automatically until the state of Display ON enabled is
reached.
*1: Wait 4 is for reference. This value depends on the LCD panel lode, it should be decided after evaluation.
S1D19105 Series (Rev.1.1)
EPSON
101
7. COMMANDS
7.5.4 Initial Setup to Display-ON (Normal use of VCORE, VDC4 is less than 2.3V and VONREG is
used)
__
Set the RES pin to LOW.
Reset
Power (VDD and VDD2) ON
Release reset
1ms or more
__
Set the RES pin to HIGH.
1µs or more
Starting VOSC
V
OSC ON
100µs or more
1µs or more
Soft reset
Set Gate In Scan Mode
Set Data
Initial setup
before turning
on power
Set Display
Set Display Timing
Set Electronic Control
Set Power Control
Sleep Out
150 ms or more
V
ONREG changes into the target voltage
Electronic Control
or
Power Control
after 3rd and 4th boosting (VDDHG and
VEE) stabilized. When making it 0V,
V
ONREG is turned off by the power control
command.
Wait4 = 4 frame or
more *1
Set Start Address
Set End Address
RAM Write
Other setup
State of Display ON enabled
It can display at any time after which can be display turned on state. It is necessary for the state which can be
display turned on to have set VCONREG as the target voltage by the electronic volume or power control command.
The display ON command should perform after changing into the target voltage of VCONREG. However, when the
time of a display ON command being executed is during the automatic wait period after sleep out, it waits
automatically until a wait period expires.
*1: Wait 4 is for reference. This value depends on the LCD panel lode, it should be decided after evaluation.
102
EPSON
S1D19105 Series (Rev.1.1)
7. COMMANDS
7.5.5 Power OFF Sequence
Sleep In
Display OFF
Discharge
White display (for normally white)
4 frames or more
Automatic execution
The stop of a built-in power supply circuit,
reset of a discharge power control register
Stop oscillation
Stop VOSC
After this, the state of VOSC OFF
It becomes low power status (standby).
Stop VREG1 to 3.
V
OSC OFF
For TEST3 = L and TEST4 = L, stop
V
CORE and discharge.
Power (VDD and VDD2) OFF
Note: To turn ON power again, perform the power ON sequence from reset.
S1D19105 Series (Rev.1.1)
EPSON
103
8. ABSOLUTE MAXIMUM RATINGS
8. ABSOLUTE MAXIMUM RATINGS
Table 33 Absolute Maximum Ratings
V
Unit
SS=0V
Parameter
Symbol
Rating
-0.3 to +4.6
-0.3 to +3.3
-0.3 to +4.6
-0.3 to +4.6
-0.3 to +7.0
-7.0 to +0.3
-0.3 to +7.0
-0.3 to +7.0
-0.3 to +7.0
-0.3 to +18.0
-18.0 to +0.3
-0.3 to +7.0
-0.3 to +7.0
-0.3 to +7.0
-7.0 to +0.6
-0.3 to +7.0
-0.3 to VDDI+0.3
-0.3 to VDDI+0.3
-40 to +85
Supply voltage (1)
Supply voltage (2)
Supply voltage (3)
Supply voltage (4)
Supply voltage (5)
Supply voltage (6)
Supply voltage (7)
Supply voltage (8)
Supply voltage (9)
Supply voltage (10)
Supply voltage (11)
Supply voltage (12)
Supply voltage (13)
Supply voltage (14)
Supply voltage (15)
Supply voltage (16)
Logic input voltage
Logic output voltage
Operating temperature
Storage temperature
V
DDI
CORE
DD2
V
V
V
DD
V
OUT
VOUTM
VDDHS
VDDRH
V
DDRL
DDHG
EE
ONREG
OFREG
V
V
V
V
V
V
COMH
V
COML
V
COMW
V
IN
OUT
opr
stg
V
T
T
°
C
-55 to +125
Notes:
1
2
Unless otherwise noted, all voltages are specified based on VSS=0V.
If the IC exceeds its absolute maximum ratings, it may be damaged. Also, if the IC is operated with the absolute
maximum ratings for a long time, its reliability may drop.
3
4
5
The power voltage (5) to (14) cannot be used by turning on the external power supply.
The VDD2 absolute maximum ratings of 4.6V is standards when it DuDseHsGit befEoEre 1st boosting or doesn’t use
the boosting power supply. As for the VDD2, 3.5V is maximum that is 1/2 of the VOUT absolute maximum
ratings.
The absolute maximum rating of the potential difference between V
to V is 33V.
104
EPSON
S1D19105 Series (Rev.1.1)
9. RECOMMENDED OPERATING CONDITIONS
9. RECOMMENDED OPERATING CONDITIONS
Table 34 Recommended Operating Conditions
V
SS=0V
Operating
voltage
Parameter
Symbol
Unit
Supply voltage (1)
Supply voltage (2)
Supply voltage (3)
Supply voltage (4)
Supply voltage (5)
Supply voltage (6)
Supply voltage (7)
Supply voltage (8)
Supply voltage (9)
Supply voltage (10)
Supply voltage (11)
Supply voltage (12)
Supply voltage (13)
Supply voltage (14)
Supply voltage (15)
Supply voltage (16)
V
V
V
DDI
CORE
DD
1.65 to 3.3
2.3 to 3.1
2.3 to 3.1
2.3 to 3.1
4.6 to 6.2
-6.2 to 0
T.B.D. to 5.5
T.B.D. to 5.5
0.0 to 1.55
7.0 to 17.0
-15.0 to -5.0
2.9 to 5.5
0 to 5.1
V
DD2
V
OUT
V
OUTM
V
V
DDHS
DDRH
V
V
DDRL
DDHG
EE
ONREG
OFREG
V
V
V
V
V
COMH
3.0 to 5.5
V
COML
V
OUTM to 0.0
V
COMW
1.5 to 3.05
Notes:
1
2
3
4
5
The IC operations are guaranteed under the recommended operating conditions only.
To prevent noise, a bypass capacitor must be inserted into the line close to power pins.
These operations are not guaranteed if a quick voltage change occurs during IC operation.
The power voltage (5) to (14) cannot be used by turning on the external power supply.
The recommended operating rating of the potential difference between VDDHG to VEE is 30V.
S1D19105 Series (Rev.1.1)
EPSON
105
10. DC CHARACTERISTICS
10. DC CHARACTERISTICS
Table 35 DC Characteristics
V
SS=0V, VDDI=1.65 to 3.3V, VCORE=1.65 to 3.1V, T =-40 to +85°C
a
Rating
Parameter
Symbol
Condition
Unit Applicable Pin
Min.
Typ.
Max.
0.3
LOW level input voltage
HIGH level input voltage
Input leak current (1)
V
IL
IH
LI1
V
SS
DDI
×
V
DDI
Logic-series
input voltage
V
V
0.7
×
-1.0
V
V
DDI
I
V
IN=VDDI or VSS
1.0
Logic-series
µ
A
input voltage
Logic-series
input voltage
Input capacity
C
IN
Ta=25°C, f=1MHz
25
pF
V
LOW level output voltage
HIGH level output voltage
V
OL1
V
DD=2.8V
OL=0.06mA
OH=-0.06mA
DD=2.8V,
=25
DD2=2.8V
OUT=5.6V
=25
DD2=2.8V
DC1=VDD2
DD2=2.8V
DC2=VDD2
DD2=2.8V
OFREG=5V
DC3=VOFREG
DD2=2.8V
OFREG=5V
DC3=VOFREG
V
SS
V
SS+0.3
VDDI
Logic series
output voltage
I
I
V
OH1
V
DDI -0.3
V
REG voltage
V
T
a
°C
V
REG
3.45
3.5
3.55
V
VREG
V
V
Output voltage deviation(DAC)
1st booster ability
∆
V
S
T
a
°
C
10
20
mV
S1 to S528
R
VOUT12
V
190
240
Ω
V
OUT
(Internal resistor) *1
V
2nd booster ability
R
R
R
VOUT2
VOUT3
VOUT4
V
220
600
275
900
Ω
Ω
V
OUTM
(Internal resistor) *1
V
3rd booster ability
V
(-double) (Internal resistor) *1
V
VEE
V
4th booster ability
(Internal resistor) *1
V
V
400
1500
Ω
VDDHG
V
Static current consumption 1
I
DDIQ
COREQ
DDQ
DD2Q
DDI1
CORE1
DD1
DD21
DDI2
CORE2
DD2
DD22
0.1
1.0
0.1
0.1
0.1
100
30
1.0
2.0
mA
mA
mA
mA
V
DDI
*2
I
V
V
DDI =VCORE
DD =VDD2=2.8V
=
V
CORE
I
I
1.0
V
DD
DD2
DDI
CORE
DD
DD2
DDI
CORE
DD
DD2
1.0
V
Dynamic current consumption 1
I
1.0
µ
A
A
A
A
V
*
5
*3
I
150
45
µ
µ
V
V
V
V
V
DDI =VCORE
=
I
DD =VDD2=2.8V
I
1560
30
1000
20
85
2400
45
1500
40
130
µ
Dynamic current consumption 3
I
µ
µ
A
A
V
*
6
*4
I
V
V
V
DDI =VCORE
=
I
µ
µ
A
A
V
V
DD =VDD2=2.8V
I
*1
T = 25°C, Capacitance = 1uF, Boosting frequency =1H x 1
a
*2 After resetting, current consumption in the state of initial value of the command.
Ta
=25°C
or VSS, since current flows into the input circuit when the input level
is at the intermediate voltage level.)DDI
(For CMOS, fix the input level at V
*3 Current consumption during still picture display (built-in power supply used, without access to RAM)
T
=25°C.
___
*4 Caurrent consumption during access to RAM (WR) (display is OFF) T =25°C.
*5 After resetting, commands other than Sleep Out, Power Control AllaON, RAM Write and Display ON are
initial values. RAM data is the state in which the following data is written alternately.
R(101010)G(101010)B(101010), R(010101)G(010101)B(010101)
*6 Current consumption when the following display data is continuously written to RAM alternately at the
frequency of 2.5MHz.
R(101010)G(101010)B(101010), R(010101)G(010101)B(010101)
106
EPSON
S1D19105 Series (Rev.1.1)
11. AC CHARACTERISTICS
11. AC CHARACTERISTICS
11.1 Oscillation Frequency
The following defines the clock frequencies to enter the oscillation frequency of built-in oscillator and external
clocks into OSC pin.
Table 36 Oscillation Frequency
V
SS=0V, VDDI=1.65 to 3.3V, VCORE=VDD=VDD2=2.3 to 3.1V, T =25°C
a
Rating
Parameter
Symbol
Condition
Unit
Min.
Typ.
1000
1000
Max.
1050
1100
Oscillation frequency
External clock input frequency fOOSSCCI
f
When built-in oscillator circuit is used 950
900
kHz
kHz
11.2 Parallel Interface
11.2.1 The 80-Series MPUs
A0
__
CS
t
CYCR8, tCYCW8
,
t
CW8
*
1
2
t
AS8
t
AH8
__
WR
___
RD
t
CCLR,
t
CCLW
t
CCHR, tCCHW
___
CS
*
__
WR
___
RD
t
DS8
t
DH8
D0 to D17,
(Write)
t
ACC8
t
OH8
D0 to D17,
(Read)
Fig.49 The 80-Series MPUs
___ ___
___
*1 If CS = LOW and if accessed by WR or RD signal
___
___
*2 If WR=LOW and if accessed by CS signal
S1D19105 Series (Rev.1.1)
EPSON
107
11. AC CHARACTERISTICS
ꢀ Normal write mode
V
SS=0V, VDDI=1.65 to 3.3V, VCORE=2.7 to 3.1V, T
a
=-40 to +85°C
Parameter
A0 hold time
A0 setup time
Symbol
Condition
Min.
10
Max.
Unit
t
AH8
ns
t
AS8
10
100
Write system cycle time
t
CYCW8
___
WR LOW level pulse width
___
t
CCLW
40
30
500
350
50
20
10
10
WR HIGH level pulse width
t
CCHW
Read system cycle time
t
CYCR8
___
RD LOW level pulse width
t
CCLR
___
RD HIGH level pulse width
t
CCHR
___ ___
___
CS-WR and RD time
Data setup time
t
CW8
t
DS8
Data hold time
t
DH8
___
RD access time
t
ACC8
OH8
300
50
CL=50pF
Output disable time
t
5
ꢀ Normal write mode
V
SS=0V, VDDI=VCORE=1.65 to 2.7V, T
a
=-40 to +85°C
Parameter
Symbol
Condition
Min.
20
Max.
Unit
A0 hold time
t
AH8
ns
A0 setup time
t
AS8
20
200
80
Write system cycle time
t
CYCW8
___
WR LOW level pulse width
t
CCLW
___
WR HIGH level pulse width
t
CCHW
60
Read system cycle time
t
CYCR8
500
350
50
30
20
___
RD LOW level pulse width
t
CCLR
___
___ ___
RD HIGH level pulse width
t
CCHR
___
CS-WR and RD time
Data setup time
t
CW8
t
DS8
Data hold time
t
DH8
20
___
RD access time
t
ACC8
OH8
300
100
CL=50pF
Output disable time
t
10
) of the input signal areDsDpIecified for less than 10ns. If high-speed system
*3 All timings are specified based on the 20% and 80% of V
.
*4 The rise and fall times (
t
r
and
t
f
cycle time is used,
t
r
+
t
f
≤
t
CYCW8
-
t
CCLW
-
t
CCHW or
t
r
+
t
f
≤
___
t
CYCR8
-
t
CCLR
-
t
CCHR must be satisfied.
___ ___
LOW level. CCLR
*5
t
CCLW and
t
are specified for the overlap period when CS is at LOW level and WR and RD are at
108
EPSON
S1D19105 Series (Rev.1.1)
11. AC CHARACTERISTICS
11.2.2 The 68-Series MPUs
A0
__
R/W
___
CS
t
CYC6
t
CW6
*
1
2
t
AS6
t
AH6
E
tEWHR
,
t
EWHW
t
EWL
,
t
EWLW
__
CS
*
E
t
DS6
t
DH6
D0 to D17,
(Write)
t
ACC6
t
OH6
D0 to D17,
(Read)
Fig.50 The 68-Series MPUs
___
*1 If CS = LOW and if accessed by E signal
___
*2 If E = HIGH and if accessed by CS signal
S1D19105 Series (Rev.1.1)
EPSON
109
11. AC CHARACTERISTICS
ꢀ Normal write mode
V
SS=0V, VDDI=1.65 to 3.3V, VCORE=2.7 to 3.1V, T
a
=-40 to +85°C
Parameter
A0 hold time
A0 setup time
Write system cycle time
E (Write) HIGH level pulse width
E (Write) LOW level pulse width
Read system cycle time
E (Read) HIGH level pulse width
Symbol
Condition
Min.
10
Max.
Unit
t
AH6
AS6
CYCW6
EWHW
ns
t
10
100
40
t
t
t
EWLW
30
t
CYCR6
500
350
50
20
10
t
EWHR
EWLR
CW6
E (Read) LOW level pulse width
t
___
CS-E time
t
Data setup time
Data hold time
Read access time
Output disable time
t
DS6
t
DH6
10
t
ACC6
OH6
300
50
CL=50pF
t
10
ꢀ Normal write mode
V
SS=0V, VDDI=VCORE=1.65 to 2.7V, T
a
=-40 to +85°C
Parameter
A0 hold time
A0 setup time
Write system cycle time
E (Write) HIGH level pulse width
E (Write) LOW level pulse width
Read system cycle time
E (Read) HIGH level pulse width
Symbol
t
Condition
Min.
20
Max.
Unit
AH6
AS6
CYCW6
EWHW
ns
t
20
200
80
60
500
350
50
30
20
t
t
t
EWLW
CYCR6
t
t
EWHR
EWLR
CW6
E (Read) LOW level pulse width
t
___
CS-E time
t
Data setup time
Data hold time
Read access time
Output disable time
t
DS6
t
DH6
20
t
ACC6
OH6
300
100
CL=50pF
t
10
) of the input signal are spDecDiIfied for less than 10ns.
*3 All timings are specified based on the 20% and 80% of V
.
*4 The rise and fall times (
t
r
and
t
f
If high-speed system cycle time is used,
must be satisfied.
t
r
+
t
f
≤
t
CYC6
-
t
EWLW
___
-
t
EWHW or
t
r
+
t
f
≤
tCYC6
-
t
EWLR
-
t
EWHR
*5
tEWLW and tEWLR are specified for the overlap period when CS is at LOW level and E is at HIGH level.
110
EPSON
S1D19105 Series (Rev.1.1)
11. AC CHARACTERISTICS
11.3 Serial Interface
t
CSH
t
CSS
___
CS
t
SCYC
SCL
SI
t
SLW
SDS
t
SHW
t
t
SDH
Fig.51 Serial Interface
V
SS=0V, VDDI=1.65 to 3.3V, VCORE=2.7 to 3.1V, T
a
=-40 to +85°C
Parameter
SCL cycle
SCL LOW level pulse width
SCL HIGH level pulse width
Data setup time
Symbol
Condition
Min.
50
Max.
Unit
t
SCYC
ns
t
SLW
10
10
10
10
t
SHW
t
SDS
Data hold time
t
SDH
___
CS setup time
t
CSS
20
___
CS hold time
t
CSH
30
V
SS=0V, VDDI=VDD=1.65 to 2.7V, T
a
=-40 to +85°C
Parameter
Symbol
Condition
Min.
100
20
20
20
20
30
45
Max.
Unit
SCL cycle
t
SCYC
ns
SCL LOW level pulse width
SCL HIGH level pulse width
Data setup time
t
SLW
t
SHW
t
SDS
SDH
CSS
CSH
Data hold time
t
___
CS setup time
t
t
___
CS hold time
) of the input signal are spDecDiIfied for less than 10ns.
*1 All timings are specified based on the 20% and 80% of V
.
*2 The rise and fall times (
t
r
and
t
f
S1D19105 Series (Rev.1.1)
EPSON
111
11. AC CHARACTERISTICS
11.4 Resetting
t
RW
____
RESH
t
R
Internal state
Resetting
Reset completed
Fig.52 Resetting
V
SS=0V, VDDI=VCORE=1.65 to 3.1V, T
a
=-40 to +85°C
Parameter
Reset time
Reset LOW level pulse width
Symbol
Condition
Min.
Max.
Unit
t
R
1
µs
t
RW
1
*1 All timings are specified based on the 20% and 80% of VDDI
.
____
*2 We recommend to hold the RES pin to LOW during power-on conditions.
*3 Applied when resetting while the power supply is stabilized.
11.5 Source Output
Clock
t
t
dLHtOD
Sn
dHLtOD
Fig.53 Source Output
V
SS=0V, VDDHS=4.5V, T
a
=-40 to +85°C
Parameter
Clock Sn output delay time (LOW
Symbol
Condition
Typ.
Max.
Unit
→
HIGH)
LOW)
t
dLHtOD
CL=20pF,
30
µs
RL=1.1K
Ω
Clock Sn output delay time (HIGH
→
t
dHLtOD
CL=20pF,
30
RL=1.1K
Ω
*1 Specified based on the clock rise edge defined by the Set Display Timing command at P1.
*2 Sn can be S1 to S528 outputs.
*3 Clock Sn output delay time-2 is set to 50mV.
112
EPSON
S1D19105 Series (Rev.1.1)
11. AC CHARACTERISTICS
11.6 RGB Interface
t
DSYN
VSYNCI
HSYNC
t
DCSS
t
DCSH
ENABLE
DOTCLK
t
DCYC
t
DLW
DDS
t
DHW
DDH
t
t
D17 to 0
Fig.54 RGB Interface
SS=0V, VDDI=1.65 to 3.3V, VCORE=2.7 to 3.1V, T
V
a
=-40 to +85°C
Parameter
DOTCLK cycle
DOTCLK LOW level pulse width
DOTCLK HIGH level pulse width
Data setup time
Data hold time
ENABLE setup time
ENABLE hold time
VSYNC setup time
Symbol
Condition
Min.
100
30
30
10
20
75
75
Max.
Unit
t
DCYC
ns
t
DLW
t
DHW
t
DDS
t
DDH
t
t
DCSS
DCSH
DSYV
DSYH
t
10
10
HSYNC setup time
t
V
SS=0V, VDDI=VCORE=1.65 to 2.7V, T
a
=-40 to +85°C
Parameter
DOTCLK cycle
DOTCLK LOW level pulse width
DOTCLK HIGH level pulse width
Data setup time
Data hold time
ENABLE setup time
ENABLE hold time
Symbol
Condition
Min.
200
60
60
20
Max.
Unit
t
DCYC
ns
t
DLW
t
DHW
t
DDS
t
DDH
40
t
DCSS
DCSH
150
150
20
t
VSYNC setup time
HSYNC setup time
t
DSYV
DSYH
t
20
) of the input signal are spDecDiIfied for less than 10ns.
*1 All timings are specified based on the 20% and 80% of V
.
*2 The rise and fall times (
t
r
and
t
f
S1D19105 Series (Rev.1.1)
EPSON
113
12. NOTES
12. NOTES
When using these development specifications, note the following points.
1. The contents of these development specifications are subject to change without notice for improvement.
2. There is no representation or warranty that anything made in accordance with this material will be free from
any patent or copyright infringement of a third party.
Examples shown in these development specifications are for understanding our products, and we are not
responsible for any circuit problems that may occur when using them.
When using the S1D19105 series, note the following points:
IC handling notes against the light:
As a semiconductor chip is principally identical to a solar cell, its performance may change if exposed to bright
light. Therefore, the IC may malfunction if exposed to light.
1
2
3
Design and mount the IC so that it is not exposed to light during actual operation.
In the test process, check the design and mounting of the IC so that it is not exposed to light.
Take all surfaces, top, bottom and sides, of the IC chip into consideration when blocking out light.
IC handling notes on ambient noise and others:
1
Though the S1D19105 series reserves the register settings, its internal state may change if excessive ambient
noise is inserted. Measures are required to prevent noise generation or influence in terms of mounting and the
system itself.
2
It is recommended that you set the software to refresh the operating state (register reset) periodically to avoid
spike noise.
114
EPSON
S1D19105 Series (Rev.1.1)
International Sales Operations
AMERICA
ASIA
EPSON ELECTRONICS AMERICA, INC.
HEADQUARTERS
EPSON (CHINA) CO., LTD.
23F, Beijing Silver Tower 2# North RD DongSanHuan
ChaoYang District, Beijing, CHINA
150 River Oaks Parkway
San Jose, CA 95134, U.S.A.
Phone: +1-408-922-0200
Phone: 64106655
FAX: 64107319
FAX: +1-408-922-0238
SHANGHAI BRANCH
SALES OFFICES
West
7F, High-Tech Bldg., 900, Yishan Road,
Shanghai 200233, CHINA
1960 E.Grand Avenue
El Segundo, CA 90245, U.S.A.
Phone: +1-310-955-5300
Phone: 86-21-5423-5577
FAX: 86-21-5423-4677
FAX: +1-310-955-5400
FAX: +1-815-455-7633
FAX: +1-781-246-5443
EPSON HONG KONG LTD.
20/F., Harbour Centre, 25 Harbour Road
Wanchai, Hong Kong
Phone: +852-2585-4600
Telex: 65542 EPSCO HX
Central
101 Virginia Street, Suite 290
Crystal Lake, IL 60014, U.S.A.
Phone: +1-815-455-7630
FAX: +852-2827-4346
EPSON TAIWAN TECHNOLOGY & TRADING LTD.
14F, No. 7, Song Ren Road,
Taipei 110
Northeast
301 Edgewater Place, Suite 120
Wakefield, MA 01880, U.S.A.
Phone: +1-781-246-3600
Phone: 02-8786-6688
FAX: 02-8786-6660
HSINCHU OFFICE
No. 99, Jiangong Road,
Hsinchu City 300
Southeast
3010 Royal Blvd. South, Suite 170
Alpharetta, GA 30005, U.S.A.
Phone: +886-3-573-9900
FAX: +886-3-573-9169
Phone: +1-877-EEA-0020
FAX: +1-770-777-2637
EPSON SINGAPORE PTE., LTD.
401 Commonwealth Drive, #07-01
Haw Par Technocentre, SINGAPORE 149598
EUROPE
EPSON EUROPE ELECTRONICS GmbH
HEADQUARTERS
Phone: +65-6586-3100
FAX: +65-6472-4291
Riesstrasse 15
SEIKO EPSON CORPORATION
KOREA OFFICE
80992 Munich, GERMANY
Phone: +49-(0)89-14005-0
FAX: +49-(0)89-14005-110
50F, KLI 63 Bldg., 60 Yoido-dong
Youngdeungpo-Ku, Seoul, 150-763, KOREA
DÜSSELDORF BRANCH OFFICE
Altstadtstrasse 176
Phone: 02-784-6027
FAX: 02-767-3677
51379 Leverkusen, GERMANY
Phone: +49-(0)2171-5045-0
GUMI OFFICE
FAX: +49-(0)2171-5045-10
6F, Good Morning Securities Bldg., 56 Songjeong-Dong,
Gumi-City, Seoul, 730-090, KOREA
UK & IRELAND BRANCH OFFICE
Unit 2.4, Doncastle House, Doncastle Road
Bracknell, Berkshire RG12 8PE, ENGLAND
Phone: 054-454-6027
- JAPAN -
FAX: 054-454-6093
SEIKO EPSON CORPORATION
Phone: +44-(0)1344-381700
FAX: +44-(0)1344-381701
SEMICONDUCTOR OPERATION DIVISION
FRENCH BRANCH OFFICE
IC Sales Department
1 Avenue de l’ Atlantique, LP 915 Les Conquerants
IC International Sales Group
Z.A. de Courtaboeuf 2, F-91976 Les Ulis Cedex, FRANCE
Phone: +33-(0)1-64862350 FAX: +33-(0)1-64862355
421-8, Hino, Hino-shi, Tokyo 191-8501, JAPAN
Phone: +81-(0)42-587-5814
FAX: +81-(0)42-587-5117
BARCELONA BRANCH OFFICE
Barcelona Design Center
Edificio Testa, Avda. Alcalde Barrils num. 64-68
E-08190 Sant Cugat del Vall
Phone: +34-93-544-2490
è
s, SPAIN
FAX: +34-93-544-2491
Scotland Design Center
Integration House, The Alba Campus
Livingston West Lothian, EH54 7EG, SCOTLAND
Phone: +44-1506-605040
FAX: +44-1506-605041
In pursuit of “Saving” Technology, Epson electronic devices.
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assists in creating the products of our customers’ dreams.
Epson IS energy savings.
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