SA25C512LN [ETC]
512Kb EEPROM SPI with 10MHz and Low Standby; 512KB EEPROM SPI与10MHz的低待机
| 型号： | SA25C512LN |
| 厂家： | 
ETC |
| 描述： | 512Kb EEPROM SPI with 10MHz and Low Standby |
| 文件： | 总19页 (文件大小：962K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Features
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Saifun NROM™ Flash Cell
Serial Peripheral Interface (SPI) Compatible
Supports SPI Modes 0 (0,0) and 3 (1,1)
Byte and Page Write Modes (up to 128 bytes)
Single Supply Voltage:
SA25C512
Data Sheet
512Kb EEPROM SPI
with 10MHz and
Low Standby
–
2.7V to 3.6V (L)
4.5V to 5.5V (H)
–
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10MHz Clock Rate
Block Write Protection:
–
Protect ¼, ½, or Entire Array
•=
Write Protect Pin and Write Disable Instructions of both Hardware and
Software Data Protection
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Self-timed Write Cycle (10mS max)
100,000 Write Cycles (Minimum)
20 Year Data Retention
Low-power Standby Current (less than 1µA)
8-SOIC Narrow Package (0.150” Wide Body, JEDEC SOIC)
Temperature Range:
–
Industrial: -40°C to +85°C
Commercial: 0°C to +70°C
–
General Description
SA25C512 is a 512Kb CMOS non-volatile serial EEPROM,
organized as a 64K x 8-bit memory. The SA25C512 is
available in a space-saving, 8-lead narrow SOIC package. In
addition, it is available in a wide range of voltages – 2.7-3.6 V
and 4.5-5.5 V.
The SA25C512 is enabled through the Chip Select (CSb) pin
and is accessed via a 3-wire interface consisting of Serial Data
Input (SI), Serial Data Output (SO) and Serial Data Clock
(SCK). All write cycles are completely self-timed, and no
separate ERASE cycle is required before write.
(continued)
http://www.saifun.com
Saifun NROMTM is a trademark of Saifun Semiconductors Ltd.
This Data Sheet states Saifun's current technical specifications regarding the Products described herein. This Data Sheet
may be revised by subsequent versions or modifications due to changes in technical specifications.
Publication# 1909 Rev: 1.1 Amendment: 1
Issue Date: January 27, 2003
SA25C512 Data Sheet
SAIFUN
2
Table of Contents
List of Figures
Figure 1. SOIC 8 – Narrow/PDIP Package (Top View).... 4
Figure 2: SA25C512 Ordering Information ...................... 5
Figure 3. AC Measurements I/O Waveform..................... 8
Figure 4. SPI Serial Interface ........................................ 10
Figure 5. SPI Mode 0 (0,0) Timing................................. 13
Figure 6. SPI Mode 0 (0,0) and 3 (1,1) Timing............... 13
Figure 7. HOLDb Timing ............................................... 14
Figure 8. Read Timing................................................... 14
Figure 9. Write Timing................................................... 14
Figure 10. Write Status Register Timing........................ 15
Figure 11. Read Status Register Timing........................ 15
Figure 12. 8-pin SOIC Package..................................... 16
Features......................................................................... 1
General Description ...................................................... 1
Ordering Information .................................................... 5
Product Specifications ................................................. 6
Absolute Maximum Ratings..................................... 6
Latch Up Specifications........................................... 6
ESD Specifications.................................................. 6
Operating Conditions............................................... 6
DC Characteristics ........................................................ 7
AC Test Conditions ....................................................... 8
Serial Interface Description.......................................... 9
Master..................................................................... 9
Slave....................................................................... 9
Transmitter/Receiver............................................... 9
Serial Opcode ......................................................... 9
Invalid Opcode ........................................................ 9
Chip Select (CSb).................................................... 9
HOLDb.................................................................... 9
Write Protect ........................................................... 9
Functional Description ............................................... 10
Write Enable (WREN) ........................................... 10
Write Disable (WRDI)............................................ 10
Read Status Register (RDSR)............................... 11
Write Status Register (WRSR).............................. 11
Read Sequence (READ) ....................................... 11
Write Sequence (WRITE)...................................... 12
Timing Diagrams......................................................... 13
Figure 13. 8-pin Molded Small Outline Package (MN),
0.150” Wide Body, JEDEC SOIC......................... 17
Figure 14. Molded Dual-in-line Package (N) Package
Number N08E...................................................... 18
List of Tables
Table 1. Pin Names......................................................... 4
Table 2. DC Characteristics............................................. 7
Table 3. AC Measurements............................................. 8
Table 4. AC Characteristics............................................. 8
Table 5. Instruction Set ................................................. 10
Table 6. Status Register Format.................................... 10
Table 7. Block Write Protect Bits................................... 11
Table 8. WPBEN Operation .......................................... 11
Table 9. Read Status Register Definition....................... 12
Physical Dimensions .................................................. 16
Life Support Policy...................................................... 19
SA25C512 Data Sheet
SAIFUN
3
General Description
(continued)
Programming the status register with top
¼, top ½ or entire array write protection
enables
BLOCK
WRITE
protection.
Separate program enable and program
disable instructions are provided for
additional data protection. Hardware data
protection is provided via the WPb pin to
protect against inadvertent write attempts
to the status register. The HOLDb pin may
be
used to suspend any serial
communication without resetting the serial
sequence.
SA25C512 Data Sheet
SAIFUN
4
Connection Diagrams
CSb
1
8
7
6
5
VCC
HOLD
SCK
SI
SO
2
3
4
SA25C512
WPb
GND
Figure 1. SOIC 8 – Narrow/PDIP Package (Top View)
Table 1. Pin Names
Pin Name
Function
CSb
SCK
SI
SO
GND
VCC
Chip Select
Serial Data Clock
Serial Data Input
Serial Data Output
Ground
Power Supply
WPb
HOLDb
Write Protect
Suspend Serial Input
SA25C512 Data Sheet
SAIFUN
5
Ordering Information
SA
25
C
XX
L
E
YY
X
Letter
Description
Blank
X
Tube
Tape and Reel
N
8-pin DIP
Package
MN
8-pin SOIC (SO8, 150 mil width)
Blank
E
0 to 70 oC
Temp. Range
-40 to +85 oC
L
2.7 V to 3.6 V
4.5 V to 5.5 V
Voltage Operating Range
H
Density 512
512 Kb with Write Protect
CMOS Technology
SPI-2 Wires
C
Interface 25
Saifun Non-Volatile
Memory
SA
Figure 2: SA25C512 Ordering Information
SA25C512 Data Sheet
SAIFUN
6
Product Specifications
Absolute Maximum Ratings
Ambient Storage Temperature
-65 °C to +150 °C
All input or output voltages with
4.5 V to -0.3 V (L)
respect to Ground
6.5 V to -0.3 V (H)
Lead Temperature
+235 °C
(Soldering, 10 seconds)
Latch Up Specifications
Latch Up
100 mA on all pins, +125°C
ESD Specifications
Human Body Model
Per MIL-STD 883 Method 3015.7
500 V to 5 KV, in increments of 500 V;
Voltage Levels
Machine Model
proceed to 8000 V or until failure
Per JEDEC standard JESD22-A115
50 V to 300 V, in increments of 50 V;
Voltage levels
proceed to 500 V or until failure
Operating Conditions
Ambient Operating Temperature:
SA25C512
0 °C to +70 °C
SA25C512E
-40 °C to +85 °C
Positive Power Supply:
SA25C512L
2.7 V to 3.6 V
4.5 V to 5.5 V
SA25C512H
SA25C512 Data Sheet
SAIFUN
7
DC Characteristics
Applicable over recommended operating range from:
•ꢀ TAI = -40 ºC to 85 ºC, VCC = 2.7-3.6 V/4.5-5.5 V
•ꢀ TAC = 0 ºC to 70 ºC, VCC = 2.7-3.6 V/4.5-5.5 V
Table 2. DC Characteristics
Limits
Typ*
Symbol
Parameter
Test Conditions
Unit Comments
Min
Max
2.7
4.5
3
5
4
4
4
4
3.6
5.5
8
V
V
mA
mA
mA
mA
L
H
L
L
H
H
VCC
Supply Voltage
FSCK = 5 MHz, VCC = 5.0 V
FSCK = 2 MHz, VCC = 5.0 V
FSCK = 5 MHz, VCC = 3.0 V
FSCK = 2 MHz, VCC = 3.0 V
Active Power Supply
Current (Read)
ICC1
8
Fwrite = 5 MHz,
10
10
10
10
15
mA
mA
mA
mA
µA
L
L
Twrite = 10 ms
Fwrite = 2 MHz,
Twrite = 10 ms
Active Power Supply
Current (Write)
ICC2
Fwrite = 5 MHz,
15
H
H
L
Twrite = 10 ms
Fwrite = 2 MHz,
Twrite = 10 ms
VCC = 3.0 V,
1
CSb = VCC
ISB
Standby Current
VCC = 5.0 V
CSb = VCC
10
H
µA
IIL
IOL
VIL
Input Leakage Current
Output Leakage Current
Input Low Voltage
VIN = GND to VCC
VIN = GND to VCC
1
1
µA
µA
V
-0.3
0.3 VCC
VCC
+
VIH
VOL
VOH
VOL
VOH
Input High Voltage
Output Low Voltage
Output High Voltage
Output Low Voltage
Output High Voltage
0.7 VCC
V
V
V
V
V
0.5
0.2
IOL = 0.15 mA
IOH = -0.1 mA
IOL = 3.0 mA
IOH = -1.6 mA
L
L
VCC
0.2
-
-
0.4
H
H
VCC
0.8
*Typical values are at TAI = 25 ºC and 3 V/5 V.
SA25C512 Data Sheet
SAIFUN
8
AC Test Conditions
Input and Output
Input Levels
Timing Reference Levels
0.8Vcc
0.7Vcc
0.3Vcc
0.2Vcc
Figure 3. AC Measurements I/O Waveform
Table 3. AC Measurements
Parameter Min
Symbol
Max
Unit
CL
Load Capacitance
Input Rise and Fall Times
Input Pulse Voltage
30
PF
NS
V
5
0.2 VCC to 0.8 VCC
Input and Output Timing
0.3 VCC to 0.7 VCC
V
Reference Voltages
Table 4. AC Characteristics
10 MHz
Typ
Symbol
Parameter
Unit
Min
Max
FSCK
tWH
tWL
SCK Clock Frequency
SCK High Time
SCK Low Time
10
MHz
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ms
40
40
50
50
50
25
25
0
tCS
CSb High Time
tCSS
tCSH
tHD
tCD
tV
CSb Setup Time
CSb HOLD Time
HOLD Time
HOLDB HOLD Time
Output Valid
Output HOLD Time
Data in HOLD Time
Data in Setup Time
Input Rise Time
40
tHO
0
15
12
tHD:DAT
tSU:DAT
tR
tF
tLZ
2
2
100
100
100
Input Fall Time
HOLDb to Output Low Z
HOLDb to Output High Z
Output Disable Time
128-byte Page
tHZ
tDIS
tWC*
8
Endurance
100K
Write cycles
* 128 bytes in the checkerboard programming formation; a maximum of 50% of the array is
programmed.
SA25C512 Data Sheet
SAIFUN
9
HOLDb
Serial Interface
Description
The HOLDb pin is used in conjunction with
the CSb pin to select the SA25C512. When
the device is selected and a serial
sequence is underway, HOLDb can be
used to pause the serial communication
with the master device without resetting the
serial sequence. To pause, the HOLDb pin
must be brought low while the SCK pin is
low. To resume serial communication, the
HOLDb pin is brought high while the SCK
pin is low (SCK may still toggle during
HOLDb). Inputs to the SI pin are ignored
while the SO pin is in the high impedance
state.
Master
The device that generates the SCK.
Slave
As the SCK pin is always an input, the
SA25C512 always operates as a slave.
Transmitter/Receiver
The SA25C512 has separate pins
designated for data transmission and
reception.
Write Protect
The WPb pin enables write operations to
the Status register when held high. When
the WPb pin is brought low and the
WPBEN bit is 1, all write operations to the
status register are inhibited (for more
details, refer to Table 8, page 11). If WPb
goes low while CSb is still low, the write to
the status register is interrupted. If the
internal write cycle has already been
initiated, WPb going low has no effect on
any write operation to the status register.
The WPb pin function is blocked when the
WPBEN bit in the status register is 0,
which enables the user to install the
SA25F020 in a system with the WPb pin
tied to ground but still able to write to the
status register. All WPb pin functions are
enabled when the WPBEN bit is set to 1.
Serial Opcode
The first byte is received after the device is
selected. This byte contains the opcode
that defines the operation to be performed
(for more details, refer to Table 5,
page 10).
Invalid Opcode
If an invalid opcode is received, no data is
shifted into the SA25C512, and the serial
output pin remains in a high impedance
state until a CSb falling edge is detected
again, which reinitializes the serial
communication.
Chip Select (CSb)
The SA25C512 is selected when the CSb
pin is low. When the device is not selected,
data is not accepted via the SI pin, and the
SO pin remains in a high impedance state.
SA25C512 Data Sheet
SAIFUN
10
Table 5. Instruction Set
Functional Description
Instruction Instruction
Operation
Name
WREN
WRDI
Format
0000X110
0000X100
Figure 4 presents a schematic diagram of
the SPI serial interface.
Set Write Enable Latch
SLAVE:
MASTER:
Reset Write Enable
SA25C512
MICROCONTROLLER
SI
Latch
DATA OUT
SO
SCK
CS
DATA IN
RDSR
WRSR
0000X101
0000X001
Read Status Register
Write Status Register
SERIAL CLOCK
SSO
SS1
SS2
Read Data from
READ
0000X011
0000X010
Memory Array
SS3
Write Data to Memory
Array
WRITE
SI
SO
SCK
CS
In addition to the instruction register, the
device also contains an 8-bit status register
that can be accessed by RDSR and WRSR
instructions. The byte defines the Block
Write Protection (BP1 and BP0) levels,
Write Enable (WEN) status, Busy/Rdy
(/RDY) status and Hardware Write Protect
(WPBEN) status of the device. Table 6
illustrates the format of the status register.
SI
SO
SCK
CS
Table 6. Status Register Format
SI
SO
SCK
CS
Bit 7
Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit1 Bit 0
BP1 BP0 WEN /RDY
WPBEN
X
X
X
Write Enable (WREN)
Figure 4. SPI Serial Interface
The device powers up in the Write Disable
state when VCC is applied. All programming
instructions must be preceded by a WREN
instruction.
The SA25C512's SPI consists of an 8-bit
instruction register that decodes a specific
instruction to be executed. Six different
instructions
(called
opcodes)
are
incorporated in the device for various
operations. Table 5 lists the instructions set
and the format for proper operation. All
opcodes, array addresses and data are
transferred in an MSB-first-LSB-last
fashion. Detailed information about each of
these opcodes is provided under individual
instruction descriptions in the sections that
follow.
Write Disable (WRDI)
To protect the device against inadvertent
writes, the WRDI instruction disables all
programming
modes.
The
WRDI
instruction is independent of the WP pin's
status.
SA25C512 Data Sheet
SAIFUN
11
NOTE:
Read Status Register (RDSR)
When the WPBEN bit is hardware write
protected, it cannot be changed back
to 0 as long as the WPb pin is held low.
The RDSR instruction provides read
access to the status register. The
BUSY/RDY and WREN statuses of the
device can also be determined by this
instruction. In addition, the Block Write
Protection bits indicate the extent of
protection employed. In order to determine
the status of the device, the value of the
/RDY bit can be continuously polled before
sending any write instruction.
Table 8. WPBEN Operation
Un-
Protected
Blocks
Status
WPb WPBEN WEN
protected
Blocks
Register
X
X
0
0
1
1
X
X
0
1
0
1
0
1
Protected Protected Protected
Protected Writable Writable
Protected Protected Protected
Protected Writable Protected
Protected Protected Protected
Protected Writable Writable
Low
Low
High
High
Write Status Register (WRSR)
The WRSR instruction enables the user to
select one of four levels of protection. The
SA25C512 is divided into four array
segments. The top quarter, top half or all of
the memory segments can be protected
(for more details, refer to Table 7). The
data within a selected segment is therefore
read-only.
Read Sequence (READ)
Reading the SA25C512 via the SO pin
requires the following sequence (for more
details, see Table 9, page 12):
1. After the CSb line is pulled low to select
the device, the READ opcode is
transmitted via the SI line, followed by
the byte address to be read. Upon
completion, any data on the SI line is
ignored.
2. The data (D7-D0) at the specified
address is then shifted out onto the SO
line.
Table 7. Block Write Protect Bits
Status Register Bits
Array Addresses
Protected
Level
BP1
BP0
0
0
0
1
1
0
1
0
1
None
1/4
1/2
All
C000 - FFFF
8000 - FFFF
0000 - FFFF
If only one byte is to be read, the CSb line
should be driven high after the data comes
out. The READ sequence can be
continued, as the byte address is
automatically incremented and data
continues to shift out. When the highest
address is reached, the address counter
rolls over to the lowest address, enabling
the entire memory to be read in one
continuous READ cycle.
The WRSR instruction (as shown in
Table 8) also allows the user to enable or
disable the WPb pin via the WPBEN bit.
Hardware write protection is enabled when
the WPb pin is low and the WPBEN bit is
1, and disabled when either the WP pin is
high or the WPBEN bit is 0. When the
device is hardware write protected, writes
to the status register are disabled.
SA25C512 Data Sheet
SAIFUN
12
Table 9. Read Status Register Definition
A WRITE instruction requires the following
sequence:
Bit
Definition
1. After the CSb line is pulled low to select
the device, the WRITE opcode is
transmitted via the SI line, followed by
the byte address and the data (D7-D0)
to be written.
2. Programming starts after the CSb pin is
brought high. The CSb pin's low-to-high
transition must occur during the SCK
low time, immediately after clock in the
D0 (LSB) data bit.
The SA25C512 is capable of up to a
128-byte (from 1 to 128 bytes) PAGE write
operation. After each byte is received, the
eight low-order address bits are internally
incremented by one. If more than 128
bytes of data are transmitted, the address
counter rolls over and the previously
written data is overwritten. The SA25C512
is automatically returned to the write
disable state at the completion of a write
cycle.
Bit 0 = 0 (/RDY) indicates that the
device is READY.
Bit 0 (/RDY)
Bit 0 = 1 indicates that a write cycle
is in progress.
Bit 1 = 0 indicates that the device is
not write enabled.
Bit 1 (WEN)
Bit 1 = 1 indicates that the device is
write enabled.
Bit 2 (BP0)
Bit 3 (BP1)
Block Write Protect Bit 0
Block Write Protect Bit 1
Bit 7
Write Protect Mode Enable Bit
(WPBEN)
Bits 4-6 are 0s when the device is not in an internal
write cycle; bits 0-7 are 1s during an internal write
cycle.
Write Sequence (WRITE)
Two separate instructions must be
executed in order to write to the
SA25C512. The device must first be write
enabled via the WREN instruction, and
then
a
WRITE instruction may be
executed. The address of the memory
locations to be written must be outside the
protected address field location selected by
the Block Write Protection level. During an
internal write cycle, all commands are
ignored except the RDSR instruction.
NOTE:
If the device is not write enabled, the
device ignores the WRITE instruction
and returns to the standby state when
CSb is brought high. A new CSb falling
edge is required to re-initiate the serial
communication.
SA25C512 Data Sheet
SAIFUN
13
Timing Diagrams
All timing diagrams are based on SPI protocol modes 0 and 1.
tCS
vIH
CS
vIL
tCSS
tCSH
vIH
tWH
tWL
SCK
SI
vIL
tSU
tH
vIH
vIL
VALID IN
tV
tHO
tDIS
vOH
vOL
HI-Z
HI-Z
SO
Figure 5. SPI Mode 0 (0,0) Timing
CS
SCK(0,0)
SCK(1,1)
SI
Figure 6. SPI Mode 0 (0,0) and 3 (1,1) Timing
SA25C512 Data Sheet
SAIFUN
14
CS
SCK
tCD
tCD
tHD
tHD
HOLD
tHZ
SO
tLZ
Figure 7. HOLDb Timing
CS
0
1
2
3
4
5
6
7
8
9
10
20 21 22 23 24 25 26 27 28 29 30 31
SCK
Instruction
16-Bit Address
15 14 13
3
2
1
0
SI
DATA OUT 1
DATA OUT 2
7
High Impedance
7
6
5
4
3
2
1
0
SO
MSB
MSB
Figure 8. Read Timing
CS
SCK
SI
0
1
2
3
4
5
6
7
8
9
10
20 21 22 23 24 25 26 27 28 29 30 31
Instruction
16-Bit Address
Data Byte 1
15 14 13
MSB
3
2
1
0
7
6
5
4
3
2
1
0
MSB
Figure 9. Write Timing
SA25C512 Data Sheet
SAIFUN
15
CSb
SCK
0
1
2
3
4
5
6
7
8
9
10 11 12 13
Status Register In
14
15
Instruction
SI
7
6
5
4
3
2
1
0
MSB
High Impedance
SO
Figure 10. Write Status Register Timing
CS
0
1
2
3
4
5
6
7
8
9
10 11 12 13 14
SCK
SI
Instruction
High Impedance
Data Out
SO
7
6
5
4
3
2
1
0
MSB
Figure 11. Read Status Register Timing
SA25C512 Data Sheet
SAIFUN
16
Physical Dimensions
All measurements are in inches (millimeters), unless otherwise specified.
Figure 12. 8-pin SOIC Package
SA25C512 Data Sheet
SAIFUN
17
Figure 13. 8-pin Molded Small Outline Package (MN), 0.150” Wide Body, JEDEC SOIC
SA25C512 Data Sheet
SAIFUN
18
Figure 14. Molded Dual-in-line Package (N) Package Number N08E
SA25C512 Data Sheet
SAIFUN
19
Saifun Semiconductors Ltd. Headquarters
ELROD Building
45 Hamelacha St.
Sappir Industrial Park
Netanya 42505
Israel
Tel.: +972-9-892-8444
Fax: +972-9-892-8445
Email: tech_support@saifun.com
http://www.saifun.com
Revision History
Rev
Date
Description of Change
Amendment
1.0
1.1
1-Sep-02
Initial Release
0
1
27-Jan-03 Document promoted from “Advanced
Information” to “Data Sheet”, ESD scheme
modification, Figure 8 modified
Prepared by
Approved by
Shai Eisen
Approved by
Doron Vertesh
Signature
Date
Golan M. Shalhov
27-Jan-03
Product Line Manager Design Project Manager Director EEPROM SBU
© Saifun Semiconductors Ltd. 2003
Saifun reserves the right, without notice, to change any of the products described in this guide, in order to improve functionality,
reliability or design. Saifun assumes no liability arising from the application or use of any product described in this guide; and
under its patent rights, gives no authorization for the use of this product or associated products. The Buyer will not hold Saifun
responsible for direct or indirect damages and expenses, as well as any claim of injury or death, associated with the
unauthorized use, including claims of manufacture or design negligence.
Other company and brand products and service names are trademarks or registered trademarks of their respective holders.
Life Support Policy
Saifun's products are not authorized for use as critical components in life support devices or systems without the express written
approval of the President of Saifun Semiconductors Ltd. As used herein:
1. Life support devices or systems are devices or
systems which, (a) are intended for surgical implant
into the body, or (b) support or sustain life, and whose
failure to perform, when properly used in accordance
with instructions for use provided in the labeling, can
be reasonably expected to result in a significant injury
to the user.
2. A critical component is any component of a life
support device or system whose failure to perform can
be reasonably expected to cause the failure of the life
support device or system, or to affect its safety or
effectiveness.
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