SDC-632-A-L-1-R [ETC]

Synchro-to-Digital Converter ; 同步到数字转换器\n
SDC-632-A-L-1-R
型号: SDC-632-A-L-1-R
厂家: ETC    ETC
描述:

Synchro-to-Digital Converter
同步到数字转换器\n

转换器
文件: 总4页 (文件大小:465K)
中文:  中文翻译
下载:  下载PDF数据表文档文件
S DC-6 3 0 /6 3 2 /6 3 4 * A/S T  
1 0 -, 1 2 -, OR 1 4 -BIT S YNCHRO-TO-DIGITAL/  
RES OLVER-TO-DIGITAL CONVERTER  
LOWER COST! PIN-FOR-PIN REPLACEMENT FOR  
SDC-630/632/634 SERIES. FOR ALL NEW DESIGNS!  
FEATURES  
DESCRIPTION  
APPLICATIONS  
Low Cost Pin-for-Pin  
The SDC-630/632/634 A/ST series These converters may be used wher-  
are low cost, low profile synchro-to- ever analog angle data from a syn-  
digital (S/D) and resolver-to-digital chro or resolver must be rapidly and  
(R/D) tracking converters with stan- accurately converted to digital form  
dard pin configurations. They use a for transmission, storage or analysis.  
unique control transformer algorithm Because these units are extremely  
that provides inherently higher accu- rugged and stable, and meet the  
racy and jitter-free output. Utilizing a requirements on MIL-STD-202E, they  
type II servo loop, these converters are suitable for the most severe  
have no velocity lag up to the speci- industrial, commercial and military  
fied tracking rate, and output data is applications. Military ground support  
always fresh and continuously avail- and avionics uses include ordnance  
able. Each unit is fully trimmed and control, radar tracking systems, navi-  
requires no adjustment or field cali- gation and collision avoidance sys-  
Replacement  
for SDC-630/632/634 Series  
Industry Standard Low Profile  
Modular Converters  
Accuracy:  
10 Bit: 21 Minutes  
12 Bit: 8.5 Minutes  
14 Bit: 4 Minutes, 0.9 LSB or  
2.6 Minutes (High Accuracy)  
bration.  
tems.  
Options (Consult Factory):  
Velocity Input  
BIT: Built-In-Test  
16-Bit Resolution  
INPUT OPTIONS  
RESISTOR (ST)  
DIVIDER  
SYNCHRO INPUT OPTION (A)  
S1  
S2  
S3  
θ
SIN  
SCOTT-T  
VEL  
TRANSFORMER  
θ
COS  
VELOCITY  
ERROR  
PROCESSOR  
AND  
REFERENCE (A)  
ISOLATION  
RH  
RL  
(OPTIONAL)  
INH  
INHIBIT  
REF  
DEMODULATOR  
)
− φ  
(θ  
SIN  
VOLTAGE  
TRANSFORMER  
RESOLVER INPUT OPTION (A)  
CONTROLLED  
OSCILLATOR  
CB  
S1  
S2  
S3  
S4  
CONVERTER  
BUSY  
RESOLVER  
ISOLATION  
TRANSFORMER  
θ
SIN  
− φ)  
(θ  
COS  
ω t  
SIN  
θ
COS  
θ
SIN  
INPUT  
OPTION  
SYNCHRO INPUT OPTION (ST)  
SOLID STATE  
CONTROL  
θ
COS  
UP-DOWN COUNTER  
(CONTAINS ANGLE φ  
SOLID STATE  
SCOTT-T  
BUFFER  
θ
S1  
S2  
S3  
SIN  
TRANSFORMER  
(CT)  
)
θ
COS  
RESOLVER INPUT OPTION (ST)  
BIT  
1
S1  
S2  
S3  
S4  
SOLID STATE  
RESOLVER  
BUFFER  
θ
SIN  
θ
COS  
BIT 10,  
12 OR 14  
BIT  
1
BIT 10, 12, OR 14  
(LSB)  
(MSB)  
FIGURE 1. SDC-630/632/634 A/ST BLOCK DIAGRAM  
* Patented  
1993, 1999 Data Device Corporation  
©
TABLE 1. SDC-630/632/634 A/ST SPECIFICATIONS  
TABLE 1. SDC-630/632/634 A/ST SPECIFICATIONS (CONTD)  
PARAMETER  
VALUE  
PARAMETER  
VALUE  
SDC-632  
12 bits  
POWER SUPPLIES  
+15 V Supply  
+ 5 V Supply  
-15 V Supply  
SDC-630  
10 bits  
SDC-634  
Nominal Voltage  
Range  
Maximum Voltage  
Without Damage  
Current (All)  
RESOLUTION  
14 bits  
3
+11 to +16.5 V -11 to -16.5 V +4.5 to +5.5  
V
ACCURACY  
Standard Units  
High Accuracy Option  
±21 min  
±8.5 min  
±5.3 min  
±2.6 min  
+18 V  
20 mA  
-18 V  
25 mA  
+7  
10 mA  
SIGNAL AND  
REFERENCE INPUT  
Signal  
Frequency  
Range  
Signal Input  
Impedance  
(L-L Balanced, Resistive)  
TEMPERATURE  
RANGES  
Operating  
-1 Option  
-3 Option  
Storage  
A*  
ST  
-55°C to +105°C  
0°C to +70°C  
-55°C to +125°C  
Synchro Input  
90V L-L, 400 Hz  
(Option H)  
148 kmin  
148 kmin  
19 kmin  
123 k  
123 k  
52 k  
350-1000 Hz  
47-1000 Hz  
350-1000 Hz  
90V L-L, 60 Hz  
(Option I)  
11.8V L-L, 400 Hz  
(Option L)  
PHYSICAL  
CHARACTERISTICS  
Size (Encapsulated  
Module)  
Resolver Input  
90V L-L, 400 Hz  
(Option H)  
3.125 x 2.625 x 0.43 inches  
(7.94 x 6.67 x 1.07 cm).  
--  
--  
148 kmin  
42 kmin  
19 kmin  
350-1000 Hz  
350-1000 Hz  
350-1000 Hz  
26V L-L, 60 Hz  
(Option M)  
11.8V L-L, 400 Hz  
(Option L)  
Weight  
4 oz.  
(113 gm.)  
70 k  
NOTE: These specifications apply over temperature range, power  
supply range, reference frequency and amplitude range, ±10%  
signal amplitude variation, and up to 10% harmonic distortion in  
reference input.  
REFERENCE INPUT  
Reference  
Voltage  
Range  
Reference Input Impedance  
(Resistive)  
Options H, I  
Options M, L  
40-150 Vrms 300 kmin  
10- 50 Vrms 80 kmin  
270 k  
60 k  
POWER SUPPLIES  
The main power supplies can vary over the specified ranges with  
no change in converter specifications, except for a proportional  
change in maximum tracking rates.  
* Transformer Isolated. Other voltages and frequencies available on  
special order.  
DIGITAL  
INPUT/OUTPUTS  
Logic Type  
Inhibit Input (INH)  
When testing or evaluating the converters, it is advisable to limit  
the current in each of the supplies. Set each current limit 50%  
greater than the maximum current listed for that supply as listed  
in TABLE 1.  
TTL/CMOS Compatible  
Logic “0” inhibits  
Does not interrupt converter tracking.  
Outputs  
Type  
10, 12, 14, (For 16  
Consult Factory)  
TTL/CMOS  
TIMING  
FIGURE 2 shows the converter timing waveforms. Whenever an  
input angle change occurs, the converter changes the digital  
angle in 1 LSB steps, and generates a Converter Busy (CB)  
pulse. The CB is a positive pulse 0.5 to 1.5 µsec long.  
Parallel Data Bits Natural Binary Angle; Positive logic  
Converter Busy (CB) 0.5 to 1.5 µsec positive pulse.  
Data changes on leading edge.  
Drive Capability  
Built-In-Test (BIT)  
(Special Order,  
Consult Factory)  
1 Std. TTL load  
6.1 µs MIN  
DEPENDS ON dθ  
dt  
"1"  
"0"  
CONVERTER  
BUSY (CB)  
VELOCITY OUTPUT  
(SPECIAL ORDER)  
Polarity  
0.5-1.5 µs  
Positive Output for increasing angle  
"1"  
"0"  
INHIBIT  
(INH)  
.5 µs  
Std. Voltage Range  
(Full Scale)  
±4 Min (Other ranges available; Consult  
Factory)  
DATA  
VALID  
DATA  
VALID  
For other Velocity  
Characteristics  
Consult Factory  
FIGURE 2. SDC-630/632/634* A/ST TIMING DIAGRAM  
2
TABLE 2. SDC-630/632/634 A/ST DYNAMIC CHARACTERISTICS  
60 HZ  
400 HZ  
Bandwidth (non F carrier)  
UNITS  
47 - 1,000  
15  
1,100  
0.1  
7,600  
33  
16.3  
360 - 1,000 (ST to 5,000)  
Hz  
Hz  
1/s  
1/s  
1/s  
1/s  
1/s  
Carrier Frequency Range  
Bandwidth (Closed Loop)  
Ka  
A1  
A2  
A
100  
48,000  
1
48,000  
220  
110  
B
RESOLUTION  
10  
12  
14  
16  
10  
12  
14  
16  
UNITS  
Tracking Rate (rps)  
Typical  
Minimum  
Acceleration (1 LSB lag)  
Settling Time (179° step, max)  
28.5  
24  
370  
500  
7.1  
6
93  
600  
1.8  
1.5  
23  
0.45  
0.37  
5.8  
192  
160  
17,000  
90  
48  
40  
4,220  
100  
12  
10  
1,050  
140  
3
rps  
rps  
°/s  
2.5  
260  
320  
2
900  
2,200  
msec  
The ABSOLUTE value of the resistor is not critical.  
Data changes on the leading edge of the CB pulse, and data can  
be transferred 0.5 µsec after the leading edge.  
In the case of the RESOLVER version (RDC), the equation is:  
RSIG = 2.2k (New L-L Voltage – Standard Unit L-L Voltage)  
The simplest method of interfacing with a computer is to transfer  
data at a fixed time interval after the Inhibit is applied. The con-  
verter will ignore an Inhibit during the “busy” interval until that  
interval is over. Timing is as follows: (a) apply the Inhibit, (b) wait  
0.5 µsec, (c) transfer the data, (d) release the Inhibit. The Inhibit  
line has no effect on converter tracking.  
The calculated resistors are connected in series with S1 and S2  
respectively. Note only two resistors are required. The required  
resistance matching and its effect on accuracy, is the same as for  
a synchro input, see FIGURE 3. The Reference Voltage is treat-  
ed in the same manner, but the value is not critical.  
SIGNAL INPUTS  
R
REF = 2.8k (New Reference – Standard Reference)  
To prevent damage to the inputs, the maximum steady-state volt-  
age should not exceed the specified input voltage by more than  
30%.  
For this use a 10% tolerance resistor is adequate.  
ACCOMMODATING NON-STANDARD INPUT  
VOLTAGES (A ONLY)  
The signal and reference input levels can be resistively scaled to  
accommodate non-standard voltages, see FIGURE 3. Select a  
converter that is the next lower standard voltage, and the voltage  
is then scaled up by using resistors in series with the synchro  
and/or reference inputs.  
R
R
R
SIG  
SIG  
S1  
S2  
S3  
NONSTANDARD  
LINE-TO-LINE  
LEVEL  
For a synchro input (SDC), a resistor RSIG is added in series  
with S1, S2 and S3 which is determined as follows:  
{
SIG  
RSIG = 1.1k (New L-L Voltage – Standard Unit L-L Voltage)  
SDC-630A  
R
REF  
That is, 1.1k for each volt above the design voltage level of the  
standard unit.  
NONSTANDARD  
REFERENCE  
LEVEL  
{
Example: An SDC-634A-L (11.8 V) is to be used at 50 V L-L.  
RSIG = 1.1k (50 – 11.8) = 42.2k  
The closest available high grade resistor with a low temperature  
coefficient of resistance should be used, and the three resistors  
should be as closely matched to each other as possible. In gen-  
eral, a 0.1% difference will introduce 1.7 arc minutes of addition-  
al error due to the effect on SIN/COS ratio relationship.  
FIGURE 3. SDC-630/632/634 A/ST NON-STANDARD  
INPUT LEVEL SCALING  
3
ORDERING INFORMATION  
XXX-XXX-X-X-X-X-X  
Reliability Grade:  
R = Enhanced Reliability  
Accuracy:  
a = High Accuracy Version,  
±2.6 Minutes (SDC-634 Only)  
Temperature Range:  
1 = -55°C to +105°C  
3 = 0°C to + 70°C  
Dimensions are in inches (mm).  
+
2.625 0.015  
-
(66.68)  
0.040 + 0.002  
-
(1.02)  
VEL  
Dia (Typ)  
14 LSB  
+
13  
12  
11  
10  
9
S4  
S3  
S2  
S1  
CB  
Signal Input Voltage and Frequency:  
H = 90 VL-L, 400 Hz (Synchro or  
Resolver)  
SDC-630A/ST  
or  
+
8
0.015  
3.125  
-
0.430  
(10.92)  
(Max)  
SDC-632A/ST  
or  
(79.38)  
INH  
+15V  
GND  
-15V  
+5V  
RL  
7
6
5
4
3
2
1
I = 90 VL-L, 60 Hz (Synchro Only)  
L = 11.8 VL-L, 400 Hz (Synchro or  
Resolver)  
SDC-634A/ST  
0.26 +  
-
(6.604)  
0.01  
Transformer Type:  
A = Internal Transformer  
ST = Solid State  
RH  
MSB  
0.20 +  
0.01  
(Typ)  
(Tol Noncum)  
-
(5.08)  
Resolution:  
2.2 +  
0.25  
(6.35)  
(Min)  
0.01  
(55.88)  
-
0.21+0.01  
-
(5.334)  
636 = 16 bits, Consult Factory  
634 = 14 bits  
632 = 12 bits  
630 = 10 bits  
SIDE VIEW  
BOTTOM VIEW  
Note: VEL is not present on the standard product.  
For VEL output contact factory.  
Input Type:  
SDC = Synchro  
RDC = Resolver  
Note: For versions with Velocity or Built-In-Test, Please  
Consult Factory.  
FIGURE 4. SDC-630/632/634 A/ST  
MECHANICAL OUTLINE  
The information in this data sheet is believed to be accurate; however, no responsibility is assumed by Data Device Corporation for its  
use, and no license or rights are granted by implication or otherwise in connection therewith.  
Specifications are subject to change without notice.  
105 Wilbur Place, Bohemia, New York 11716-2482  
For Technical Support - 1-800-DDC-5757 ext. 7389 or 7413  
Headquarters - Tel: (631) 567-5600 ext. 7389 or 7413, Fax: (631) 567-7358  
Southeast - Tel: (703) 450-7900, Fax: (703) 450-6610  
West Coast - Tel: (714) 895-9777, Fax: (714) 895-4988  
Europe - Tel: +44-(0)1635-811140, Fax: +44-(0)1635-32264  
Asia/Pacific - Tel: +81-(0)3-3814-7688, Fax: +81-(0)3-3814-7689  
World Wide Web - http://www.ddc-web.com  
ILC DATA DEVICE CORPORATION  
REGISTERED TO ISO 9001  
FILE NO. A5976  
D-08/99-500  
PRINTED IN THE U.S.A.  
4

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