SED1520 [ETC]
DOT MATRIX LCD DRIVER; 点阵LCD驱动器
| 型号： | SED1520 |
| 厂家： | 
ETC |
| 描述： | DOT MATRIX LCD DRIVER |
| 文件： | 总52页 (文件大小：200K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
SED1520/21
DOT MATRIX LCD DRIVER
S-MOS Systems, Inc.
October, 1996
Version 1.0 (Preliminary)
THIS PAGE INTENTIONALLY BLANK
2
371-1.0
S-MOS Systems, Inc. • 150 River Oaks Parkway • San Jose, CA 95134 • Tel: (408) 922-0200 • Fax: (408) 922-0238
Table of Contents
1.0
2.0
GENERAL DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
1.1 Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
1.2 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
1.3 SED1520 Family Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
1.4 Model Classification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
BLOCK DIAGRAMS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
2.1 System Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
2.2 Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
2.3 Description of Circuit Blocks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
2.3.1 MPU Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
2.3.2 Busy Flag . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
2.3.3 Display Start Line Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
2.3.4 Column Address Counter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
2.3.5 Page Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
2.3.6 Display Data RAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
2.3.7 Common Timing Generator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
2.3.8 Display Data Latch Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
2.3.9 LCD Driver Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
2.3.10 Display Timing Generator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
2.3.11 Oscillation Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
2.3.12 Reset Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
3.0
PIN CONFIGURATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
3.1 Pin Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
3.2 Pin Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
3.2.1 Power Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
3.2.2 System Bus Interface Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
3.2.3 LCD Drive Circuit Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
4.0
COMMANDS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
4.1 Display ON/OFF . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
4.2 Display Start Line . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
4.3 Set Page Address . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
4.4 Column Address . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
4.5 Read Status. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
4.6 Write Display Data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
4.7 Read Display Data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
4.8 Select ADC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
4.9 Static Drive ON/OFF . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
4.10 Select Duty . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
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Table of Contents
4.11 Read Modify Write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
4.11.1 Cursor Blinking Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
4.12 End . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
4.12.1 End Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
4.13 Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
4.14 Save Power (Combined Command) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
4.14.1 External Resistor Division Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
5.0
ELECTRICAL CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
5.1 Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
5.2 DC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
5.3 Timing Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
5.3.1 System Bus Read/Write I (80 Family MPU) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
5.3.2 System Bus Read/Write II (68 Family MPU) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
5.3.3 Display Control Timing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
6.0
7.0
MPU INTERFACE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
6.1 80 Family MPU . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
6.2 68 Family MPU . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
LCD DRIVER INTERCONNECTIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
7.1 SED1520FOA - SED1520FOA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
7.2 SED1520FAA - SED1520FAA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
7.3 SED1520FOA - SED1521FOA *1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
7.4 SED1520FAA - SED1521FAA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
7.5 HD44103CH - SED1521FAA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
8.0
TYPICAL CONNECTIONS WITH LCD PANEL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
8.1 Duty 1/16, 10 characters x 2 lines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
8.2 Duty 1/16, 23 characters x 2 lines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
8.3 Duty 1/32, 33 characters x 4 lines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
8.4 Duty 1/32, 20 kanji characters x 2 lines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
8.5 Duty 1/32, 2–screen display, 20 kanji characters x 4 lines. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
9.0
PACKAGE DIMENSIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
9.1 Plastic QFP 5-100 Pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
10.0 PAD LAYOUT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49
10.1 Pad Layout (SED1520D/SED1521D) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49
10.1.1 Al Pad . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
10.1.2 Au Bump Pad . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
10.2 Pad Coordinates (SED1520DAB) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51
4
371-1.0
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1.0 General Description
1.0 – 1.2
1.0 GENERAL DESCRIPTION
1.1
DESCRIPTION
The SED1520 is a dot matrix LCD driver LSI intended for display of characters and graphics. The
bit-addressable display data, which is sent from a microcomputer, is stored in a built-in display data
RAM and generates the LCD drive signal.
The SED1520 incorporates innovative circuit design strategies to assure very low current dissipa-
tion and a wide range of operating voltages. With these features, the SED1520 permits the user to
implement high-performance handy systems operating from a miniature battery.
In order for the user to adaptively configure his system, the SED1520 family offers two application
forms. One form allows an LCD display of 12 characters × 2 lines with an indicator with a single
chip. The other is dedicated to driving a total of 80 segments, enabling a medium-size display to
be achieved by using a minimum number of drivers.
1.2
FEATURES
• Low-power CMOS technology
• Fast CPU 8-bit data interface (80xx, 68xx)
• Segment output . . . . . . . . . . 61 outputs
• Common output . . . . . . . . . . 16 outputs
• Duty cycle . . SED1520 . . . 1/16 to 1/32
SED1521 . . . 1/8 to 1/32
• Built-in display data RAM. . . 2560 bits
• Rich display command setting
• On-chip CR oscillation circuit
• Recommended expansion segment driver: 80 bit
• Master/slave operation is supported
• Low power consumption . . . 30µW
• LCD voltage . . . . . . . . . . . . . 3.5 to 13V
• Single power supply. . . . . . . 2.4 to 7.0V
• Package. . . . . . . . . . . . . . . . QFP5-100 pin (FOA, FAA)
QFP15-100 pin (FOC, FAC)
Al pad (DOA, DAA)
Au bump (DOB, DAB)
TAB (TOA)
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1.3 – 1.4
1.0 General Description
1.3
SED1520 FAMILY SPECIFICATIONS
Clock Frequency
No. of SEG
Drivers
No. of COM
Drivers
Product Name
Applicable Driver
On Chip
18kHz
—
External
18kHz
18kHz
2kHz
SED1520FOA
SED1521FOA
SED1520FAA
61
80
61
16
0
SED1520FOA,
SED1521FOA
—
SED1520FAA,
SED1521FAA,
HD44103CH
16
SED1521FAA
—
2kHz
80
0
1.4
MODEL CLASSIFICATION
Operating Clock
SEG
Driver
COM
Driver
Model Name
Connectable Drivers
Internal
External
clock
oscillator
SED1520FO*
SED1520FA*
18KHz
—
18KHz
2KHz
SED1520FO*, SED1521FO* 61 ports 16 ports
SED1520FA*, SED1521FA* 61 ports 16 ports
6
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2.0 Block Diagrams
2.0 – 2.1
2.0 BLOCK DIAGRAMS
2.1
SYSTEM BLOCK DIAGRAM
COM0~COM15
28 CHAR × 2 LINES
SEG0~SEG60
SEG0~SEG79
FR
Ck
SED1520
SED1521
VDD
M/S
M/S
GND
DATA
CONTROL
CPU (68xx, 80xx)
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2.2 – 2.2
2.0 Block Diagrams
2.2
BLOCK DIAGRAM
MPU INTERFACE
COMMAND
DECODER
STATUS
COLUMN ADDRESS REGISTER
COLUMN ADDRESS COUNTER
COLUMN ADDRESS DECODER
FR
CL
DISPLAY
TIMING
GENERATOR
(OSC2)
DISPLAY DATA RAM
2560 BITS
COMMON
COUNTER
DISPLAY DATA LATCH CIRCUIT
LCD DRIVER CIRCUIT
8
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2.0 Block Diagrams
2.3 – 2.3.1.3
2.3
DESCRIPTION OF CIRCUIT BLOCKS
2.3.1 MPU Interface
2.3.1.1 Selection of Interface Type
The SED1520 Series uses 8 bits of bi-directional data bus (D0–D7) to transfer data. The reset pin
is capable of selecting MPU interface; setting the polarity of RES to either “H” or “L” can provide
direct interface of the SED1520 with a 68 or 80 family MPU (see Table 1 below).
With CS at high level, the SED1520 is independent from the MPU bus and stays in standby mode.
In this mode, however, the reset signal is input independently of the internal status.
Table 1
Polarity of RES
Type
A0
↑
E
↑
R/W
↑
CS
↑
D0–D7
“L” active
“H” active
68 MPU
80 MPU
↑
↑
↑
RD
WR
↑
2.3.1.2 Identification of Data Bus Signals
The SED1520 uses a combination of A0, E, R/W, (RD, WR) to identify a data bus signal.
Table 2
Common
68 MPU
80 MPU
Function
A0
1
R/W
RD
0
WR
1
1
0
1
0
Read display data
Write display data
Read status
1
1
0
0
0
1
0
1
0
Write to internal register (command)
2.3.1.3 Access to Display Data RAM and Internal Register
In order to make matching of operating frequencies between the MPU and the display data RAM
or internal register, the SED1520 performs a sort of LSI–LSI pipelining via the bus holder attached
to the internal data bus.
Consider the case where the MPU reads the content of the display data RAM. In the first data read
cycle (dummy), the data is stored on the bus holder. In the next data read cycle, the data is read
from the bus holder to the system bus.
Also, consider the case where the MPU writes data to the display data RAM. In the first data write
cycle, the data is held on the bus holder. The data is written to the display data RAM before the
next data write cycle begins.
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2.3.1.4 – 2.3.1.5
2.0 Block Diagrams
Therefore, MPU’s access to the SED1520 is affected not by display data RAM access time (tACC,
tDS) but by cycle time (tCYC). This leads to faster transfer of data to and from the MPU. If the cycle
time requirement is not met, the MPU has only to execute the NOP instruction and this is appar-
ently equivalent to execution of a waiting operation. However, there is a restriction on the read
sequence of the display data RAM; when an address is set, its data is output not to the first read
instruction (immediately following the address setting operation) but to the second read instruction.
Thus, one dummy read cycle is necessary after an address set or write cycle. This relation is
shown in Figures 2.3.1.4 and 2.3.1.5.
2.3.1.4 Write Timing Diagram
WR
MPU
N
N + 1
N + 2
N + 3
DATA
Bus
Holder
N
N + 1
N + 2
N + 3
Internal
Timing
WR
2.3.1.5 Read Timing Diagram
WR
RD
MPU
N
N
Dummy Read
n
n+1
DATA
Address Set
at N
Data Read
at N
Data Read
at N+1
WR
RD
Internal
Timing
Column
Address
N
N + 1
N + 2
Bus
Holder
N
n
n + 1
n + 2
10
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2.0 Block Diagrams
2.3.2 – 2.3.6
2.3.2 Busy Flag
Busy flag being “1” means that the SED1520 is performing its internal operation and any instruction
other than Read Status is disabled. The busy flag is output to pin D7 by a Read Status instruction.
As long as the cycle time (tCYC) requirement is met, the flag need not be checked before each com-
mand and this dramatically improves the MPU performance.
2.3.3 Display Start Line Register
This register is a pointer which determines the start line corresponding to COM0 (normally, the up-
permost line of display) for display of data in the display data RAM. It is used for scrolling the dis-
play or changing the page from one to another. Executing the Set Display Start Line command
sets 5 bits of display start address in this register. Its content is preset in the line counter at each
timing the FR signal changes. The line counter is incremented synchronously to a CL input, thus
generating a line address for sequential reading of 80 bits of data from the display data RAM to the
LCD driver circuit.
2.3.4 Column Address Counter
The column address counter is a 7–bit presettable counter which gives column addresses of the
display data RAM as shown in Fig. 2.3.8.1. When a Read/Write Display Data command comes in,
the counter is incremented by 1. For any nonexisting address over 50H, the counter is locked and
not incremented.
The column address counter is independent from the page register.
2.3.5 Page Register
This register gives a page address of the display data RAM as shown in Fig. 2.3.8.1. The Set Page
Address command permits the MPU to access a new page of the display data RAM.
2.3.6 Display Data RAM
Dot data for display is stored in this RAM. Since the MPU and LCD driver circuit operate indepen-
dently of each other, data can be changed asynchronously without adverse effect on the display.
One bit of the display data RAM is assigned to one bit of LCD:
LCD on = “1”
LCD off = “0”
The ADC command inverts the assignment relationship between a display data RAM column ad-
dress and a segment output (see Fig. 2.3.8.1).
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2.3.7 – 2.3.8
2.0 Block Diagrams
2.3.7 Common Timing Generator
This circuit generates common timing and frame (FR) signals from the basic clock (CL). The Se-
lect Duty command selects a duty of 1/16 or 1/32. The 1/32 duty is achieved by a two-chip (master
and slave) configuration (common multi-chip system).
2.3.7.1 Common Timing Diagram
FR
(Master
Output)
Master
Common
0
1
2
14 15
0
1
15
Slave
Common
16 17
30 31
16 17
31
2.3.8 Display Data Latch Circuit
The display data latch circuit temporarily stores the data which will be output from the display
data RAM to the LCD driver circuit at one-common intervals. The display ON/OFF and Static
Driver ON/OFF commands control the latched data so that the data in the display data RAM
remains unchanged.
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2.0 Block Diagrams
2.3.8.1 – 2.3.8.1
2.3.8.1 Relationship between Display Data RAM Locations and Addresses (Display Start
Line: 08)
D i s p l a y A r e a
4 F
4 E
4 D
0 0 7 9
0 1 7 8
0 2 7 7
0 7
0 6
0 5
0 4
0 3
0 2
0 1
4 8 7
4 9 6
4 A 5
4 B 4
4 C 3
4 D 2
4 E 1
H 0 0 H 4 F
= 0 “ O D ” = 0 “ I D ”
A D C
S E G 0
S E G P i n
C o l u m n A d d r e s s
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2.3.9 – 2.3.11
2.0 Block Diagrams
2.3.9 LCD Driver Circuit
This circuit generates 80 sets of multiplexer that generate quartet levels for LCD driving. Display
data in the display data latch, common timing generator output and FR signal are combined to out-
put an LCD driving waveform.
2.3.10 Display Timing Generator
Thiscircuitgeneratesaninternaldisplaytimingsignalfromthebasicclock(CL)andframesignal(FR).
The frame signal FR makes the LCD driver circuit generate a dual frame AC driving waveform
(type B) to drive LCD, while making both the line counter and common timing generator synchro-
nized to the FR signal output LSI (dedicated common driver or the SED1520 master LSI). To
achieve these functions, the FR signal must be a clock with a duty of 50% which is synchronized
to the frame period.
The clock CL is a clock used to operate the line counter. For a system in which both the SED1520
and SED1521F coexist, they should be of LSI types having the same clock frequency to be applied
to pin CL.
2.3.11 Oscillation Circuit
This circuit is a low-power CR oscillator which uses an oscillation resistor Rf alone to adjust the
oscillation frequency. It generates display timing signals. The SED1520 is available in two LSI
types if classified by oscillation: one LSI type contains an oscillation circuit and the other uses an
externally provided clock.
The oscillation resistor Rf is connected as shown below. Where an LSI containing an oscillation
circuit is operated with an external clock, it is necessary to input the clock with the same phase as
OSC2 of the master LSI to OSC2 of the slave LSI.
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2.0 Block Diagrams
2.3.11.1 – 2.3.11.2
2.3.11.1 LSI Containing Oscillator
VDD
Master LSI
Slave LSI
(CS) (CL)
M/S
M/S
(CS)
(CL)
OSC1 OSC2
OSC1 OSC2
VSS
Rf
Open
*2
*1
* As the parasitic capacitance in this portion increases, the oscillation frequency will shift to a lower level. The Rf must
have a smaller value than the specification.
* For a system having two or more slave LSIs, a CMOS buffer is necessary.
2.3.11.2 LSI Operating with External Clock
Y-Driver
CL2
SED1521FAA
CL
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2.3.12 – 2.3.12
2.0 Block Diagrams
2.3.12 Reset Circuit
This circuit senses the leading edge or trailing edge of RES and initializes the system when its
power is switched on.
Initialization:
(a) Display off
(b) Display start line register: First line
(c) Static drive off
(d) Column address counter: Address 0
(e) Page address register: Page 0
(f) Select duty: 1/32
(g) Select ADC: Forward (ADC command D0 = “0”, ADC status flag = “1”)
(h) Read modify write off
The input at pin RES is level-sensed to select an MPU interface mode as shown in Table 1. For
interfacing with an 80 family MPU, an “H” active reset signal is input to pin RES. For interfacing
with a 68 family MPU, an “L” active reset signal is input to the pin. (See Fig. 7.)?????
As exemplified in section 6 “MPU Interface”, pin RES is connected to the MPU reset pin. Thus the
SED1520 and the MPU are initialized at the same time. If system is initialized by pin RES at power-
on, it may no longer be reset.
The Reset command causes initialization (b), (d) and (e).
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2.0 Block Diagrams
2.3.12.1 – 2.3.12.1
2.3.12.1 Example of LCD Driving Waveform
1/5 bias, 1/16 duty
1/6 bias, 1/32 duty
0 1 2 3
0 1 2 3
15 0 1 2 3
31 0 1 2 3
15
31
VDD
VSS
FR
VDD
V 1
V 2
V 3
V 4
V 5
COM 0
COM0
1
2
3
4
5
6
7
VDD
V 1
V 2
V 3
V 4
V 5
COM1
COM2
SEG0
SEG1
VDD
V 1
V 2
V 3
V 4
V 5
8
9
10
11
12
13
14
15
VDD
V 1
V 2
V 3
V 4
V 5
VDD
V 1
V 2
V 3
V 4
V 5
V 5
V 4
V 3
V 2
V 1
COM0~SEG0
VDD
–V 1
–V 2
–V 3
–V 4
–V 5
V 5
V 4
V 3
V 2
V 1
COM0~SEG1
VDD
–V 1
–V 2
–V 3
–V 4
–V 5
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THIS PAGE INTENTIONALLY BLANK
18
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3.0 Pin Configuration
3.0 – 3.1
3.0 PIN CONFIGURATION
3.1
PIN CONFIGURATION
80
75
70
65
60
55
SEG22
DB2
50
SEG23
SEG24
SEG25
SEG26
SEG27
SEG28
SEG29
SEG30
SEG31
SEG32
SEG33
SEG34
SEG35
SEG36
SEG37
SEG38
SEG39
SEG40
SEG41
DB3
DB4
DB5
DB6
DB7
85
90
45
40
V
DD
RES
FR
V5
SED1520/SED1521
V3
V2
Index
M/5
V4
V1
95
COM0
COM1
COM2
COM3
COM4
35
30
100
1
5
10
15
20
25
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3.2 – 3.2.2
3.0 Pin Configuration
3.2
PIN DESCRIPTION
Pin No.
Product name
74
OSC1
CS
75
OSC2
CL
96~100, 1~11
COM0~COM15*
SEG76~SEG61
COM0~COM15*
SEG76~SEG61
93
94
V4
95
V1
SED1520FOA
SED1521FOA
SED1520FAA
SED1521FAA
M/S
SEG79
M/S
SEG78
V4
SEG77
V1
CS
CL
CS
CL
SEG79
SEG78
SEG77
* Master LSI common outputs COM0–COM15 correspond to slave LSI outputs COM31–COM16.
3.2.1 Power Signals
VDD
Connected to +5V power. Common to MPU power pin VCC.
VSS
0V, connected to system GND.
V1–V5
Multi-level power used to drive LCDs. Voltage specified to each LCD cell is divided by
resistorsorimpedance-convertedbyanoperationalamplifierbeforebeingapplied. Each
voltage to be applied must be based on VDD, while fulfilling the following conditions:
VDD ≥ V1 ≥ V2 ≥ V3 ≥ V4 ≥ V5
3.2.2 System Bus Interface Signals
D7–D0
8–bit, tri-state, bi-directional I/O bus. Normally, connected to the data bus of an 8–/16–
bit standard microcomputer.
A0
Input pin. Normally, the LSB of the MPU address bus is connected to this input pin to
provide data/command selection.
0: Display control data on D7–D0
1: Display data on D7–D0
RES
Input pin. The SED1520 can be reset or initialized by setting RES to low level (if it is
interfaced with a 68 family MPU) or high level (if with an 80 family MPU). This reset op-
eration occurs when an edge of the RES signal is sensed. The level input selects the
type of interface with the 68 or 80 family MPU:
High level: Interface with 68 family MPU
Low level: Interface with 80 family MPU
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3.0 Pin Configuration
3.2.3 – 3.2.3
CS
Chip Select input signal which is normally obtained by decoding an address bus sig-
nal. Effective with “L” active and a chip operating with external clocks. For a chip con-
taining an oscillator, CS works as an oscillation amplifier input pin to which an
oscillation resistor (Rf) is connected. In this case, RD, WR and E must be a signal
ANDed with CS.
E(RD)
Chip interfaced with 68 family MPU:
Enable Clock signal input for the 68 family MPU.
Chip interfaced with 80 family MPU:
“L” Active input pin to which the 80 family MPU RD signal is connected.
With this signal held at “L”, the SED1520 data bus works as output.
R/W (WR) Chip interface with 68 family MPU:
Read/Write control signal input pin.
R/W = “H” : Read
R/W = “L” : Write
Chip interfaced with 80 family MPU:
“L” Active input pin to which the 80 family WR is connected. The signal
on the data bus is fetched by the leading edge of WR.
3.2.3 LCD Drive Circuit Signals
CL
Input signal effective with a chip using external clocks. This display data latch signal
increments the line counter (at the trailing edge) or the common counter (at the lead-
ing edge). CL is connected to CL2 of the common driver. For a chip containing an
oscillator, this pin works as the oscillation amplifier output pin to which an oscillation
resistor (Rf) is connected.
FR
LCD AC signal I/O pin. Connected to pin M of the common driver.
I/O selection:
Chip containing commons
M/S = 1 : Output
M/S = 0 : Input
Chip containing segments alone
: Input
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3.2.3.1 – 3.2.3.2
3.0 Pin Configuration
SEG0–
SEG79
LCD column (segment) driving output. One of the VDD, V2, V3 and V5 levels is
selected by a combination of the content of display RAM and the FR signal.
3.2.3.1 LCD Column (Segment) Driving Output Timing
FR
1
0
DATA
1
0
1
0
VDD
V2
V5
V3
Output Level
COM0–
COM15
LCD common (row) driving output. One of the VDD, V1, V4 and V5 levels is
selected by a combination of the output of the common counter and the FR
(COM31– signal. The common (row) scanning order for the slave LSI is reverse to that for
COM16) the master LSI.
3.2.3.2 LCD common (row) driving output
FR
1
0
Counter Output
Output Level
1
0
1
0
VS
V1 VDD
V4
M/S
Input signal which selects the master or slave LSI. Connected to VDD or VSS.
(SEG79)
M/S = VDD: Master
M/S = VSS : Slave
M/S selection changes the function of pins FR, COM0–COM15, OSC1 (CS) and
OSC2 (CL):
M/S
VDD
VSS
FR
COM output
COM0–COM15
COM31–COM16
OSC1
Input
NC
OSC2
Output
Input
Output
Input
The common scanning order for the slave driver is reverse to that for master.
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4.0 Commands
4.0 – 4.2
4.0 COMMANDS
Table 3 lists the commands used with the SED1520. This LSI uses a combination of A0, R/W (RD,
WR) to identify a data bus signal. Interpretation and execution of a command depends not on ex-
ternal clock but on internal timing alone. Therefore, a command can be executed so fast that no
busy check is needed.
A detailed description of commands follows.
4.1
DISPLAY ON/OFF
This command forces all display to turn on or off.
R/W
A0 RD WR D7
D0
D
0
1
0
1
0
1
0
1
1
1
D 0 = Display OFF
1 = Display ON
4.2
DISPLAY START LINE
This command specifies a line address (shown in Fig. 2.3.8.1) thus marking the display line that
corresponds to COM0. Display begins with the specified line address and covers as many lines as match
the display duty in address ascending order. Dynamic line address change with the Display Start Line
command enables column-wise scrolling or page change.
R/W
A0 RD WR D7
D0
A4 A3 A2 A1 A0
– High-order bits
0
1
0
1
1
0
A4
0
A3
0
A2
0
A1
0
A0
0
Line address
0
1
0
0
0
0
1
—
—
1
—
—
31
1
1
1
1
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4.3 – 4.4
4.0 Commands
4.3
SET PAGE ADDRESS
This command is used to specify a page address equivalent to a row address for MPU access to
the display data RAM. A required bit of the display data RAM can be accessed by specifying its
page address and column address. Changing the page address causes no change in display.
R/W
A0 RD WR D7
D0
0
1
0
1
0
1
1
1
0
A1 A0
A1
0
A0
Page
0
1
0
1
0
1
2
3
0
1
1
4.4
COLUMN ADDRESS
This command specifies a display data RAM column address. The column address is incremented
by 1 each time the MPU accesses from the set address to the display data RAM. Thus, it is pos-
sible for the MPU to gain continuous access to only the data. This incrementing stops with address
80; the page address is not continuously changed.
R/W
A0 RD WR D7
D0
0
1
0
0
A6 A5 A4 A3 A2 A1 A0
A6 A5 A4 A3 A2 A1 A0 Column address
0
0
0
0
0
0
0
0
0
0
0
0
0
1
0
1
—
—
1
—
—
79
1
0
0
1
1
1
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4.0 Commands
4.5 – 4.6
4.5
READ STATUS
R/W
A0 RD WR D7
D0
0
ON/
OFF
Reset
Busy ADC
0
0
1
0
0
0
BUSY:
BUSY being “1” means that system is performing an internal operation or is reset. No
command is accepted before BUSY = “0”. As long as the cycle time requirement is met,
no BUSY check is needed.
ADC:
Indicates assignment of column addresses to segment drivers.
0: Inverted (column address 79-n ↔ segment driver n)
1: Forward (column address n ↔ segment driver n)
ON/OFF: Indicates display on or off.
0: Display on
1: Display off
This bit has polarity reverse to the Display ON/OFF command.
RESET: Indicates that system is being initialized by the RES signal or the Reset command.
0: Display mode
1: Being reset
4.6
WRITE DISPLAY DATA
This command allows the MPU to write 8 bits of data into the display data RAM. Once the data is
written, the column address is automatically incremented by 1; this enables the MPU to write multi-
word data continuously.
R/W
A0 RD WR D7
D0
1
1
0
Write data
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4.7 – 4.9
4.0 Commands
4.7
READ DISPLAY DATA
This command allows the MPU to read 8 bits of data from the display data RAM location specified
by a column address and a page address. Once the data is read, the column address is automat-
ically incremented by 1; this enables the MPU to read multi-word data continuously.
A dummy read is needed immediately after the column address is set. For details, see 3. (1)–(c).??
R/W
A0 RD WR D7
D0
1
0
1
Read data
4.8
SELECT ADC
This command inverts the relation of assignment between display data RAM column addresses
and segment driver outputs. In other words, the Select ADC command can software-invert the or-
der of segment driver output pins, reducing the restrictions on the configuration of ICs at LCD mod-
ule assembly. For details, see Fig. 2.3.8.1.
Incrementing the column address by 1, which takes place after the MPU writing or reading display
data, follows the sequence of column addresses specified in Fig. 2.3.8.1.
A0 RD WR D7
D0
D
0
1
0
1
0
1
0
0
0
0
D = 0:
D = 1:
Clockwise output (forward)
Counterclockwise output (reverse)
4.9
STATIC DRIVE ON/OFF
This command forces all display to be on and, at the same time, all common output to be selected.
R/W
A0 RD WR D7
D0
D
0
1
0
1
0
1
0
0
1
0
D = 0:
D = 1:
Static drive off
Static drive on
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4.0 Commands
4.10 – 4.11
4.10 SELECT DUTY
This command is used to select the duty (degree of multiplexity) of LCD driving. It is valid for the
SED1520F (actively operating LSI) only, not valid for the SED1521F (passively operating LSI).
The SED1521F operates with any duty determined by the FR signal.
R/W
A0 RD WR D7
D0
D
0
1
0
1
0
1
0
1
0
0
D = 0:
D = 1:
Duty 1/16
Duty 1/32
If the system contains both SED1520FOA (internal oscillation) and the SED1521FOA LSIs, they
must have the same duty.
4.11 READ MODIFY WRITE
This command is used with the End command in a pair. Once it has been entered, the column
address will be incremented not by the Read Display Data command but by the Write Display Data
command only. This mode will stay until the End command is entered.
Entry of the End command causes the column address to return to the address which was valid
when the Read Modify Write command was entered. This function lessens the load of the MPU
when the data in a specific display area are repeatedly updated (as blinking cursor).
R/W
A0 RD WR D7
D0
0
0
1
0
1
1
1
0
0
0
0
Even in the Read Modify Write mode, any command other than Read/Write Data and Set Column
Address may be used.
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4.11.1 – 4.12.1
4.0 Commands
4.11.1 Cursor Blinking Sequence
Page Address Set
Column Address Set
Read Modify Write
Dummy Read
Data Read
Data Write
No
Modify
Ended?
End
4.12 END
This command cancels the Read Modify Write command, returning the column address to the ini-
tial mode address.
R/W
A0 RD WR D7
D0
0
0
1
0
1
1
1
0
1
1
1
4.12.1 End Timing
Return
Column
Address
N
N + 1
N + 2
N + m
N
Read Modify Write Mode Set
End
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4.0 Commands
4.13 – 4.14.1
4.13 RESET
This command initializes the display start line register, column address counter, and page address
counter without any effect on the display data RAM. For details, see section 2.3.12.
The reset operation follows entry of the Reset command.
R/W
A0 RD WR D7
D0
0
0
1
0
1
1
1
0
0
0
1
Initialization at power-on is performed not by the Reset command but by a reset signal applied to
the RES pin.
4.14 SAVE POWER (COMBINED COMMAND)
Static drive going on with display off invokes power-saving mode, reducing current consumption
to nearly static current level. During this mode, the SED1520 holds the following conditions:
(a)It stops driving the LCD; the segment and common driver outputs are at VDD level.
(b)Oscillation and external clock input are disabled; OSC2 is in floating condition.
(c) The display data and operational mode are held.
The power-saving mode is cancelled by display on or static drive off.
If an external resistor division circuit is used to give LCD driving voltage level, the current flowing
into the resistors must be cut off by the power-save signal.
4.14.1 External Resistor Division Circuit
VDD
VDD
V1
V2
SED1520
V3
V4
– •
V5
Power
Save
Signal
VSSH
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4.14.1 – 4.14.1
4.0 Commands
Table 3 Commands
Code
Command
Function
A0 RD WR D7 D6 D5 D4 D3 D2 D1 D0
Turns all display on or off, independently of dis-
play RAM data or internal status.
(1)
(2)
Display ON/OFF
Display start line
0
1
0
1
0
1
0
1
1
1
0/1
1: ON
0: OFF (Power-saving mode with static drive on)*
Display Start Address Specifies RAM line corresponding to uppermost
0
0
0
1
1
1
0
0
0
1
1
0
1
0
0
1
(0–31)
line (COM0) of display.
Page
(0–3)
(3) Set page address
1
1
0
Sets display RAM page in page address register.
Set column
(4)
Sets display RAM column address in column
address register.
Column Address (0–79)
(segment) address
Reads the following status:
BUSY
ADC
1: Internal operation, 0: Ready
1: CW output (forward),
0: CCW output (reverse)
(5)
Read status
0
0
1
0
0
0
0
ON/OFF 1: Display off, 0: Display on
RESET 1: Being reset, 0: Normal
Writes data from
data bus into
display RAM.
Display RAM location
whose address has been
preset is accessed. After
access, the column
address is incremented
by 1.
(6) Write display data
(7) Read display data
1
1
1
0
0
1
Write Data
Read Data
Reads data from
display RAM onto
data bus.
Used to invert relationship of assignment
between display RAM column addresses and
segment driver outputs.
(8)
Select ADC
0
1
0
1
0
1
0
0
0
0
0/1
0: CW output (forward)
1: CCW output (reverse)
Selects normal display or static driving operation.
Static drive ON/
OFF
(9)
0
0
1
1
0
0
1
1
0
0
1
1
0
0
0
1
1
0
0
0
0/1
0/1
1: Static drive (power-saving mode)
0: Normal driving
Selects LCD cell driving duty.
(10)
Select duty
1: 1/32
0: 1/16
Increments column address counter by 1 when
display data is written. (This is not done when
data is read.)
(11) Read modify write
0
0
0
1
1
1
0
0
0
1
1
1
1
1
1
1
1
1
0
0
0
0
1
0
0
1
0
0
1
1
0
0
0
(12)
(13)
End
Clears read modify write mode.
Sets display start line register on the first line.
Also sets column address counter and page
address counter to 0.
Reset
* With display off (command (1)), static drive going on (9) invokes power-saving mode.
30
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5.0 Electrical Characteristics
5.0 – 5.1
5.0 ELECTRICAL CHARACTERISTICS
5.1
ABSOLUTE MAXIMUM RATINGS
Parameter
Supply voltage (1)
Symbol
VSS
Standard
–8.0 ~ +0.3
–16.5 ~ +0.3
Unit
V
Supply voltage (2)
V5
V
V1, V4
V2, V3
Supply voltage (3)
V5 ~ +0.3
V
Input voltage
VIN
VO
VSS – 0.3 ~ +0.3
VSS – 0.3 ~ +0.3
250
V
V
Output voltage
Allowable loss
PD
mW
°C
Operating temperature
Storage temperature
Soldering temperature/time
TOPR
TSTG
TSOLDER
–30 ~ +85
–65 ~ +150
°C
260/10 (at leads)
°C/Sec
Notes:
1. All voltages are based on VDD = 0V.
2. The following condition must always hold true with voltages V1, V2, V3, V4 and V5:
VDD ≥ V1 ≥ V2 ≥ V3 ≥ V4 ≥ V5
3. The LSI may be permanently damaged if used with any value in excess of the absolute maximum ratings. During normal
operation, the LSI should preferably be used within the specified electrical characteristics. Failure to meet them can
cause the LSI to malfunction or lose its reliability.
4. Generally, flat package LSIs may have moisture resistance lowered when solder dipped. In mounting LSIs on a board,
it is recommended to use a method which is least unlikely to give thermal stress on the package resin.
371-1.0
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5.2 – 5.2
5.0 Electrical Characteristics
5.2
DC CHARACTERISTICS
VDD = 0V, Ta = –20 ~ 75°C
Applicable
Symbol
Parameter
Condition
Min.
Typ.
Max.
Unit
pin
Operating Recommended
voltage
–5.5
–7.0
–5.0
–4.5
–2.4
–3.5
VSS
V
VSS
Allowable
(1)*1
Recommended
–13.0
–13.0
0.6 × V5
V5
V5
V
V5 *10
Operating
Allowable
voltage
Allowable
(2)
V1, V2
V3, V4
VDD
V
V
V1, V2
V3, V4
Allowable
0.4 × V5
VSS +
2.0
VIHT
VDD
*2
*3
High level input voltage
V
V
VIHC
VILT
VILC
0.2 × VSS
VSS
VDD
VSS + 0.8
0.8 × VSS
*2
*3
Low level input voltage
High level output voltage
VSS
VSS +
2.4
VOHT IOH = –3.0mA
*4
*5
V
V
VOHC1 IOH = –2.0mA
VSS + 2.4
OSC2
VOHC2 IOH = –120µA
0.2 × VSS
VOLT
IOL = 3.0mA
VSS + 0.4
VSS + 0.4
0.8 × VSS
1.0
*4
*5
Low level output voltage
VOLC1 IOL = 2.0mA
OSC2
VOLC2 IOL = 120µA
Input leakage current
Output leakage current
ILI
–1.0
–3.0
µA
µA
*6
*7
ILO
3.0
V5 = –5.0V
V5 = –3.5V
5.0
7.5
SEG 0 ~ 79
*11
COM 0 ~ 15
LCD driver ON resistor
Static current dissipation
RON
IDDQ
Ta = 25°C
KΩ
µA
10.0
50.0
CS = CL = VDD
fCL = 2KHz
0.05
2.0
9.5
5.0
1.0
5.0
VDD
VDD *12
*13
During
IDD (1) display
V5 = –5.0V
Rf = 1MΩ
15.0
10.0
µA
Dynamic current dissipation
Input pin capacitance
*14
fCL = 18KHz
During access
tCYC = 200KHz
IDD (2)
CIN
300
5.0
500
8.0
µA
*8
Ta = 25°C
f = 1MHz
All input
pins
pF
32
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5.0 Electrical Characteristics
5.2 – 5.2
(Continued)
VDD = 0V, Ta = –20 ~ 75°C
Applicable
Symbol
Parameter
Condition
Min.
Typ.
18
Max.
Unit
pin
Rf = 1.0MΩ ± 2%
VSS = –5.0V
15
21
Oscillation frequency
fOSC
tR
KHz
*9
Rf = 1.0MΩ ± 2%
VSS = –3.0V
11
16
21
Reset time
Notes:
1.0
1000
µs
RES
*1. Operation over a wide range of voltages is guaranteed except where a sudden voltage
change occurs during access.
*2. Pins A0, D0–D7, E(RD), R/W (WR) and CS
*3. Pins CL, FR, M/S and RES
*4. Pins D0–D7
*5. Pin FR
*6. Pins A0, E (RD), R/W (WR), CS, CL and RES
*7. Applicable when pins D0–D7 and FR are at high impedance.
*8. This value is current consumption when a vertical stripe pattern is written at tCYC. Current
consumption during access is nearly proportionate to access frequency (tCYC). Only TDD (1)
is consumed while no access is made.
*9. Relationship between oscillation frequency, frame and Rf (SED1520FOA)
Duty 1/16, 1/32
200
100
40
30
20
10
Ta = 25°C
VSS = –5V
Ta = 25°C
VSS = –5V
0
0.5
1.0
1.5
2.0 2.5
0
0.5
1.0
1.5
2.0 2.5
Rf (MΩ)
Rf (MΩ)
371-1.0
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5.2 – 5.2
5.0 Electrical Characteristics
Notes (continued):
Relationship between external clock (fCL) and frame (SED1520FAA)
200
1/32
1/16
100
0
1
2
3
fCL (kHz)
*10. Operating voltage ranges of VSS and V5
–15
–10
–5
Operating
Voltage
Range
0
–2
–4
–6
–8
VSS (V)
*11. Resistance with a voltage of 0.1V applied between the output pin (SEG, COM) and each pow-
er pin (V1, V2, V3, V4). It is specified within the operating voltage range.
*12, 13, 14. Current consumed by each discrete IC, not including LCD panel and wiring capaci-
tances.
*12. Applicable to SED1520FAA and SED1521FAA
*13. Applicable to SED1520FOA
*14. Applicable to SED1521FOA
34
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5.0 Electrical Characteristics
5.3 – 5.3.1
5.3
TIMING CHARACTERISTICS
5.3.1 System Bus Read/Write I (80 Family MPU)
tAH8
A0, CS
tAW8
tCYC8
tCC
WR, RD
tDS8
tDH8
D0 ~ D7
(WRITE)
tACC8
tOH8
D0 ~ D7
(READ)
Ta = –20 to 75°C, VSS = –5.0V ± 10%, Unit: ns
Signal
Symbol
Parameter
Min.
Max.
Condition
t AH8
t AW8
Address hold time
Address setup time
10
20
A0, CS
t CYC8
t CC
System cycle time
Control pulse width
1000
200
WR, RD
D0–D7
t DS8
t DH8
t ACC8
t OH8
Data setup time
Data hold time
80
10
RD access time
Output disable time
90
60
CL = 100pF
10
*1. Each of the values where VSS = –3.0V is about 200% of that where VSS = –5.0V (i.e., the listed value).
*2. The rise or fall time of input signals should be less than 15 ns.
371-1.0
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5.3.2 – 5.3.2
5.0 Electrical Characteristics
5.3.2 System Bus Read/Write II (68 Family MPU)
tCYC6
E
tAW6
tEW
R/W
tAH6
A0, CS
tDS6
tDH6
D0 ~ D7
(WRITE)
tACC6
tOH6
D0 ~ D7
(READ)
Ta = –20 to 75°C, VSS = –5.0V ± 10%, Unit: ns
Signal
Symbol
Parameter
Min.
Max.
Condition
1
A0, CS
R/W
System cycle time
Address setup time
Address hold time
1000
20
t CYC6*
t AW6
10
t AH6
D0–D7
t DS6
t DH6
tOH6
Data setup time
Data hold time
80
10
10
Output disable time
Access time
60
90
CL = 100pF
t ACC6
t EW
E
Enable pulse width
Read
Write
100
80
*1. t CYC6 indicates the cycle time during which CS•E = “H”. It does not mean the cycle time of signal E.
*2. Each of the values where VSS = –3.0V is about 200% of that where VSS = –5.0V (i.e., the listed value).
*3. The rise or fall time of input signals should be less than 15 ns.
36
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5.0 Electrical Characteristics
5.3.3 – 5.3.3.2
5.3.3 Display Control Timing
CL
tWHCL
tDFR
tWLCL
tf
tr
FR
5.3.3.1 Input Timing
Ta = –20 to 75°C, VSS = –5.0V ± 10%
Unit: µs (tWLCL, tWHCL, tDFR), ns (tr, tf)
Signal
Symbol
tWLCL
tWHCL
tr
Parameter
Low level pulse width
High level pulse width
Rise time
Min.
35
Typ.
Max.
Condition
CL
35
30
30
150
150
2.0
tf
Fall time
tDFR
FR delay time
–2.0
0.2
FR
5.3.3.2 Output Timing
Ta = –20 to 75°C, VSS = –5.0V ± 10%, Unit: µs
Signal
Symbol
Parameter
Min.
Typ.
Max.
Condition
tDFR
FR delay time
0.2
0.4
CL = 100pF
FR
*1. The listed FR input delay time applies to the SED1521 and SED1520 (slave).
The listed FR output delay time applies to the SED1520 (master).
*2. Each of the values where VSS = –3.0V is about 200% of that where VSS = –5.0V (i.e., the listed value).
371-1.0
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THIS PAGE INTENTIONALLY BLANK
38
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6.0 MPU Interface
6.0 – 6.1
6.0 MPU INTERFACE
6.1
80 FAMILY MPU
VDD
VCC
VCC
A 0
A 0
CS
A 2 A 7
IORQ
Decoder
MPU
SED1520
D0 D7
D0 D7
RD
WR
RD
WR
RES
RES
VSS VS
GND
RESET
371-1.0
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6.2 – 6.2
6.0 MPU Interface
6.2
68 FAMILY MPU
VDD
VCC
VCC
A 0
A 0 A 13
VMA
A 0
CS
Decoder
MPU
SED1520
D0 D7
D0 D7
E
E
R/W
RES
R/W
RES
VSS VS
GND
RESET
* These examples also apply to the SED1521FOA/SED1521FAA.
* The SED1520 (containing an oscillator) does not have pin CS. The output ORed with CS must be applied to pins A0,
RD (E) and WR (R/W).
A0
Decoder
SED1520FOA
CS
D0~D7
RD(E)
WR(R/W)
RES
40
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7.0 LCD Driver Interconnections
7.0 – 7.3
7.0 LCD DRIVER INTERCONNECTIONS
7.1
SED1520FOA - SED1520FOA
To
To
LCD
SEG
LCD
SEG
SED1520FOA
Master
SED1520FOA
Slave
COM
To LCD
To LCD COM
VDD
M/S
M/S
VSS
Rf
7.2
SED1520FAA - SED1520FAA
To
LCD
To
LCD
SEG
SEG
SED1520FAA
Master
SED1520FAA
Slave
COM
To LCD
To LCD COM
VSS
VDD
M/S
M/S
External Clock
7.3
SED1520FOA - SED1521FOA *1
To
LCD
To
LCD
SEG
SEG
SED1520FOA
SED1521FOA
COM
To LCD
VDD
M/S
Rf
*2
371-1.0
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7.4 – 7.5
7.0 LCD Driver Interconnections
7.4
SED1520FAA - SED1521FAA
To
LCD
To
LCD
SEG
SEG
SED1520FAA
SED1521FAA
COM
To LCD
VDD
M/S
External Clock
7.5
HD44103CH - SED1521FAA
To
LCD
To
LCD
COM
SEG
HD44103CH
SED1521FAA
Common Driver
Segment Driver
*1. In this connection, the duty of the SED1521FOA must be the same as that of the SED1520FOA.
*2. A CMOS buffer is needed for a system having two or more slave LSIs.
42
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8.0 Typical Connections with LCD Panel
8.0 – 8.2
8.0 TYPICAL CONNECTIONS WITH LCD PANEL
8.1
DUTY 1/16, 10 CHARACTERS X 2 LINES
(Full dot LCD panel: 1 character = 6 × 8 dots)
1
LCD 16 × 61
16
1
61
SEG
SED1520
COM
8.2
DUTY 1/16, 23 CHARACTERS X 2 LINES
(Full dot LCD panel: 1 character = 6 × 8 dots)
1
LCD 16 × 141
16
1
61
62
141
SEG
SEG
SED1520
SED1521
COM
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8.3 – 8.4
8.0 Typical Connections with LCD Panel
8.3
DUTY 1/32, 33 CHARACTERS X 4 LINES
(Full dot LCD panel: 1 character = 6 × 8 dots)
1
16
LCD 32 × 202
17
1
61
62
141
142
202 32
SEG
SEG
SEG
COM
SED1520
Master
SED1520
Slave
SED1521
COM
* SED1521F may be omitted. If it is not used, the panel consists of 32 × 122 dots.
Note: Type AA (using external clock) and type 0A (containing an oscillator) cannot coexist for the same panel.
8.4
DUTY 1/32, 20 KANJI CHARACTERS X 2 LINES
(Kanji – Character 16 x 16 dots)
1
LCD 32 × 320
32
1
80
81
160
161
240
241
320
SEG
SEG
SEG
SEG
SED1521FAA
(1)
SED1521FAA
(2)
SED1521FAA
(3)
SED1521FAA
(4)
44
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8.0 Typical Connections with LCD Panel
8.5 – 8.5
8.5
DUTY 1/32, 2–SCREEN DISPLAY, 20 KANJI CHARACTERS X 4 LINES
SED1521FAA
(5)
SED1521FAA
(6)
SED1521FAA
(7)
SED1521FAA
(8)
SEG
SEG
SEG
SEG
1
LCD 64 × 320
32
33
64
1
80
81
160
161
240
241
320
SEG
SEG
SEG
SEG
SED1521FAA
(1)
SED1521FAA
(2)
SED1521FAA
(3)
SED1521FAA
(4)
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46
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9.0 Package Dimensions
9.0 – 9.1
9.0 PACKAGE DIMENSIONS
9.1
PLASTIC QFP 5-100 PIN
0.4
25.6 ±
0.1
20 ±
80
51
81
50
Index
100
31
1
30
0.1
0.1
0.65 ±
0.30 ±
0 ~12°
2.8
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48
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10.0 Pad Layout
10.0 – 10.1
10.0 PAD LAYOUT
10.1 PAD LAYOUT (SED1520D/SED1521D)
100
95
90
85
1
80
75
70
65
60
55
5
Y
10
15
20
25
30
X
7.04 mm
SED1520DAA
35
40
45
50
4.80 mm
371-1.0
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10.1.1 – 10.1.2
10.0 Pad Layout
10.1.1 Al Pad
Chip Specification
Chip size
Dimensions (mm)
7.04 × 4.80
Chip thickness
Pad size
0.400 ± 0.025
0.10 × 0.10
10.1.2 Au Bump Pad
Chip Specification
Chip size
Dimensions (mm)
7.04 × 4.80
Chip thickness
Pad size
0.525 ± 0.025
0.132 × 0.111
Pad pitch
0.199 min
Bump height
0.020 + 0.01 to –0.005
50
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10.0 Pad Layout
10.2 – 10.2
10.2 PAD COORDINATES (SED1520DAB)
Pad
Name
Pad
Name
Pad
Name
X
Y
X
Y
X
Y
No.
1
No.
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
No.
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
COM5
COM6
159
159
159
159
159
159
159
159
159
159
159
159
159
159
159
159
159
159
159
159
159
159
159
159
159
159
159
159
159
159
504
704
903
1103
6507
6308
6108
5909
5709
5510
5310
5111
4911
4712
4512
4169
3969
3770
3570
3371
3075
2876
2676
2477
2277
2078
1878
1679
1479
1280
1080
881
SEG37
SEG36
SEG35
SEG34
SEG33
SEG32
SEG31
SEG30
SEG29
SEG28
SEG27
SEG26
SEG25
SEG24
SEG23
SEG22
SEG21
SEG20
SEG19
SEG18
SEG17
SEG16
SEG15
SEG14
SEG13
SEG12
SEG11
SEG10
SEG9
1302
1502
1701
1901
2100
2300
2499
2699
2898
3098
3297
3497
2696
3896
4095
4295
4641
4641
4641
4641
4641
4641
4641
4641
4641
4641
4641
4641
4641
4641
4641
4641
4641
4641
159
159
SEG3
SEG2
SEG1
SEG0
A0
4641
4641
4641
4641
4641
4641
4641
4641
4641
4641
4641
4641
4295
4095
3896
3696
3497
3297
3098
2898
2699
2699
2300
2100
1901
1701
1502
1302
1103
903
4148
4347
4547
4789
5048
5247
5447
5646
5846
6107
6307
6506
6884
6884
6884
6884
6884
6884
6884
6884
6884
6884
6884
6884
6884
6884
6884
6884
6884
6884
6884
6884
2
3
COM7
159
4
COM8
159
5
COM9
159
6
COM10
COM11
COM12
COM13
COM14
COM15
SEG60
SEG59
SEG58
SEG57
SEG56
SEG55
SEG54
SEG53
SEG52
SEG51
SEG50
SEG49
SEG48
SEG47
SEG46
SEG45
SEG44
SEG43
SEG42
SEG41
SEG40
SEG39
SEG38
159
CS
7
159
CL
8
159
E(RD)
R/W (WR)
VSS
9
159
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
159
159
DB0
DB1
DB2
DB3
DB4
DB5
DB6
DB7
VDD
159
159
159
159
159
482
681
881
1080
1280
1479
1679
1878
2078
2277
2477
2676
2876
3075
3275
3474
3674
3948
RES
FR
V5
V3
V2
M/S
V4
V1
COM0
COM1
COM2
COM3
COM4
681
482
SEG8
159
SEG7
704
159
SEG6
504
159
SEG5
159
SEG4
371-1.0
51
S-MOS Systems, Inc. • 150 River Oaks Parkway • San Jose, CA 95134 • Tel: (408) 922-0200 • Fax: (408) 922-0238
S-MOS assumes no responsibility or liability for (1) any errors or inaccuracies contained in the
information herein and (2) the use of the information or a portion thereof in any application, in-
cluding any claim for (a) copyright or patent infringement or (b) direct, indirect, special or con-
sequential damages. There are no warranties extended or granted by this document. The
information herein is subject to change without notice from S-MOS.
October 1996
© Copyright 1996 S-MOS Systems, Inc.
Printed in U.S.A.
371-1.0
52
371-1.0
S-MOS Systems, Inc. • 150 River Oaks Parkway • San Jose, CA 95134 • Tel: (408) 922-0200 • Fax: (408) 922-0238
相关型号：
SED1520D0A
LIQUID CRYSTAL DISPLAY DRIVER, UUC100, 7.04 X 4.80 MM, 0.40 MM HEIGHT, ALUMINUM PAD, DIE-100
SEIKO
SED1521D0A
LIQUID CRYSTAL DISPLAY DRIVER, UUC100, 7.04 X 4.80 MM, 0.40 MM HEIGHT, ALUMINUM PAD, DIE-100
SEIKO
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