SEU06464H1CF1SA-25R [ETC]
512MB DDR2 â SDRAM DIMM;
| 型号： | SEU06464H1CF1SA-25R |
| 厂家： | 
ETC |
| 描述： | 512MB DDR2 â SDRAM DIMM 动态存储器 双倍数据速率 |
| 文件： | 总14页 (文件大小：616K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Data Sheet
Rev.1.1
18.11.2010
512MB DDR2 – SDRAM DIMM
Features:
.
240-pin 64-bit DDR2 Dual-In-Line Double Data Rate
synchronous DRAM Module
240 Pin UDIMM
SEU06464H1CF1SA-25R
512MB PC2-6400 in FBGA Technology
RoHS compliant
.
.
.
.
.
.
Module organization: single rank 64M x 64
VDD = 1.8V ±0.1V, VDDQ 1.8V ±0.1V
1.8V I/O ( SSTL_18 compatible)
Serial Presence Detect (SPD) EEPROM
Gold-contact pad
This module is fully pin and functional compatible to the
JEDEC PC2-6400 spec. and JEDEC- Standard MO-237.
(see www.jedec.org)
Options:
.
The pcb and all components are manufactured according
.
Data Rate / Latency
Marking
to the RoHS compliance specification
[EU Directive 2002/95/EC Restriction of Hazardous
Substances (RoHS)]
DDR2 800 MT/s CL6
DDR2 667 MT/s CL5
-25
-30
.
DDR2 - SDRAM component Samsung
K4T1G164QF-BCF7
.
Module Density
512MB with 4 dies and 1 rank
.
.
.
.
.
.
.
.
.
.
64Mx16 DDR2 SDRAM in FBGA-84 package
Four bit prefetch architecture
.
Standard Grade
Grade E
(tA)
(tc)
(tA)
(tc)
0°C to 70°C
0°C to 85°C
0°C to 85°C
0°C to 95°C *)
DLL to align DQ and DQS transitions with CK
Eight internal device banks for concurrent operation
Programmable CAS latency (CL)
Grade W
(tA) -40°C to 85°C
(tc) -40°C to 95°C *)
Posted CAS additive latency (AL)
WRITE latency = READ latency – 1 tCK
Programmable burst length: 4 or 8
Adjustable data-output drive strength
On-die termination (ODT)
*) The refresh rate has to be doubled when 85°C<TC<95°C
Environmental Requirements:
.
Operating temperature (ambient)
standard Grade
0°C to 70°C
.
.
.
.
.
Operating Humidity
10% to 90% relative humidity, noncondensing
Operating Pressure
105 to 69 kPa (up to 10000 ft.)
Storage Temperature
-55°C to 100°C
Storage Humidity
5% to 95% relative humidity, noncondensing
Storage Pressure
Figure: mechanical dimensions1
1682 PSI (up to 5000 ft.) at 50°C
1if no tolerances specified ± 0.15mm
Swissbit AG
Industriestrasse 4
CH-9552 Bronschhofen
Fon: +41 (0) 71 913 03 03
Fax: +41 (0) 71 913 03 15
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eMail: info@swissbit.com
Page 1
of 14
Data Sheet
Rev.1.1
18.11.2010
This Swissbit module is an industry standard 240-pin 8-byte DDR2 SDRAM Dual-In-line Memory Module
(UDIMM) which is organized as x64 high speed CMOS memory arrays. The module uses internally configured
octal-bank DDR2 SDRAM devices. The module uses double data rate architecture to achieve high-speed
operation. DDR2 SDRAM modules operate from a differential clock (CK and CK#). READ and WRITE accesses
to a DDR2 SDRAM module is burst-oriented; accesses start at a selected location and continue for a
programmed number of locations in a programmed sequence. The burst length is either four or eight locations. An
auto precharge function can be enabled to provide a self-timed row precharge that is initiated at the end of a burst
access. The DDR2 SDRAM devices have a multibank architecture which allows a concurrent operation that is
providing a high effective bandwidth. A self refresh mode is provided and a power-saving “power-down” mode. All
inputs and all full drive-strength outputs are SSTL_18 compatible.
The DDR2 SDRAM module uses the optional serial presence detect (SPD) function implemented via serial
EEPROM using the standard I2C protocol. This nonvolatile storage device contains 256 bytes. The first 128 bytes
are utilized by the DIMM manufacturer (swissbit) to identify the module type, the module’s organization and
several timing parameters. The second 128 bytes are available to the end user.
Module Configuration
Row
Addr.
Device Bank
Addr.
Column
Addr.
Module
Bank Select
Organization
DDR2 SDRAMs used
Refresh
64M x 64bit
4 x 64M x 16bit (1024Mbit)
13
BA0, BA1, BA2
10
8k
S0#
Module Dimensions
in mm
133.35 (long) x 30(high) x 2,70 [max] (thickness)
Timing Parameters
Part Number
Module Density
Transfer Rate
Clock Cycle/Data bit rate
Latency
SEU06464H1CF1SA-30R
512 MB
5.3 GB/s
3.0ns/667MT/s
5-5-5
SEU06464H1CF1SA-25R
512 MB
6.4 GB/s
2.5ns/800MT/s
6-6-6
Pin Name
A0 – 9, A11 – A12
A10/AP
Address Inputs
Address Input / Autoprecharge Bit
Bank Address Inputs
BA0 – BA2
DQ0 – DQ63
DM0 – DM7
DQS0 - DQS7
DQS0# - DQS7#
S0#
Data Input / Output
Input Data Mask
Data Strobe, positive line
Data Strobe, negative line (only used when differential data strobe mode is enabled)
Chip Select
RAS#
Row Address Strobe
Column Address Strobe
Write Enable
CAS#
WE#
CKE0
Clock Enable
ODT0
On-Die Termination
Clock Inputs, positive line
CK0
Swissbit AG
Industriestrasse 4
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Page 2
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Data Sheet
Rev.1.1
18.11.2010
CK0#
VDD
Clock Inputs, negative line
Supply Voltage (1.8V+0.1V)
Input / Output Reference
Ground
VREF
VSS
VDDSPD
SCL
Serial EEPROM Positive Power Supply
Serial Clock for Presence Detect
Serial Data Out for Presence Detect
Presence Detect Address Inputs
On-Die Termination
SDA
SA0 – SA1
ODT0
NC
No Connection
Pin Configuration
PIN #
1
Front Side
PIN #
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
Back Side
VSS
PIN #
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
Front Side
A4
PIN #
181
182
183
184
185
186
187
188
189
190
191
192
193
194
195
196
197
198
199
200
201
202
203
204
205
206
207
208
209
210
211
212
Back Side
VDDQ
A3
VREF
VSS
2
DQ4
DQ5
VSS
VDDQ
3
DQ0
DQ1
VSS
A2
A1
4
VDD
VDD
5
DM0
NC
VSS
CK0
CK0#
VDD
6
DQS0#
DQS0
VSS
VSS
7
VSS
VDD
8
DQ6
DQ7
VSS
NC(Par_In)
VDD
A0
9
DQ2
DQ3
VSS
VDD
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
A10/AP
BA0
BA1
VDDQ
RAS#
S0#
DQ12
DQ13
VSS
DQ8
DQ9
VSS
VDDQ
WE#
DM1
NC
CAS#
VDDQ
VDDQ
ODT0
A13
DQS1#
DQS1
VSS
VSS
NC(CS1#)
NC(ODT1)
VDDQ
NC(CK1)
NC(CK1#)
VSS
VDD
NC(Reset)
NC
VSS
VSS
DQ36
DQ37
VSS
VSS
DQ14
DQ15
VSS
DQ32
DQ33
VSS
DQ10
DQ11
VSS
DM4
NC
DQ20
DQ21
VSS
DQS4#
DQS4
VSS
DQ16
DQ17
VSS
VSS
DQ38
DQ39
VSS
DM2
NC
DQ34
DQ35
VSS
DQS2#
DQS2
VSS
VSS
DQ44
DQ45
VSS
DQ22
DQ23
VSS
DQ40
DQ41
VSS
DQ18
DQ19
VSS
DM5
NC
DQ28
DQS5#
Swissbit AG
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Page 3
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Data Sheet
Rev.1.1
18.11.2010
PIN #
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
Front Side
DQ24
DQ25
VSS
PIN #
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
177
178
179
180
Back Side
PIN #
93
Front Side
DQS5
VSS
PIN #
213
214
215
216
217
218
219
220
221
222
223
224
225
226
227
228
229
230
231
232
233
234
235
236
237
238
239
240
Back Side
VSS
DQ29
VSS
94
DQ46
DQ47
VSS
DM3
95
DQ42
DQ43
VSS
DQS3#
DQS3
VSS
NC
96
VSS
97
DQ52
DQ53
VSS
DQ30
DQ31
VSS
98
DQ48
DQ49
VSS
DQ26
DQ27
VSS
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
NC(CK2)
NC(CK2#)
VSS
NC(CB4)
NC(CB5)
VSS
SA2
NC(CB0)
NC(CB1)
VSS
NC(TEST)
VSS
DM6
NC(DM8)
NC
DQS6#
DQS6
VSS
NC
NC(DQS8#)
NC(DQS8)
VSS
VSS
VSS
DQ54
DQ55
VSS
NC(CB6)
NC(CB7)
VSS
DQ50
DQ51
VSS
NC(CB2)
NC(CB3)
VSS
DQ60
DQ61
VSS
VDDQ
DQ56
DQ57
VSS
VDDQ
NC(CKE1)
VDD
CKE0
VDD
DM7
NC(A15)
NC(A14)
VDDQ
DQS7#
DQS7
VSS
NC
BA2
VSS
NC(Par_Out)
VDDQ
DQ62
DQ63
VSS
A12
DQ58
DQ59
VSS
A11
A9
A7
VDD
VDDSPD
SA0
VDD
A8
SDA
A5
A6
SCL
SA1
Signals in brackets (…) may be connected at the DIMM socket, but are not used on the DIMM
Swissbit AG
Industriestrasse 4
CH-9552 Bronschhofen
Fon: +41 (0) 71 913 03 03
Fax: +41 (0) 71 913 03 15
www.swissbit.com
eMail: info@swissbit.com
Page 4
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Data Sheet
Rev.1.1
18.11.2010
FUNCTIONAL BLOCK DIAGRAMM 512MB DDR2 SDRAM DIMM,
1 RANK AND 4 COMPONENTS
Swissbit AG
Industriestrasse 4
CH-9552 Bronschhofen
Fon: +41 (0) 71 913 03 03
Fax: +41 (0) 71 913 03 15
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Page 5
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Data Sheet
Rev.1.1
18.11.2010
MAXIMUM ELECTRICAL DC CHARACTERISTICS
PARAMETER/ CONDITION
Supply Voltage
I/O Supply Voltage
VDDL Supply Voltage
Voltage on any pin relative to VSS
SYMBOL
VDD
VDDQ
VDDL
Vin, Vout
MIN
-1.0
-0.5
-0.5
-0.5
MAX
UNITS
2.3
2.3
2.3
2.3
V
V
V
V
INPUT LEAKAGE CURRENT
Any input 0V ≤ VIN ≤ VDD, VREF pin 0V ≤ VIN ≤ 0.95V
(All other pins not under test = 0V)
µA
II
Command/Address
RAS#, CAS#, WE#, S#, CKE
-40
40
CK, CK#
DM
-20
-5
20
5
µA
µA
OUTPUT LEAKAGE CURRENT
(DQ’s and ODT are disabled; 0V ≤ VOUT ≤ VDDQ
IOZ
-5
5
)
DQ, DQS, DQS#
VREF LEAKAGE CURRENT ; VREF is on a valid level
IVREF
-16
16
DC OPERATING CONDITIONS
PARAMETER/ CONDITION
Supply Voltage
I/O Supply Voltage
SYMBOL
VDD
MIN
1.7
1.7
NOM
1.8
1.8
MAX
1.9
1.9
UNITS
V
V
V
VDDQ
VDDL
VDDL Supply Voltage
1.7
1.8
1.9
I/O Reference Voltage
I/O Termination Voltage (system)
Input High (Logic 1) Voltage
Input Low (Logic 0) Voltage
VREF
VTT
VIH (DC)
VIL (DC)
0.49 x VDDQ
VREF – 0.04
VREF + 0.125
-0.3
0.50 x VDDQ
VREF
0.51x VDDQ
VREF + 0.04
VDDQ + 0.3
VREF – 0.125
V
V
V
V
AC INPUT OPERATING CONDITIONS
PARAMETER/ CONDITION
Input High (Logic 1) Voltage
Input Low (Logic 0) Voltage
SYMBOL
VIH (AC)
MIN
VREF + 0.25
-
MAX
-
VREF - 0.25
UNITS
V
V
VIL (AC)
CAPACITANCE
At DDR2 data rates, it is recommended to simulate the performance of the module to achieve optimum values.
When inductance and delay parameters associated with trace lengths are used in simulations, they are
significantly more accurate and realistic than a gross estimation of module capacitance. Simulations can then
render a considerably more accurate result. JEDEC modules are now designed by using simulations to close
timing budgets.
Swissbit AG
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Page 6
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Data Sheet
Rev.1.1
18.11.2010
IDD Specifications and Conditions
(0°C ≤ TCASE ≤ + 85°C; VDDQ = +1.8V ± 0.1V, VDD = +1.8V ± 0.1V)
Parameter
max.
Symbol
Unit
& Test Condition
5300-555
6400-666
OPERATING CURRENT *) :
One device bank Active-Precharge;
IDD0
220
mA
200
tRC= tRC (IDD); tCK = tCK (IDD); CKE is HIGH, CS# is HIGH
between valid commands;
DQ inputs changing once per clock cycle; Address and
control inputs changing once every two clock cycles
OPERATING CURRENT *) :
IDD1
260
mA
240
One device bank; Active-Read-Precharge;
IOUT = 0mA; BL = 4, CL = CL (IDD), AL = 0;
tCK = tCK (IDD), tRC= tRC (IDD), tRAS = tRAS MIN (IDD),
tRCD = tRCD (IDD); CKE is HIGH, CS# is HIGH between
valid commands; Address inputs changing once every
two clock cycles; Data Pattern is same as IDD4W
PRECHARGE POWER-DOWN CURRENT:
All device banks idle; Power-down mode;
tCK = tCK (IDD); CKE is LOW; All Control and Address
bus inputs are not changing; DQ’s are floating at VREF
PRECHARGE QUIET STANDBY CURRENT:
All device banks idle;
IDD2P
40
88
mA
mA
40
88
IDD2Q
tCK = tCK (IDD); CKE is HIGH, CS# is HIGH;
All Control and Address bus inputs are not changing;
DQ’s are floating at VREF
PRECHARGE STANDBY CURRENT:
All device banks idle;
tCK = tCK (IDD); CKE is HIGH, CS# is HIGH;
All other Control and Address bus inputs are changing
once every two clock cycles; DQ inputs changing once
per clock cycle
ACTIVE POWER-DOWN
CURRENT:
All device banks open; tCK = tCK (IDD);
CKE is LOW; All Control and
IDD2N
IDD3P
IDD3N
116
mA
mA
mA
108
Fast PDN Exit
MR[12] = 0
100
80
96
80
Slow PDN Exit
MR[12] = 1
Address bus inputs are not
changing; DQ’s are floating at VREF
ACTIVE STANDBY CURRENT:
All device banks open; tCK = tCK (IDD),
160
148
tRAS = tRAS MAX (IDD), tRP = tRP (IDD);
CKE is HIGH, CS# is HIGH between valid commands;
All other Control and Address bus inputs are changing
once every two clock cycles; DQ inputs changing once
per clock cycle
OPERATING READ CURRENT:
IDD4R
420
mA
380
All device banks open, Continuous burst reads; One
module rank active; IOUT = 0mA; BL = 4, CL = CL (IDD),
AL = 0; tCK = tCK (IDD), tRAS = tRAS MAX (IDD), tRP = tRP
(IDD); CKE is HIGH, CS# is HIGH between valid
commands; Address bus inputs are changing once
every two clock cycles; DQ inputs changing once per
clock cycle
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Page 7
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Data Sheet
Rev.1.1
18.11.2010
Parameter
max.
Symbol
IDD4W
Unit
& Test Condition
5300-555
6400-666
OPERATING WRITE CURRENT:
380
mA
360
All device banks open, Continuous burst writes; One
module rank active; BL = 4, CL = CL (IDD), AL = 0;
tCK = tCK (IDD), tRAS = tRAS MAX (IDD), tRP = tRP (IDD);
CKE is HIGH, CS# is HIGH between valid commands;
Address bus inputs are changing once every two clock
cycles; DQ inputs changing once per clock cycle
BURST REFRESH CURRENT:
IDD5
440
mA
420
tCK = tCK (IDD); refresh command at every tRFC (IDD)
interval, CKE is HIGH, CS# is HIGH between valid
commands; All other Control and Address bus inputs
are changing once every two clock cycles; DQ inputs
changing once per clock cycle
SELF REFRESH CURRENT:
IDD6
40
mA
mA
40
CK and CK# at 0V; CKE ≤ 0.2V; All other Control and
Address bus inputs are floating at VREF; DQ’s are
floating at VREF
OPERATING CURRENT*) :
IDD7
720
660
Four device bank interleaving READs, IOUT = 0mA; BL = 4,
CL = CL (IDD), AL = tRCD (IDD) – 1 x tCK (IDD); tCK = tCK
(IDD), tRC = tRC (IDD), tRRD = tRRD (IDD), tRCD = tRCD (IDD);
CKE is HIGH, CS# is HIGH between valid commands;
Address bus inputs are not changing during
DESELECT; DQ inputs changing once per clock cycle
*) Value calculated as one module rank in this operating condition, and all other module ranks in
IDD2P (CKE LOW) mode.
TIMING VALUES USED FOR IDD MEASUREMENT
IDD MEASUREMENT CONDITIONS
SYMBOL
CL (IDD
tRCD (IDD
tRC (IDD
tRRD (IDD
tCK (IDD
tRAS MIN (IDD
RAS MAX
(IDD
tRP (IDD
tRFC (IDD
5300-555
6400-666
Unit
tCK
ns
ns
ns
ns
ns
ns
5
15
60
10
3.0
6
15
60
10
2.5
45
)
)
)
)
)
45
70,000
)
70,000
t
)
15
127.5
15
127.5
)
ns
ns
)
Swissbit AG
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Page 8
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Data Sheet
Rev.1.1
18.11.2010
DDR2 SDRAM COMPONENT ELECTRICAL CHARACTERISTICS AND RECOMMENDED
AC OPERATING CONDITIONS
(0°C ≤ TCASE ≤ + 85°C; VDDQ = +1.8V ± 0.1V, VDD = +1.8V ± 0.1V)
AC CHARACTERISTICS
PARAMETER
5300-555
6400-666
SYMBOL
MIN
MAX
-
MIN
2.5
3.0
MAX
8.0
8.0
Unit
ns
ns
ns
ns
tCK
tCK
ps
Clock cycle time
CL = 6
-
CL = 5
CL = 4
CL = 3
3.0
3.75
5.0
0.48
0.48
8.0
8.0
8.0
0.52
0.52
tCK (5)
tCK (4)
tCK (3)
tCH
tCL
tHP
3.75
5.0
8.0
8.0
CK high-level width
CK low-level width
Half clock period
0.48
0.48
0.52
0.52
min
(tCH, tCL)
-0.45
min
(tCH, tCL)
-0.40
Access window (output) of DQS
from CK/CK#
Data-out high-impedance
window from CK/CK#
Data-out low-impedance window
from CK/CK#
+0.45
+0.40
ns
ns
ns
ns
tAC
tHZ
tLZ
+0.45
(= tAC max)
+0.40
(= tAC max)
-0.45
+0.45
-0.40
+0.40
(= tAC min) (= tAC max) (= tAC min) (= tAC max)
DQ and DM input setup time
relative to DQS
0.30
0.25
tDSa
DQ and DM input hold time
relative to DQS
DQ and DM input setup time
relative to DQS
0.30
0.1
0.25
0.05
ns
ns
tDHa
tDS(base)
DQ and DM input hold time
relative to DQS
DQ and DM input pulse width
( for each input )
0.175
0.35
0.125
0.35
ns
tDH(base)
tDIPW
tCK
Data hold skew factor
0.34
0.30
ns
ns
tQHS
tQH
DQ-DQS hold, DQS to first DQ
to go non-valid, per access
Data valid output window
DQS input high pulse width
DQS input low pulse width
DQS output access time from
CK/CK#
DQS falling edge to CK rising
- setup time
DQS falling edge from CK rising
- hold time
DQS –DQ skew, DQS to last DQ
valid, per group, per access
DQS read preamble
DQS read postamble
DQS write preamble
DQS write preamble setup time
DQS write postamble
Positive DQS latching edge to
associated clock edge
Write command to first DQS
latching transition
Address and control input pulse
width ( for each input )
Address and control input setup
time
tHP - tQHS
tHP - tQHS
tQH - tDQSQ
0.35
0.35
tQH - tDQSQ
0.35
0.35
ns
tCK
tCK
ns
tDVW
tDQSH
tDQSL
tDQSCK
-0.40
+0.40
0.24
-0.35
+0.35
0.20
0.2
0.2
0.2
0.2
tCK
tCK
ns
tDSS
tDSH
tDQSQ
0.9
0.4
0.35
0
0.4
- 0.25
1.1
0.6
0.9
0.4
0.35
0
0.4
- 0.25
1.1
0.6
tCK
tCK
tCK
ns
tCK
tCK
tRPRE
tRPST
tWPRE
tWPRES
tWPST
tDQSS
0.6
+ 0.25
0.6
+ 0.25
WL-
tDQSS
0.6
WL+
tDQSS
WL-
tDQSS
0.6
WL+
tDQSS
tCK
tCK
ns
tIPW
tISa
0.4
0.375
Swissbit AG
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Page 9
of 14
Data Sheet
Rev.1.1
18.11.2010
DDR2 SDRAM COMPONENT ELECTRICAL CHARACTERISTICS AND RECOMMENDED
AC OPERATING CONDITIONS (Continued)
(0°C ≤ TCASE ≤ + 85°C; VDDQ = +1.8V ± 0.1V, VDD = +1.8V ± 0.1V)
AC CHARACTERISTICS
PARAMETER
5300-555
6400-666
SYMBOL
MIN
MAX
MIN
MAX
Unit
Address and control input hold
time
Address and control input setup
time
Address and control input hold
time
CAS# to CAS# command delay
0.4
0.20
0.275
0.375
0.175
0.25
ns
tIHa
ns
ns
tISb
tIHb
tCCD
2
60
2
60
tCK
ns
ACTIVE to ACTIVE (same bank)
command period
tRC
ACTIVE bank a to ACTIVE bank
b command
ACTIVE to READ or WRITE
delay
10
15
10
15
ns
ns
tRRD
tRCD
Four bank Activate period
ACTIVE to PRECHARGE
command
50
40
45
40
ns
ns
tFAW
tRAS
70,000
70,000
Internal READ to precharge
command delay
7.5
7.5
ns
tRTP
Write recovery time
Auto precharge write recovery +
precharge time
15
tWR + tRP
15
tWR + tRP
ns
ns
tWR
tDAL
Internal WRITE to READ
command delay
7.5
7.5
ns
tWTR
PRECHARGE command period
PRECHARGE ALL command
period
15
tRP + tCK
15
tRP + tCK
ns
ns
tRP
tRPA
LOAD MODE command cycle
time
2
2
tCK
tMRD
CKE low to CK, CK# uncertainty
tIS + tCK + tIH
127.5
tIS + tCK + tIH
127.5
tCK
ns
tDELAY
tRFC
REFRESH to ACTIVE or
REFRESH to REFRESH
command interval
Average periodic refresh interval
0 °C ≤ TCASE ≤ 85°C
85 °C < TCASE ≤ 95°C
7.8
3.9
7.8
3.9
µs
ns
tREFI
tRFC(min)
+ 10
tRFC(min)
+ 10
Exit SELF REFRESH to non-
READ command
tXSNR
Exit SELF REFRESH to READ
command
Exit SELF REFRESH timing
reference
ODT turn-on delay
ODT turn-on
200
200
tCK
ps
tXSRD
tISXR
tAOND
tIS
tIS
2
2
tCK
ps
tAC(min)
tAC(max)
+ 1,000
tAC(min)
tAC(max)
+ 1,000
tAON
ODT turn-off delay
ODT turn-off
2.5
tAC(min)
2.5
tAC(max)
+ 700
2.5
tAC(min)
2.5
tAC(max)
+ 600
tCK
ps
tAOFD
tAOF
tAC(min) + 2 x tCK
2,000 tAC(max)
+ 1,000
tAC(min) + 2.5 x tCK tAC(min) + 2.5 x tCK
+
tAC(min) + 2 x tCK
2,000 tAC(max)
+ 1,000
+
ODT turn-on (power-down
mode)
ps
tAONPD
ODT turn-off (power-down
mode)
ps
tAOFPD
2,000
+
2,000
+
tAC(max)
+ 1,000
tAC(max)
+ 1,000
ODT to power-down entry
latency
3
3
tCK
tANPD
Swissbit AG
Industriestrasse 4
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Fon: +41 (0) 71 913 03 03
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eMail: info@swissbit.com
Page 10
of 14
Data Sheet
Rev.1.1
18.11.2010
DDR2 SDRAM COMPONENT ELECTRICAL CHARACTERISTICS AND RECOMMENDED
AC OPERATING CONDITIONS (Continued)
(0°C ≤ TCASE ≤ + 85°C; VDDQ = +1.8V ± 0.1V, VDD = +1.8V ± 0.1V)
AC CHARACTERISTICS
PARAMETER
ODT power-down exit latency
ODT enable from MRS
command
5300-555
6400-666
SYMBOL
tAXPD
tMOD
MIN
MAX
MIN
MAX
Unit
tCK
ns
8
0
8
0
12
12
Exit active power-down to READ
command, MR [bit 12 = 0]
Exit active power-down to READ
command, MR [bit 12 = 1]
Exit precharge power-down to
any non-READ command
CKE minimum high/low time
2
2
tCK
tCK
tCK
tCK
tXARD
tXARDS
tXP
7 – AL
8 – AL
2
3
2
3
tCKE
Swissbit AG
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Page 11
of 14
Data Sheet
Rev.1.1
18.11.2010
SERIAL PRESENCE-DETECT MATRIX
BYTE
DESCRIPTION
5300-555
6400-666
0
NUMBER OF SPD BYTES USED
0x80
1
2
3
4
5
6
7
8
TOTAL NUMBER OF BYTES IN SPD DEVICE
FUNDAMENTAL MEMORY TYPE
0x08
0x08
0x0D
0x0A
0x60
0x40
0x00
0x05
NUMBER OF ROW ADDRESSES ON ASSEMBLY
NUMBER OF COLUMN ADDRESSES ON ASSEMBLY
DIMM HIGHT AND MODULE RANKS
MODULE DATA WIDTH
MODULE DATA WIDTH (continued)
MODULE VOLTAGE INTERFACE LEVELS (VDDQ
)
SDRAM CYCLE TIME, (tCK ) [max CL]
CAS LATENCY = 6 (6400), CL = 5 (5300)
9
0x30
0x45
0x25
0x40
SDRAM ACCESS FROM CLOCK, (tAC) [max CL]
CAS LATENCY = 6 (6400); CL = 5 (5300)
10
11
12
13
14
MODULE CONFIGURATION TYPE
REFRESH RATE / TYPE
0x00
0x82
0x10
0x00
SDRAM DEVICE WIDTH (PRIMARY SDRAM)
ERROR- CHECKING SDRAM DATA WIDTH
MINIMUM CLOCK DELAY, BACK-TO-BACK
RANDOM COLUMN ACCESS
15
0x00
16
17
18
19
20
21
BURST LENGTHS SUPPORTED
NUMBER OF BANKS ON SDRAM DEVICE
CAS LATENCIES SUPPORTED
MODULE THICKNESS
0x0C
0x08
0x38
0x70
0x01
0x02
0x00
DDR2 DIMM TYPE
SDRAM MODULE ATTRIBUTES
SDRAM DEVICE ATTRIBUTES: Weak Driver and 50
ODT
22
23
24
25
26
0x07
SDRAM CYCLE TIME, (tCK) [max CL – 1]
CAS LATENCY = 5 (6400), CL = 4 (5300)
0x3D
0x50
0x50
0x60
0x30
0x45
0x3D
0x50
SDRAM ACCESS FROM CK, (tAC) [max CL – 1]
CAS LATENCY = 5 (6400), CL = 4 (5300)
SDRAM CYCLE TIME, (tCK) [max CL – 2]
CAS LATENCY = 4 (6400), CL = 3 (5300)
SDRAM ACCESS FROM CK, (tAC) [max CL – 2]
CAS LATENCY = 4 (6400), CL = 3 (5300)
27
28
29
30
31
MINIMUM ROW PRECHARGE TIME, (tRP
MINIMUM ROW ACTIVE TO ROW ACTIVE, (tRRD
MINIMUM RAS# TO CAS# DELAY, (tRCD
)
0x3C
0x28
0x3C
0x2D
0x80
)
)
MINIMUM RAS# PULSE WIDTH, (tRAS
)
MODULE BANK DENSITY
Swissbit AG
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CH-9552 Bronschhofen
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Page 12
of 14
Data Sheet
Rev.1.1
18.11.2010
SERIAL PRESENCE-DTECT MATRIX (continued)
BYTE
32
DESCRIPTION
5300-555
0x20
6400-666
ADDRESS AND COMMAND SETUP TIME, (tISb
)
0x17
0x25
0x05
0x12
33
ADDRESS AND COMMAND HOLD TIME, (tIHb
)
0x27
34
DATA / DATA MASK INPUT SETUP TIME, (tDSb
)
0x10
35
DATA / DATA MASK INPUT HOLD TIME, (tDHb
WRITE RECOVERY TIME, (tWR
WRITE to READ Command Delay, (tWTR
)
0x17
36
)
0x3C
0x1E
0x1E
0x00
0x06
0x3C
37
)
38
READ to PRECHARGE Command Delay, (tRTP
Mem Analysis Probe
)
39
40
Extension for Bytes 41 and 42
41
MIN ACTIVE AUTO REFRESH TIME, (tRC)
MINIMUM AUTO REFRESH TO ACTIVE /
AUTO REFRESH COMMAND PERIOD, (tRFC)
SDRAM DEVICE MAX CYCLE TIME, (tCKMAX)
42
0x7F
0x80
43
44
SDRAM DEVICE MAX DQS-DQ SKEW TIME, (tDQSQ
SDRAM DEVICE MAX READ DATA HOLD SKEW
)
0x18
0x22
0x14
0x1E
45
46
FACTOR, (tQHS
)
PLL Relock Time
0x00
0x00
0x13
47-61 Optional Features, not supported
62
63
SPD REVISION
CHECKSUM FOR BYTES 0-62
0xA7
0x71
64-66 MANUFACTURER`S JEDEC ID CODE
67 MANUFACTURER`S JEDEC ID CODE (continued)
68-71 MANUFACTURER`S JEDEC ID CODE (continued)
72 MANUFACTURING LOCATION
73-90 MODULE PART NUMBER (ASCII)
0x7F
0Xda
0x00
0x01 (Switzerland) | 0x02 (Germany) | 0x03 (USA)
“SEU06464H1CF1SA-xxR”
91
92
93
94
PCB IDENTIFICATION CODE
X
X
IDENTIFICATION CODE (continued)
YEAR OF MANUFACTURE IN BCD
WEEK OF MANUFACTURE IN BCD
X
X
95-98 MODULE SERIAL NUMBER
X
99-127 MANUFACTURER-SPECIFIC DATA (RSVD)
0x00
128-
Open for customer use
255
0xff
Part Number Code
S
1
E
2
U
3
064 64 H1
C
7
F
8
1
9
SA
10
-
25
11
*
12
R
13
4
5
6
*RoHs compl.
Swissbit AG
SDRAM DDR2
240 Pin Unbuffered 1.8V
Depth (512MB)
DDR2-800MT/s
Chip Vendor (SAMSUNG)
1 Module Rank
Chip Rev. F
Width
PCB-Type (B62U616 1.0)
Chip organisation x16
* optional / additional information
Swissbit AG
Industriestrasse 4
CH-9552 Bronschhofen
Fon: +41 (0) 71 913 03 03
Fax: +41 (0) 71 913 03 15
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eMail: info@swissbit.com
Page 13
of 14
Data Sheet
Rev.1.1
18.11.2010
Locations
Swissbit AG
Industriestrasse 4 – 8
CH – 9552 Bronschhofen
Switzerland
Phone:
Fax:
+41 (0)71 913 03 03
+41 (0)71 913 03 15
_____________________________
Swissbit Germany GmbH
Wolfener Strasse 36
D – 12681 Berlin
Germany
Phone:
Fax:
+49 (0)30 93 69 54 – 0
+49 (0)30 93 69 54 – 55
_____________________________
Swissbit NA, Inc.
14 Willett Avenue, Suite 301A
Port Chester, NY 10573
USA
Phone:
Fax:
+1 914 935 1400
+1 914 935 9865
_____________________________
Swissbit NA, Inc.
3913 Todd Lane, Suite – 307
Austin, TX 78744
USA
Phone:
Fax:
+1 512 302 9001
+1 512 302 4808
_____________________________
Swissbit Japan, Inc.
3F Core Koenji,
2-1-24 Koenji-Kita, Suginami-Ku,
Tokyo 166-0002
Japan
Phone:
Fax:
+81 3 5356 3511
+81 3 5356 3512
Swissbit AG
Industriestrasse 4
CH-9552 Bronschhofen
Fon: +41 (0) 71 913 03 03
Fax: +41 (0) 71 913 03 15
www.swissbit.com
eMail: info@swissbit.com
Page 14
of 14
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