SI8261 [ETC]
5 KV LED EMULATOR INPUT, 4.0 A ISOLATED GATE DRIVERS; 5 KV LED仿真器输入， 4.0隔离栅极驱动器
| 型号： | SI8261 |
| 厂家： | 
ETC |
| 描述： | 5 KV LED EMULATOR INPUT, 4.0 A ISOLATED GATE DRIVERS |
| 文件： | 总42页 (文件大小：405K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Si826x
5 KV LED EMULATOR INPUT, 4.0 A ISOLATED GATE DRIVERS
Features
Pin Assignments:
Pin-compatible, drop-in upgrades for Robust protection features
See page 24
popular high speed opto-coupled
gate drivers
Low power diode emulator simplifies
design-in process
Multiple UVLO ordering options
(5, 8, and 12 V) with hysteresis
60 ns propagation delay,
VDD
VO
1
2
8
7
UVLO
independent of input drive current
0.6 and 4.0 Amp peak output drive
current
Wide VDD range: 5 to 30 V
ANODE
3.75 and 5 kV reinforced isolation
UL, CSA, VDE
AEC-Q100 qualified
e
Rail-to-rail output voltage
Performance and reliability
advantages vs. opto-drivers
Resistant to temperature and age
10x lower FIT rate for longer
service life
14x tighter part-to-part matching
Higher common-mode transient
immunity: >50 kV/µs typical
CATHODE
NC
3
4
6
5
VO
Wide operating temperature range
–40 to +125 °C
RoHS-compliant packages
SOIC-8 (Narrow body)
DIP8 (Gull-wing)
GND
SOIC-8, DIP8, LGA8
Industry Standard Pinout
SDIP6 (Stretched SO-6)
LGA8
VDD
VO
1
2
3
6
5
4
ANODE
NC
UVLO
Applications
e
IGBT/ MOSFET gate drives
Industrial, HEV and renewable
energy inverters
Variable speed motor control in
consumer white goods
Isolated switch mode and UPS
power supplies
CATHODE
GND
AC, Brushless and DC motor
controls and drives
SDIP6
Industry Standard Pinout
Safety Regulatory Approvals (Pending)
Patent pending
UL 1577 recognized
VDE certification conformity
IEC60747-5-2/VDE0884 Part 10
(basic/reinforced insulation)
CQC certification approval
GB4943.1
Up to 5000 Vrms for 1 minute
CSA component notice 5A approval
IEC 60950-1, 61010-1, 60601-1
(reinforced insulation)
Description
The Si826x isolators are pin-compatible, drop-in upgrades for popular opto-
coupled gate drivers, such as 0.6 A ACPL-0302/3020, 2.5 A HCPL-3120/ACPL-
3130, HCNW3120/3130, and similar opto-drivers. The devices are ideal for driving
power MOSFETs and IGBTs used in a wide variety of inverter and motor control
applications. The Si826x isolated gate drivers utilize Silicon Laboratories'
proprietary silicon isolation technology, supporting up to 5.0 kVRMS withstand
voltage per UL1577. This technology enables higher-performance, reduced
variation with temperature and age, tighter part-to-part matching, and superior
common-mode rejection compared to opto-coupled gate drivers. While the input
circuit mimics the characteristics of an LED, less drive current is required,
resulting in higher efficiency. Propagation delay time is independent of input drive
current, resulting in consistently short propagation times, tighter unit-to-unit
variation, and greater input circuit design flexibility. As a result, the Si826x series
offers longer service life and dramatically higher reliability compared to opto-
coupled gate drivers.
Preliminary Rev. 0.9 4/13
Copyright © 2013 by Silicon Laboratories
Si826x
This information applies to a product under development. Its characteristics and specifications are subject to change without notice.
Si826x
Functional Block Diagram
Diode
Emulator
VDD
A1
Output Driver
REC
XMIT
OUT
IF
C1
GND
Diode Emulator Model and I-V Curve
10
Anode
2.2 V
700
Cathode
2
Preliminary Rev. 0.9
Si826x
TABLE OF CONTENTS
Section
Page
1. Electrical Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4
2. Regulatory Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9
3. Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15
3.1. Theory of Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15
4. Technical Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16
4.1. Device Behavior . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16
4.2. Device Startup . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16
4.3. Under Voltage Lockout (UVLO) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .17
5. Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18
5.1. Input Circuit Design . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18
5.2. Output Circuit Design . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19
5.3. Layout Considerations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19
5.4. Power Dissipation Considerations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20
5.5. Parametric Differences between Si826x and HCPL-0302 and HCPL-3120
Opto Drivers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .22
6. Pin Descriptions (SOIC-8, DIP8, LGA8) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .23
7. Pin Descriptions (SDIP6) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .24
8. Ordering Guide . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .25
9. Package Outline: 8-Pin Narrow Body SOIC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .28
10. Land Pattern: 8-Pin Narrow Body SOIC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .29
11. Package Outline: DIP8 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .30
12. Land Pattern: DIP8 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .31
13. Package Outline: SDIP6 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .32
14. Land Pattern: SDIP6 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .34
15. Package Outline: LGA8 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .35
16. Land Pattern: LGA8 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .36
17. Top Markings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .37
17.1. Si826x Top Marking (Narrow Body SOIC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .37
17.2. Top Marking Explanation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .37
17.3. Si826x Top Marking (DIP8) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .38
17.4. Top Marking Explanation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .38
17.5. Si826x Top Marking (SDIP6) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .39
17.6. Top Marking Explanation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .39
17.7. Si826x Top Marking (LGA8) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .40
17.8. Top Marking Explanation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .40
Contact Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .42
Preliminary Rev. 0.9
3
Si826x
1. Electrical Specifications
Table 1. Recommended Operating Conditions
Parameter
Supply Voltage
Symbol
Min
5
Typ
—
Max
30
Unit
V
V
DD
Input Current
I
6
—
30
mA
°C
F(ON)
Operating Temperature (Ambient)
T
–40
—
125
A
Table 2. Electrical Characteristics 1
VDD = 15 V or 30 V, GND = 0 V, IF = 6 mA, TA = –40 to +125 °C; typical specs at 25 °C
Parameter
DC Parameters
Symbol
Test Conditions
Min
Typ
Max Units
2
Supply Voltage
V
I
(V – GND)
5
—
30
V
DD
DD
I = 10 mA
F
V
V
= 15 V
= 30 V
—
—
1.8
2.0
2.4
2.7
mA
mA
Supply Current (Output High)
Supply Current (Output Low)
DD
DD
DD
V = –0.3 to +1.5 V
F
I
V
V
= 15 V
= 30 V
—
—
1.5
1.7
2.1
2.4
mA
mA
DD
DD
DD
Input Current Threshold
Input Current Hysteresis
I
6
—
—
—
mA
mA
F(TH)
I
—
0.34
—
HYS
Input Forward Voltage (OFF)
V
Measured at ANODE with
respect to CATHODE.
—
1
V
F(OFF)
Input Forward Voltage (ON)
Input Capacitance
V
Measured at ANODE with
respect to CATHODE.
1.6
—
2.8
V
F(ON)
C
f = 100 kHz,
I
—
—
15
15
—
—
pF
V = 0 V,
F
V = 2 V
F
Si826xAxx devices
—
—
—
—
15
2.6
5.0
0.8
—
5.1
—
Output Resistance High
(Source)
R
OH
3
Si826xBxx devices (I = -1 A)
OH
Si826xAxx devices
3
R
Output Resistance Low (Sink)
OL
Si826xBxx devices (I = 2 A)
2.0
OL
Notes:
1. See "8.Ordering Guide" on page 25 for more information.
2. Minimum value of (VDD - GND) decoupling capacitor is 1 µF.
3. Both VO pins are required to be shorted together for 4.0 A compliance.
4. When performing this test, it is recommended that the DUT be soldered to avoid trace inductances, which may cause
over-stress conditions.
4
Preliminary Rev. 0.9
Si826x
Table 2. Electrical Characteristics (Continued)1
VDD = 15 V or 30 V, GND = 0 V, IF = 6 mA, TA = –40 to +125 °C; typical specs at 25 °C
Parameter
Symbol
Test Conditions
Si826xAxx devices (I = 0),
Min
Typ
Max Units
F
(t
< 250 ns)
—
0.4
—
PW_IOH
(see Figure 2)
3,4
I
A
Output High Current (Source)
OH
Si826xBxx devices (I = 0),
F
(t
< 250 ns),
PW_IOH
(V – V = 4 V)
(see Figure 2)
0.5
—
1.8
0.6
—
DD
O
Si826xAxx devices
(I = 10 mA),
F
—
(t
< 250 ns)
PW_IOL
(see Figure 1)
3,4
I
A
Output Low Current (Sink)
OL
Si826xBxx devices
(I = 10 mA),
F
(t
< 250 ns),
PW_IOL
1.2
—
4.0
—
(V - GND = 2.5 V)
O
(see Figure 1)
Si826xAxx devices
(I
V
–
DD
—
0.4
= –100 mA)
OUT
Si826xBxx devices
(I = –100 mA)
V
0.25
–
DD
V
0.5
–
DD
—
V
V
High-Level Output Voltage
OH
OUT
Si826xBxx devices
(I = 0 mA),
—
—
V
—
DD
OUT
(I = 0 mA)
F
Si826xAxx devices
(I = 100 mA),
—
320
OUT
(I = 10 mA)
F
V
mV
200
Low-Level Output Voltage
OL
Si826xBxx devices
(I = 100 mA),
—
5
80
5.6
5.3
300
OUT
(I = 10 mA)
F
UVLO Threshold +
(Si826xxAx mode)
VDD
VDD
See Figure 10 on page 17.
rising
6.3
6.0
—
V
V
UV+
V
DD
UVLO Threshold –
(Si826xxAx mode)
4.7
—
See Figure 10 on page 17.
falling
UV–
V
DD
UVLO lockout hysteresis
(Si826xxAx mode)
mV
VDD
HYS
Notes:
1. See "8.Ordering Guide" on page 25 for more information.
2. Minimum value of (VDD - GND) decoupling capacitor is 1 µF.
3. Both VO pins are required to be shorted together for 4.0 A compliance.
4. When performing this test, it is recommended that the DUT be soldered to avoid trace inductances, which may cause
over-stress conditions.
Preliminary Rev. 0.9
5
Si826x
Table 2. Electrical Characteristics (Continued)1
VDD = 15 V or 30 V, GND = 0 V, IF = 6 mA, TA = –40 to +125 °C; typical specs at 25 °C
Parameter
UVLO Threshold +
Symbol
Test Conditions
Min
Typ
Max Units
VDD
See Figure 11 on page 17.
7.5
8.4
9.4
V
UV+
V
rising
(Si826xxBx mode)
DD
UVLO Threshold –
(Si826xxBx mode)
VDD
See Figure 11 on page 17.
falling
6.9
7.9
8.9
V
UV–
V
DD
UVLO lockout hysteresis
(Si826xxBx mode)
—
500
12
—
mV
V
VDD
VDD
HYS
UVLO Threshold +
(Si826xxCx mode)
See Figure 12 on page 17.
rising
10.5
13.5
UV+
V
DD
UVLO Threshold –
(Si826xxCx mode)
VDD
See Figure 12 on page 17.
falling
9.4
—
10.7
1.3
12.2
—
V
V
UV–
HYS
V
DD
UVLO lockout hysteresis
(Si826xxCx mode)
VDD
AC Switching Parameters
Propagation delay (Low-to-High)
Propagation delay (High-to-Low)
Pulse Width Distortion
Propagation Delay Difference
Rise time
t
t
C = 200 pF
20
10
—
—
—
—
—
40
30
10
—
60
50
—
20
15
20
30
ns
ns
ns
ns
ns
ns
µs
PLH
L
C = 200 pF
PHL
L
PWD
PDD
|t
– t
|
PLH
PHL
|t
– t
|
PHLMAX
PLHMIN
t
C = 200 pF
5.5
8.5
16
R
L
Fall time
t
C = 200 pF
L
F
Device Startup Time
t
START
Common Mode
Transient Immunity
CMTI
Output = low or high
kV/µs
(V
= 1500 V), (I > 6 mA)
CM
F
35
50
—
(See Figure 3)
Notes:
1. See "8.Ordering Guide" on page 25 for more information.
2. Minimum value of (VDD - GND) decoupling capacitor is 1 µF.
3. Both VO pins are required to be shorted together for 4.0 A compliance.
4. When performing this test, it is recommended that the DUT be soldered to avoid trace inductances, which may cause
over-stress conditions.
6
Preliminary Rev. 0.9
Si826x
VDD = 15 V
SCHOTTKY
VDD
10
IN
OUT
Si826x
+
9 V
VSS
100 µF
_
1 µF
INPUT
1 µF
CER
10 µF
EL
Measure
RSNS
0.1
50 ns
IF
GND
200 ns
INPUT WAVEFORM
Figure 1. IOL Sink Current Test Circuit
VDD = 15 V
VDD
10
IN
OUT
Si826x
SCHOTTKY
+
VSS
100 µF
1 µF
5.5 V
_
INPUT
1 µF
CER
10 µF
EL
Measure
RSNS
0.1
50 ns
IF
GND
200 ns
INPUT WAVEFORM
Figure 2. IOH Source Current Test Circuit
Preliminary Rev. 0.9
7
Si826x
15 V
Supply
267
Si826x
ANODE
VDD
VO
Input Signal
Switch
5V
Isolated
Supply
Oscilloscope
GND
CATHODE
Isolated
Ground
Output
High Voltage
Differential Probe
Input
Vcm Surge
Output
High Voltage
Surge Generator
Figure 3. Common Mode Transient Immunity Characterization Circuit
8
Preliminary Rev. 0.9
Si826x
2. Regulatory Information
Table 3. Regulatory Information (Pending)*
CSA
The Si826x is certified under CSA Component Acceptance Notice 5A. For more details, see File 232873.
61010-1: Up to 600 V reinforced insulation working voltage; up to 600 V basic insulation working voltage.
RMS
RMS
60950-1: Up to 1000 V
age.
reinforced insulation working voltage; up to 1000 V
basic insulation working volt-
RMS
RMS
60601-1: Up to 250 V
reinforced insulation working voltage; up to 500 V
basic insulation working voltage.
RMS
RMS
VDE
The Si826x is certified according to IEC 60747-5-2. For more details, see File 5006301-4880-0001.
60747-5-2: Up to 1414 V
for reinforced insulation working voltage.
peak
UL
The Si826x is certified under UL1577 component recognition program. For more details, see File E257455.
Rated up to 5000 V
isolation voltage for basic protection.
RMS
CQC
The Si826x is certified under GB4943.1-2011. For more details, see File number pending.
Rated up to 1000 V reinforced insulation working voltage; up to 1000 V basic insulation working voltage.
RMS
RMS
*Note: Regulatory Certifications apply to 3.75 kVRMS rated devices which are production tested to 4.5 kVRMS for 1 sec.
Regulatory Certifications apply to 5.0 kVRMS rated devices which are production tested to 6.0 kVRMS for 1 sec.
For more information, see "8.Ordering Guide" on page 25.
Table 4. Insulation and Safety-Related Specifications
Value
Parameter
Symbol Test Condition
Unit
SOIC-8
DIP8
SDIP6
LGA8
L(IO1)
L(IO2)
4.7 min
7.2 min
9.6 min 10.0 min
8.3 min 10.0 min
mm
mm
Nominal Air Gap (Clearance)
Nominal External Tracking
(Creepage)
3.9 min
0.016
7.0 min
0.016
Minimum Internal Gap
(Internal Clearance)
0.016
0.016
mm
V
Tracking Resistance
(Proof Tracking Index)
PTI
ED
IEC60112
f = 1 MHz
600
600
600
600
0.031
0.031
0.057
0.021
mm
Erosion Depth
12
12
12
12
R
10
10
10
10
Resistance (Input-Output)*
Capacitance (Input-Output)*
IO
C
1
1
1
1
pF
IO
*Note: To determine resistance and capacitance, the Si826x is converted into a 2-terminal device. Pins 1–4 (1–3, SDIP6) are
shorted together to form the first terminal, and pins 5–8 (4–6, SDIP6) are shorted together to form the second terminal.
The parameters are then measured between these two terminals.
Preliminary Rev. 0.9
9
Si826x
Table 5. IEC 60664-1 (VDE 0844 Part 2) Ratings
Specification
DIP8 SDIP6
Parameter
Test Conditions
SOIC-8
LGA8
Basic Isolation Group
Material Group
Rated Mains Voltages <
I
I
I
I
I-IV
I-IV
I-IV
I-IV
150 V
RMS
Rated Mains Voltages <
300 V
I-IV
I-III
I-III
—
I-IV
I-III
I-III
—
I-IV
I-IV
I-IV
—
I-IV
I-IV
I-IV
I-III
RMS
Installation
Classification
Rated Mains Voltages <
450 V
RMS
Rated Mains Voltages <
600 V
RMS
Rated Mains Voltages <
1000 V
RMS
Table 6. IEC 60747-5-2 Insulation Characteristics*
Characteristic
DIP8 SDIP6
Symbol
Test Condition
Unit
Parameter
SOIC-8
LGA8
Maximum Working
Insulation Voltage
V
630
891
1140
1414
V peak
V peak
IORM
Method b1
(V
x 1.875 = V
100%
,
PR
IORM
Input to Output Test
Voltage
V
1181
1671
2138
2652
PR
Production Test, t = 1 sec,
m
Partial Discharge < 5 pC)
V
V
t = 60 sec
6000
10
6000
10
8000
10
8000
10
V peak
Transient Overvoltage
Surge Voltage
IOTM
1.2 s rise, 50 s fall 50%
kV peak
IOSM
Pollution Degree
(DIN VDE 0110, Table 1)
2
2
2
2
Insulation Resistance at
9
9
9
9
R
>10
>10
>10
>10
S
T , V = 500 V
S
IO
*Note: This isolator is suitable for reinforced electrical isolation only within the safety limit data. Maintenance of the safety
data is ensured by protective circuits. The Si826x provides a climate classification of 40/125/21.
10
Preliminary Rev. 0.9
Si826x
Table 7. IEC Safety Limiting Values*
Max
Parameter
Symbol
Test Condition
Unit
SOIC-8
140
DIP8
140
SDIP6
140
LGA8
Case Temperature
Input Current
T
I
140
185
°C
S
= 110 °C/W (SOIC-8),
110 °C/W (DIP8),
105 °C/W (SDIP6),
220 °C (LGA8),
370
370
390
mA
S
JA
V = 2.8 V, T = 140 °C,
F
J
T = 25 °C
A
Output Power
P
1
1
1
0.5
W
S
*Note: Maximum value allowed in the event of a failure; also see the thermal derating curve in Figures 4, 5, 6, and 7.
Preliminary Rev. 0.9
11
Si826x
Table 8. Thermal Characteristics
Typ
Parameter
Symbol
Unit
SOIC-8
DIP8
SDIP6
LGA8
IC Junction-to-Air Thermal
Resistance
110
110
105
220
ºC/W
JA
1200
1000
800
ꢀPsꢀꢀ(mW)
600
Isꢀ(mA)
400
200
0
0
20
40
60
80
100
120
140
TsꢀͲ CaseꢀTemperatureꢀ(°C)
Figure 4. (SOIC-8) Thermal Derating Curve, Dependence of Safety Limiting Values
with Case Temperature per DIN EN 60747-5-2
1200
1000
ꢀPsꢀꢀ(mW)
800
600
Isꢀ(mA)
400
200
0
0
20
40
60
80
100
120
140
TsꢀͲ CaseꢀTemperatureꢀ(°C)
Figure 5. (DIP8) Thermal Derating Curve, Dependence of Safety Limiting Values
with Case Temperature per DIN EN 60747-5-2
12
Preliminary Rev. 0.9
Si826x
1200
1000
800
600
400
200
0
ꢀPsꢀꢀ(mW)
Isꢀ(mA)
0
20
40
60
80
100
120
140
TsꢀͲ CaseꢀTemperatureꢀ(°C)
Figure 6. (SDIP6) Thermal Derating Curve, Dependence of Safety Limiting Values
with Case Temperature per DIN EN 60747-5-2
600
500
Psꢀꢀ(mW)
400
300
Isꢀ(mA)
200
100
0
0
20
40
60
80
100
120
140
TsꢀͲ CaseꢀTemperatureꢀ(°C)
Figure 7. (LGA8) Thermal Derating Curve, Dependence of Safety Limiting Values
with Case Temperature per DIN EN 60747-5-2
Preliminary Rev. 0.9
13
Si826x
Table 9. Absolute Maximum Ratings*
Parameter
Storage Temperature
Symbol
Min
–65
–40
—
Max
+150
+125
+140
30
Units
°C
T
STG
Operating Temperature
T
°C
A
Junction Temperature
T
°C
J
Average Forward Input Current
I
—
mA
A
F(AVG)
Peak Transient Input Current
(< 1 µs pulse width, 300 ps)
I
—
1
FTR
Peak Output Current (t
Peak Output Current (t
Reverse Input Voltage
Supply Voltage
= 10 µs) (Si826xA)
= 10 µs) (Si826xB)
I
I
—
—
0.6
4.0
0.3
36
A
A
PW
PW
OPK
OPK
V
—
V
R
VDD
–0.5
–0.5
—
V
Output Voltage
V
36
V
OUT
Output Current
I
10
mA
mW
mW
mW
O(AVG)
Input Power Dissipation
Output Power Dissipation
Total Power Dissipation
P
—
75
I
P
—
225
300
O
P
—
T
(all packages limited by thermal derating curve)
Lead Solder Temperature (10 s)
HBM Rating ESD
—
4
260
—
°C
kV
V
Machine Model ESD
300
2000
—
—
CDM
—
V
Maximum Isolation Voltage (1 s) SOIC-8
Maximum Isolation Voltage (1 s) DIP8
Maximum Isolation Voltage (1 s) SDIP6
Maximum Isolation Voltage (1 s) LGA8
4500
6500
6500
6500
V
V
V
V
RMS
RMS
RMS
RMS
—
—
—
*Note: Permanent device damage may occur if the absolute maximum ratings are exceeded. Functional operation should be
restricted to the conditions specified in the operational sections of this data sheet.
14
Preliminary Rev. 0.9
Si826x
3. Functional Description
3.1. Theory of Operation
The Si826x is a functional upgrade for popular opto-isolated drivers, such as the Avago HPCL-3120, HPCL-0302,
Toshiba TLP350, and others. The operation of an Si826x channel is analogous to that of an opto coupler, except an
RF carrier is modulated instead of light. This simple architecture provides a robust isolated data path and requires
no special considerations or initialization at start-up. A simplified block diagram for the Si826x is shown in Figure 8.
Transmitter
Receiver
RF
OSCILLATOR
VDD
Semiconductor-
Based Isolation
Barrier
LED
Emulator
MODULATOR
DEMODULATOR
A
B
0.6 to 4.0 A
peak
Gnd
Figure 8. Simplified Channel Diagram
Preliminary Rev. 0.9
15
Si826x
4. Technical Description
4.1. Device Behavior
Truth tables for the Si826x are summarized in Table 10.
Table 10. Si826x Truth Table Summary*
Input
V
V
O
DD
OFF
OFF
ON
> UVLO
< UVLO
> UVLO
< UVLO
LOW
LOW
HIGH
LOW
ON
*Note: This truth table assumes VDD is powered. If VDD is below UVLO, see "4.3.Under Voltage
Lockout (UVLO)" on page 17 for more information.
4.2. Device Startup
Output V is held low during power-up until V
rises above the UVLO+ threshold for a minimum time period of
DD
O
t
. Following this, the output is high when the current flowing from anode to cathode is > I
. Device startup,
START
F(ON)
normal operation, and shutdown behavior is shown in Figure 9.
UVLO+
VDDHYS
UVLO-
VDD
IF(ON)
IHYS
IF
tPHL
tPLH
tSTART
tSTART
VO
Figure 9. Si826x Operating Behavior (IF > IF(MIN) when VF > VF(MIN)
)
16
Preliminary Rev. 0.9
Si826x
4.3. Under Voltage Lockout (UVLO)
The UVLO circuit unconditionally drives V low when V is below the lockout threshold. Referring to Figures 10
O
DD
through 12, upon power up, the Si826x is maintained in UVLO until VDD rises above VDD
. During power down,
UV+
the Si826x enters UVLO when VDD falls below the UVLO threshold plus hysteresis (i.e., VDD < VDD
–
UV+
VDD
).
HYS
VDDUV+ (Typ)
VDDUV+ (Typ)
3.5
4.0 4.5 5.0 5.5 6.0 6.5 7.0 7.5
9.5 10.0 10.5 11.0 11.5 12.0 12.5 13.0
Supply Voltage (VDD - GND) (V)
Supply Voltage (VDD - GND) (V)
Figure 10. Si826xxAx UVLO Response (5 V)
Figure 12. Si826xxCx UVLO Response (12 V)
VDDUV+ (Typ)
6.0
6.5 7.0 7.5 8.0 8.5 9.0 9.5 10.0
Supply Voltage (VDD - GND) (V)
Figure 11. Si826xxBX UVLO Response (8 V)
Preliminary Rev. 0.9
17
Si826x
5. Applications
The following sections detail the input and output circuits necessary for proper operation. Power dissipation and
layout considerations are also discussed.
5.1. Input Circuit Design
Opto driver manufacturers typically recommend the circuits shown in Figures 13 and 14. These circuits are
specifically designed to improve opto-coupler input common-mode rejection and increase noise immunity.
Si826x
Vdd
N/C
1
2
R1
ANODE
Control
Input
3
4
CATHODE
N/C
Open Drain or
Collector
Figure 13. Si826x Input Circuit
Vdd
Si826x
N/C
1
2
ANODE
Control
Input
Q1
3
4
CATHODE
N/C
R1
Figure 14. High CMR Si826x Input Circuit
The optically-coupled driver circuit of Figure 13 turns the LED on when the control input is high. However, internal
capacitive coupling from the LED to the power and ground conductors can momentarily force the LED into its off
state when the anode and cathode inputs are subjected to a high common-mode transient. The circuit shown in
Figure 14 addresses this issue by using a value of R1 sufficiently low to overdrive the LED, ensuring it remains on
during an input common-mode transient. Q1 shorts the LED off in the low output state, again increasing common-
mode transient immunity.
Some opto driver applications recommend reverse-biasing the LED when the control input is off to prevent coupled
noise from energizing the LED. The Si826x input circuit requires less current and has twice the off-state noise
margin compared to opto couplers. However, high CMR opto coupler designs that overdrive the LED (see
Figure 14) may require increasing the value of R1 to limit input current I to its maximum rating when using the
F
Si826x. In addition, there is no benefit in driving the Si826x input diode into reverse bias when in the off state.
Consequently, opto coupler circuits using this technique should either leave the negative bias circuitry unpopulated
18
Preliminary Rev. 0.9
Si826x
or modify the circuitry (e.g., add a clamp diode or current limiting resistor) to ensure that the anode pin of the
Si826x is no more than –0.3 V with respect to the cathode when reverse-biased.
New designs should consider the input circuit configurations of Figure 15, which are more efficient than those of
Figures 13 and 14. As shown, S1 and S2 represent any suitable switch, such as a BJT or MOSFET, analog
transmission gate, processor I/O, etc. Also, note that the Si826x input can be driven from the I/O port of any MCU
or FPGA capable of sourcing a minimum of 6 mA (see Figure 15B). Additionally, note that the Si826x propagation
delay and output drive do not significantly change for values of I between I
and I
.
F
F(MIN)
F(MAX)
Si826x
Si826x
N/C
+5V
S1
1
2
N/C
1
2
Control
Input
R1
S2
MCU I/O
Port pin
ANODE
ANODE
R1
3
4
CATHODE
CATHODE
3
4
N/C
N/C
A
B
Figure 15. Si826x Other Input Circuit Configurations
5.2. Output Circuit Design
GND can be biased at, above, or below ground as long as the voltage on V with respect to GND is a maximum
DD
of 30 V. V
decoupling capacitors should be placed as close to the package pins as possible. The optimum
DD
values for these capacitors depend on load current and the distance between the chip and its power source. It is
recommended that 0.1 and 10 µF bypass capacitors be used to reduce high-frequency noise and maximize
performance.
5.3. Layout Considerations
It is most important to minimize ringing in the drive path and noise on the V
lines. Care must be taken to
DD
minimize parasitic inductance in these paths by locating the Si826x as close as possible to the device it is driving.
In addition, the V supply and ground trace paths must be kept short. For this reason, the use of power and
DD
ground planes is highly recommended. A split ground plane system having separate ground and V
power devices and small signal components provides the best overall noise performance.
planes for
DD
Preliminary Rev. 0.9
19
Si826x
5.4. Power Dissipation Considerations
Proper system design must assure that the Si826x operates within safe thermal limits across the entire load range.
The Si826x total power dissipation is the sum of the power dissipated by bias supply current, internal switching
losses, and power delivered to the load, as shown in Equation 1.
PD = IF VF DC + VDD IDDQ + Qd + CL VDD f
where: PD is the total device power dissipation (W)
IF is the diode current (30 mA max)
VF is the diode anode to cathode voltage (2.8 V max)
DC is duty cycle (0.5 typical)
VDD is the driver-side supply voltage (30 V max)
IDDQ is the driver maximum bias current (2.5 mA)
Qd is 3 nC
CL is the load capacitance
f is the switching frequency (Hz)
Equation 1.
The maximum allowable power dissipation for the Si826x is a function of the package thermal resistance, ambient
temperature, and maximum allowable junction temperature, as shown in Equation 2.
T
jmax – TA
---------------------------
PDmax
where:
ja
PDmax is the maximum allowable power dissipation (W)
Tjmax is the maximum junction temperature (140 °C)
TA is the ambient temperature (°C)
ja is the package junction-to-air thermal resistance (110 °C/W)
Equation 2.
Substituting values for P
T
, T , and
into Equation 2 results in a maximum allowable total power
ja
Dmax jmax
A
dissipation of 1.0 W. Note that the maximum allowable load is found by substituting this limit and the appropriate
datasheet values from Table 2 on page 4 into Equation 1 and simplifying. Graphs are shown in Figures 16 and 17.
All points along the load lines in these graphs represent the package dissipation-limited value of C for the
L
corresponding switching frequency.
20
Preliminary Rev. 0.9
Si826x
Figure 16. (SOIC-8, DIP8, SDIP6) Maximum Load vs. Switching Frequency (25 °C)
Figure 17. (LGA8) Maximum Load vs. Switching Frequency (25 °C)
Preliminary Rev. 0.9
21
Si826x
5.5. Parametric Differences between Si826x and HCPL-0302 and HCPL-3120
Opto Drivers
The Si826x is designed to directly replace HCPL-3120 and similar opto drivers. Parametric differences are
summarized in Tables 11 and 12 below.
Table 11. Parametric Differences of Si8261 vs. HCPL-3120
Parameter
Si8261
HCPL-3120
Units
Max supply voltage
30
6 to 30
30
7 to 16
–0.3 to +0.8
–5
V
mA
V
ON state forward input current
OFF state input voltage
–0.6 to +1.6
–0.3
Max reverse input voltage
UVLO threshold (rising)
V
5 to 10.5
4.7 to 9.4
0.3 to 1.3
100
11.0 to 13.5
9.7 to 12.0
1.6
V
UVLO threshold (falling)
V
UVLO hysteresis
V
Rise/fall time into 10 in series with 10 nF
100
ns
Table 12. Parametric Differences of Si8261 vs. HCPL-0302
Parameter
Si8261
HCPL-0302
Units
Max supply voltage
30
6 to 30
30
7 to 16
–0.3 to +0.8
–5
V
mA
V
ON state forward input current
OFF state input voltage
–0.6 to +1.6
–0.3
Max reverse input voltage
UVLO threshold (rising)
V
5 to 10.5
4.7 to 9.4
0.3 to 1.3
100
11.0 to 13.5
9.7 to 12.0
1.6
V
UVLO threshold (falling)
V
UVLO hysteresis
V
Rise/fall time into 10 in series with 10 nF
100
ns
5.5.1. Input Diode Differences
The Si826x input circuit requires less current and has twice the off-state noise margin compared to opto drivers.
However, high CMR opto driver designs that overdrive the LED (see Figure 14) may require increasing the value of
R1 to limit input current I to its maximum rating when using the Si826x. In addition, there is no benefit in driving
F
the Si826x input diode into reverse bias when in the off state. Consequently, opto driver circuits using this
technique should either leave the negative bias circuitry unpopulated or modify the circuitry (e.g. add a clamp diode
or current limiting resistor) to ensure that the anode pin of the Si826x is no more than –0.3 V with respect to the
cathode when reverse-biased. For more information on configuring the input, see “AN677: Using the Si826x Family
of Isolated Gate Drivers”.
5.5.2. Supply Voltage and UVLO Considerations
The supply voltage of the Si826x is limited to 30 V, from which the UVLO voltage thresholds are scaled accordingly.
Opto replacement applications should limit their supply voltages to 30 V or less.
22
Preliminary Rev. 0.9
Si826x
6. Pin Descriptions (SOIC-8, DIP8, LGA8)
VDD
VO
NC
1
2
8
7
UVLO
ANODE
e
CATHODE
NC
3
4
6
5
VO
GND
SOIC-8, DIP8, LGA8
Industry Standard Pinout
Figure 18. Pin Configuration
Table 13. Pin Descriptions (SOIC-8, DIP8, LGA8)
Description
Pin
1
Name
NC*
No connect.
2
ANODE Anode of LED emulator. V follows the signal applied to this input with respect to the
O
CATHODE input.
3
4
5
CATHODE Cathode of LED emulator. V follows the signal applied to ANODE with respect to this input.
O
NC*
No connect.
GND
External MOSFET source connection and ground reference for V . This terminal is typically
DD
connected to ground but may be tied to a negative or positive voltage.
6
7
8
V
V
Output signal. Both V pins are required to be shorted together for 4.0 A compliance.
O
O
O
Output signal. Both V pins are required to be shorted together for 4.0 A compliance.
O
V
Output-side power supply input referenced to GND (30 V max).
DD
*Note: No Connect. These pins are not internally connected. To maximize CMTI performance, these pins should be
connected to the ground plane.
Preliminary Rev. 0.9
23
Si826x
7. Pin Descriptions (SDIP6)
VDD
VO
1
2
3
6
5
4
ANODE
UVLO
e
NC
CATHODE
GND
SDIP6
Industry Standard Pinout
Figure 19. Pin Configuration
Table 14. Pin Descriptions (SDIP6)
Description
Pin
Name
1
ANODE Anode of LED emulator. V follows the signal applied to this input with respect to the
O
CATHODE input.
2
3
4
NC*
No connect.
CATHODE Cathode of LED emulator. V follows the signal applied to ANODE with respect to this input.
O
GND
External MOSFET source connection and ground reference for V . This terminal is typically
DD
connected to ground but may be tied to a negative or positive voltage.
5
6
V
O
Output signal.
V
Output-side power supply input referenced to GND (30 V max).
DD
*Note: No Connect. These pins are not internally connected. To maximize CMTI performance, these pins should be
connected to the ground plane.
24
Preliminary Rev. 0.9
Si826x
8. Ordering Guide
Table 15. Si826x Ordering Guide1,2,3
Ordering Options
New Ordering
Part Number
Output
Cross
Reference Voltage
UVLO Insulation
Rating
Temp Range
Pkg Type
SOIC-8
SOIC-8
DIP8/GW
DIP8/GW
SDIP6
(OPN)
Configuration
Si8261AAC-C-IS
(Sampling)
0.6 A driver
HCPL-0314
—
5 V
5 V
5 V
5 V
5 V
5 V
5 V
5 V
3.75 kVrms –40 to +125 °C
3.75 kVrms –40 to +125 °C
3.75 kVrms –40 to +125 °C
3.75 kVrms –40 to +125 °C
5.0 kVrms –40 to +125 °C
5.0 kVrms –40 to +125 °C
5.0 kVrms –40 to +125 °C
5.0 kVrms –40 to +125 °C
Si8261BAC-C-IS
(Sampling)
4.0 A driver
0.6 A driver
4.0 A driver
0.6 A driver
4.0 A driver
0.6 A driver
4.0 A driver
Si8261AAC-C-IP
(Sampling)
HCPL-3140
Si8261BAC-C-IP
(Sampling)
TLP 350
HCPL-3120
Si8261AAD-C-IS
(Sampling)
ACPL-W314
TLP 700F
—
Si8261BAD-C-IS
(Sampling)
SDIP6
Si8261AAD-C-IM
(Sampling)
LGA8
Si8261BAD-C-IM
(Sampling)
HCNW-3120
LGA8
Notes:
1. All packages are RoHS-compliant. Moisture sensitivity level is MSL3 with peak reflow temperature of 260 °C according
to the JEDEC industry standard classifications and peak solder temperature.
2. “Si” and “SI” are used interchangeably.
3. AEC-Q100 qualified.
Preliminary Rev. 0.9
25
Si826x
Table 15. Si826x Ordering Guide1,2,3
Ordering Options
New Ordering
Part Number
(OPN)
Output
Cross
Reference Voltage
UVLO Insulation
Rating
Temp Range
Pkg Type
SOIC-8
SOIC-8
DIP8/GW
DIP8/GW
SDIP6
Configuration
Si8261ABC-C-IS
(Sampling)
0.6 A driver
4.0 A driver
0.6 A driver
4.0 A driver
0.6 A driver
4.0 A driver
0.6 A driver
4.0 A driver
HCPL-0314
—
8 V
8 V
8 V
8 V
8 V
8 V
8 V
8 V
3.75 kVrms –40 to +125 °C
3.75 kVrms –40 to +125 °C
3.75 kVrms –40 to +125 °C
3.75 kVrms –40 to +125 °C
5.0 kVrms –40 to +125 °C
5.0 kVrms –40 to +125 °C
5.0 kVrms –40 to +125 °C
5.0 kVrms –40 to +125 °C
Si8261BBC-C-IS
(Sampling)
Si8261ABC-C-IP
(Sampling)
HCPL-3140
Si8261BBC-C-IP
(Sampling)
TLP 350
HCPL-3120
Si8261ABD-C-IS
(Sampling)
ACPL-W314
TLP 700F
—
Si8261BBD-C-IS
(Sampling)
SDIP6
Si8261ABD-C-IM
(Sampling)
LGA8
Si8261BBD-C-IM
(Sampling)
HCNW-3120
LGA8
Notes:
1. All packages are RoHS-compliant. Moisture sensitivity level is MSL3 with peak reflow temperature of 260 °C according
to the JEDEC industry standard classifications and peak solder temperature.
2. “Si” and “SI” are used interchangeably.
3. AEC-Q100 qualified.
26
Preliminary Rev. 0.9
Si826x
Table 15. Si826x Ordering Guide1,2,3
Ordering Options
New Ordering
Part Number
(OPN)
Output
Cross
Reference Voltage
UVLO Insulation
Rating
Temp Range
Pkg Type
SOIC-8
SOIC-8
DIP8/GW
DIP8/GW
SDIP6
Configuration
Si8261ACC-C-IS
(Sampling)
0.6 A driver
4.0 A driver
0.6 A driver
4.0 A driver
0.6 A driver
4.0 A driver
0.6 A driver
4.0 A driver
HCPL-0314
—
12 V
12 V
12 V
12 V
12 V
12 V
12 V
12 V
3.75 kVrms –40 to +125 °C
3.75 kVrms –40 to +125 °C
3.75 kVrms –40 to +125 °C
3.75 kVrms –40 to +125 °C
5.0 kVrms –40 to +125 °C
5.0 kVrms –40 to +125 °C
5.0 kVrms –40 to +125 °C
5.0 kVrms –40 to +125 °C
Si8261BCC-C-IS
(Sampling)
Si8261ACC-C-IP
(Sampling)
HCPL-3140
Si8261BCC-C-IP
(Sampling)
TLP 350
HCPL-3120
Si8261ACD-C-IS
(Sampling)
ACPL-W314
TLP 700F
—
Si8261BCD-C-IS
(Sampling)
SDIP6
Si8261ACD-C-IM
(Sampling)
LGA8
Si8261BCD-C-IM
(Sampling)
HCNW-3120
LGA8
Notes:
1. All packages are RoHS-compliant. Moisture sensitivity level is MSL3 with peak reflow temperature of 260 °C according
to the JEDEC industry standard classifications and peak solder temperature.
2. “Si” and “SI” are used interchangeably.
3. AEC-Q100 qualified.
Preliminary Rev. 0.9
27
Si826x
9. Package Outline: 8-Pin Narrow Body SOIC
Figure 20 illustrates the package details for the Si826x in an 8-pin narrow-body SOIC package. Table 16 lists the
values for the dimensions shown in the illustration.
Figure 20. 8-Pin Narrow Body SOIC Package
Table 16. 8-Pin Narrow Body SOIC Package Diagram Dimensions
Millimeters
Symbol
Min
Max
1.75
A
A1
A2
B
1.35
0.10
0.25
1.40 REF
0.33
1.55 REF
0.51
C
D
E
0.19
0.25
4.80
5.00
3.80
4.00
e
1.27 BSC
H
h
5.80
0.25
0.40
0
6.20
0.50
1.27
8
L
28
Preliminary Rev. 0.9
Si826x
10. Land Pattern: 8-Pin Narrow Body SOIC
Figure 21 illustrates the recommended land pattern details for the Si826x in an 8-pin narrow-body SOIC. Table 17
lists the values for the dimensions shown in the illustration.
Figure 21. 8-Pin Narrow Body SOIC Land Pattern
Table 17. 8-Pin Narrow Body SOIC Land Pattern Dimensions
Dimension
Feature
Pad Column Spacing
Pad Row Pitch
Pad Width
(mm)
5.40
1.27
0.60
1.55
C1
E
X1
Y1
Pad Length
Notes:
1. This Land Pattern Design is based on IPC-7351 pattern SOIC127P600X173-8N for
Density Level B (Median Land Protrusion).
2. All feature sizes shown are at Maximum Material Condition (MMC) and a card
fabrication tolerance of 0.05 mm is assumed.
Preliminary Rev. 0.9
29
Si826x
11. Package Outline: DIP8
Figure 22 illustrates the package details for the Si826x in a DIP8 package. Table 18 lists the values for the
dimensions shown in the illustration.
Figure 22. DIP8 Package
Table 18. DIP8 Package Diagram Dimensions
Dimension
Min
—
Max
4.19
0.75
3.43
0.55
1.78
1.14
0.33
9.90
7.87
6.60
9.90
A
A1
A2
b
0.55
3.17
0.35
1.14
0.76
0.20
9.40
7.37
6.10
9.40
b2
b3
c
D
E
E1
E2
e
2.54 BSC.
L
0.38
—
0.89
0.25
aaa
Notes:
1. All dimensions shown are in millimeters (mm) unless otherwise noted.
2. Dimensioning and Tolerancing per ANSI Y14.5M-1994.
30
Preliminary Rev. 0.9
Si826x
12. Land Pattern: DIP8
Figure 23 illustrates the recommended land pattern details for the Si826x in a DIP8 package. Table 19 lists the
values for the dimensions shown in the illustration.
Figure 23. DIP8 Land Pattern
Table 19. DIP8 Land Pattern Dimensions*
Dimension
Min
Max
C
E
X
Y
8.85
8.90
2.54 BSC
0.60
1.65
0.65
1.70
*Note: This Land Pattern Design is based on the IPC-7351 specification.
Preliminary Rev. 0.9
31
Si826x
13. Package Outline: SDIP6
Figure 24 illustrates the package details for the Si826x in an SDIP6 package. Table 20 lists the values for the
dimensions shown in the illustration.
Figure 24. SDIP6 Package
Table 20. SDIP6 Package Diagram Dimensions
Dimension
Min
—
Max
2.65
0.30
—
A
A1
A2
b
0.10
2.05
0.31
0.20
0.51
0.33
c
D
E
4.58 BSC
11.50 BSC
7.50 BSC
1.27 BSC
E1
e
L
0.40
0.25
1.27
0.75
h
Notes:
1. All dimensions shown are in millimeters (mm) unless otherwise noted.
2. Dimensioning and Tolerancing per ANSI Y14.5M-1994.
32
Preliminary Rev. 0.9
Si826x
Table 20. SDIP6 Package Diagram Dimensions (Continued)
Dimension
Min
0°
Max
8°
θ
aaa
bbb
ccc
ddd
eee
fff
—
—
—
—
—
—
0.10
0.33
0.10
0.25
0.10
0.20
Notes:
1. All dimensions shown are in millimeters (mm) unless otherwise noted.
2. Dimensioning and Tolerancing per ANSI Y14.5M-1994.
Preliminary Rev. 0.9
33
Si826x
14. Land Pattern: SDIP6
Figure 25 illustrates the recommended land pattern details for the Si826x in an SDIP6 package. Table 21 lists the
values for the dimensions shown in the illustration.
Figure 25. SDIP6 Land Pattern
Table 21. SDIP6 Land Pattern Dimensions*
Dimension
Min
Max
C
E
X
Y
10.45
10.50
1.27 BSC
0.55
2.00
0.60
2.05
*Note: This Land Pattern Design is based on the IPC-7351 specification.
34
Preliminary Rev. 0.9
Si826x
15. Package Outline: LGA8
Figure 26 illustrates the package details for the Si826x in an LGA8 package. Table 22 lists the values for the
dimensions shown in the illustration.
Figure 26. LGA8 Package
Table 22. Package Diagram Dimensions
Dimension
Min
0.74
1.15
Nom
0.84
Max
0.94
1.25
A
b
1.20
D
10.00 BSC.
2.54 BSC.
12.50 BSC.
1.10
e
E
L
1.05
0.05
—
1.15
0.15
0.10
0.10
0.10
0.10
L1
aaa
bbb
ccc
ddd
0.10
—
—
—
—
—
—
—
Notes:
1. All dimensions shown are in millimeters (mm) unless otherwise noted.
2. Dimensioning and Tolerancing per ANSI Y14.5M-1994.
3. Recommended card reflow profile is per the JEDEC/IPC J-STD-020
specification for Small Body Components.
Preliminary Rev. 0.9
35
Si826x
16. Land Pattern: LGA8
Figure 27 illustrates the recommended land pattern details for the Si826x in an LGA8 package. Table 23 lists the
values for the dimensions shown in the illustration.
Figure 27. LGA8 Land Pattern
Table 23. LGA8 Land Pattern Dimensions
Dimension
Feature
Pad Column Spacing
Pad Row Pitch
Pad Width
(mm)
11.80
2.54
C1
E
X1
Y1
1.30
Pad Length
1.80
Notes:
1. This Land Pattern Design is based on IPC-7351 specifications.
2. All feature sizes shown are at Maximum Material Condition (MMC) and a card
fabrication tolerance of 0.05 mm is assumed.
36
Preliminary Rev. 0.9
Si826x
17. Top Markings
17.1. Si826x Top Marking (Narrow Body SOIC)
17.2. Top Marking Explanation
Customer Part Number
826 = ISOdriver product series
C = Input configuration
1 = Opto input type
I = Peak output current
A = 0.6 A; B = 4.0 A
Line 1 Marking:
U = UVLO level
A = 5 V; B = 8 V; C = 12 V
V = Isolation rating
C = 3.75 kV; D = 5.0 kV
RTTTTT = Mfg Code
Manufacturing Code from the Assembly Purchase
Order form.
Line 2 Marking:
“R” indicates revision.
Circle = 43 mils Diameter
“e4” Pb-Free Symbol
Left-Justified
Line 3 Marking:
YY = Year
Assigned by the Assembly House. Corresponds to
the year and work week of the mold date.
WW = Work Week
Preliminary Rev. 0.9
37
Si826x
17.3. Si826x Top Marking (DIP8)
17.4. Top Marking Explanation
Customer Part Number
Si826 = ISOdriver product series
C = Input configuration
1 = Opto input type
I = Peak output current
A = 0.6 A; B = 4.0 A
Line 1 Marking:
U = UVLO level
A = 5 V; B = 8 V; C = 12 V
V = Isolation rating
C = 3.75 kV; D = 5.0 kV
YY = Year
WW = Work Week
Assigned by the Assembly House. Corresponds to
the year and work week of the mold date.
Line 2 Marking:
Line 3 Marking:
RTTTTT = Mfg Code
Manufacturing Code from the Assembly Purchase
Order form.
“R” indicates revision.
Circle = 51 mils Diameter
Center-Justified
“e4” Pb-Free Symbol
CO = Country of Origin
Country of Origin
ISO Code Abbreviation
38
Preliminary Rev. 0.9
Si826x
17.5. Si826x Top Marking (SDIP6)
17.6. Top Marking Explanation
Device
Si826 = ISOdriver product series
C = Input configuration
1 = Opto input type
Line 1 Marking:
Device Rating
I = Peak output current
A = 0.6 A; B = 4.0 A
U = UVLO level
Line 2 Marking:
A = 5 V; B = 8 V; C = 12 V
V = Isolation rating
C = 3.75 kV; D = 5.0 kV
RTTTTT = Mfg Code
Manufacturing Code from the Assembly Purchase
Order form.
Line 3 Marking:
“R” indicates revision.
YY = Year
WW = Work Week
Assigned by the Assembly House. Corresponds to the
year and work week of the mold date.
Line 4 Marking:
Preliminary Rev. 0.9
39
Si826x
17.7. Si826x Top Marking (LGA8)
17.8. Top Marking Explanation
Device Part Number
Si826 = ISOdriver product series
C = Input configuration
1 = Opto input type
I = Peak output current
A = 0.6 A; B = 4.0 A
Line 1 Marking:
U = UVLO level
A = 5 V; B = 8 V; C = 12 V
V = Isolation rating
C = 3.75 kV; D = 5.0 kV
YY = Year
WW = Work Week
Assigned by the Assembly House. Corre-
sponds to the year and work week of the
assembly release.
Line 2 Marking:
RTTTTT = Mfg Code
Manufacturing Code from the Assembly Pur-
chase Order form.
“R” indicates revision.
Circle = 1.6 mm Diameter
“e4” Pb-Free Symbol
Center-Justified
Line 3 Marking:
CO = Country of Origin
Country of Origin
ISO Code Abbreviation
Circle = 0.75 mm Diameter
Lower Left-Justified
Pin 1 Identifier
Line 4 Marking:
40
Preliminary Rev. 0.9
Si826x
NOTES:
Preliminary Rev. 0.9
41
Si826x
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42
Preliminary Rev. 0.9
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