SL3204_技术文档

TITAN TECHNOLOGY Co. Ltd.

SL3204

SL3204 Data sheet description Ver5.0

1. Features

2. General Description

Block Diagram

3. Pad Description

Absolute Maximum Ratings

4. DC Characteristic

5. AC Characteristic

6. Function Description

Display Memory RAM

System Oscillator

Time Base and Watchdog Timer (WDT)

Tone Output

LCD Driver

7. Command Format

8. Interfacing

9. Application Circuit

10. Timing Diagram

11. Command Index

12. Pin Assignment

13. Pad Coordinates

14. Package

SSOP48、SOP32、SKDIP28、COB48、LQFP48

15. History

1

TITAN TECHNOLOGY Co. Ltd.

SL3204

z Features

z

Operating voltage: 2.4V~5.5V

Built-in 256KHz RC oscillator

External 32.768KHz crystal or 256KHz

frequency source input

Selection of 1/2 or 1/3 bias, and selection of 1/2

or 1/3 or 1/4 duty LCD applications

Internal time base frequency sources

Two selectable buzzer frequencies

(2KHz/4KHz)

z

Time base or WDT overflow output

8 kinds of time base/WDT clock sources

32x4 LCD driver

Built-in 32x4 bit display RAM

3-wire serial interface

Internal LCD driving frequency source

Software configuration feature

Data mode and command mode instructions

R/W address auto increment

Three data accessing modes

VLCD pin for adjusting LCD operating voltage

z

Power down command reduces power

consumption

Built-in time base generator and WDT

z General Description

The SL3204 is a 128 patterns (32x4), memory mapping, and multi-function LCD driver. The S/W

configuration feature of the SL3204 makes it suitable for multiple LCD applications including LCD modules

and display subsystems. Only three or four lines are required for the interface between the host controller

and the SL3204. The SL3204 contains a power down command to reduce power consumption.

Block Diagram

Display RAM

OSCO

OSCI

Control

and

Timing

Circuit

CSB

RDB

COM0

COM3

SEG0

LCD Driver /

Bias Circuit

WRB

DATA

SEG31

VLCD

VDD

VSS

Watchdog Timer

and

Time Base Generator

BZ

Tone Frequency

Generator

IRQB

BZB

Note:

CSB: Chip selection

BZ, BZB: Tone outputs

WRB, RDB, DATA: Serial interface

COM0~COM3, SEG0~SEG31: LCD outputs

IRQB: Time base or WDT overflow output

2

TITAN TECHNOLOGY Co. Ltd.

SL3204

z Pad Description

Pad

No.

Pad Name

I/O Function

Chip selection input with pull high resistor When the CSB is logic high, the

data and command read from or written to the SL3204are disabled. The serial

interface circuit is also reset. But if CSB is at logic low level and is input to the

CSB pad, the data and command transmission between the host controller

and the SL3204 are all enabled.

CSB

I

1

READ clock input with pull high resistor Data in the RAM of the SL3204 are

clocked out on the falling edge of the RDB signal. The clocked out data will

appear on the DATA line. The host controller can use the next rising edge to

latch the clocked out data.

2

3

RDB

I

WRITE clock input with pull high resistor Data on the DATA line are latched

into the SL3204on the rising edge of the WRB signal.

WRB

4

5

DATA

VSS

I/O Serial data input/output with pull high resistor

-

Negative power supply, ground

The OSCI and OSCO pads are connected to a 32.768KHz crystal in order to

generate a system clock. If the system clock comes from an external clock

source, the external clock source should be connected to the OSCI pad. But if

an on chip RC oscillator is selected instead, the OSCI and OSCO pads can be

left open.

6

7

OSCO

OSCI

O

I

8

VLCD

VDD

I

LCD power input

9

-

Positive power supply

10

IRQB

O

Time base or WDT overflow flag, NMOS open drain output

2KHz or 4KHz tone frequency output pair

LCD common outputs

11~12 BZ, BZB

13~16 COM0~COM3

17~48 SEG31~SEG0

LCD segment outputs

Absolute Maximum Ratings

Supply Voltage……………………………………………... –0.3V ~ 5.5V

Input Voltage……………………………………………… VSS-0.3V ~ VDD+0.3V

Storage Temperature…………………………………….. -50°C ~ 125°C

Operating Temperature…………………………………… -25°C ~ 75°C

3

TITAN TECHNOLOGY Co. Ltd.

SL3204

z DC Characteristic

Test Conditions

Conditions

No load

Power down mode

No load

Power down mod

No load, internal RC

oscillator on

No load, internal RC

oscillator on

Symbol

Istb1

Istb2

Idd1

Idd2

Io1

Parameter

Min

-

Typical

5

Max

Unit.

uA

VDD

5V

Standby Current

Operation current

-

3v

5v

2

uA

120

48

uA

3v

uA

LCD Common Sink

Current

LCD Common

Source Current

LCD Segment Sink

Current

5V

VOL=2.5V

VOH=2.5V

VOL=2.5V

VOH=2.5V

2.36

1.51

1.58

0.9

mA

Io2

Io3

LCD Segment

Source Current

Io4

z AC Characteristic

Symbol

Fint3

Parameter

Internal RC oscillator

External input clock

VDD

3V

5V

3V

5V

3V

5V

Min

Typ.

Max

3.5

Unit.

KHz

MHz

ns

133

256

Fint5

Fext5

Trdbl3

Trdbl5

Twrbl3

Twrbl5

Tcsbh5

Minimum read low pulse

Minimum write low pulse

Minimum CSB high pulse

350

50

ns

V

DD

90%

WRB

RDB

50%

10%

GND

Twrbl

Trdbl

Twrbl

Trdbl

Tcsbh

50%

V

DD

CSB

GND

V

DD

WRB

RDB

GND

4

TITAN TECHNOLOGY Co. Ltd.

SL3204

z Functional Description

Display Memory RAM

he static display memory (RAM) is organized into 32x4 bits and stores the displayed data. The contents of

the RAM are directly mapped to the contents of the LCD driver. Data in the RAM can be accessed by the

READ, WRITE, and READ-MODIFY-WRITE commands. The following is a mapping from the RAM to the

LCD pattern

COM3 COM2 COM1 COM0

SEG0

SEG1

SEG2

SEG3

0

1

2

3

Address 6 bits

(A5,A4,…,A0)

SEG31

31

Addr

D3

D2

D1

D0

Data

Data 4 bits

(D3,D2,D1,D0)

System Oscillator

The SL3204 system clock is used to generate the time base/Watchdog Timer (WDT) clock frequency,

LCD driving clock, and tone frequency. The source of the clock may be from an on chip RC oscillator (256

KHz), a crystal oscillator (32.768 KHz), or an external 256 KHz clock by the S/W setting. The configuration

of the system oscillator is as shown. After the SYS DIS command is executed, the system clock will stop

and the LCD bias generator will turn off. That command is, however, available only for the on chip RC

oscillator or for the crystal oscillator. Once the system clock stops, the LCD display will become blank, and

the time base/WDT lose its function as well.

The LCD OFF command is used to turn the LCD bias generator off. After the LCD bias generator switches

off by issuing the LCD OFF command, using the SYS DIS command reduces power consumption, serving

as a system power down command. But if the external clock source is chosen as the system clock, using

the SYS DIS command can neither turn the oscillator off nor carry out the power down mode. The crystal

oscillator option can be applied to connect an external frequency source of 32 KHz to the OSCI pin. In this

case, the system fails to enter the power down mode, similar to the case in the external 256 KHz clock

source operation.

At the initial system power on, the SL3204 is at the SYS DIS state.

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SL3204

Time Base and Watchdog Timer (WDT)

The time base generator is comprised by an 8-stage count-up ripple counter and is designed to generate

an accurate time base. The watch dog timer (WDT), on the other hand, is composed of an 8 stage time

base generator along with a 2 stage count-up counter, and is designed to break the host controller or other

subsystems from abnormal states such as unknown or unwanted jump, execution errors, etc. The WDT

time out will result in the setting of an internal WDT time out flag. The outputs of the time base generator

and of the WDT time out flag can be connected to the IRQB output by a command option. There are totally

eight frequency sources available for the time base generator and the WDT clock. The frequency is

32KHz

2ⁿ

calculated by the following equation.

Where the value of n ranges from 0 to 7 by

=

f

WDT

command options. The 32 KHz in the above equation indicates that the source of the system frequency is

derived from a crystal oscillator of 32.768 KHz, an on chip oscillator (256 KHz), or an external frequency of

256 KHz. If an on chip oscillator (256 KHz) or an external 256 KHz frequency is chosen as the source of

the system frequency, the frequency source is by default prescaled to 32 KHz by a 3 stage prescaler.

Employing both the time base generator and the WDT related commands, one should be careful since the

time base generator and WDT share the same 8-stage counter. For example, invoking the WDT DIS

command disables the time base generator whereas executing the WDT EN command not only enables

the time base generator but activates the WDT time out flag output (connect the WDT time out flag to the

IRQB pin). After the TIMER EN command is transferred, the WDT is disconnected from the IRQB pin, and

the output of the time base generator is connected to the IRQB pin. The WDT can be cleared by executing

the CLR WDT command and the contents of the time base generator is cleared by executing the CLR

WDT or the CLR TIMER command.

OSCI

Crystal Oscillator

32768Hz

OSCO

External Clock Source

256KHz

System

Clock

1/8

On-chip RC Oscillator

256KHz

System oscillator configuration

Timer/WDT

TIMER EN / DIS

WDT EN / DIS

Clock Sources

/256

System Clock

f=32kHz

IRQB

/2ⁿ

n=0~7

VDD

D

Q

WDT

/4

CK

IRQB EN / DIS

R

Timer and WDT configuration

CLR WDT

6

TITAN TECHNOLOGY Co. Ltd.

SL3204

The CLR WDT or the CLR TIMER command should be executed prior to the WDT EN or the TIMER EN

command respectively. Before executing the IRQB EN command the CLR WDT or CLR TIMER command

should be executed first. The CLR TIMER command has to be executed before switching from the WDT

mode to the time base mode. Once the WDT time out occurs, the IRQB pin will stay at a logic low level

until the CLR WDT or the IRQB DIS command is issued. After the IRQB output is disabled the IRQB pin

will remain at the floating state. The IRQB output can be enabled or disabled by executing the IRQB EN or

the IRQB DIS command, respectively. The IRQB EN makes the output of the time base generator or of the

WDT time out flag appear on the IRQB pin. The configuration of the time base generator along with the

WDT is as shown. In the case of on chip RC oscillator or crystal oscillator, the power down mode can

reduce power consumption since the oscillator can be turned on or off by the corresponding system

commands. At the power down mode the time base/WDT loses all its functions. On the other hand, if an

external clock is selected as the source of system frequency the SYS DIS command turns out invalid and

the power down mode fails to be carried out. That is, after the external clock source is selected, the

SL3204 will continue working until system power fails or the external clock source is removed. After the

system power on, the IRQB will be disabled.

Name

Command Code

10000000010X

Function

LCD OFF

Turn off LCD outputs

LCD ON

10000000011X

1000010abXcX

Turn on LCD outputs

BIAS & COM

c=0 : 1/2 bias option

c=1 : 1/3 bias option

ab=00 : 2 commons option

ab=01 : 3 commons option

ab=10 : 4 commons option

Tone Output

A simple tone generator is implemented in the SL3204. The tone generator can output a pair of differential

driving signals on the BZ and BZB, which are used to generate a single tone. By executing the TONE4K

and TONE2K commands there are two tone frequency outputs selectable. The TONE4K and TONE2K

commands set the tone frequency to 4 KHz and 2 KHz, respectively. The tone output can be turned on or

off by invoking the TONE ON or the TONE OFF command. The tone outputs, namely BZ and BZB, are a

pair of differential driving outputs used to drive a buzzer.

LCD Driver

The SL3204 is a 128 (32x4) pattern LCD driver. It can be configured as 1/2 or 1/3 bias and 2 or 3 or 4

commons of LCD driver by the S/W configuration. This feature makes the SL3204 suitable for multiple

LCD applications. The LCD driving clock is derived from the system clock. The value of the driving clock is

always 256Hz even when it is at a 32.768 KHz crystal oscillator frequency, an on chip RC oscillator

frequency, or an external frequency. The LCD corresponding commands are summarized in the table. The

bold form of 1 0 0, namely 1 0 0, indicates the command mode ID. If successive commands have been

issued, the command mode ID except for the first command will be omitted. The LCD OFF command turns

the LCD display off by disabling the LCD bias generator. The LCD ON command, on the other hand, turns

the LCD display on by enabling the LCD bias generator. The BIAS and COM are the LCD panel related

commands. Using the LCD related commands; the SL3204 can be compatible with most types of LCD

7

TITAN TECHNOLOGY Co. Ltd.

SL3204

panels.

z Command Format

The SL3204 can be configured by the S/W setting. There are two mode commands to configure the

SL3204 resources and to transfer the LCD display data. The configuration mode of the SL3204 is called

command mode, and its command mode ID is 1 0 0. The command mode consists of a system

configuration command, a system frequency selection command, a LCD configuration command, a tone

frequency selection command, a timer/WDT setting command, and an operating command. The data

mode, on the other hand, includes READ, WRITE, and READ-MODIFY-WRITE operations. The following

are the data mode Ids and the command mode ID:

Operation

Mode

Data

ID

READ

1 1 0

1 0 1

1 0 0

WRITE

Data

READ-MODIFY-WRITE

COMMAND

Data

Command

The mode command should be issued before the data or command is transferred. If successive

commands have been issued, the command mode ID, namely 1 0 0, can be omitted. While the system is

operating in the non-successive command or the non-successive address data mode, the CSB pin should

be set to “1” and the previous operation mode will be reset also. Once the CSB pin returns to “0” a new

operation mode ID should be issued first.

z Interfacing

Only four lines are required to interface with the SL3204. The CSB line is used to initialize the serial

interface circuit and to terminate the communication between the host controller and the SL3204. If the

CSB pin is set to “1”, the data and command issued between the host controller and the SL3204 are first

disabled and then initialized. Before issuing a mode command or mode switching, a high level pulse is

required to initialize the serial interface of the SL3204. The DATA line is the serial data input/output line.

Data to be read or written or commands to be written have to be passed through the DATA line. The RDB

line is the READ clock input. Data in the RAM are clocked out on the falling edge of the RDB signal, and

the clocked out data will then appear on the DATA line. It is recommended that the host controller read in

correct data during the interval between the rising edge and the next falling edge of the RDB signal. The

WRB line is the WRITE clock input. The data, address, and command on the DATA line are all clocked

into the SL3204 on the rising edge of the WRB signal. There is an optional IRQB line to be used as an

interface between the host controller and the SL3204. The IRQB pin can be selected as a timer output or a

WDT overflow flag output by the S/W setting. The host controller can perform the time base or the WDT

function by being connected with the IRQB pin of the SL3204.

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SL3204

z Application Circuit

CSB

RDB

VLCD

VDD

WRB

VR

MCU

DATA

SL3204

R

BZ

IRQB

Clock Out

OSCI

OSCO

External Clock 1

External Clock 2

On-chip OSC

BZB

COM0~COM3

SEG0~SEG31

C1

1/2 or 1/3 Bias; 1/2, 1/3 or 1/4 Duty

Crystal

32768Hz

LCD Pannel

C2

Host controller with a SL3204 display system

Note: See next page for notes.

Note: The connection of IRQB and RDB pin can be selected depending on the requirement of the up

The voltage applied to V_LCDpin must be lower then V_DD

.

Adjust VR to fit LCD display, at V_DD= 5V, V_LCD= 4V, VR = 15Kohm +/- 20%.

Adjust R to fit user’s time base clock.

9

TITAN TECHNOLOGY Co. Ltd.

SL3204

z Timing Diagram

Command mode (command code : 1 0 0)

CSB

WRB

DATA

C8 C7 C6 C5 C4 C3 C2 C1 C0

0

C8 C7 C6 C5 C4 C3 C2 C1 C0

Command i

1

0

Command 1

Command ...

Command

or

Data Mode

READ mode (command code : 1 1 0)

CSB

WRB

RDB

DATA

1

0

A5 A4 A3 A2 A1 A0 D0 D1 D2 D3

Memory Address 1 (MA1) Data (MA1)

A5 A4 A3 A2 A1 A0 D0 D1 D2 D3

Memory Address 2 (MA2) Data (MA2)

1

0

READ mode (successive address reading)

CSB

WRB

RDB

DATA

1

0

A5 A4 A3 A2 A1 A0 D0 D1 D2 D3 D0 D1 D2 D3 D0 D1 D2 D3 D0 D1 D2 D3

Memory Address (MA) Data (MA) Data(MA+1) Data(MA+2) Data(MA+3)

WRITE mode (command code : 1 0 1)

CSB

WRB

DATA

1

0

1

A5 A4 A3 A2 A1 A0 D0 D1 D2 D3

Memory Address 1 (MA1) Data (MA1)

A5 A4 A3 A2 A1 A0 D0 D1 D2 D3

Memory Address 2 (MA2) Data (MA2)

1

0

1

WRITE mode (successive address reading)

CSB

WRB

DATA

1

0

1

A5 A4 A3 A2 A1 A0 D0 D1 D2 D3 D0 D1 D2 D3 D0 D1 D2 D3 D0 D1 D2 D3

Memory Address (MA) Data (MA) Data(MA+1) Data(MA+2) Data(MA+3)

10

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SL3204

z Command Index

Name

ID Command Code

D/C Function

Def.

READ

1 1 0 A5A4A3A2A1A0D0D1D2D3

1 0 1 A5A4A3A2A1A0D0D1D2D3

D

Read data from the RAM

Write data to the RAM

READ and WRITE to the RAM

WRITE

READ-

MODIFY-

WRITE

SYS DIS

1 0 0 0000-0000-X

C

Turn off both system oscillator and LCD bias Yes

generator

SYS EN

LCD OFF

LCD ON

TIMER DIS 1 0 0 0000-0100-X

WDT DIS 1 0 0 0000-0101-X

TIMER EN 1 0 0 0000-0110-X

WDT EN 1 0 0 0000-0111-X

TONE OFF 1 0 0 0000-1000-X

TONE ON 1 0 0 0000-1001-X

CLR

1 0 0 0000-0001-X

1 0 0 0000-0010-X

1 0 0 0000-0011-X

C

Turn on system oscillator

Turn off LCD bias generator

Turn on LCD bias generator

Disable time base output

Disable WDT time-out flag output

Enable time base output

Enable WDT time-out flag output

Turn off tone outputs

Turn on tone outputs

Yes

1 0 0 0000-1101-X

Clear the contents of time base generator

TIMER

CLR WDT 1 0 0 0000-1111-X

XTAL 32K 1 0 0 0001-01XX-X

RC 256K

C

Clear the contents of WDT stage

System clock source, crystal oscillator

System clock source, on chip RC oscillator

System clock source, external clock source

LCD 1/2 bias option

ab=00: 2 commons option

ab=01: 3 commons option

ab=10: 4 commons option

LCD 1/3 bias option

1 0 0 0001-10XX-X

EXT 256K 1 0 0 0001-11XX-X

BIAS 1/2

BIAS 1/3

1 0 0 0010-abX0-X

1 0 0 0010-abX1-X

C

ab=00: 2 commons option

ab=01: 3 commons option

ab=10: 4 commons option

TONE 4K

TONE 2K

IRQB DIS 1 0 0 100X-0XXX-X

IRQB EN

F1

1 0 0 010X-XXXX-X

1 0 0 011X-XXXX-X

C

Tone frequency, 4KHz

Tone frequency, 2KHz

Disable IRQB output

Enable IRQB output

Yes

1 0 0 100X-1XXX-X

1 0 0 101X-X000-X

Time base/WDT clock output:1Hz

The WDT time-out flag after: 4s

Time base/WDT clock output:2Hz The WDT

time-out flag after: 2s

Time base/WDT clock output:4Hz

The WDT time-out flag after: 1s

Time base/WDT clock Output: 8Hz

The WDT time-out flag after: 1/2 s

Time base/WDT clock output: 16Hz The WDT

time-out flag after: 1/4 s

Time base/WDT clock output: 32Hz

The WDT time-out flag after: 1/8 s

Time base/WDT clock output:64Hz

The WDT time-out flag after: 1/16 s

Time base/WDT clock output:128Hz

The WDT time-out flag after: 1/32 s

Test mode, user don’t use.

F2

1 0 0 101X-X001-X

1 0 0 101X-X010-X

1 0 0 101X-X011-X

1 0 0 101X-X100-X

1 0 0 101X-X101-X

1 0 0 101X-X110-X

1 0 0 101X-X111-X

C

F4

F8

F16

F32

F64

F128

Yes

TEST

NORMAL

1 0 0 1110-0000-X

1 0 0 1110-0011-X

C

Normal mode

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SL3204

Note:

X: Don’t care

A5~A0: RAM addresses

D3~D0: RAM data

D/C: Data/command mode

Def.: Power on reset default

All the bold forms, namely 1 1 0, 1 0 1, and 1 0 0, are mode commands. Of these 1 0 0 indicates the

command mode ID. If successive commands have been issued, the command mode ID except for the first

command will be omitted. The source of the tone frequency and of the time base/WDT clock frequency

can be derived from an on chip 256KHz RC oscillator, a 32.768 KHz crystal oscillator, or an external

256KHz clock. Calculation of the frequency is based on the system frequency sources as stated above. It

is recommended that the host controller should initialize the SL3204 after power on reset, for power on

reset may fail, which in turn leads to the malfunctioning of the SL3204.

z Pin Assignment

SEG12

SEG13

SEG14

SEG15

SEG16

SEG17

SEG18

SEG19

SEG20

SEG21

SEG22

SEG23

SEG24

CSB

RDB

WRB

DATA

VSS

LOGO

OSCO

OSCI

VLCD

VDD

IRQB

BZ

The IC substrate should be connected to VDD in the PCB layout artwork.

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SL3204

z Pad Coordinates

No.

1

Name

CSB

x

y

No.

25

26

27

28

29

30

31

32

33

34

35

36

37

38

39

40

41

42

43

44

45

46

47

48

Name

SEG23

SEG22

SEG21

SEG20

SEG19

SEG18

SEG17

SEG16

SEG15

SEG14

SEG13

SEG12

SEG11

SEG10

SEG9

x

Y

68.80

1499.44

1371.44

1243.44

1115.44

987.44

859.44

731.44

603.44

475.44

348.24

188.80

60.80

1820.80

1604.80

1476.80

1348.80

1220.80

1092.80

964.80

218.24

346.24

474.24

602.24

730.24

858.24

986.24

2

RDB

68.80

3

WRB

68.80

4

DATA

VSS

68.80

5

68.80

6

OSCO

OSCI

60.80

7

60.80

8

VLCD

VDD

60.80

1114.24

1242.24

1370.24

1498.24

1626.24

1627.44

9

60.80

10

11

12

13

14

15

16

17

18

19

20

21

22

23

24

IRQB

60.80

BZ

60.80

BZB

188.88

324.56

452.56

580.56

708.56

836.56

964.56

1092.56

1220.56

1348.56

1476.56

1604.56

1820.80

435

COM0

COM1

COM2

COM3

SEG31

SEG30

SEG29

SEG28

SEG27

SEG26

SEG25

SEG24

LOGO

60.80

SEG8

60.80

SEG7

60.80

SEG6

60.80

SEG5

836.80

60.80

SEG4

708.80

60.80

SEG3

580.80

60.80

SEG2

452.80

60.80

SEG1

324.80

90.24

SEG0

196.80

1072

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TITAN TECHNOLOGY Co. Ltd.

SL3204

z Package

SSOP 48 Pins

SEG7

SEG6

SEG5

SEG4

SEG3

SEG2

SEG1

SEG0

CSB

SEG8

SEG9

25

24

48

1

SEG10

SEG11

SEG12

SEG13

SEG14

SEG15

SEG16

SEG17

SEG18

SEG19

SEG20

SEG21

SEG22

SEG23

SEG24

SEG25

SEG26

SEG27

SEG28

SEG29

SEG30

SEG31

A

B

RDB

WRB

DATA

VSS

OSCO

OSCI

VLCD

VDD

IRQB

BZ

BZB

COM0

COM1

COM2

COM3

C

C'

G

H

D

E

F

SSOP 48pin

A

B

C

C’

613~637

D

E

F

G

H

Unit

395~420 291~299

8~12

85~99

25

4~10

25~35

4~12

mil

SOP 32 Pins

SEG31

SEG30

SEG29

SEG28

SEG27

SEG26

SEG25

SEG24

SEG23

SEG22

SEG21

SEG10

SEG9

1

2

3

4

5

6

7

8

32

COM3

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

COM2

COM1

COM0

VDD

VLCD

VSS

DATA

WRB

CSB

SEG0

SEG1

SEG2

SEG3

SEG4

SEG5

9

10

11

12

13

14

15

16

0.15

20.98

SEG8

SEG7

SEG6

unit: mm

1.27

0.35

SL3204CS

-SOP32

14

TITAN TECHNOLOGY Co. Ltd.

SL3204

SKDIP 28 Pins

A

SEG5

SEG3

SEG1

CSB

1

2

3

4

5

6

7

8

9

28 SEG7

27 SEG9

26 SEG11

25 SEG13

24 SEG15

23 SEG17

22 SEG19

21 SEG21

20 SEG23

19 SEG25

18 SEG27

17 SEG29

16 SEG31

15 COM2

15

14

28

B

1

RDB

WRB

DATA

VSS

H

VLCD

VDD 10

IRQB 11

BZ 12

COM0 13

COM1 14

C

D

I

G

F

E

HW3204D

SKDIP28

A

B

C

D

E

F

G

H

I

Unit

1375~1395 276~299 125~135 125~140

16~21

50~70

100

295~315 330~375

mil

COB48

SEG7

SEG6

SEG5

SEG4

SEG3

SEG2

SEG1

SEG0

CSB

SEG8

SEG9

48

25

24

SL3204

SEG10

SEG11

SEG12

SEG13

SEG14

SEG15

SEG16

SEG17

SEG18

SEG19

SEG20

SEG21

SEG22

SEG23

SEG24

SEG25

SEG26

SEG27

SEG28

SEG29

SEG30

SEG31

B

1

C

C'

RDB

WRB

DATA

VSS

OSCO

OSCI

VLCD

VDD

IRQB

BZ

BZB

D

E

COM0

COM1

COM2

COM3

COB48

B

C

C’

613~637

D

E

Unit

mil

300

15

15~17

25

15

TITAN TECHNOLOGY Co. Ltd.

SL3204

LQFP48

C

H

G

D

36

25

48 47 46 45 44 43 42 41 40 39 38 37

CSB

RDB

WRB

DATA

VSS

OSCO

OSCI

VLCD

VDD

IRQB

BZ

1

36

35

34

33

32

31

30

29

28

27

26

25

SEG12

SEG13

SEG14

SEG15

SEG16

SEG17

SEG18

SEG19

SEG20

SEG21

SEG22

SEG23

I

2

37

24

3

4

5

SL3204BQ

XXXXXXXXXXXX

XXXX

F

6

B

7

A

8

E

9

10

11

12

48

13

BZB

K

α

13 14 15 16 17 18 19 20 21 22 23 24

J

12

1

Dimensions in mm

Symbol

Min.

Nom.

─

Max.

9.10

7.10

9.10

7.10

─

A

B

C

D

E

F

G

H

I

8.90

6.90

5.90

6.90

─

0.50

0.20

─

1.35

─

1.45

1.60

─

0.10

─

J

0.45

0.10

0ꢀ

0.75

0.20

7ꢀ

─

K

α

─

16

TITAN TECHNOLOGY Co. Ltd.

SL3204

z History

Date

Name

Version

1.0

1.1

1.2

2.0

3.0

3.1

3.2

3.3

3.4

3.5

3.6

3.7

3.8

3.9

4.0

4.1

4.2

4.3

4.4

4.5

4.6

Comment

Initial

2003/2/9

2003/2/13

2003/3/17

2003/5/26

2003/9/05

2003/9/15

2003/9/20

2003/9/25

CC Kuo

Insert the package information

Modify timing diagram

Add the AC spec

Modify the pin assignment

Add package information

Modify the AC spec.

2003/11/20 CC Kuo

2004/2/24

2005/3/23

2005/4/20

2005/5/10

2005/6/8

CC Kuo

Rong

Lisa

Add the DC Absolute Maximum Ratings

Add the D.C. spec.

Lisa

Modify the Operating voltage

Modify the command code

Modify the Operating voltage

Modify the pin location

Lisa

2005/6/17

2005/7/12

2005/11/2

2005/11/9

Lisa

Alec

Modify index

Modify pin assignment and pin location

Modify the pin assignment

Modify margins of document

Re-typesetting

2005/12/06 Alec

2005/12/8

ACLin

2006/10/16 ACLin

2007/1/22

ACLin

4.7

4.8

Add package SOP32 & SKDIP28 spec.

2007/2/2

Modify application circuit graphic & Add COB48

2007/4/20

Add: The IC substrate should be connected to VDD in the PCB

layout artwork.

2007/7/25

2007/8/6

2007/8/24

ACLin

Jazz

4.81

4.82

5.0

Modify package SSOP48 picture.

Add LQFP48 package.

ACLin

Change all picture format. And modify LQFP48 information.

17


型号：	SL3204
厂家：	ETC
描述：	128 patterns (324),memory mapping,and multi-function LCD driver 128图案（3 24），存储器映射和多功能的LCD驱动存储驱动 CD
文件：	总17页 (文件大小：646K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

SL3204 [ETC]

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