SLN04G72F1BB1SA-CCRT

preliminary Data Sheet

Rev.0.9

07.06.2013

4GB DDR3L – SDRAM ECC SO-UDIMM

Features:

204 Pin ECC SO-UDIMM

.

204-pin 72-bit DDR3 Small Outline, Dual-In-Line Double

Data Rate synchronous DRAM Module

Module organization: single rank 512M x 72

V_DD= 1.35V and 1.5V

SLN04G72F1BB1SA-xxRT

4GByte in FBGA Technology

RoHS compliant

.

V_DDQ1.35V and 1.5V

1.5V I/O ( SSTL_15 compatible)

Fly-by-bus with termination for C/A & CLK bus

On-board I²C temperature sensor with integrated serial

presence-detect (SPD) EEPROM

Gold-contact pad

Options:

.

Data Rate / Latency

DDR3 1333 MT/s CL9

DDR3 1600 MT/s CL11

Marking

-CC

.

This module is fully pin and functional compatible to the

JEDEC EP3-12800 DDR3 SDRAM 72bit-SO-DIMM design

spec. and JEDEC- Standard MO-268. (see www.jedec.org)

The pcb and all components are manufactured according

-DC

.

Module Density

4GByte with 9 dies and 1 rank

to the RoHS compliance specification

[EU Directive 2002/95/EC Restriction of Hazardous

Substances (RoHS)]

.

Standard Grade

(T_A)

(T_C)

0°C to 70°C

0°C to 85°C

.

DDR3L - SDRAM component Samsung

K4B4G0846B-HYXX

.

512Mx8 DDR3 SDRAM in PG-TFBGA-78 package

8-bit prefetch architecture

Programmable CAS Latency, CAS Write Latency, Additive

Latency, Burst Length and Burst Type.

On-Die-Termination (ODT) and Dynamic ODT for

improved signal integrity.

*) The refresh rate has to be doubled when 85°C<T_C<95°C

.

Environmental Requirements:

.

Refresh, Self Refresh and Power Down Modes.

ZQ Calibration for output driver and ODT.

System Level Timing Calibration Support via Write

Leveling and Multi Purpose Register (MPR) Read Pattern.

.

Operating temperature (ambient)

Standard Grade

0°C to 70°C

.

Operating Humidity

10% to 90% relative humidity, noncondensing

Operating Pressure

105 to 69 kPa (up to 10000 ft.)

Storage Temperature

-55°C to 100°C

Storage Humidity

5% to 95% relative humidity, noncondensing

Storage Pressure

Figure: mechanical dimensions¹

1682 PSI (up to 5000 ft.) at 50°C

1

if no tolerances specified ± 0.15mm

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Page 1

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preliminary Data Sheet

Rev.0.9

07.06.2013

This Swissbit module is an industry standard 204-pin 8-byte DDR3 SDRAM ECC Small Outline Dual-In-line

Memory Module (SO-UDIMM) which is organized as x72 high speed CMOS memory arrays. The module uses

internally configured octal-bank DDR3 SDRAM devices. The module uses double data rate architecture to

achieve high-speed operation. DDR3 SDRAM modules operate from a differential clock (CK and CK#). READ

and WRITE accesses to a DDR3 SDRAM module is burst-oriented; accesses start at a selected location and

continue for a programmed number of locations in a programmed sequence. The burst length is either four or

eight locations. An auto precharge function can be enabled to provide a self-timed row precharge that is initiated

at the end of a burst access. The DDR3 SDRAM devices have a multibank architecture which allows a concurrent

operation that is providing a high effective bandwidth. A self refresh mode is provided and a power-saving “power-

down” mode. All inputs and all full drive-strength outputs are SSTL_15 compatible.

The DDR3 SDRAM module uses the serial presence detect (SPD) function implemented via serial EEPROM

using the standard I²C protocol. This nonvolatile storage device contains 256 bytes. The first 128 bytes are

utilized by the SO-UDIMM manufacturer (Swissbit) to identify the module type, the module’s organization and

several timing parameters. The second 128 bytes are available to the end user.

Module Configuration

Row

Addr.

Device Bank

Addr.

Column

Addr.

Module

Bank Select

Organization

DDR3 SDRAMs used

Refresh

512M x 72bit

9 x 512M x 8bit (4Gbit)

16

BA0, BA1, BA2

10

8k

S0#

Module Dimensions

in mm

67.60 (long) x 30(high) x 3.80 [max] (thickness)

Timing Parameters

Part Number

Module Density

Transfer Rate Clock Cycle/Data bit rate

Latency

SLN04G72F1BB1SA-CCRT

4GByte

10.6 GB/s

12.8 GB/s

1.5ns / 1333MT/s

1.25ns / 1600MT/s

9-9-9

SLN04G72F1BB1SA-DCRT

4GByte

11-11-11

Pin Name

A0 – A9, A11 – A15

A10/AP

Address Inputs

Address Input / Autoprecharge Bit

Bank Address Inputs

Data Input / Output

BA0 – BA2

DQ0 – DQ63

CB0 – CB07

DM0 – DM8

DQS0 – DQS8

DQS0# – DQS8#

RAS#

ECC check bits

Input Data Mask

Data Strobe, positive line

Data Strobe, negative line (only used when differential data strobe mode is enabled)

Row Address Strobe

Column Address Strobe

Write Enable

CAS#

WE#

CKE0

Clock Enable

S0#

Chip Select

CK0

Clock Inputs, positive line

Clock Inputs, negative line

CK0#

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Page 2

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preliminary Data Sheet

Rev.0.9

07.06.2013

Event#

V_DD

Temperature event: The EVENT# pin is asserted by the temperature sensor when critical

Supply Voltage (1.35V -0.067V/+0.1V and 1.5V ± 0.075V)

Reference voltage: DQ, DM (V_DD/2)

V_REFDQ

V_REFCA

V_SS

Reference voltage: Control, command, and address (V_DD/2)

Ground

V_TT

Termination voltage: Used for control, command, and address (V_DD/2).

Serial EEPROM Positive Power Supply

Serial Clock for Presence Detect

V_DDSPD

SCL

SDA

Serial Data Out for Presence Detect

SA0 – SA1

ODT0

NC

Presence Detect Address Inputs

On-Die Termination

No Connection

Pin Configuration

Frontside

1

Symbol

V_REFDQ

V_SS

53

55

57

59

61

63

65

67

69

71

Symbol

V_SS

103

105

107

109

111

113

115

117

119

121

123

125

127

129

131

133

135

137

139

141

143

145

147

149

151

153

Symbol

A3

155

157

159

161

163

165

167

169

171

173

175

177

179

181

183

185

187

189

191

193

195

197

199

201

203

Symbol

V_SS

3

DQ24

DQ25

DM3

V_SS

A1

DM5

DQ42

DQ43

V_SS

5

DQ0

DQ1

V_SS

A0

7

V_DD

9

CK0

11

13

15

17

19

21

23

25

27

29

31

33

35

37

39

41

43

45

47

49

51

DM0

DQ2

DQ3

V_SS

DQ26

DQ27

V_SS

CK0#

V_DD

DQ48

DQ49

V_SS

A10/AP

BA0

CB0

DQS6#

DQS6

V_SS

DQ8

DQ9

V_SS

CB1

WE#

V_DD

Key

73

75

77

79

81

83

85

87

89

91

93

95

97

99

101

V_SS

DQS8#

DQS8

V_SS

CAS#

S0#

DQ50

DQ51

V_SS

DQS1#

DQS1

V_SS

NC(S1#)

V_DD

DQ56

DQ57

V_SS

DQ10

DQ11

V_SS

CB2

DQ32

DQ33

V_SS

CB3

V_DD

DM7

DQ58

DQ59

V_SS

DQ16

DQ17

V_SS

CKE0

NC(CKE1)

BA2

DQS4#

DQS4

V_SS

DQS2#

DQS2

V_SS

V_DD

DQ34

DQ35

V_SS

SA0

A12/BC#

A8

V_DDSPD

SA1

DQ18

DQ19

A5

DQ40

DQ41

V_TT

V_DD

(Sig): Signal in brackets may be routed to the socket connector, but is not used on the module

Swissbit AG

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Page 3

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preliminary Data Sheet

Rev.0.9

07.06.2013

Backside

2

Symbol

V_SS

54

56

58

60

62

64

66

68

70

72

Symbol

DQ28

DQ29

V_SS

104

106

108

110

112

114

116

118

120

122

124

126

128

130

132

134

136

138

140

142

144

146

148

150

152

154

Symbol

A4

Symbol

DQS5

V_SS

156

158

160

162

164

166

168

170

172

174

176

178

180

182

184

186

188

190

192

194

196

198

200

202

204

4

DQ4

DQ5

V_SS

A2

6

BA1

DQ46

DQ47

V_SS

8

DQS3#

DQS3

V_SS

V_DD

10

12

14

16

18

20

22

24

26

28

30

32

34

36

38

40

42

44

46

48

50

52

DQS0#

DQS0

V_SS

NC(CK1)

NC(CK1#)

V_DD

DQ52

DQ53

V_SS

DQ30

DQ31

V_SS

DQ6

DQ7

V_SS

NC(S3#)

NC(S2#)

RAS#

V_DD

DM6

CB4

DQ54

DQ55

V_SS

DQ12

DQ13

V_SS

Key

74

76

78

80

82

84

86

88

90

92

94

96

98

100

102

CB5

DM8

V_SS

ODT0

NC(ODT1)

A13

DQ60

DQ61

V_SS

DM1

Reset#

V_SS

CB6

CB7

V_REFCA

V_DD

A15

A14

A9

V_DD

DQ36

DQ37

V_SS

DQS7#

DQS7

V_SS

DQ14

DQ15

V_SS

DM4

DQ62

DQ63

V_SS

DQ20

DQ21

DM2

V_SS

DQ38

DQ39

V_SS

V_DD

A11

A7

EVENT#

SDA

DQ44

DQ45

V_SS

DQ22

DQ23

V_SS

SCL

A6

V_TT

V_DD

DQS5#

(Sig): Signal in brackets may be routed to the socket connector, but is not used on the module

Swissbit AG

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Page 4

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preliminary Data Sheet

Rev.0.9

07.06.2013

FUNCTIONAL BLOCK DIAGRAMM 4096MB DDR3 SDRAM SO-UDIMM,

1 RANK AND 9 COMPONENTS

S0

DQS4

DQS0

DM4

DM0

DM CS

DQS DQS

DM CS

DQS DQS

I/O 0

I/O 1

I/O 2

I/O 3

I/O 4

I/O 5

I/O 6

I/O 7

I/O 0

I/O 1

I/O 2

I/O 3

I/O 4

I/O 5

I/O 6

I/O 7

DQ32

DQ33

DQ34

DQ35

DQ36

DQ37

DQ38

DQ39

DQ0

DQ1

DQ2

DQ3

DQ4

DQ5

DQ6

DQ7

D4

D0

ZQ

DQS5

DQS1

DM5

DM1

DM CS

DQS DQS

DM CS

DQS DQS

I/O 0

I/O 1

I/O 2

I/O 3

I/O 4

I/O 5

I/O 6

I/O 7

I/O 0

I/O 1

I/O 2

I/O 3

I/O 4

I/O 5

I/O 6

I/O 7

DQ40

DQ41

DQ42

DQ43

DQ44

DQ45

DQ46

DQ47

DQ8

DQ9

D5

D1

DQ10

DQ11

DQ12

DQ13

DQ14

DQ15

ZQ

DQS6

DQS2

DM6

DM2

DM CS

DQS DQS

DM CS

DQS DQS

I/O 0

I/O 1

I/O 2

I/O 3

I/O 4

I/O 5

I/O 6

I/O 7

I/O 0

I/O 1

I/O 2

I/O 3

I/O 4

I/O 5

I/O 6

I/O 7

DQ48

DQ49

DQ50

DQ51

DQ52

DQ53

DQ54

DQ55

DQ16

DQ17

DQ18

DQ19

DQ20

DQ21

DQ22

DQ23

D6

D2

ZQ

DQS7

DQS3

DM7

DM3

DM CS

DQS DQS

DM CS

DQS DQS

I/O 0

I/O 1

I/O 2

I/O 3

I/O 4

I/O 5

I/O 6

I/O 7

I/O 0

I/O 1

I/O 2

I/O 3

I/O 4

I/O 5

I/O 6

I/O 7

DQ56

DQ57

DQ58

DQ59

DQ60

DQ61

DQ62

DQ63

DQ24

DQ25

DQ26

DQ27

DQ28

DQ29

DQ30

DQ31

D7

D3

ZQ

DQS8

DM8

V_DDSPD

V_DD/V_DDQ

V_REFDQ

SPD

DM CS

DQS DQS

I/O 0

I/O 1

I/O 2

I/O 3

I/O 4

I/O 5

I/O 6

I/O 7

CB0

CB1

CB2

CB3

CB4

CB5

CB6

CB7

D0-D8

D8

D0-D8

V_REFCA

V_SS

D0-D8

ZQ

Notes:

BA0-BA2

A0-A14

BA0-BA2: SDRAM D0-D8

A0-A14: SDRAM D0-D8

1. DQ-to-I/O wiring is shown as recommended but may

be changed.

RAS

CAS

WE

ODT0

CKE0

CK0

RESET

RAS: SDRAM D0-D8

CAS: SDRAM D0-D8

WE: SDRAM D0-D8

ODT: SDRAM D0-D8

CKE: SDRAM D0-D8

CK: SDRAM D0-D8

RESET: SDRAM D0-D8

2. DQ/DQS/DQS/ODT/DM/CKE/S relationship must be

maintained as shown.

3. DQ, DM, DQS/DQS resistors: Refer to associated

topology diagram.

4. Refer to the appropriate clock wiring topology under

the DIMM wiring details section of the JEDED document.

5. For each DRAM, a unique ZQ resistor is connected to

GND. The ZQ resistor is 240O±1%.

6. Refer to associated figure for SPD details.

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Page 5

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preliminary Data Sheet

Rev.0.9

07.06.2013

MAXIMUM ELECTRICAL DC CHARACTERISTICS

PARAMETER/ CONDITION

Supply Voltage

I/O Supply Voltage

SYMBOL

V_DD

V_DDQ

V_IN, V_OUT

MIN

-0.4

MAX

UNITS

1.975

V

Voltage on any pin relative to V_SS

INPUT LEAKAGE CURRENT

Any input 0V ≤ V_IN≤ V_DD,V_REFpin 0V ≤ V_IN≤ 0.95V

(All other pins not under test = 0V)

I_I

µA

Command/Address

RAS#, CAS#, WE#, S#, CKE

-16

16

CK, CK#

DM

-16

-2

16

2

OUTPUT LEAKAGE CURRENT

(DQ’s and ODT are disabled; 0V ≤ V_OUT≤ V_DDQ

I_OZ

-5

5

µA

)

DQ, DQS, DQS#

V_REFLEAKAGE CURRENT ; V_REFis on a valid level

I_VREF

-8

8

DC OPERATING CONDITIONS

PARAMETER/ CONDITION

Supply Voltage

I/O Supply Voltage

SYMBOL

V_DD

MIN

1.283

NOM

1.35

0.50 x V_DDQ

MAX

1.450

UNITS

V

V_DDQ

V_REF

V_TT

V_{IH (DC90)}

V_{IL (DC90)}

I/O Reference Voltage

0.49 x V_DDQ

0.49 x V_DDQ-20mV

V_REF+ 90mV

-0.3

0.51x V_DDQ

0.51x V_DDQ+20mV

V_DDQ+ 0.3

I/O Termination Voltage (system)

Input High (Logic 1) Voltage

Input Low (Logic 0) Voltage

V_REF– 90mV

Under 1.5V operation this DDR3L device operates in accordance to the following specification:

SGN04G72F1BB1SA-XXRT

AC INPUT OPERATING CONDITIONS

PARAMETER/ CONDITION

Input High (Logic 1) Voltage

Input Low (Logic 0) Voltage

SYMBOL

V_{IH (AC135)}

V_{IL (AC135)}

MIN

V_REF+ 0.135mV

-

MAX

-

V_REF– 0.135mV

UNITS

V

CAPACITANCE

At DDR3 data rates, it is recommended to simulate the performance of the module to achieve optimum values.

When inductance and delay parameters associated with trace lengths are used in simulations, they are

significantly more accurate and realistic than a gross estimation of module capacitance. Simulations can then

render a considerably more accurate result. JEDEC modules are now designed by using simulations to close

timing budgets.

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Page 6

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preliminary Data Sheet

Rev.0.9

07.06.2013

I_DDSpecifications and Conditions

(0°C ≤ T_CASE≤ + 85°C; V_DDQ, V_DD= +1.283V – 1.45V)

Parameter

max.

12800-CL11

& Test Condition

Symbol

10600-CL9

Unit

OPERATING CURRENT *) :

One device bank Active-Precharge;

mA

I_DD0

360

t_RC= t_RC(I_DD); t_CK= t_CK(I_DD); CKE is HIGH, CS# is HIGH

between valid commands;

DQ inputs changing once per clock cycle; Address and

control inputs changing once every two clock cycles

OPERATING CURRENT *) :

One device bank; Active-Read-Precharge;

I_OUT= 0mA; BL = 4, CL = CL (I_DD), AL = 0;

t_CK= t_CK(I_DD), t_RC= t_RC(I_DD), t_RAS= t_RASMIN (I_DD),

t_RCD= t_RCD(I_DD); CKE is HIGH, CS# is HIGH between

valid commands; Address inputs changing once every

two clock cycles; Data Pattern is same as I_DD4W

mA

I_DD1

495

450

Fast Exit

PRECHARGE POWER-DOWN

I_DD2P

135

180

135

180

CURRENT:

All device banks idle; Power-down mode;

Slow Exit

t_CK= t_CK(I_DD); CKE is LOW; All Control and

Address bus inputs are not changing; DQ’s

are floating at V_REF

PRECHARGE QUIET STANDBY CURRENT:

All device banks idle;

t_CK= t_CK(I_DD); CKE is HIGH, CS# is HIGH;

All Control and Address bus inputs are not changing;

DQ’s are floating at V_REF

PRECHARGE STANDBY CURRENT:

All device banks idle;

mA

I_DD2Q

I_DD2N

180

t_CK= t_CK(I_DD); CKE is HIGH, CS# is HIGH;

All other Control and Address bus inputs are changing

once every two clock cycles; DQ inputs changing once

per clock cycle

ACTIVE POWER-DOWN CURRENT:

mA

I_DD3P

180

270

180

270

All device banks open; t_CK= t_CK(I_DD); CKE is LOW; All

Control and Address bus inputs are not changing; DQ’s

are floating at V_REF(always fast exit)

ACTIVE STANDBY CURRENT:

All device banks open; t_CK= t_CK(I_DD),

I_DD3N

t_RAS= t_RASMAX (I_DD), t_RP= t_RP(I_DD);

CKE is HIGH, CS# is HIGH between valid commands;

All other Control and Address bus inputs are changing

once every two clock cycles; DQ inputs changing once

per clock cycle

OPERATING READ CURRENT:

mA

I_DD4R

900

765

All device banks open, Continuous burst reads; One

module rank active; I_OUT= 0mA; BL = 4, CL = CL (I_DD),

AL = 0; t_CK= t_CK(I_DD), t_RAS= t_RASMAX (I_DD), t_RP= t_RP

(I_DD); CKE is HIGH, CS# is HIGH between valid

commands; Address bus inputs are changing once

every two clock cycles; DQ inputs changing once per

clock cycle

Swissbit AG

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Page 7

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preliminary Data Sheet

Rev.0.9

07.06.2013

Parameter

max.

12800-CL11

& Test Condition

Symbol

10600-CL9

765

Unit

OPERATING WRITE CURRENT:

mA

I_DD4W

945

All device banks open, Continuous burst writes; One

module rank active; BL = 4, CL = CL (I_DD), AL = 0;

t_CK= t_CK(I_DD), t_RAS= t_RASMAX (I_DD), t_RP= t_RP(I_DD);

CKE is HIGH, CS# is HIGH between valid commands;

Address bus inputs are changing once every two clock

cycles; DQ inputs changing once per clock cycle

BURST REFRESH CURRENT:

mA

I_DD5

1305

t_CK= t_CK(I_DD); refresh command at every t_RFC(I_DD)

interval, CKE is HIGH, CS# is HIGH between valid

commands; All other Control and Address bus inputs

are changing once every two clock cycles; DQ inputs

changing once per clock cycle

SELF REFRESH CURRENT:

mA

I_DD6

135

CK and CK# at 0V; CKE ≤ 0.2V; All other Control and

Address bus inputs are floating at V_REF; DQ’s are

floating at V_REF

OPERATING CURRENT *) :

I_DD7

1530

1485

Four device bank interleaving READs, I_OUT= 0mA; BL = 4,

CL = CL (I_DD), AL = t_RCD(I_DD) – 1 x t_CK(I_DD); t_CK= t_CK

(I_DD), t_RC= t_RC(I_DD), t_RRD= t_RRD(I_DD), t_RCD= t_RCD(I_DD);

CKE is HIGH, CS# is HIGH between valid commands;

Address bus inputs are not changing during

DESELECT; DQ inputs changing once per clock cycle

*) Value calculated as one module rank in this operating condition, and all other module ranks in IDD2P (CKE LOW)

mode.

TIMING VALUES USED FOR I_DDMEASUREMENT

I_DDMEASUREMENT CONDITIONS

SYMBOL

CL (I_DD

t_RCD(I_DD

t_RC(I_DD

t_RRD(I_DD

t_CK(I_DD

t_RASMIN (I_DD

t_RASMAX (I_DD

t_RP(I_DD

t_RFC(I_DD

12800-CL11

11

10600-CL9

9

Unit

t_CK

ns

)

13.75

48.75

6

1.25

35

70’200

13.75

260

13.5

49.5

6

1.5

36

70’200

13.5

260

)

Swissbit AG

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Page 8

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preliminary Data Sheet

Rev.0.9

07.06.2013

DDR3 SDRAM COMPONENT ELECTRICAL CHARACTERISTICS AND RECOMMENDED

AC OPERATING CONDITIONS

(0°C ≤ T_CASE≤ + 85°C; V_DDQ, V_DD= +1.283V – 1.45V)

AC CHARACTERISTICS

PARAMETER

12800-CL11

10600-CL9

SYMBOL

t_CK(11)

t_CK(10)

t_CK(9)

t_CK(8)

t_CK(7)

t_CK(6)

t_CK(5)

t_AA

MIN

1.25

1.5

MAX

-

MIN

-

MAX

-

Unit

Clock cycle time

CL = 11

CL = 10

CL = 9

CL = 8

CL = 7

CL = 6

CL = 5

<1.875

<2.5

3.3

1.5

1.875

2.5

<1.875

<2.5

3.3

1.5

1.875

2.5

ns

3.0

3.3

3.0

3.3

Internal READ command to first

data

13.75

-

13.5

-

CK high-level width

CK low-level width

0.47

0.53

0.47

0.53

t_CK

t_CH

t_CL

(AVG)

Data-out high-impedance

window from CK/CK#

Data-out low-impedance window

from CK/CK#

t_HZ

-

225

-

250

ps

t_LZ

-450

-500

DQ and DM input setup time

relative to DQS V_REF=1V/ns

t_DS1V

160

-

180

-

ps

DQ and DM input hold time

relative to DQS V_REF=1V/ns

DQ and DM input pulse width

( for each input )

DQS, DQS# to DQ skew, per

access

DQ-DQS hold, DQS to first DQ

to go non-valid, per access

DQS input high pulse width

t_DH1V

t_DIPW

t_DQSQ

t_QH

145

360

-

165

400

-

ps

-

100

-

125

-

t_CK

(AVG)

t_CK

0.38

0.45

0.55

0.45

0.55

t_DQSH

t_DQSL

DQS input low pulse width

t_CK

DQS, DQS# rising to/from CK,

CK#

DQS, DQS# rising to/from CK,

CK# when DLL disabled

t_DQSCK

-225

1

225

-250

1

250

ps

t_DQSCK

DLL_DIS

10

-

10

-

ns

t_CK

DQS falling edge to CK rising

- setup time

DQS falling edge from CK rising

- hold time

t_DSS

0.18

0.2

t_DSH

-

0.9

0.3

0.9

0.3

Note¹

0.9

0.3

0.9

0.3

Note¹

t_CK

DQS read preamble

t_RPRE

t_RPST

t_WPRE

t_WPST

t_DQSS

Note²

DQS read postamble

DQS write preamble

DQS write postamble

Positive DQS latching edge to

associated clock edge

Address and control input pulse

width ( for each input )

CTRL, CMD, Addr setup to CK,

CK#

-

- 0.27

560

45

+ 0.27

- 0.25

620

65

+ 0.25

t_CK

ps

t_IPW

-

t_IS(Base)

t_IS(1V)

CTRL, CMD, Addr setup to CK,

220

240

CK#

V_REF@ 1V/ns

1

The maximum preamble is bound by tLZDQS (MAX)

The maximum postamble is bound by tHZDQS (MAX)

2

Swissbit AG

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Page 9

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preliminary Data Sheet

Rev.0.9

07.06.2013

DDR3 SDRAM COMPONENT ELECTRICAL CHARACTERISTICS AND RECOMMENDED

AC OPERATING CONDITIONS (Continued)

(0°C ≤ T_CASE≤ + 85°C; V_DDQ, V_DD= +1.283V – 1.45V)

AC CHARACTERISTICS

PARAMETER

12800-CL11

MIN MAX

10600-CL9

SYMBOL

MIN

MAX

Unit

CTRL, CMD, Addr hold to CK,

CK#

120

-

140

-

ps

t_IH(Base)

CTRL, CMD, Addr hold to CK,

220

4

-

240

4

-

ps

t_CK

ns

t_IH(1V)

t_CCD

t_RC

CK#

V_REF@ 1V/ns

CAS# to CAS# command delay

ACTIVE to ACTIVE (same bank)

command period

48.75

49.5

ACTIVE to ACTIVE minimum

command period

ACTIVE to READ or WRITE

delay

max

ns

t_RRD

t_RCD

t_FAW

t_RAS

4nCK,6ns

-

13.75

13.5

Four bank

Activate period

1K Page size

2K Page size

30

40

-

30

45

-

ACTIVE to PRECHARGE

command

35

70’200

36

70’200

Internal READ to precharge

command delay

Write recovery time

Auto precharge write recovery +

precharge time

max

-

ns

t_RTP

t_WR

t_DAL

4nCK,7.5ns

15

t_WR+ t_RP/t_CK

Internal WRITE to READ

command delay

PRECHARGE command period

LOAD MODE command cycle

time

max

-

ns

t_CK

t_WTR

t_RP

4nCK,7.5ns

13.75

4

13.5

4

t_MRD

REFRESH to ACTIVE or

REFRESH to REFRESH

command interval

Average periodic refresh interval

0 °C ≤ TCASE ≤ 85°C

260

70’200

260

70’200

ns

µs

t_RFC

-

7.8

3.9

-

7.8

3.9

t_REFI

t_{REFI (IT)}

t_AON

85 °C < TCASE ≤ 95°C

RTT turn-on from ODTL on

reference

RTT turn-on from ODTL off

reference

Asynchronous RTT turn-on

delay (power Down with DLL off)

Asynchronous RTT turn-off

delay (power Down with DLL off)

RTT dynamic change skew

-225

225

-250

250

ps

t_CK

ns

0.3

2

0.7

8,5

0.3

2

0.7

8,5

t_AOF

t_AONPD

2

8,5

0.7

2

8,5

0.7

ns

t_AOFPD

t_ADC

0.3

t_CK

Exit self refresh to commands

not requiring a locked DLL

max

5nCK,tR

FC + 10ns

max

5nCK,tR

FC + 10ns

-

ns

t_XS

Write levelling setup from rising

CK, CK# crossing to rising DQS,

DQS# crossing

Write levelling setup from rising

DQS, DQS# crossing to rising

CK, CK# crossing

-

165

-

195

ps

t_WLS

-

ps

t_WLH

First DQS, DQS# rising edge

DQS, DQS# delay

-

40

25

-

40

25

t_CK

t_WLMRD

t_WLDQSEN

Swissbit AG

Industriestrasse 4

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Fax: +41 (0) 71 913 03 15

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Page 10

of 17

preliminary Data Sheet

Rev.0.9

07.06.2013

DDR3 SDRAM COMPONENT ELECTRICAL CHARACTERISTICS AND RECOMMENDED

AC OPERATING CONDITIONS (Continued)

(0°C ≤ T_CASE≤ + 85°C; V_DDQ, V_DD= +1.283V – 1.45V)

AC CHARACTERISTICS

PARAMETER

12800-CL11

10600-CL9

SYMBOL

MIN

MAX

MIN

MAX Unit

Exit reset from CKE HIGH to a

valid command

max

t_XPR

-

t_CK

5nCK,

t_RFC+ 10ns

Begin power supply ramp to

power supplies stable

RESET# LOW to power supplies

stable

RESET# LOW to I/O and RTT

High-Z

Exit precharge power-down to

any non-READ command

CKE minimum high/low time

t

VDDPR

-

0

-

200

20

-

0

-

200

20

-

ms

ns

t_RPS

t_IOz

t_XP

max

3nCK,6ns

max

3nCK,6ns

t_CK

max

3nCK,

5ns

max

3nCK,

5.625ns

t_CKE

-

t_CK

Temperature Sensor with Serial Presence-Detect EEPROM

SCL

SDA

WP/EVENT

EVENT

R1

0Ω

SA0

SA1

SA2

SA1

Temperature Sensor with Serial Presence-Detect EEPROM Operating Conditions

Parameter / Condition

Supply voltage

Symbol

V_DDSPD

I_DD

VIH

VIL

MIN

+3

MAX

+3.6

+2.0

V_DDSPD+1

550

Unit

V

mA

V

mV

µA

°C

Supply current: V_DD= 3.3V

Input high voltage: Logic 1; SCL, SDA

Input low voltage: Logic 0; SCL, SDA

Output low voltage: I_OUT= 2.1mA

Input current

+1.45

-

-5.0

T.B.D

VOL

IIN

400

5.0

Temperature sensing range

Temperature sensor accuracy

T.B.D

°C

Swissbit AG

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Page 11

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preliminary Data Sheet

Rev.0.9

07.06.2013

A.C. Characteristics of Temperature Sensor

V_CC= 3.3 V ± 10%, T_A= −40°C to +125°C

Symbol Parameter / Condition

MIN

10

MAX

Unit

kHz

ns

fSCL

tBUF

tF

SCL clock frequency

400

Bus Free Time Between STOP and START

SDA fall time

1300

300

ns

tR

SDA rise time

ns

Data hold time (accepted for Input Data)

Data Hold Time (guaranteed for Output Data)

Start condition hold time

0

ns

tHD:DAT

300

600

1300

100

600

25

900

ns

tH:STA

tHIGH

tLOW

ns

High Period of SCL

ns

Low Period of SCL

ns

tSU:DAT

tSU:STA

tSU:STO

tTIMEOUT

tI

Data setup time

ns

Start condition setup time

Stop condition setup time

ns

SMBus SCL Clock Low Timeout

Noise Pulse Filtered at SCL and SDA Inputs

Write Cycle Time

35

ms

ns

100

5

tWR

ms

tPU

Power-up Delay to Valid Temperature Recording

100

Temperature Characteristics of Temperature Sensor

V_CC= 3.3 V ± 10%, T_A= −40°C to +125°C

Parameter

Test Conditions/Comments

+75°C ≤ T_A≤ +95°C, active range

+40°C ≤ T_A≤ +125°C, monitor range

MAX

Unit

°C

Bits

°C

±1.0

±2.0

±3.0

12

0.0625

100

Temperature Reading Error

Class B, JC42.4 compliant

-40°C ≤ T_A≤ +125°C, sensing range

ADC Resolution

Temperature Resolution

Conversion Time

Ms

°C/W

Thermal Resistance¹θ_JA

Junction-to-Ambient (Still Air)

92

¹Power Dissipation is defined as P_J= (T_J− T_A)/θ_JA, where TJ is the junction temperature and TA is the ambient temperature. The thermal

resistance value refers to the case of a package being used on a standard 2-layer PCB.

Slave Address Bits of Temperature Sensor

Device

Device Type Identifier

Select Address Signals R/W#

b7¹

1

b6

0

b5

1

b4

0

b3

A₂

b2

A₁

b1

A₀

b0

EEPROM

R/W#

Temp. Sensor

0

1

¹The most significant bit, b7, is sent first.

Swissbit AG

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Page 12

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preliminary Data Sheet

Rev.0.9

07.06.2013

SERIAL PRESENCE-DETECT MATRIX

12800-CL11

10600-CL9

Byte

Byte Description

0

1

CRC RANGE, EEPROM BYTES, BYTES USED

SPD REVISON

0x92

0x11

0x0B

0x08

0x04

0x21

0x02

0x01

0x0B

0x11

0x01

0x08

2

DRAM DEVICE TYPE

3

MODULE TYPE (FORM FACTOR)

SDRAM DEVICE DENSITY & BANKS

SDRAM DEVICE ROW & COLUMN COUNT

MODULE NOMINAL VOLTAGE, V_DD

MODULE RANKS & DEVICE DQ COUNT

ECC TAG & MODULE MEMORY BUS WIDTH

FINE TIMEBASE DIVIDEND/DIVISOR

MEDIUM TIMEBASE DIVIDEND

4

5

6

7

8

9

10

11

12

13

14

15

16

17

18

19

20

21

22

23

24

25

26

MEDIUM TIMEBASE DIVISOR

MIN SDRAM CYCLE TIME (t_{CK MIN}

)

0x0A

0Xfe

0x0C

0x3E

BYTE 13 RESERVED

0x00

CAS LATENCIES SUPPORTED (CL4 => CL11)

CAS LATENCIES SUPPORTED (CL12 => CL18)

0x00

0x69

0x78

0x69

0x30

0x69

0x11

MIN CAS LATENCY TIME (t_{AA MIN}

MIN WRITE RECOVERY TIME (t_{WR MIN}

MIN RAS# TO CAS# DELAY (t_{RCD MIN}

MIN ROW ACTIVE TO ROW ACTIVE DELAY (t_{RRD MIN}

)

MIN ROW PRECHARGE DELAY (t_{RP MIN}

)

UPPER NIBBLE FOR t_RAS& t_RC

MIN ACTIVE TO PRECHARGE DELAY (t_{RAS MIN}

)

0x18

0x81

0x20

0x89

MIN ACTIVE TO ACTIVE/REFRESH DELAY (t_{RC MIN}

MIN REFRESH RECOVERY DELAY (t_{RFC MIN}) LSB

MIN REFRESH RECOVERY DELAY (t_{RFC MIN}) MSB

)

0x20

0x08

0x3C

MIN INTERNAL WRITE TO READ CMD DELAY (t_{WTR MIN}

)

MIN INTERNAL READ TO PRECHARGE CMD DELAY

27

0x3C

(t_{RTP MIN}

)

28

29

30

31

MIN FOUR ACTIVE WINDOW DELAY (t_{FAW MIN}) MSB

MIN FOUR ACTIVE WINDOW DELAY (t_{FAW MIN}) LSB

SDRAM DEVICE OUTPUT DRIVERS SUPPORTED

SDRAM DEVICE THERMAL & REFRESH OPTIONS

0x00

0xF0

0x83

0x01

Swissbit AG

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Page 13

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preliminary Data Sheet

Rev.0.9

07.06.2013

12800-CL11

10600-CL9

Byte

Byte Description

Module Thermal Sensor

32

33-59

60

0x80

0x00

0x0F

0x11

0x02

BYTES 32-59 RESERVED

MODULE HEIGHT (NOMINAL)

MODULE THICKNESS (MAX)

REFERENCE RAW CARD ID

61

62

63

64-116

117

ADDRESS MAPPING EDGE CONECTOR TO DRAM

BYTES 64-116 RESEVED

0x00

0x83

MODULE MFR ID (LSB)

118

MODULE MFR ID (MSB)

0xDA

0x01 (Switzerland)

0x02 (Germany)

0x03 (USA)

119

MODULE MFR LOCATION ID

120

121

MODULE MFR YEAR

MODULE MFR WEEK

X

122-125 MODULE SERIAL NUMBER

126-127 CRC

X

0x5D0E

0x5D09

128-145 MODULE PART NUMBER

"SLN04G72F1BB1SA-xx"

146

147

148

149

MODULE DIE REV

X

MODULE PCB REV

X

DRAM DEVICE MFR ID (LSB)

DRAM DEVICE MFR (MSB)

0x80

0xCE

0x00

0xFF

150-175 MFR RESERVED BYTES 150-175

176-255 CUSTOMER RESERVED BYTES 176-255

Part Number Code

S

1

L

2

N

3

04G 72 F1

B

7

B

8

1

9

SA

10

-

DC

11

*

12

R

13

**

14

4

5

6

*RoHs compl.

DDR3-1600MT/s

Swissbit AG

SDRAM DDR3L

204 Pin SO-DIMM

Capacity (4GByte)

Width (72bit)

PCB-Type (B83S781 1.00)

Chip Vendor (Samsung)

1 Module Rank

Chip Rev. B

Chip organisation x8

* optional / additional information

**T=Thermal Sensor

Swissbit AG

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Page 14

of 17

preliminary Data Sheet

Rev.0.9

07.06.2013

Revision History

Revision

0.9

Changes

Date

07.06.2013

preliminary Version

Swissbit AG

Industriestrasse 4

CH – 9552 Bronschhofen

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Page 15

of 17

preliminary Data Sheet

Rev.0.9

07.06.2013

Locations

Swissbit AG

Industriestrasse 4

CH – 9552 Bronschhofen

Switzerland

Phone:

Fax:

+41 (0)71 913 03 03

+41 (0)71 913 03 15

_____________________________

Swissbit Germany GmbH

Wolfener Strasse 36

D – 12681 Berlin

Germany

Phone:

Fax:

+49 (0)30 93 69 54 – 0

+49 (0)30 93 69 54 – 55

_____________________________

Swissbit NA, Inc.

1117 E Plaza Drive Unit E Suites 105/205

Eagle, ID 83616

USA

Phone:

Fax:

+1 208 258-6254

+1 208 938-4525

_____________________________

Swissbit Japan, Inc.

3F Core Koenji,

2-1-24 Koenji-Kita, Suginami-Ku,

Tokyo 166-0002

Japan

Phone:

Fax:

+81 3 5356 3511

+81 3 5356 3512

________________________________

Swissbit AG

Industriestrasse 4

CH – 9552 Bronschhofen

Fon: +41 (0) 71 913 03 03

Fax: +41 (0) 71 913 03 15

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eMail: info@swissbit.com

Page 16

of 17

preliminary Data Sheet

Rev.0.9

07.06.2013

Declaration of Conformity

We

Manufacturer:

Swissbit AG

Industriestrasse 4

CH-9552 Bronschhofen

Switzerland

declare under our sole responsibility that the product

Product Type:

Brand Name:

Product Series:

Part Number:

4GB DDR3L SO-UDIMM

SWISSMEMORY™

DDR3L SO-UDIMM

SLN04G72F1BB1SA-xxxRT

to which this declaration relates is in conformity with the following directives:

2002/96/EC Category 3 (WEEE)

following the provisions of Directive

Restriction of the use of certain hazardous substances 2011/65/EU

Swissbit AG, Juni 2013

Manuela Kögel

Head of Quality Management

Swissbit AG

Industriestrasse 4

CH – 9552 Bronschhofen

Fon: +41 (0) 71 913 03 03

Fax: +41 (0) 71 913 03 15

www.swissbit.com

eMail: info@swissbit.com

Page 17

of 17


型号：	SLN04G72F1BB1SA-CCRT
厂家：	ETC
描述：	4GB DDR3L â SDRAM ECC SO-UDIMM 动态存储器双倍数据速率
文件：	总17页 (文件大小：789K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

SLN04G72F1BB1SA-CCRT [ETC]

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