SLU08G72K1BD2SA-DCRT [ETC]
8192MB DDR3L â SDRAM ECC DIMM;
| 型号： | SLU08G72K1BD2SA-DCRT |
| 厂家： | 
ETC |
| 描述： | 8192MB DDR3L â SDRAM ECC DIMM 动态存储器 双倍数据速率 |
| 文件： | 总16页 (文件大小：729K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Data Sheet
Rev.1.0
17.02.2014
8192MB DDR3L – SDRAM ECC DIMM
240 Pin unbuffered ECC DIMM
SLU08G72K1BD2SA-xxRT
8GByte in FBGA Technology
RoHS compliant
Features:
.
240-pin 72-bit DDR3 Dual-In-Line Double Data Rate
Synchronous DRAM module with ECC
.
.
.
.
.
.
Module organization: dual rank 1G x 72
VDD
= 1.35V and 1.5V
VDDQ = 1.35V and 1.5V
1.5V I/O ( SSTL_15 compatible)
Supports ECC, error detection and correction
On-board I2C temperature sensor with integrated serial
presence-detect (SPD) EEPROM
Options:
.
Data Rate / Latency
DDR3 1333 MT/s CL9
DDR3 1600 MT/s CL11
Marking
-CC
(according to JEDEC JESD21C)
.
.
Finish Process: OSP with 30µ” AU on contact fingers
This module is fully pin and functional compatible to the
JEDEC PC3-12800 spec. and JEDEC- Standard MO-269.
(see www.jedec.org)
-DC
.
Module Density
8GByte with 18 dies and 2 ranks
.
The pcb and all components are manufactured according
to the RoHS compliance specification [EU Directive
2002/95/EC Restriction of Hazardous Substances (RoHS)]
.
Standard Grade
E-Grade
(TA)
(TC)
(TA)
(TC)
0°C to 70°C
0°C to 85°C
0°C to 85°C
0°C to 95°C *)
W-Grade
(TA) -40°C to 85°C
(TC) -40°C to 95°C *)
.
.
.
.
DDR3L - SDRAM component Samsung K4B4G0846D
512Mx8 DDR3 SDRAM in PG-TFBGA-78 package
8-bit pre-fetch architecture
The refresh rate has to be doubled when 85°C<TC<95°C
Programmable CAS Latency, CAS Write Latency, Additive
Latency, Burst Length and Burst Type.
Environmental Requirements:
.
On-Die-Termination (ODT) and Dynamic ODT for improved
signal integrity.
.
Operating temperature (ambient)
Standard Grade
E-Grade
W-Grade
Operating Humidity
10% to 90% relative humidity, noncondensing
Operating Pressure
105 to 69 kPa (up to 10000 ft.)
Storage Temperature
-55°C to 100°C
Storage Humidity
0°C to 70°C
0°C to 85°C
-40°C to 85°C
.
.
.
Refresh. Self Refresh and Power Down Modes.
ZQ Calibration for output driver and ODT.
.
.
.
.
.
System Level Timing Calibration Support via Write Leveling
and Multi Purpose Register (MPR) Read Pattern.
Figure: mechanical dimensions1
5% to 95% relative humidity, noncondensing
Storage Pressure
1682 PSI (up to 5000 ft.) at 50°C
1
if no tolerances specified ± 0.15mm
Swissbit AG
Industriestrasse 4
CH-9552 Bronschhofen
Fon: +41 (0) 71 913 03 03
Fax: +41 (0) 71 913 03 15
www.swissbit.com
eMail: info@swissbit.com
Page 1
of 16
Data Sheet
Rev.1.0
17.02.2014
This Swissbit module is an industry standard 240-pin 8-byte DDR3 SDRAM Dual-In-line Memory Module
(UDIMM) which is organized as x72 high speed CMOS memory arrays. The module uses internally configured
octal-bank DDR3 SDRAM devices. The module uses double data rate architecture to achieve high-speed
operation. DDR3 SDRAM modules operate from a differential clock (CK and CK#). READ and WRITE accesses
to a DDR3 SDRAM module is burst-oriented; accesses start at a selected location and continue for a
programmed number of locations in a programmed sequence. The burst length is either four or eight locations. An
auto precharge function can be enabled to provide a self-timed row precharge that is initiated at the end of a burst
access. The DDR3 SDRAM devices have a multibank architecture which allows a concurrent operation that is
providing a high effective bandwidth. A self refresh mode is provided and a power-saving “power-down” mode. All
inputs and all full drive-strength outputs are SSTL_15 compatible.
The module can operate either at DDR3 mode (1.50V VDD) or DDR3L mode (1.35V VDD)
The DDR3 SDRAM module uses the serial presence detect (SPD) function implemented via serial EEPROM
using the standard I2C protocol. This nonvolatile storage device contains 256 bytes. The first 128 bytes are
utilized by the DIMM manufacturer (Swissbit) to identify the module type, the module’s organization and several
timing parameters. The second 128 bytes are available to the end user.
Module Configuration
Row
Addr.
Device Bank
Addr.
Column
Addr.
Module
Bank Select
Organization
DDR3 SDRAMs used
Refresh
1G x 72bit
18 x 512M x 8bit (4Gbit)
16
BA0, BA1, BA2
10
8k
S0#, S1#
Module Dimensions
in mm
133.35 (long) x 18.75 (high) x 4.00 [max] (thickness)
Timing Parameters
Part Number
Module Density
Transfer Rate
Clock Cycle/Data bit rate
Latency
SLU08G72K1BD2SA-CCRT
8GByte
10.6 GB/s
1.5ns/1333MT/s
9-9-9
SLU08G72K1BD2SA-DCRT
8GByte
12.8 GB/s
1.25ns/1600MT/s
11-11-11
Pin Name
A0 – A9, A11 – A15
A10/AP
Address Inputs
Address Input / Autoprecharge Bit
Address Input / Burst chop
Bank Address Inputs
Data Input / Output
A12/BC#
BA0 – BA2
DQ0 – DQ63
CB0 – CB7
DM0 – DM8
DQS0 – DQS8
DQS0# - DQS8#
RAS#
ECC check bits
Input Data Mask
Data Strobe, positive line
Data Strobe, negative line (only used when differential data strobe mode is enabled)
Row Address Strobe
Column Address Strobe
Write Enable
CAS#
WE#
CKE0 – CKE1
S0#, S1#
Clock Enable
Chip Select
CK0 – CK1
Clock inputs, positive line
Swissbit AG
Industriestrasse 4
CH-9552 Bronschhofen
Fon: +41 (0) 71 913 03 03
Fax: +41 (0) 71 913 03 15
www.swissbit.com
eMail: info@swissbit.com
Page 2
of 16
Data Sheet
Rev.1.0
17.02.2014
CK0# – CK1#
Event#
VDD
Clock inputs, negative line
Temperature event: The EVENT# pin is asserted by the temperature sensor when critical
Supply Voltage (1.35V -0.067V/+0.1V and 1.5V ± 0.075V)
Reference voltage: DQ, DM (VDD/2)
VREFDQ
VREFCA
VSS
Reference voltage: Control, command, and address (VDD/2)
Ground
VTT
Termination voltage: Used for control, command, and address (VDD/2).
Serial EEPROM Positive Power Supply
Serial Clock for Presence Detect
VDDSPD
SCL
SDA
Serial Data Out for Presence Detect
SA0 – SA2
ODT0, ODT1
NC
Presence Detect Address Inputs
On-Die Termination
No Connection
Pin Configuration
Frontside
PIN
1
Symbol
VREFDQ
VSS
PIN
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
Symbol
DQ18
DQ19
VSS
PIN
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
Symbol
NC(VTT)
CKE0
VDD
PIN
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
Symbol
VDD
PIN
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
Symbol
VSS
2
S1#
DQS6#
DQS6
VSS
3
DQ0
ODT1
VDD
4
DQ1
DQ24
DQ25
VSS
BA2
5
VSS
NC(Err_Out#)
VDD
NC(S2#)
VSS
DQ50
DQ51
VSS
6
DQS0#
DQS0
VSS
7
DQS3#
DQS3
VSS
A11
DQ32
DQ33
VSS
8
A7
DQ56
DQ57
VSS
9
DQ2
VDD
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
DQ3
DQ26
DQ27
VSS
A5
DQS4#
DQS4
VSS
VSS
A4
DQS7#
DQS7
VSS
DQ8
VDD
DQ9
CB0
A2
DQ34
DQ35
VSS
VSS
CB1
VDD
DQ58
DQ59
VSS
DQS1#
DQS1
VSS
VSS
CK1
DQS8#
DQS8
VSS
CK1#
VDD
DQ40
DQ41
VSS
SA0
DQ10
DQ11
VSS
VDD
SCL
CB2
VREFCA
NC(Par_In)
VDD
DQS5#
DQS5
VSS
SA2
CB3
VTT
DQ16
DQ17
VSS
VSS
NC(VTT)
A10/ AP
BA0
DQ42
DQ43
VSS
DQS2#
DQS2
VSS
VDD
WE#
CAS#
DQ48
DQ49
Signals in brackets (…) may be connected at the DIMM socket, but are not used on the DIMM
Swissbit AG
Industriestrasse 4
CH-9552 Bronschhofen
Fon: +41 (0) 71 913 03 03
Fax: +41 (0) 71 913 03 15
www.swissbit.com
eMail: info@swissbit.com
Page 3
of 16
Data Sheet
Backside
Rev.1.0
17.02.2014
Pin
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
Symbol
VSS
Pin
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
Symbol
DQ23
Pin
169
170
171
172
173
174
175
176
177
178
179
180
181
182
183
184
185
186
187
188
189
190
191
192
193
194
Symbol
Pin
195
196
197
198
199
200
201
202
Symbol
Pin
221
222
223
224
225
226
227
228
229
230
231
232
233
234
235
236
237
238
239
240
Symbol
DM6(DQS15)
NC(DQS15#)
VSS
CKE1
VDD
ODT0
A13
DQ4
VSS
DQ5
DQ28
A15)
A14
VDD
VDD
VSS
DQ29
NC(S3#)
VSS
DQ54
DM0(DQS9)
NC(DQS9#)
VSS
VSS
DQ55
DM3(DQS12)
NC(DQS12#)
VSS
A12, BC#
A9
DQ36
DQ37
VSS
VSS
DQ60
DQ6
VDD
DQ61
DQ7
DQ30
A8
203 DM4(DQS13)
VSS
VSS
DQ31
A6
204
205
206
207
208
209
210
211
NC(DQS13#)
VSS
DM7(DQS16)
NC(DQS16#)
VSS
DQ12
VSS
VDD
DQ13
CB4
A3
DQ38
DQ39
VSS
VSS
CB5
A1
DQ62
DM1(DQS10)
NC(DQS10#)
VSS
VSS
VDD
DQ63
DM8(DQS17)
NC(DQS17#)
VSS
VDD
DQ44
DQ45
VSS
VSS
CK0
CK0#
VDD
VDDSPD
SA1
DQ14
DQ15
CB6
212 DM5(DQS14)
SDA
VSS
CB7
EVENT#
A0
213
214
215
216
217
218
219
220
NC(DQS14#)
VSS
VSS
DQ20
VSS
VTT
DQ21
NC(TEST)
RESET#
VDD
DQ46
DQ47
VSS
VSS
BA1
VDD
DM2(DQS11)
NC(DQS11#)
VSS
RAS#
S0#
VDD
DQ52
DQ53
VSS
DQ22
Signals in brackets (…) may be connected at the DIMM socket, but are not used on the DIMM
Swissbit AG
Industriestrasse 4
CH-9552 Bronschhofen
Fon: +41 (0) 71 913 03 03
Fax: +41 (0) 71 913 03 15
www.swissbit.com
eMail: info@swissbit.com
Page 4
of 16
Data Sheet
Rev.1.0
17.02.2014
FUNCTIONAL BLOCK DIAGRAMM 8192MB DDR3 SDRAM DIMM,
2 RANKS AND 18 COMPONENTS
S1
S0
DQS4
DQS4
DQS0
DQS0
DM4
DM0
DM CS
DQS DQS
DM CS
DQS DQS
DM CS
DQS DQS
DM CS
DQS DQS
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
DQ32
DQ33
DQ34
DQ35
DQ36
DQ37
DQ38
DQ39
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
D13
D9
D4
D0
ZQ
ZQ
ZQ
ZQ
DQS5
DQS5
DQS1
DQS1
DM5
DM1
DM CS
DQS DQS
DM CS
DQS DQS
DM CS
DQS DQS
DM CS
DQS DQS
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
DQ40
DQ41
DQ42
DQ43
DQ44
DQ45
DQ46
DQ47
DQ8
DQ9
D5
D14
D10
D1
DQ10
DQ11
DQ12
DQ13
DQ14
DQ15
ZQ
ZQ
ZQ
ZQ
DQS6
DQS6
DQS2
DQS2
DM6
DM2
DM CS
DQS DQS
DM CS
DQS DQS
DM CS
DQS DQS
DM CS
DQS DQS
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
DQ48
DQ49
DQ50
DQ51
DQ52
DQ53
DQ54
DQ55
DQ16
DQ17
DQ18
DQ19
DQ20
DQ21
DQ22
DQ23
D15
D6
D11
D2
ZQ
ZQ
ZQ
ZQ
DQS7
DQS7
DQS3
DQS3
DM7
DM3
DM CS
DQS DQS
DM CS
DQS DQS
DM CS
DQS DQS
DM CS
DQS DQS
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
DQ56
DQ57
DQ58
DQ59
DQ60
DQ61
DQ62
DQ63
DQ24
DQ25
DQ26
DQ27
DQ28
DQ29
DQ30
DQ31
D7
D16
D12
D3
ZQ
ZQ
ZQ
ZQ
DQS8
DQS8
DM8
VDDSPD
VDD/VDDQ
SPD
DM CS
DQS DQS
DM CS
DQS DQS
D0-D17
D0-D17
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
CB0
CB1
CB2
CB3
CB4
CB5
CB6
CB7
D17
D8
VREFDQ
VREFCA
VSS
D0-D17
D0-D17
ZQ
ZQ
BA0-BA2
A0-A15
BA0-BA2: SDRAM D0-D17
A0-A15: SDRAM D0-D17
Notes:
1. DQ-to-I/O wiring is shown as recommended but may
be changed.
2. DQ/DQS/DQS/ODT/DM/CKE/S relationship must be
maintained as shown.
3. DQ, DM, DQS/DQS resistors: Refer to associated
topology diagram.
RAS
CAS
WE
ODT0
ODT1
RAS: SDRAM D0-D17
CAS: SDRAM D0-D17
WE: SDRAM D0-D17
ODT: SDRAM D0-D8
ODT: SDRAM D9-D17
4. Refer to the appropriate clock wiring topology under
the DIMM wiring details section of the JEDED document.
5. For each DRAM, a unique ZQ resistor is connected to
GND. The ZQ resistor is 240O±1%.
CKE0
CKE1
CK0,CK1
CK0,CK1
RESET
CKE: SDRAM D0-D8
CKE: SDRAM D9-D17
CK: SDRAM D0-D17
CK: SDRAM D0-D17
RESET: SDRAM D0-D17
6. Refer to associated figure for SPD details.
Swissbit AG
Industriestrasse 4
CH-9552 Bronschhofen
Fon: +41 (0) 71 913 03 03
Fax: +41 (0) 71 913 03 15
www.swissbit.com
eMail: info@swissbit.com
Page 5
of 16
Data Sheet
Rev.1.0
17.02.2014
MAXIMUM ELECTRICAL DC CHARACTERISTICS
PARAMETER/ CONDITION
SYMBOL
VDD
VDDQ
VIN, VOUT
MIN
-0.4
-0.4
-0.4
MAX
UNITS
VDD Supply Voltage relative to VSS
I/O VDD Supply Voltage relative to VSS
Voltage on any pin relative to VSS
1.975
1.975
1.975
V
V
V
INPUT LEAKAGE CURRENT
Any input 0V ≤ VIN ≤ VDD, VREF pin 0V ≤ VIN ≤ 0.95V
(All other pins not under test = 0V)
II
µA
Command/Address
RAS#, CAS#, WE#, S#, CKE
-16
16
CK, CK#
DM
-16
-2
16
2
OUTPUT LEAKAGE CURRENT
(DQ’s and ODT are disabled; 0V ≤ VOUT ≤ VDDQ
IOZ
-5
5
µA
µA
)
DQ, DQS, DQS#
VREF LEAKAGE CURRENT ; VREF is on a valid level
IVREF
-8
8
DDR3L (1.35V) DC OPERATING CONDITIONS
PARAMETER/ CONDITION
PARAMETER/ CONDITION
Supply Voltage
I/O Supply Voltage
I/O Reference Voltage
SYMBOL
SYMBOL
VDD
VDDQ
VREF
VTT
VIH (DC90)
MIN
MIN
1.283
1.283
NOM
NOM
1.35
MAX
MAX
1.450
UNITS
UNITS
V
V
V
V
V
1.35
0.50 x VDDQ
0.50 x VDDQ
1.450
0.49 x VDDQ
0.49 x VDDQ-20mV
VREF + 90mV
0.51x VDDQ
0.51x VDDQ+20mV
VDDQ + 0.3
I/O Termination Voltage (system)
Input High (Logic 1) Voltage
DDR3 (1.50V) DC OPERATING CONDITIONS
PARAMETER/ CONDITION
Supply Voltage
I/O Supply Voltage
SYMBOL
VDD
MIN
1.425
1.425
NOM
1.5
1.5
MAX
1.575
1.575
UNITS
V
V
V
V
V
V
VDDQ
VREF
VTT
VIH (DC)
VIL (DC)
I/O Reference Voltage
0.49 x VDDQ
0.49 x VDDQ-20mV
VREF + 0.1
-0.3
0.50 x VDDQ
0.50 x VDDQ
0.51x VDDQ
0.51x VDDQ+20mV
VDDQ + 0.3
VREF – 0.1
I/O Termination Voltage (system)
Input High (Logic 1) Voltage
Input Low (Logic 0) Voltage
AC INPUT OPERATING CONDITIONS
PARAMETER/ CONDITION
Input High (Logic 1) Voltage
Input Low (Logic 0) Voltage
SYMBOL
VIH (AC)
VIL (AC)
MIN
VREF + 0.175
-
MAX
-
VREF - 0.175
UNITS
V
V
CAPACITANCE
At DDR3 data rates, it is recommended to simulate the performance of the module to achieve optimum values.
When inductance and delay parameters associated with trace lengths are used in simulations, they are
significantly more accurate and realistic than a gross estimation of module capacitance. Simulations can then
render a considerably more accurate result. JEDEC modules are now designed by using simulations to close
timing budgets.
Swissbit AG
Industriestrasse 4
CH-9552 Bronschhofen
Fon: +41 (0) 71 913 03 03
Fax: +41 (0) 71 913 03 15
www.swissbit.com
eMail: info@swissbit.com
Page 6
of 16
Data Sheet
Rev.1.0
17.02.2014
IDD Specifications and Conditions
(0°C ≤ TCASE ≤ + 85°C°, VDDQ = +1.35V, VDD = +1.35V)
Parameter
& Test Condition
max.
12800 CL11 10600 CL9
Symbol
Unit
OPERATING CURRENT *) :
One device bank Active-Precharge;
mA
IDD0
324
315
tRC= tRC (IDD); tCK = tCK (IDD); CKE is HIGH, CS# is HIGH
between valid commands;
DQ inputs changing once per clock cycle; Address and
control inputs changing once every two clock cycles
OPERATING CURRENT *) :
mA
IDD1
414
396
One device bank; Active-Read-Precharge;
IOUT = 0mA; BL = 4, CL = CL (IDD), AL = 0;
tCK = tCK (IDD), tRC= tRC (IDD), tRAS = tRAS MIN (IDD),
tRCD = tRCD (IDD); CKE is HIGH, CS# is HIGH between
valid commands; Address inputs changing once every
two clock cycles; Data Pattern is same as IDD4W
Fast Exit
PRECHARGE POWER-DOWN CURRENT:
All device banks idle; Power-down mode;
tCK = tCK (IDD); CKE is LOW; All Control and
Address bus inputs are not changing; DQ’s
are floating at VREF
mA
IDD2P
144
144
180
144
144
180
Slow Exit
PRECHARGE QUIET STANDBY CURRENT:
All device banks idle;
mA
mA
IDD2Q
tCK = tCK (IDD); CKE is HIGH, CS# is HIGH;
All Control and Address bus inputs are not changing;
DQ’s are floating at VREF
PRECHARGE STANDBY CURRENT:
All device banks idle;
IDD2N
198
198
tCK = tCK (IDD); CKE is HIGH, CS# is HIGH;
All other Control and Address bus inputs are changing
once every two clock cycles; DQ inputs changing once
per clock cycle
ACTIVE POWER-DOWN CURRENT:
mA
mA
IDD3P
198
378
198
360
All device banks open; tCK = tCK (IDD); CKE is LOW; All
Control and Address bus inputs are not changing; DQ’s
are floating at VREF (always fast exit)
ACTIVE STANDBY CURRENT:
All device banks open; tCK = tCK (IDD),
IDD3N
tRAS = tRAS MAX (IDD), tRP = tRP (IDD);
CKE is HIGH, CS# is HIGH between valid commands;
All other Control and Address bus inputs are changing
once every two clock cycles; DQ inputs changing once
per clock cycle
OPERATING READ CURRENT:
mA
IDD4R
684
603
All device banks open, Continuous burst reads; One
module rank active; IOUT = 0mA; BL = 4, CL = CL (IDD), AL
= 0; tCK = tCK (IDD), tRAS = tRAS MAX (IDD), tRP = tRP (IDD);
CKE is HIGH, CS# is HIGH between valid commands;
Address bus inputs are changing once every two clock
cycles; DQ inputs changing once per clock cycle
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Data Sheet
Rev.1.0
17.02.2014
Parameter
& Test Condition
max.
12800 CL11 10600 CL9
Symbol
IDD4W
Unit
OPERATING WRITE CURRENT:
mA
mA
684
603
All device banks open, Continuous burst writes; One
module rank active; BL = 4, CL = CL (IDD), AL = 0;
tCK = tCK (IDD), tRAS = tRAS MAX (IDD), tRP = tRP (IDD);
CKE is HIGH, CS# is HIGH between valid commands;
Address bus inputs are changing once every two clock
cycles; DQ inputs changing once per clock cycle
BURST REFRESH CURRENT:
IDD5
1782
1782
tCK = tCK (IDD); refresh command at every tRFC (IDD) interval,
CKE is HIGH, CS# is HIGH between valid commands; All
other Control and Address bus inputs are changing once
every two clock cycles; DQ inputs changing once per
clock cycle
SELF REFRESH CURRENT:
mA
mA
IDD6
216
216
CK and CK# at 0V; CKE ≤ 0.2V; All other Control and
Address bus inputs are floating at VREF; DQ’s are floating
at VREF
OPERATING CURRENT*) :
IDD7
1206
1179
Four device bank interleaving READs, IOUT = 0mA; BL = 4, CL
= CL (IDD), AL = tRCD (IDD) – 1 x tCK (IDD); tCK = tCK (IDD), tRC
= tRC (IDD), tRRD = tRRD (IDD), tRCD = tRCD (IDD);
CKE is HIGH, CS# is HIGH between valid commands;
Address bus inputs are not changing during DESELECT;
DQ inputs changing once per clock cycle
*) Value calculated as one module rank in this operating condition, and all other module ranks in IDD2P (CKE LOW)
mode.
TIMING VALUES USED FOR IDD MEASUREMENT
IDD MEASUREMENT CONDITIONS
SYMBOL
CL (IDD
tRCD (IDD
tRC (IDD
tRRD (IDD
tCK (IDD
tRAS MIN (IDD
tRAS MAX (IDD
tRP (IDD
tRFC (IDD
12800 CL11
11
10600 CL9
9
Unit
tCK
ns
ns
ns
ns
ns
ns
ns
tCK
)
13.75
48.75
6.25
1.25
35
70’200
13.75
260
13.5
49.5
6
1.5
36
70’200
13.5
260
)
)
)
)
)
)
)
)
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Page 8
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Data Sheet
Rev.1.0
17.02.2014
DDR3 SDRAM COMPONENT ELECTRICAL CHARACTERISTICS AND RECOMMENDED
AC OPERATING CONDITIONS
(0°C ≤ TCASE ≤ + 85°C; VDDQ = +1.5V ± 0.075V, VDD = +1.5V ± 0.075V)
AC CHARACTERISTICS
PARAMETER
12800 CL11
10600 CL9
SYMBOL
tCK (11)
tCK (10)
tCK (9)
tCK (8)
tCK (7)
tCK (6)
tCK (5)
tAA
MIN
MAX
MIN
MAX
Unit
ns
ns
ns
ns
ns
ns
ns
ns
Clock cycle time
CL = 11
1.25
1.5
1.5
1.875
1.875
2.5
1.5
-
-
CL = 10
CL = 9
CL = 8
CL = 7
CL = 6
CL = 5
<1.875
<1.875
<2.5
<2.5
3.3
1.5
1.5
1.875
1.875
2.5
<1.875
<1.875
<2.5
<2.5
3.3
3.0
3.3
3.0
3.3
Read CMD to 1st data
CK high-level width
CK low-level width
13.75
0.47
0.47
-
13.5
0.47
0.47
-
0.53
0.53
0.53
0.53
tCK
tCK
tCH (avg)
tCL (avg)
Data-out high-impedance
window from CK/CK#
Data-out low-impedance window
from CK/CK#
DQ and DM input pulse width
( for each input )
DQ-DQS hold, DQS to first DQ
to go non-valid, per access
DQS input high pulse width
DQS input low pulse width
DQS read preamble
DQS read postamble
DQS write preamble
tHZ
-
225
-
250
ps
ps
ps
tLZ
-450
360
0.38
225
-500
400
0.38
250
tDIPW
tQH
-
-
-
-
tCK
(AVG)
tCK
tCK
tCK
tCK
tCK
tCK
0.45
0.45
0.9
0.3
0.9
0.55
0.55
Note1
Note2
-
0.45
0.45
0.9
0.3
0.9
0.55
0.55
Note1
Note2
-
tDQSH
tDQSL
tRPRE
tRPST
tWPRE
tWPST
DQS write postamble
0.3
-
0.3
-
1
The maximum preamble is bound by tLZDQS (MAX)
The maximum postamble is bound by tHZDQS (MAX)
2
The DQ, DQS setup and hold times as well as Command/Address setup and hold times need to be calculated using the
respective component data sheets with derating tables and the driver slew rate in combination with the JEDEC min/max
routing information
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Page 9
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Data Sheet
Rev.1.0
17.02.2014
DDR3 SDRAM COMPONENT ELECTRICAL CHARACTERISTICS AND RECOMMENDED
AC OPERATING CONDITIONS (Continued)
(0°C ≤ TCASE ≤ + 85°C; VDDQ = +1.5V ± 0.075V, VDD = +1.5V ± 0.075V)
AC CHARACTERISTICS
PARAMETER
12800 CL11
MIN MAX
10600 CL9
SYMBOL
MIN
MAX
Unit
CAS# to CAS# command delay
-
-
4
4
tCK
tCCD
ACTIVE to ACTIVE (same bank)
command period
ACTIVE bank a to ACTIVE bank
b command
ACTIVE to READ or WRITE
delay
-
-
48.75
49.5
ns
ns
ns
ns
ns
tRC
max
4nCK,6ns
max
4nCK,6ns
-
-
tRRD
tRCD
tFAW
tRAS
-
-
13.75
13.5
Four bank
Activate period
1K Page size
2K Page size
30
40
-
-
30
45
-
-
ACTIVE to PRECHARGE
command
35
70’200
36
70’200
Internal READ to precharge
command delay
Write recovery time
Auto precharge write recovery +
precharge time
max
max
-
-
-
-
-
-
ns
ns
ns
tRTP
tWR
tDAL
4nCK,7.5ns
4nCK,7.5ns
15
15
tWR +
tRP/tCK
tWR
+
tRP/tCK
Internal WRITE to READ
command delay
PRECHARGE command period
LOAD MODE command cycle
time
max
max
-
-
-
-
-
-
ns
ns
tCK
tWTR
tRP
4nCK,7.5ns
4nCK,7.5ns
13.75
4
13.5
4
tMRD
REFRESH to ACTIVE or
REFRESH to REFRESH
command interval
Average periodic refresh interval
0 °C ≤ TCASE ≤ 85°C
260
70’200
260
70’200
ns
µs
tRFC
-
-
7.8
3.9
225
-
-
7.8
3.9
250
tREFI
tREFI (IT)
tAON
85 °C < TCASE ≤ 95°C
RTT turn-on from ODTL on
reference
RTT turn-on from ODTL off
reference
Asynchronous RTT turn-on
delay (power Down with DLL off)
Asynchronous RTT turn-off
delay (power Down with DLL off)
RTT dynamic change skew
First DQS, DQS# rising edge
DQS, DQS# delay
-225
-250
ps
tCK
ns
ns
0.3
2
0.7
8,5
8,5
0.3
2
0.7
8,5
8,5
tAOF
tAONPD
tAOFPD
2
2
0.3
40
25
0.7
-
-
0.3
40
25
0.7
-
-
tCK
tCK
tCK
tADC
tWLMRD
tWLDQSEN
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Page 10
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Data Sheet
Rev.1.0
17.02.2014
DDR3 SDRAM COMPONENT ELECTRICAL CHARACTERISTICS AND RECOMMENDED
AC OPERATING CONDITIONS (Continued)
(0°C ≤ TCASE ≤ + 85°C; VDDQ = +1.5V ± 0.075V, VDD = +1.5V ± 0.075V)
AC CHARACTERISTICS
PARAMETER
12800 CL11
10600 CL9
SYMBOL
MIN
MAX
MIN
MAX Unit
Exit reset from CKE HIGH to a
valid command
max
max
tXPR
-
-
tCK
5nCK,
5nCK,
tRFC + 10ns
tRFC + 10ns
Begin power supply ramp to
power supplies stable
RESET# LOW to power supplies
stable
RESET# LOW to I/O and RTT
High-Z
Exit precharge power-down to
any non-READ command
CKE minimum high/low time
t
VDDPR
-
0
-
200
200
20
-
-
-
-
200
200
20
-
ms
ms
ns
tRPS
tIOz
tXP
max
3nCK,6ns
max
3nCK,6ns
tCK
max
3nCK,
5ns
max
3nCK,
5.625ns
tCKE
-
-
tCK
Temperature Sensor with Serial Presence-Detect EEPROM
SCL
SDA
WP/EVENT
EVENT
R1
0Ω
SA0
SA0
SA1
SA2
SA2
SA1
Temperature Sensor with Serial Presence-Detect EEPROM Operating Conditions
Parameter / Condition
Supply voltage
Symbol
VDDSPD
IDD
VIH
VIL
MIN
+3
MAX
+3.6
+2.0
VDDSPD +1
550
Unit
V
mA
V
mV
mV
µA
°C
Supply current: VDD = 3.3V
Input high voltage: Logic 1; SCL, SDA
Input low voltage: Logic 0; SCL, SDA
Output low voltage: IOUT = 2.1mA
Input current
+1.45
-
-
-5.0
T.B.D
T.B.D
VOL
IIN
400
5.0
Temperature sensing range
Temperature sensor accuracy
T.B.D
T.B.D
°C
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Page 11
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Data Sheet
Rev.1.0
17.02.2014
SERIAL PRESENCE-DETECT MATRIX
Byte
Byte Description
12800 CL11
10600 CL9
0
CRC RANGE, EEPROM BYTES, BYTES USED
SPD REVISON
0x92
0x12
0x0B
0x02
0x04
0x21
0x02
0x09
0x0B
0x11
0x01
0x08
1
2
DRAM DEVICE TYPE
3
MODULE TYPE (FORM FACTOR)
SDRAM DEVICE DENSITY & BANKS
SDRAM DEVICE ROW & COLUMN COUNT
BYTE 6 RESERVED
4
5
6
7
MODULE RANKS & DEVICE DQ COUNT
ECC TAG & MODULE MEMORY BUS WIDTH
FINE TIMEBASE DIVIDEND/DIVISOR
MEDIUM TIMEBASE DIVIDEND
MEDIUM TIMEBASE DIVISOR
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
MIN SDRAM CYCLE TIME (tCK MIN
BYTE 13 RESERVED
)
0x0A
0xFE
0x0C
0x3E
0x00
CAS LATENCIES SUPPORTED (CL4 => CL11)
CAS LATENCIES SUPPORTED (CL12 => CL18)
0x00
0x69
0x78
0x69
0x30
0x69
0x11
MIN CAS LATENCY TIME (tAA MIN
MIN WRITE RECOVERY TIME (tWR MIN
MIN RAS# TO CAS# DELAY (tRCD MIN
MIN ROW ACTIVE TO ROW ACTIVE DELAY (tRRD MIN
)
)
)
)
MIN ROW PRECHARGE DELAY (tRP MIN
)
UPPER NIBBLE FOR tRAS & tRC
MIN ACTIVE TO PRECHARGE DELAY (tRAS MIN
)
0x18
0x81
0x20
0x89
MIN ACTIVE TO ACTIVE/REFRESH DELAY (tRC MIN
MIN REFRESH RECOVERY DELAY (tRFC MIN) LSB
MIN REFRESH RECOVERY DELAY (tRFC MIN) MSB
)
0x20
0x08
0x3C
0x3C
0x00
0xF0
0x83
0x01
MIN INTERNAL WRITE TO READ CMD DELAY (tWTR MIN
)
MIN INTERNAL READ TO PRECHARGE CMD DELAY (tRTP MIN
MIN FOUR ACTIVE WINDOW DELAY (tFAW MIN) MSB
MIN FOUR ACTIVE WINDOW DELAY (tFAW MIN) LSB
SDRAM DEVICE OUTPUT DRIVERS SUPPORTED
SDRAM DEVICE THERMAL & REFRESH OPTIONS
)
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Page 12
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Data Sheet
Rev.1.0
17.02.2014
Byte
Byte Description
12800 CL11
10600 CL9
32
33-59
60
DDR3-MODULE THERMAL SENSOR
BYTES 32-59 RESERVED
0x80
0x00
0x03
0x11
0x09
MODULE HEIGHT (NOMINAL)
MODULE THICKNESS (MAX)
REFERENCE RAW CARD ID (RC K1)
61
62
63
64-116
117
ADDRESS MAPPING EDGE CONECTOR TO DRAM
BYTES 64-116 RESEVED
0x01
0x00
0x83
MODULE MFR ID (LSB)
118
MODULE MFR ID (MSB)
0xDA
0x01 (Switzerland)
0x02 (Germany)
0x03 (USA)
119
MODULE MFR LOCATION ID
120
121
MODULE MFR YEAR
MODULE MFR WEEK
X
X
122-125 MODULE SERIAL NUMBER
126-127 CRC
X
0xD1FB
0xE524
128-145 MODULE PART NUMBER
"SLU08G72K1BD2SA-xx"
146
147
148
149
MODULE DIE REV
X
MODULE PCB REV
X
DRAM DEVICE MFR ID (LSB)
DRAM DEVICE MFR (MSB)
0x80
0xCE
0xFF
0xFF
150-175 MFR RESERVED BYTES 150-175
176-255 CUSTOMER RESERVED BYTES 176-255
Part Number Code
S
1
L
2
U
3
08G 72 K1
B
7
D
8
2
9
SA
10
-
DC
11
*
12
R
13
**
14
4
5
6
*RoHs compl.
DDR3-1600MT/s
Swissbit AG
SDRAM DDR3L
240 Pin UDIMM
capacity (8GByte)
Width (72bit)
PCB-Type (D3U28K)
Chip Vendor (Samsung)
2 Module Ranks
Chip Rev. D
Chip organisation x8
* optional / additional information
** Thermal Sensor
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Page 13
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Data Sheet
Rev.1.0
17.02.2014
Revision History
Revision
1.0
Changes
Date
17.02.2014
First release
Swissbit AG
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Page 14
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Data Sheet
Rev.1.0
17.02.2014
Locations
Swissbit AG
Industriestrasse 4
CH – 9552 Bronschhofen
Switzerland
Phone:
Fax:
+41 (0)71 913 03 03
+41 (0)71 913 03 15
_____________________________
Swissbit Germany GmbH
Wolfener Strasse 36
D – 12681 Berlin
Germany
Phone:
Fax:
+49 (0)30 93 69 54 – 0
+49 (0)30 93 69 54 – 55
_____________________________
Swissbit NA, Inc.
1117 E Plaza Drive Unit E Suites 105/205
Eagle, ID 83616
USA
Phone:
Fax:
+1 208 258-6254
+1 208 938-4525
_____________________________
Swissbit Japan, Inc.
3F Core Koenji,
2-1-24 Koenji-Kita, Suginami-Ku,
Tokyo 166-0002
Japan
Phone:
Fax:
+81 3 5356 3511
+81 3 5356 3512
________________________________
Swissbit AG
Industriestrasse 4
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Page 15
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Data Sheet
Rev.1.0
17.02.2014
Declaration of Conformity
We
Manufacturer:
Swissbit AG
Industriestrasse 4
CH-9552 Bronschhofen
Switzerland
declare under our sole responsibility that the product
Product Type:
Brand Name:
Product Series:
Part Number:
8GB DDR3L ECC UDIMM
SWISSMEMORY™
DDR3L UDIMM
SLU08G72K1BD2SA-xxxRT
to which this declaration relates is in conformity with the following directives:
2002/96/EC Category 3 (WEEE)
following the provisions of Directive
Restriction of the use of certain hazardous substances 2011/65/EU
Swissbit AG, February 2014
Manuela Kögel
Head of Quality Management
Swissbit AG
Industriestrasse 4
CH-9552 Bronschhofen
Fon: +41 (0) 71 913 03 03
Fax: +41 (0) 71 913 03 15
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eMail: info@swissbit.com
Page 16
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