SM2964C16 [ETC]
8-Bit Micro-controller; 8位微控制器
| 型号： | SM2964C16 |
| 厂家： | 
ETC |
| 描述： | 8-Bit Micro-controller |
| 文件： | 总15页 (文件大小：368K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
SyncMOS Technologies Inc.
SM2964
8 - Bit Micro-controller
December 1998
with 64KB flash embedded
Product List
Features
SM2964C16, 16 MHz 64KB internal flash MCU
SM2964C25, 25 MHz 64KB internal flash MCU
SM2964C40, 40 MHz 64KB internal flash MCU
Working voltage:4.5V through 5.5V
General 8051 family compatible
12 clocks per machine cycle
64K byte internal flash memory
Description
256 byte data RAM
The SM2964 series product is an 8 - bit single
chip micro controller with 64KB flash embedded.It
provides hardware features and a powerful instruction
set, necessary to make it a versatile and cost effective
controller for those applications demand up to 32 I/O
pins or need up to 64 K byte memory either for program
or for data or mixed.
Three 16 bit Timers/Counters
Four 8-bit I/O ports
Full duplex serial channel
Bit operation instructions
Page free jumps
8-bit Unsigned Division
8-bit Unsigned Multiply
BCD arithmetic
To program the flash block, a commercial programmer
is capable to do it.
Ordering Information
Direct Addressing
Indirect Addressing
yyww
SM2964ihhk
Nested Interrupt
Two priority level interrupt
A serial I/O port
yy: year, ww:week
v: version identifier { , A, B, ...}
i: process identifier {C}
hh: working clock in MHz {16, 25, 40}
k: package type postfix {as below table}
Power save modes:
Idle mode and Power down mode
Code protection function
Pin/Pad
Logo Size at
Postfix
Package
Configuration Dimension Top Marking
P
J
Q
U
40L PDIP
44L PLCC
44L PQFP
44L LQFP
page 2
page 2
page 2
page 2
page 11
page 12
5.0 x 4.2 mm
4.5 x 3.8 mm
2.8 x 2.4 mm
2.8 x 2.4 mm
-
-
Taiwan
4F, No.1 Creation Road 1,
Science-Based Industrial Park,
Hsinchu, Taiwan 30077
TEL: 886-3-578-3344
FAX: 886-3-579-2960
886-3-578-0493
Specifications subject to change without notice,contact your sales representatives for the most recent information.
1/15
Ver1.0 PID 2964 08/00
SyncMOS Technologies Inc.
SM2964
December 1998
Pin Configurations
44 43 42 41 40 39 38 37 36 35 34
33
P1.5/FD5
1
2
P0.4/FA4
1
44 43 42 41 40
39
3
2
6
5
4
P1.6/FD6
P1.5/FD7
32
P0.5/FA5
P0.6/FA6
P0.7/FA7
#EA
NC
ALE/#FCE
P0.4/FA4
P0.5/FA5
P0.6/FA6
P0.7/FA7
7
8
9
P1.5/FD5
P1.6/FD6
P1.7/FD7
RES
3
4
31
30
29
38
37
RES
RXD/P3.0
ihh-yyyQ
SM2964
5
6
ihh-yyyJ
36
SM2964
28
10
11
12
13
NC
TXD/P3.1
#INT0/P3.2
44L PQFP
(Top View)
35
34
#EA
NC
ALE/#FCE
RXD/P3.0
27
26
25
24
23
7
44L PLCC
(Top View)
8
NC
TXD/P3.1
#INT0/P3.2
#INT1/P3.3
T0/P3.4
#PSEN/#FOE
P2.7/FA15
P2.6/FA14
P2.5/FA13
33
32
31
30
29
#INT1/P3.3
9
10
11
14
15
16
17
T0/P3.4
T1/P 3.5
#PSEN/#FOE
P2.7/FA15
P2.6/FA14
P2.5/FA13
12
22
20 21
13 14 15 16 17 18
19
T1/P3.5
21
25 26 27 28
22 23 24
18 19 20
1
2
3
T2/P1.0/FD0
T2EX/P1.1/FD1
P1.2/FD2
VDD
40
P0.0/FA0
39
38
37
P0.1/FA1
P0.2/FA2
P0.3/FA3
P0.4/FA4
4
5
P1.3/FD3
P1.4/FD4
44 43 42 41 40 39 38 37 36 35 34
33
36
35
P1.5/FD5
P1.6/FD6
P1.5/FD7
1
P0.4/FA4
2
6
7
32
P1.5/FD5
P1.6/FD6
P0.5/FA5
P0.6/FA6
P0.7/FA7
#EA
NC
ALE/#FCE
34
33
32
31
30
P0.5/FA5
P0.6/FA6
3
4
31
30
29
RES
RXD/P3.0
NC
TXD/P3.1
#INT0/P3.2
#INT1/P3.3
8
ihh-yyyU
SM2964
P1.7/FD7
RES
5
6
P0.7/FA7
#EA
9
28
44L LQFP
(Top View)
10
27
26
25
RXD/P3.0
TXD/P3.1
7
ALE/#FCE
8
11
#PSEN/#FOE
P2.7/FA15
P2.6/FA14
P2.5/FA13
9
#PSEN/#FOE
29
28
12
13
#INT0/P3.2
#INT1/P3.3
T0/P3.4
10
T0/P3.4
T1/P 3.5
24
23
P2.7/FA15
P2.6/FA14
P2.5/FA13
11
12
22
20 21
13 14 15 16 17 18
19
27
26
25
24
23
14
15
T1/P3.5
P2.4/FA12
P2.3/FA11
P2.2/FA10
16
17
#WR/P3.6
#RD/P3.7/#FWE
XTAL2
18
19
20
22
21
P2.1/FA9
P2.0/FA8
XTAL1
VSS
Specifications subject to change without notice,contact your sales representatives for the most recent information.
2/15
Ver1.0 PID 2964 08/00
SyncMOS Technologies Inc.
SM2964
December 1998
Block Diagram
Decoder &
Register
256 bytes
RAM
Stack
Pointer
Timer 1
Timer 2
Timer 0
Buffer
DPTR
to pertinent blocks
to whole chip
RES
Reset
Circuit
Acc
Vdd
Vss
PC
Incrementer
Power
Circuit
Buffer2
Buffer1
to pertinent blocks
Program
Counter
Interrupt
Circuit
ALU
Register
PSW
XTAL2
XTAL1
#EA
to whole system
ALE
Timing
#PSEN
Generator
64K
bytes
Instruction
Register
Flash
Memory
Port 1
Latch
Port 3
Latch
Port 2
Latch
Port 0
Latch
Port 1
Port 0
Driver & Mux
Port 2
Port 3
Driver & Mux Driver & Mux
Driver & Mux
8
8
8
8
Specifications subject to change without notice,contact your sales representatives for the most recent information.
3/15
Ver1.0 PID 2964 08/00
SyncMOS Technologies Inc.
SM2964
December 1998
Pin Descriptions
40L 44L
PDIP LQFP PQFP PLCC
44L
44L
Symbol
Active I/O
Names
Pin# Pin#
Pin#
40
41
42
43
44
1
Pin#
2
3
4
5
1
40
41
42
43
44
1
T2/P1.0/FD0
T2EX/P1.1/FD1
P1.2/FD2
P1.3/FD3
P1.4/FD4
P1.5/FD5
P1.6/FD6
P1.7/FD7
RES
RXD/P3.0
TXD/P3.1
#INT0/P3.2
#INT1/P3.3
T0/P3.4
i/o bit 0 of port 1 & timer 2 & bit 0 of flash block address
2
3
i/o bit 1 of port 1 & timer control & bit 1 of flash block address
i/o bit 2 of port 1 & bit 2 of flash/ext. memory address
i/o bit 3 of port 1 & bit 3 of flash/ext. memory address
i/o bit 4 of port 1 & bit 4 of flash/ext. memory address
i/o bit 5 of port 1 & bit 5 of flash/ext. memory address
i/o bit 6 of port 1 & bit 6 of flash/ext. memory address
i/o bit 7 of port 1 & bit 7 of flash/ext. memory address
4
5
6
7
6
7
8
9
2
3
4
5
7
8
9
2
3
4
5
7
8
9
8
9
10
11
13
14
15
16
17
18
19
20
21
22
24
25
26
27
28
29
30
31
32
33
35
36
37
38
39
40
41
42
43
44
H
i
Reset
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
i/o bit 0 of port 3 & Receive data & flash block enable
i/o bit 1 of port 3 & Transmit data
i/o bit 2 of port 3 & low true interrupt 0
i/o bit 3 of port 3 & low true interrupt 1
i/o bit 4 of port 3 & Timer 0
L/ -
L/ -
10
11
12
13
14
15
16
18
19
20
21
22
23
24
25
26
27
29
30
31
32
33
34
35
36
37
38
10
11
12
13
14
15
16
18
19
20
21
22
23
24
25
26
27
29
30
31
32
33
34
35
36
37
38
T1/P3.5
i/o bit 5 of port 3 & Timer 1
i/o bit 6 of port 3 & o/p enable to flash block (low enable)
#WR/P3.6
#RD/P3.7/#FWE
XTAL2
XTAL1
VSS
L/ -
L/ - /L i/o bit 7 of port 3 & write enable to flash block (low enable)
o
i
Crystal out
Crystal in
Sink Voltage, Ground
P2.0/FA8
P2.1/FA9
P2.2/FA10
P2.3/FA11
P2.4/FA12
P2.5/FA13
P2.6/FA14
P2.7/FA15
#PSEN/#FOE
ALE/#FCE
#EA
P0.7/FA7
P0.6/FA6
P0.5/FA5
P0.4/FA4
P0.3/FA3
P0.2/FA2
P0.1/FA1
P0.0/FA0
VDD
i/o bit 0 of port 2 & bit 8 of flash block address
i/o bit 1 of port 2 & bit 9 of flash block address
i/o bit 2 of port 2 & bit 10 of flash block address
i/o bit 3 of port 2 & bit 11 of flash block address
i/o bit 4 of port 2 & bit 12 of flash block address
i/o bit 5 of port 2 & bit 13 of flash block address
i/o bit 6 of port 2 & bit 14 of flash block address
i/o bit 7 of port 2 & bit 15 of flash block address
o/i program storage enable
L/L
- /L
L
o/i address latch enable
i
external access
i/o bit 7 of port 0 & data bit 7 of flash block
i/o bit 6 of port 0 & data bit 6 of flash block
i/o bit 5 of port 0 & data bit 5 of flash block
i/o bit 4 of port 0 & data bit 4 of flash block
i/o bit 3 of port 0 & data bit 3 of flash block
i/o bit 2 of port 0 & data bit 2 of flash block
i/o bit 1 of port 0 & data bit 1 of flash block
i/o bit 0 of port 0 & data bit 0 of flash block
Drive Voltage, +5 Vcc
Specifications subject to change without notice,contact your sales representatives for the most recent information.
4/15
Ver1.0 PID 2964 08/00
SyncMOS Technologies Inc.
SM2964
December 1998
Operating Conditions
Symbol
TA
Description
Min.
0
Typ.
25
Max.
70
Unit.
degree C
V
Remarks
Ambient temperature under bias
Supply voltage
VCC5
4.5
3.0
16
5.0
16
5.5
16
SM2964C
Fosc 16
Fosc 25
Fosc 40
Oscillator Frequency
MHz
SM2964C16
SM2964C25
SM2964C40
25
25
MHz
25
40
40
MHz
AC Characteristics
(16/25/40 MHZ, operating conditions; CL for Port 0, ALE and PSEN Outputs=150uF; CL for all Other Output=80pF)
Valid
Cycle
f osc 16
Min. Typ. Max
Variable f osc
Typ. Max
Unit Remarks
Symbol
T LHLL
T AVLL
T LLAX
T LLIV
Parameter
Min.
ALE pulse width
RD/WRT 115
2xT - 10
T - 20
nS
nS
nS
Address Valid to ALE low
Address Hold after ALE low
ALE low to Valid Instruction In
ALE low to #PSEN low
#PSEN pulse width
RD/WRT
RD/WRT
RD
43
53
T - 10
240
177
4xT - 10 nS
T LLPL
T PLPH
T PLIV
RD
53
T - 10
nS
nS
RD
173
3xT - 15
#PSEN low to Valid Instruction In
Instruction Hold after #PSEN
Instruction Float after #PSEN
Address to Valid Instruction In
#PSEN low to Address Float
#RD pulse width
RD
3xT - 10 nS
nS
T PXIX
T PXIZ
RD
0
0
RD
87
292
10
T + 25 nS
5xT - 20 nS
10 nS
nS
T AVIV
RD
T PLAZ
T RLRH
T WLWH
T RLDV
T RHDX
T RHDZ
T LLDV
T AVDV
T LLYL
RD
RD
365
365
6xT - 10
6xT - 10
#WR pulse width
WRT
RD
nS
#RD low to Valid Data In
Data Hold after #RD
302
5xT - 10 nS
nS
RD
0
0
Data Float after #RD
RD
145
590
542
2xT + 20 nS
8xT - 10 nS
9xT - 20 nS
3xT + 10 nS
nS
ALE low to Valid Data In
Address to Valid Data In
ALE low to #WR High or #RD low
Address Valid to #WR or #RD low
Data Valid to #WR High
Data Valid to #WR transition
Data hold after #WR
RD
RD
RD/WRT
RD/WRT
WRT
WRT
WRT
RD
178
230
403
38
197 3xT - 10
4xT - 20
7xT - 35
T - 25
T AVYL
T QVWH
T QVWX
T WHQX
T RLAZ
T YALH
T CHCL
T CLCX
T CLCH
T CHCX
nS
nS
73
T + 10
nS
#RD low to Address Float
#WR or #RD high to ALE high
clock fall time
5
nS
RD/WRT
53
72
T -10
T + 10 nS
nS
nS
nS
nS
nS
clock low time
clock rise time
clock high time
T , TCLCL clock period
63
1/fosc
Specifications subject to change without notice,contact your sales representatives for the most recent information.
5/15
Ver1.0 PID 2964 08/00
SyncMOS Technologies Inc.
SM2964
December 1998
DC Characteristics
(12MHz, typical operating conditions, valid for SM2964C series)
Symbol
VILX
Parameter
Input low voltage
Valid
XTAL1
#EA
RES
XTAL1
Min.
Typ.
Max
Unit Test Conditions
-0.5
0
-0.5
20%Vcc-0.1
20%Vcc-0.3
20%Vcc-0.1
Vcc+0.5
V
V
V
V
V
V
VILR
VIHX
"
Input High Voltage
70% Vcc
20%Vcc+0.9
70%Vcc
#EA
RES
Vcc+0.5
Vcc+0.5
VIHR
"
Output Low Voltage
ALE, #PSEN
ports 0,3
ports 1,2
ALE, #PSEN
450 mV IOL=3.2mA
450 mV IOL=3.2mA
350 mV IOL=1.6mA
VOL0
VOL1
"
"
Output High Voltage
2.4
90%Vcc
2.4
90%Vcc
2.4
90%Vcc
2.4
90%Vcc
V
V
V
V
V
V
V
V
IOH= -60uA
IOH= -10uA
IOH= -800uA
IOH= -80uA
IOH= -60uA
IOH= -10uA
IOH= -60uA
IOH= -10uA
"
"
"
"
"
"
"
VOH0
VOH1
VOH2
port 0
port 1,3
port 2
IOL0
IIL
IIH
Output Low Current
Logical 0 Input Current
Logical 1 Input Current
ports 0,3
ports 1,2,3
port 0
mA VOL=0.45V,note1
50 uA Vin=0.45V
1.5 uA Vin=5.0V
ITL
ILI
Logic Transition Current
Input Leakage Current
port 1,2,3
port 0
RES
650 uA Vin=2.0V
10 uA 0.45V<Vin<Vcc
150 Kohm
R RES Reset Pull-down Resistance
50
50
R X
CIO
ICC
Crystal feedback Resistance XTAL1,2
Pin Capacitance
Power Supply Current
330 Kohm
10 pF Freq=1MHZ,Ta=25 C
20 mA Active mode, 12MHZ
6.5 mA Idle mode, 12MHZ
150 uA Power down mode
Vdd
Vdd
Vdd
VIL1
VIL2
VIL3
VIH1
VIH2
VIH3
Input Low Voltage
port 0,1,2,3,#EA
RST
XTAL1
port 0,1,2,3,#EA
RST
XTAL1
0.5
0.4
0.4
V
V
V
V
V
V
Vcc= 5V
“
"
"
"
"
"
"
Input Low Voltage
1.3
3.0
3.0
"
"
note1: no more than 80 mA IOLs for all 16-bit ports & 3 output pins.
To Programme
The Program mean is identical to MVI's flash V29C51002 except the memory size. This SM2964 has
512K bit (64K x 8) while the V29C51002 has 2 mega bit (256K x 8). Of course, the pin configuration is not
identical. MVI provides an adapter board M9015 to transform those pins to fit into pins of commercial
2-mega-bit flash which is organized in 8-bit width.
Specifications subject to change without notice,contact your sales representatives for the most recent information.
6/15
Ver1.0 PID 2964 08/00
SyncMOS Technologies Inc.
SM2964
December 1998
Application Reference
Valid for SM2964C
XI
X'tal
C1
C2
R
3MHz
6MHz
30 pF
30 pF
open
9MHz
12MHz
30 pF
30 pF
open
30 pF
30 pF
open
30 pF
30 pF
open
X'tal
SM2964C
R
X'tal
C1
C2
R
16MHz
30 pF
30 pF
open
25MHz
15 pF
15 pF
62KΩ
33MHz 40MHz
X2
10 pF
10 pF
6.8KΩ
2 pF
2 pF
4.7KΩ
C2
C1
NOTE : Oscillation circuit may differs with different crystal or ceramic
resonator, especially in higher oscillation frequency which was
due to each crystal or ceramic resonator has its own characteristics.
User should check with the crystal or ceramic resonator manufacture
for appropriate value of external components.
Data Memory Read Cycle Timing
T3
T12
T11
T1
T2
T10
T6
T7
T8
T9
T12
T1
T3
T5
T2
T4
OSC
ALE
1
2
#PSEN
#RD
5
7
3
ADDRESS A15 - A8
PORT2
PORT0
3
4
8
6
Float
DATA in
INST in Float
A7 - A0
Float
ADDRESS
or Float
Specifications subject to change without notice,contact your sales representatives for the most recent information.
7/15
Ver1.0 PID 2964 08/00
SyncMOS Technologies Inc.
SM2964
December 1998
Program Memory Read Cycle Timing
T1
T11
T12
T10
T2
T9
T8
T6
T2
T3
T4
T5
T7
T12
T1
OSC
ALE
1
2
5
7
#PSEN
#RD,#WR
3
3
PORT2
PORT0
ADDRESS A15 - A8
ADDRESS A15 - A8
4
6
8
Float
A7 - A0
Float
A7 - A0
Float
Float
Float
INST in
INST in
Data Memory Write Cycle Timing
T12
T3
T10
T11
T1
T2
T9
T8
T7
T4
T5
T6
T2
T3
T1
T12
OSC
ALE
1
#PSEN
#WR
5
6
2
PORT2
PORT0
ADDRESS A15 - A8
2
4
3
ADDRESS
or Float
INST
Float
DATA OUT
A7 - A0
Specifications subject to change without notice,contact your sales representatives for the most recent information.
8/15
Ver1.0 PID 2964 08/00
SyncMOS Technologies Inc.
SM2964
December 1998
I/O Ports Timing
T8
T6
T7
T5
T4
T3
T2
T1
T12
T11
T10
T7
T9
T8
T6
X1
sampled
inputs P0,P1
sampled
inputs P2,P3
Output by
current data
next data
Mov Px,Src
RxD at Serial Port
Shift Clock
sampled
(Mode 0)
Timing Critical, Requirement of External Clock (Vss=0.0V is assumed)
TCLCL
Vdd-0.5V
70%Vdd
20%Vdd-0.1V
0.45V
TCLCX
TCHCX
TCHCL
TCLCH
Tm.I
External Program Memory Read Cycle
TPLPH
#PSEN
ALE
TLHLL
TAVLL
TLLPL
TPXIZ
TPXIX
TPLAZ
TLLAX
TPLIV
Instruction. IN
A0 - A7
A0 - A7
PORT 0
TAVIV
A8 - A15
A8 - A15
PORT 2
Specifications subject to change without notice,contact your sales representatives for the most recent information.
9/15
Ver1.0 PID 2964 08/00
SyncMOS Technologies Inc.
SM2964
December 1998
Tm.II External Data Memory Read Cycle
#PSEN
ALE
TYHLH
TLLDV
TLLYL
TRLRH
#RD
TAVLL
TLLAX
TRHDZ
TRHDX
DATA IN
TRLDV
TRLAZ
A0 - A7
A0 - A7
FROM PCL
INSTRL
IN
PORT 0
PORT 2
from Ri or DPL
TAVYL
TAVDV
A8 - A15 from PCH
P2.0 - P2.7 or A8 - A15 from DPH
Tm.III External Data Memory Write Cycle
#PSEN
ALE
TYHLH
TLHLL
TLLYL
TWLWH
TAVLL
#WR
TQVWX
TLLAX
TWHQX
TQVWH
A0-A7
from Ri or DPL
A0-A7
From PCL
INSTRL
IN
DATA OUT
PORT 0
TAVYL
A8-A15 from PCH
P2.0-P2.7 or A8-A15 from DPH
PORT 2
Specifications subject to change without notice,contact your sales representatives for the most recent information.
10/15
Ver1.0 PID 2964 08/00
SyncMOS Technologies Inc.
SM2964
December 1998
40L 600mil PDIP Information
E
D
S
E1
A2
C
A1
A
L
e1
B1
eA
B
a
Note:
Dimension in inch
minimal/maximal
- / 0.210
Dimension in mm
minimal/maximal
- / 5.33
1.Dimension D Max & S include mold flash or tie bar
Symbol
A
burrs.
2.Dimension E1 does not include inter lead flash.
A1
A2
B
B1
C
D
E
E1
e1
L
0.010 / -
0.25 / -
3.Dimension D & E1 include mold mismatch and are
determined at the mold parting line.
4.Dimension B1 does not include dam bar protrusion/
infusion.
5.Controlling dimension is inch.
6.General appearance spec. should base on final visual
inspection spec.
0.150 / 0.160
0.016 / 0.022
0.048 / 0.054
0.008 / 0.014
- / 2.070
0.590 / 0.610
0.540 / 0.552
0.090 / 0.110
0.120 / 0.140
0 / 15
3.81 / 4.06
0.41 / 0.56
1.22 / 1.37
0.20 / 0.36
- / 52.58
14.99 / 15.49
13.72 / 14.02
2.29 / 2.79
3.05 / 3.56
0 / 15
a
eA
S
0.630 / 0.670
- / 0.090
16.00 / 17.02
- / 2.29
Specifications subject to change without notice,contact your sales representatives for the most recent information.
11/15
Ver1.0 PID 2964 08/00
SyncMOS Technologies Inc.
SM2964
December 1998
44L Plastic Chip Carrier (PLCC)
L
6
7
E
HE
GE
y
D
A2
A
HD
A1
C
Dimension in inch
minimal/maximal
- / 0.185
Dimension in mm
minimal/maximal
- / 4.70
b1
b
θ
Symbol
A
e
A1
A2
b1
b
C
D
0.020 / -
0.51 / -
GD
0.145 / 0.155
0.026 / 0.032
0.016 / 0.022
0.008 / 0.014
0.648 / 0.658
0.648 / 0.658
0.050 BSC
0.590 / 0.630
0.590 / 0.630
0.680 / 0.700
0.680 / 0.700
0.090 / 0.110
- / 0.004
3.68 / 3.94
0.66 / 0.81
0.41 / 0.56
0.20 / 0.36
16.46 / 16.71
16.46 / 16.71
1.27 BSC
14.99 / 16.00
14.99 / 16.00
17.27 / 17.78
17.27 / 17.78
2.29 / 2.79
- / 0.10
Note:
1.Dimension D & E does not include inter lead flash.
2.Dimension b1 does not include dam bar protrusion/
intrusion.
3.Controlling dimension: Inch
4.General appearance spec. should base on final visual
inspection spec.
E
e
GD
GE
HD
HE
L
θ
y
/
/
Specifications subject to change without notice,contact your sales representatives for the most recent information.
12/15
Ver1.0 PID 2964 08/00
SyncMOS Technologies Inc.
SM2964
December 1998
Dice Pad Assignment
PAD-NAME
P0.3
P0.2
P0.1
P0.0
Vdd
PAD-NAME
INDEX
INDEX
PAD-NAME
INDEX
INDEX
PAD-NAME
P3.6
P3.7
XTAL2
XTAL1
Vss
Vss
Vss
P2.0
P2.1
P2.2
P2.3
P2.4
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
P2.5
P2.6
P2.7
#FOE
#FCE
#EA
P0.7
P0.6
P0.5
P0.4
1
2
3
4
5
6
7
8
9
13
14
15
16
17
18
19
20
21
22
P1.5
P1.6
P1.7
RES
P3.0
P3.1
P3.2
P3.3
P3.4
P3.5
Vdd
Vdd
Vss
P1.0
P1.1
P1.2
P1.3
P1.4
10
11
12
45 44 43 42 41 40 39 38 37 36
35
34
1
2
33
32
31
30
29
28
3
4
5
6
7
8
MSU2964
PAD SIZE: 90x 90 (um)
substrate should be bonded to Vss (Gnd)
27
26
25
9
10
11
12
pid 264* 02/98
pid 264** 04/98
pid 264*** 11/98
pid 264**** 12/98
pid 264A 01/99
pid 264A* 08/00
24
23
13 14 15 16 17 18 19 20 21 22
Specifications subject to change without notice,contact your sales representatives for the most recent information.
13/15
Ver1.0 PID 2964 08/00
SyncMOS Technologies Inc.
SM2964
December 1998
Feedback / Inquiry:
:SyncMOS Technologies, Inc.
:MKT / Customer Service Dept.
:886-3-579-2960
:886-3-578-0493
:886-3-579-2988
:886-3-579-2926
To
Attn
Fax
From :
Company
:
Dept, Section :
Position Title :
Tel
Inquiry Date
Ref No
:
:
Logo Top Marking Request & Spec.
Below is the specification of logo in 20:1 scale base. This logo diagram is clear
enough and is able to be shrunk directly to fit into available top marking area on top
of the device package.
Description:
Specifications subject to change without notice,contact your sales representatives for the most recent information.
14/15
Ver1.0 PID 2964 08/00
SyncMOS Technologies Inc.
SM2964
December 1998
SM2964 Application Note
SM2964 may need pull-up resistor when
driving multiple device with its I/O pins.The
pull-up resistor value 10Kohm to 47Kohm
DEVICE 1
pull-up resister
10Kohm to
47Kohm
N> 1
I/O pin
DEVICE N
SM2964
e.g. Original program Modified program
When using port 0 as input pin, user
need to set corresponding SFR
(special function register) to 1 before
read in data through port 0. Otherwise
data read may be incorrect.
mov b,#0dh
djnz b,$
mov b,#0dh
djnz b,$
setb p0.2
mov c,p0.2
mov.7, c
mov c,p0.2
mov acc.7, c
Extra instruction added
SM2964 has 64KB internal ROM addressing space which fully
occupies 16-bit address line.
/EA pin of SM2964 will be disabled after internal ROM been
protected. This feature will prevent internal ROM content been dump
externally.
If the internal ROM not been protected, /EA pin function of SM2964 will be the
same as /EA pin function of intel 80C52.
Specifications subject to change without notice,contact your sales representatives for the most recent information.
15/15
Ver1.0 PID 2964 08/00
相关型号：
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