SPHE8200A [ETC]
DVD SINGLE CHIP MPEG A/V PROCESSOR; DVD单芯片MPEG A / V处理器
| 型号： | SPHE8200A |
| 厂家： | 
ETC |
| 描述： | DVD SINGLE CHIP MPEG A/V PROCESSOR |
| 文件： | 总40页 (文件大小：1677K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
DVD Single Chip MPEG A/V
Processor
Preliminary
OCT. 07, 2003
Version 0.2
SUNPLUS TECHNOLOGY CO. reserves the right to change this documentation without prior notice. Information provided by SUNPLUS TECHNOLOGY CO.
is believed to be accurate and reliable. However, SUNPLUS TECHNOLOGY CO. makes no warranty for any errors which may appear in this document.
Contact SUNPLUS TECHNOLOGY CO. to obtain the latest version of device specifications before placing your order. No responsibility is assumed by
SUNPLUS TECHNOLOGY CO. for any infringement of patent or other rights of third parties which may result from its use. In addition, SUNPLUS products
are not authorized for use as critical components in life support devices/ systems or aviation devices/systems, where a malfunction or failure of the product may
reasonably be expected to result in significant injury to the user, without the express written approval of Sunplus.
Preliminary
SPHE8200A
Table of Contents
PAGE
1. GENERAL DESCRIPTION......................................................................................................................................................................4
2. FEATURE ...............................................................................................................................................................................................5
3. BLOCK DIAGRAM..................................................................................................................................................................................6
4. SIGNAL DESCRIPTION..........................................................................................................................................................................7
4.1. PIN MAP ...........................................................................................................................................................................................7
4.2. GROUP MAP .....................................................................................................................................................................................8
4.3. PIN DESCRIPTION..............................................................................................................................................................................9
5. FUNCTIONAL DESCRIPTIONS............................................................................................................................................................18
5.1. PLL AND CLOCKGEN .......................................................................................................................................................................18
5.2. POWER CONTROL ...........................................................................................................................................................................18
5.3. EMBEDDED 32-BIT RISC CONTROLLER.............................................................................................................................................18
5.4. RISC INTERFACE ............................................................................................................................................................................19
5.5. ROM/FLASH/SRAM CONTROLLER....................................................................................................................................................20
5.6. RISC MEMORY INTERFACE ..............................................................................................................................................................20
5.7. PERIPHERAL CONTROL INTERFACE ...................................................................................................................................................20
5.8. CSS/CPPM SUPPORT.....................................................................................................................................................................20
5.9. MPEG VIDEO DECODER..................................................................................................................................................................20
5.10.GRAPHICS ENGINE BONDYPRO®......................................................................................................................................................21
5.11.VIDEO POST PROCESSING ...............................................................................................................................................................21
5.12.AUDIO DSP ....................................................................................................................................................................................21
5.13.AUDIO INTERFACE ...........................................................................................................................................................................22
5.14.INTEGRATED AUDIO QUALITY ADC....................................................................................................................................................22
5.15.I/O PROCESSOR..............................................................................................................................................................................22
5.16.SDRAM CONTROLLER ....................................................................................................................................................................22
5.17.SUB-PICTURE DECODER ..................................................................................................................................................................22
5.18.ON SCREEN DISPLAY.......................................................................................................................................................................22
5.19.DISPLAY INTERFACE.........................................................................................................................................................................22
5.20.VIDEO DAC ....................................................................................................................................................................................23
5.21.ATAPI INTERFACE ...........................................................................................................................................................................23
5.22.GPIO.............................................................................................................................................................................................23
5.23.UART ............................................................................................................................................................................................23
6. ELECTRICAL SPECIFICATIONS .........................................................................................................................................................24
6.1. ABSOLUTE MAXIMUM RATINGS .........................................................................................................................................................24
6.2. DC OPERATING CONDITIONS............................................................................................................................................................24
6.3. CAPACITANCE..................................................................................................................................................................................24
6.4. AC CHARACTERISTICS.....................................................................................................................................................................25
6.4.1. SDRAM interface timing diagrams ......................................................................................................................................25
6.4.2. ROM / flash interface timing diagrams.................................................................................................................................26
6.4.3. Audio interface timing diagrams ..........................................................................................................................................27
6.4.4. Video timing diagrams.........................................................................................................................................................28
7. REGISTER LIST ...................................................................................................................................................................................30
8. PACKAGE/PAD LOCATION .................................................................................................................................................................38
© Sunplus Technology Co., Ltd.
Proprietary & Confidential
2
OCT. 07, 2003
Preliminary Version: 0.2
Preliminary
SPHE8200A
8.1. OUTLINE DIMENSIONS......................................................................................................................................................................38
9. DISCLAIMER........................................................................................................................................................................................39
10.REVISION HISTORY.............................................................................................................................................................................40
© Sunplus Technology Co., Ltd.
Proprietary & Confidential
3
OCT. 07, 2003
Preliminary Version: 0.2
Preliminary
SPHE8200A
DVD SINGLE CHIP MPEG A/V PROCESSOR
1.GENERAL DESCRIPTION
SPHE8200A A/V decoder is a single-chip integrated DVD A/V
decoder. It performs real-time decoding and playback of ISO/IEC
11172 MPEG1 and 13818 MPEG2 stream for multiple bitstream
sources.
SPHE8200A supports Dolby Digital, DTS, MPEGI/II Layer1/2 ,
PCM, LPCM, WMA audio playback.
SPHE8200A also combines all the functions required for a
high-performance progressive-scan DVD system. Built-in
de-interlacing hardware allows high quality DVD playback. The
embedded digital audio decoder is able to support key control and
audio sound effects for Karaoke.
SPHE8200A supports DVD-Video, DVD-Audio, Super Video CD,
Video CD, CD-DA, HDCD, OKO, CD-ROM different disc formats.
SPHE8200A is designed to maximize system performance with
minimum cost. For typical DVD application it integrates DVD/CD
servo controller, multi-channel multi-format TV-encoder and audio
quality ADC, with high quality 5.1ch Audio, or low cost 2-ch AC3
system.
In additional to that SPHE8200A includes a flexible 2D graphics
engine for high quality user interface and other applications.
Complex application could be built using this platform easily.
Development tools of SPHE8200A include complete compiler tools,
programming guide and system application libraries.
Application utilizing the SPHE8200A is presented below:
6-ch video output
VFD
front panel
SPHE8200A
Audio
DAC
Audio
amplifier
2~10 ch
DVD-loader
RF
SDRAM
ROM
© Sunplus Technology Co., Ltd.
Proprietary & Confidential
4
OCT. 07, 2003
Preliminary Version: 0.2
Preliminary
SPHE8200A
2.FEATURE
ꢀSingle Chip Integrated DVD Servo and A/V Decoder
ꢀIntegrated DVD/CD Servo Controller
— Support 1x ~ 2x DVD format reading
— Support 1x ~ 16x CD format reading
ꢀEmbedded 32-bit RISC Processor without external host
controller
— Support up to 4 SDRAM devices
— Support 16M/64M/128M/256M SDRAM devices
ꢀGraphics
— Embedded 2D Graphics Accelerator
— BitBlt, line, triangle drawing support
ꢀDisplay
ꢀEmbedded Audio Processor supports multiple audio standards
ꢀEmbedded I/O processor supports programmable interface
control
ꢀEmbedded TV encoder with multi-channel built-in high-speed
video DAC supports various display standards
ꢀEmbedded audio ADC supports stereo analog audio input
ꢀBuilt-in system PLL and audio PLL generate all clock sources
required from single 27MHz input
— De-interlacing of interlaced video source
— Flexible vertical interpolation
— Flexible horizontal interpolation with optional CIF filter
— Powerful cropping and panning effect
— Support YUV422, 8-bit indexed color or 16-bit direct color
format
ꢀOSD
— Multiple OSD regions with different formats
— Support 4/16/256 indexed color
— Support 16/24-bit direct color
— Support x2/x3/x4 horizontal scaling
ꢀEmbedded TV encoder
ꢀSupport following disc format:
— DVD Navigation 1.0
— DVD audio
— SVCD (Chaoji VCD)
— OKO disc
— Simultaneous multi-channel output
— Support 480i/480p/576i/576p format
— Support 640x480 VGA / 800x600 SVGA format
— Support CVBS output
— VCD 2.0/1.1/1.0
— CDDA / HDCD
— CDROM (game, WMA and JPEG disc)
ꢀCSS/CPPM hardware
— Support SVideo, Component (YUV / YPbPr) or RGB output
— Macrovision 7.01 and Macrovision AGC v1.03 copy
protection
— Built-in CSS hardware
— Built-in CPPM C2_DCBC and C2_D/C2_D function
ꢀVideo Decoder
ꢀInterface
— Real time MPEG2 MP@ML decoding
— Real time MPEG1 D1 (720x480x30 /720x576x25) decoding
— Hardware accelerated JPEG decoding
— Advanced decoding and display control
ꢀSub-picture Decoder
— 27MHz crystal driver
— 16/32-bit SDRAM interface
— 8/16-bit ROM/FLASH/SRAM interface
— UART ports
— IR and VFD support
— Advanced Sub-Picture Decoder for DVD SVCD and OKO
— Support hardware vertical scaling
ꢀAudio Decoder
— Video DAC analog output
— Simultaneous 10-channel audio DAC output
— IEC958/SPDIF digital input / output
— Analog audio input
— Flexible Programmable DSP Architecture
— Embedded high resolution audio quality ADC
— Support CDDA, HDCD, and DVD-Audio
— Support LPCM, PCM, and WMA playback
— Support MPEGI/II layer 1/2 and MPEG 2.5 playback (with
optional down-mixing)
— External ADC digital input interface (optional)
— Optional ATAPI and I2S interface support
— Optional Parallel Port interface support
ꢀLow power
— Advanced low power design
— Selective standby mode
— Support Dolby Digital AC3 5.1ch / DTS 5.1ch playback (with
optional down-mixing)
— Support Key Shift of 2 channels
— Programmable low speed operation
ꢀTechnology
— Support equalization, reverb and special sound field
ꢀSDRAM controller
— Advanced CMOS technology
— 216pin LQFP package
— High Performance SDRAM controller
— Support 16 or 32 bit operation
— 3v (I/O) and 1.8v (kernel) power supplies
— 5v I/O tolerance
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5
OCT. 07, 2003
Preliminary Version: 0.2
Preliminary
SPHE8200A
3.BLOCK DIAGRAM
EPROM/SRAM
RISC
PLLv PLLa
EPROM/
SRAM
interface
loader inf.
Servo
ECC
icache dcache
Power control
loader RF input
Intr. control
Timer
Graphics
Engine
SDRAM
controller
SDRAM /16 or /32
DMA
Engine
I/O
processor
IR/VFD/(I2C)
OSD
decoder
GPIO
UART
UART / smartcard
Video post-
processing
Audio
DSP
Sub-picture
decoder
icache mem
Audio Analog In
DAC digital out
IEC 958 I/O
ADC
Video
encoder
MPEG
video
decoder
Audio
Interface
CSS/
CPPM
Video output
Video DAC
ADC digital in
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6
OCT. 07, 2003
Preliminary Version: 0.2
Preliminary
SPHE8200A
4.SIGNAL DESCRIPTION
4.1. Pin Map
A_DATA4/GPIO
A_IEC_RX/GPIO
A_IEC_TX/GPIO
A_DATA0/GPIO
VDD_O7
163
164
165
166
167
168
169
170
171
172
173
174
175
176
177
178
179
180
181
182
183
184
185
186
187
188
189
190
191
192
193
194
195
196
197
198
199
200
201
202
203
204
205
206
207
208
209
210
211
212
213
214
215
216
108
107
106
105
104
103
102
101
100
99
98
97
96
95
94
93
92
91
90
89
88
87
86
85
84
83
82
81
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
M_CKE
VSS_K3
M_CLKO
VDD_O3
M_D8
A_DATA1/GPIO
A_DATA2/GPIO
A_DATA3/GPIO
A_LRCK/GPIO
VSS_K6/VSS_O7
A_BCK/GPIO
A_XCK/GPIO
UA0_RX/GPIO
UA0_TX/GPIO
VDD_K6
M_D9
M_D10
M_D11
VSS_K3
M_D12
M_D13
M_D14
M_D15
VDD_K3
M_BA0
V_COMP
M_CS_B
M_RAS_B
M_CAS_B
VSS_O2
M_WE_B
M_D0
V_BIAS
V_FSADJ
V_REFOUT
TV_DAC0
VDD_TVA0
VSS_TVA0
TV_DAC1
TV_DAC2
VDD_TVA1
VSS_TVA1
TV_DAC3
TV_DAC4
VDD_TVA2
VSS_TVA2
TV_DAC5
PWM_VDD
TRAY_OUT
SC1_OUT
SPDC_OUT
SC_OUT
M_D1
M_D2
VDD_O2
M_D3
SPHE8200A
M_D4
M_D5
M_D6
M_D7
VSS_K2
CLKIN
216 PIN LQFP
24x24mm2
CLKOUT
VDD_K2
VSS_PLLA
VDD_PLLA
VSS_PLLV
VDD_PLLV
R_CS3_B/GPIO
R_CS2_B/GPIO
R_CS1_B/GPIO
R_WE_B/GPIO
R_OE_B/GPIO
R_A19/GPIO
R_A18
DMEA
FGIN
PWM_VSS
DAVSS
TEO
FEO
DAVDD
HGIN
LGIN2
R_A17
LGIN1
VSS_O1
R_A16
LPFNIN
PDFLT1
R_A7
FDFLT
R_A6
VREFO
R_A5
PLLVDD
R_A4
PDRSET
R_A3
FDRSET
R_A2
PLLVSS
VDD_O1
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7
OCT. 07, 2003
Preliminary Version: 0.2
Preliminary
SPHE8200A
4.2. Group Map
VSS_*
VDD_*
TEO
FEO
System
Interface
CLKIN
RSTB
TESTMODE
HGIN
LGIN1
LGIN2
LPFNIN
PDFLT1
FDFLT
VREFO
PDRSET
FDRSET
DRESET
CNIN
AIN_L/MIC
AIN_R
ATO
ADC
analog
interface
VM
SERVO
AUI_BCK
AUI_LRCK
AUI_DATA
SLVL
RFO
ADC
digital input
RFRP
RFRPLP
TEXOLP
TEXO
TEI
FEI
CSI
SBAO
VREF
VRGO
AU_XCK
AU_BCK
AU_LRCK
AU_DATA[3:0]
AU_IEC_TXRV
Audio
digita l output
interface
SPHE8200A
(216pin)
R_A[21:0]
R_D[7:0]
ROM
Flash
interface
R_CS_B[3:0]
R_WE_B
R_OE_B
R_WP_B
IO_CHRDY
TRAY_OUT
SC1_OUT
SPDC_OUT
SC_OUT
DMEA
M_CLKO
FGIN
SRV_SCLK
SERVO
M_RAS_B
M_CAS_B
M_WE_B
M_CS_B
M_BA[1:0]
M_A[11:0]
M_D[31:0]
M_DQ M[3:0]
SRV_SDATA
SRV_SDEN
SRV_FDCT
T_PLCK
SDRAM
interface
T_SLRF
TDM_DX
TDM_DR
TDM_FSX
TDM_CLK
TDM
IR_IN
VFD_CLK
VFD_STB
VFD_DATA
U0_DI
IR
VFD
UART
GPIOs
V_FSAD
J
Video
output
interface
V_COMP
U0_DO
V_REFOUT
V_REFIN
V_DACO[5:0]
Other
GPIOs
© Sunplus Technology Co., Ltd.
Proprietary & Confidential
8
OCT. 07, 2003
Preliminary Version: 0.2
Preliminary
SPHE8200A
4.3. Pin Description
Signal
Pin
State
Description
Supply Pins (51)
VSS_K*
VSS_O*
30, 47, 79, 100, 124,
S
S
Ground pins for chip kernel logic
142
36, 63, 90, 107, 116,
Ground pins for chip output
132, 152
VSS_K6/O7
VDD_K*
172
S
S
Shared ground pin
24, 42, 76, 95, 120,
1.8V power supply pins for chip kernel logic and input pre-driver
3.3V power supply pins for output pins
137, 177
VDD_O*
32, 55, 85, 105, 112,
S
128, 147, 167,
VSS_PLLV
VDD_PLLV
VSS_PLLA
VDD_PLLA
VDD_TVA*
VSS_TVA*
VSS_ADA
VDD_ADA
PWM_VSS
PWM_VDD
DA_VSS
DA_VDD
PLLVDD
73
S
S
S
S
S
S
S
S
S
S
S
S
S
S
S
S
S
S
Ground pin for system PLL
1.8V power supply pin for system PLL
Ground pin for audio PLL
3.3V power supply pin for audio PLL
3.3V power supply pin for TV DAC
Ground pin for TV DAC
72
75
74
183, 187, 191
184. 188. 192
162
161
201
194
202
205
213
216
6
Ground pin for on-chip audio ADC
3.3V power supply pin for on-chip audio ADC
Servo PWM ground (digital)
Servo PWM 3.3V power (digital)
Servo DAC ground
Servo DAC 3.3V power
Servo PLL 3.3V power
PLLVSS
Servo PLL ground
SVSS
Servo analog ground
SVDD
4
Servo analog 3.3V power
Servo ADC ground
ADVSS
18
ADVDD
11
Servo ADC 3.3V power
System Control Pin
RST_B
33
I
System reset (active low reset)
ROM / SRAM / Flash Interface (33)
R_A[8]
34
35
37
38
39
40
41
43
44
45
O
O
O
O
O
O
O
O
ROM / SRAM / flash address bus bit [8]
ROM / SRAM / flash address bus bit [9]
ROM / SRAM / flash address bus bit [10]
ROM / SRAM / flash address bus bit [11]
ROM / SRAM / flash address bus bit [12]
ROM / SRAM / flash address bus bit [13]
ROM / SRAM / flash address bus bit [14]
ROM / SRAM / flash address bus bit [15]
R_A[9]
R_A[10]
R_A[11]
R_A[12]
R_A[13]
R_A[14]
R_A[15]
R_D[7]
R_D[6]
I/O
I/O
ROM / SRAM / flash data bus [7]
ROM / SRAM / flash data bus [6]
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OCT. 07, 2003
Preliminary Version: 0.2
Preliminary
SPHE8200A
Signal
R_D[5]
Pin
46
48
49
50
51
52
53
54
56
57
58
59
60
61
62
64
65
66
State
I/O
I/O
I/O
I/O
I/O
I/O
O
Description
ROM / SRAM / flash data bus [5]
ROM / SRAM / flash data bus [4]
ROM / SRAM / flash data bus [3]
ROM / SRAM / flash data bus [2]
ROM / SRAM / flash data bus [1]
ROM / SRAM / flash data bus [0]
R_D[4]
R_D[3]
R_D[2]
R_D[1]
R_D[0]
R_A[0]
R_A[1]
R_A[2]
R_A[3]
R_A[4]
R_A[5]
R_A[6]
R_A[7]
R_A[16]
R_A[17]
R_A[18]
R_A19/GPIO
ROM / SRAM / flash address bus bit [0]
ROM / SRAM / flash address bus bit [1]
ROM / SRAM / flash address bus bit [2]
ROM / SRAM / flash address bus bit [3]
ROM / SRAM / flash address bus bit [4]
ROM / SRAM / flash address bus bit [5]
ROM / SRAM / flash address bus bit [6]
ROM / SRAM / flash address bus bit [7]
ROM / SRAM / flash address bus bit [16]
ROM / SRAM / flash address bus bit [17]
ROM / SRAM / flash address bus bit [18]
ROM / SRAM / flash address bus bit 19 or GPIO
O
O
O
O
O
O
O
O
O
O
I/O
Priority selection
sft_cfg0[0]=1’b1
sft_cfg2[4:2]=3’b010
(other)
Function
R_A19 (default)
UART0 TX
GPIO[32]
R_OE_B/GPIO
R_WE_B/GPIO
67
68
I/O
I/O
ROM / SRAM / flash output enable or GPIO
Priority selection
sft_cfg1[4]=1’b1
sft_cfg4[2:0]=3’b100
(other)
Function
R_OE_B (default)
DSP FL0
GPIO[33]
ROM / SRAM / flash write strobe or GPIO
Priority selection
sft_cfg1[5]=1’b1
sft_cfg4[5:3]=3’b100
(other)
Function
R_WE_B (default)
DSP FL1
GPIO[34]
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Preliminary Version: 0.2
Preliminary
SPHE8200A
Signal
Pin
State
Description
ROM / SRAM / flash chip select #1 (first device) or GPIO
R_CS1_B/GPIO
69
I/O
Priority selection
sft_cfg1[0]=1’b1
(other)
Function
R_CS1_B (default)
GPIO[13]
R_CS2_B/GPIO
R_CS3_B/GPIO
70
71
I/O
I/O
ROM / SRAM / flash chip select #2 or GPIO
Priority selection
sft_cfg1[1]=1’b1
sft_cfg4[8:6]=3’b100
(other)
Function
R_CS2_B (default)
DSP FL2
GPIO[35]
ROM / SRAM / flash chip select #3 or GPIO
Priority selection
sft_cfg1[2]=1’b1
sft_cfg4[11:9]=3’b100
(other)
Function
R_CS3_B (default)
DSP FLAGOUT
GPIO[36]
Crystal / Clock Pins (2)
CLKIN
78
77
I
Clock input / crystal in (XTALI)
Clock output / crystal out (XTALO)
SDRAM Interface Pins (57)
SDRAM data bus [7]
CLKOUT
O
M_DD[7]
M_DD[6]
M_DD[5]
M_DD[4]
M_DD[3]
M_DD[2]
M_DD[1]
M_DD[0]
M_WE_B
M_CAS_B
M_RAS_B
M_CS_B
M_BA0
80
81
82
83
84
86
87
88
89
91
92
93
94
96
97
98
99
101
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
O
SDRAM data bus [6]
SDRAM data bus [5]
SDRAM data bus [4]
SDRAM data bus [3]
SDRAM data bus [2]
SDRAM data bus [1]
SDRAM data bus [0]
SDRAM write enable / row precharge
SDRAM column address strobe
SDRAM row address strobe / precharge
SDRAM chip select
O
O
O
O
SDRAM bank select address [0]
SDRAM data bus [15]
M_DD[15]
M_DD[14]
M_DD[13]
M_DD[12]
M_DD[11]
I/O
I/O
I/O
I/O
I/O
SDRAM data bus [14]
SDRAM data bus [13]
SDRAM data bus [12]
SDRAM data bus [11]
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Preliminary Version: 0.2
Preliminary
SPHE8200A
Signal
M_DD[10]
Pin
102
103
104
106
108
109
State
I/O
I/O
I/O
O
Description
SDRAM data bus [10]
SDRAM data bus [9]
SDRAM data bus [8]
SDRAM clock output
SDRAM clock enable
M_DD[9]
M_DD[8]
M_CLKO
M_CKE
O
M_A[11]/GPIO
I/O
SDRAM address bus [11] or GPIO
Priority selection
Function
sft_cfg6[4]=1’b1
(other)
M_A[11] (default)
GPIO[14]
M_A[9]
M_A[8]
M_A[7]
M_A[6]
M_A[5]
M_A[4]
M_DQM1
M_DQM0
M_BA1
110
111
113
114
115
117
118
119
121
O
O
O
O
O
O
O
O
O
SDRAM address bus [9]
SDRAM address bus [8]
SDRAM address bus [7]
SDRAM address bus [6]
SDRAM address bus [5]
SDRAM address bus [4]
SDRAM data input/output mask for M_DD[15:8]
SDRAM data input/output mask for M_DD[7:0]
SDRAM bank select address [1]
Priority selection
sft_cfg6[6]=1’b1
(other)
Function
M_BA1
GPIO[15]
M_A[10]
122
123
125
126
127
129
130
131
133
134
135
136
138
139
140
141
143
O
SDRAM address bus [10]
SDRAM address bus [0]
SDRAM address bus [1]
SDRAM address bus [2]
SDRAM address bus [3]
SDRAM data bus bit 31
SDRAM data bus bit 30
SDRAM data bus bit 29
SDRAM data bus bit 28
SDRAM data bus bit 27
SDRAM data bus bit 26
SDRAM data bus bit 25
SDRAM data bus bit 24
M_A[0]
O
M_A[1]
O
M_A[2]
O
M_A[3]
O
M_DD[31]
M_DD[30]
M_DD[29]
M_DD[28]
M_DD[27]
M_DD[26]
M_DD[25]
M_DD[24]
M_DQM3/GPIO
M_DQM2/GPIO
M_DD[23]
M_DD[22]
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
SDRAM data input/output mask for M_DD[31:24]
SDRAM data input/output mask for M_DD[23:16]
SDRAM data bus bit 23
SDRAM data bus bit 22
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Signal
M_DD[21]
Pin
144
145
146
148
149
150
151
State
I/O
I/O
I/O
I/O
I/O
I/O
I/O
Description
SDRAM data bus bit 21
SDRAM data bus bit 20
SDRAM data bus bit 19
SDRAM data bus bit 18
SDRAM data bus bit 17
SDRAM data bus bit 16
M_DD[20]
M_DD[19]
M_DD[18]
M_DD[17]
M_DD[16]
M_A[12]/GPIO
SDRAM address bus [12] or GPIO
Priority selection
Function
sft_cfg6[5]=1’b1
(other)
M_A[12] (default)
GPIO[18]
Audio Interface (10)
A_DATA[4] / GPIO
A_IEC_RX/GPIO
A_IEC_TX/GPIO
A_DATA[0] / GPIO
A_DATA[1] / GPIO
163
164
165
166
168
I/O
I/O
I/O
I/O
I/O
Serial audio data output for channel 9/8 or GPIO
Priority selection
sft_cfg3[5]=1’b1
(other)
Function
A_DATA[4] (default)
GPIO[57]
IEC-958 receive data
Priority selection
sft_cfg3[7]=1’b1
(other)
Function
A_IEC_RX (default)
GPIO[58]
IEC-958 transmit data
Priority selection
sft_cfg3[7]=1’b1
(other)
Function
A_IEC_TX (default)
GPIO[19]
Serial audio data output for channel 1/0 or GPIO
Priority selection
sft_cfg3[7]=1’b1
(other)
Function
A_DATA[0] (default)
GPIO[20]
Serial audio data output for channel 3/2 or GPIO
Priority selection
sft_cfg3[7]=1’b1
(other)
Function
A_DATA[1] (default)
GPIO[21]
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SPHE8200A
Signal
Pin
State
Description
A_DATA[2] / GPIO
169
I/O
Serial audio data output for channel 5/4 or GPIO
Priority selection
sft_cfg3[3]=1’b1
(other)
Function
A_DATA[2] (default)
GPIO[59]
A_DATA[3] / GPIO
A_LRCK/GPIO
A_BCK/GPIO
170
171
173
174
I/O
I/O
I/O
I/O
Serial audio data output for channel 7/6 or GPIO
Priority selection
sft_cfg3[4]=1’b1
(other)
Function
A_DATA[3] (default)
GPIO[60]
PCM data output L/R strobe
Priority selection
sft_cfg3[6]=1’b1
(other)
Function
A_LRCK (default)
GPIO[61]
PCM bit clock
Priority selection
sft_cfg3[7]=1’b1
(other)
Function
A_BCK (default)
GPIO[22]
A_XCK/GPIO
Audio over-sampling clock
Priority selection
sft_cfg3[7]=1’b1
(other)
Function
A_XCK (default)
GPIO[23]
GPIO (7)
GPIO
31
I/O
GPIO pin
Priority selection
sft_cfg2[8:5]=4’b1110
sft_cfg1[6]=1’b1
Function
UART1_TX
ISA_CH_RDY
DSP_IRQE
sft_cfg5[2:0]=3’b011
sft_cfg5[8:6]=3’b011
sft_cfg5[11:9]=3’b011
sft_cfg5[14:12]=3’b011
(other)
RI_INT[12]
RISC_INT[3]
RISC_INTE[1]
GPIO[4] (default)
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Preliminary
SPHE8200A
Signal
Pin
State
Description
GPIO (for IR) or TDM data receive
IR_IN/TDM_DR
153
I/O
Priority selection
sft_cfg4[14:13]=2’b10
(other)
Function
TDM_DR
GPIO[53] (default)
VFD_CLK/TDM_D
X
154
155
156
I/O
I/O
I/O
GPIO (for VFD clock) or TDM data transmit
This pin must be pull-high to 3.3v.
Priority selection
sft_cfg4[14:13]=2’b10
(other)
Function
TDM_DX
GPIO[54] (default)
VFD_STB/TDM_FS
X
GPIO (for VFD strobe) or TDM frame sync
This pin must be pull-high to 3.3v.
Priority selection
sft_cfg4[14:13]=2’b10
(other)
Function
TDM_FSXR
GPIO[55] (default)
VFD_DATA/TDM_C
LK
GPIO (for VFD data) or TDM clock
This pin must be pull-high to 3.3v.
Priority selection
Function
sft_cfg4[14:13]=2’b10
(other)
TDM_CLK
GPIO[56] (default)
UA0_RX/GPIO
UA0_TX/GPIO
175
176
I/O
I/O
UART #0 data receive or GPIO
Priority selection
Function
sft_cfg2[4:2]=3’b101
(other)
UART0_RX (default)
GPIO[62]
UART #0 data transmit or GPIO
Priority selection
Function
sft_cfg2[4:2]=3’b101
(other)
UART0_TX (default)
GPIO[63]
Audio ADC pins (4)
AIN/AIN_L
AI_BCK
157
A
ADC input (left channel, with OP)
(bonding option) Digital audio input interface bit clock
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Preliminary Version: 0.2
Preliminary
SPHE8200A
Signal
Pin
State
Description
ATO
158
A
ADC OP output. When not used, connect a 0.1uF to ground.
(bonding option) Digital audio input interface L/R strobe
ADC input (right channel)
(bonding option) Digital audio input interface data
ADC input voltage reference. When not used, connect a 0.1uF to ground.
TV DAC (10)
AI_LRCK
AIN_R
AI_DATA
VM
159
160
178
A
A
A
V_COMP
Compensation pin. A 0.1pF ceramic capacitor must be used to bypass this pin to
VSSA. The lead length must be kept as short as possible to avoid noise.
V_BIAS
179
180
V_FSADJ
A
A
A
A
A
A
A
A
Full-Scale adjustment control pin. The full-scale current of D/A converters can be
adjusted by connecting a resistor (RSET) between this pin and ground.
Voltage reference output. It generates typical 1.2V voltage reference and may be
used to drive V_REFIN pin directly.
V_REFOUT
V_DAC[0]
V_DAC[1]
V_DAC[2]
V_DAC[3]
V_DAC[4]
V_DAC[5]
181
182
185
186
189
190
193
Video DAC output #0. This is a high-impedance current source output. These
outputs can drive a 37.5 Ω load directly.
Video DAC output #1. This is a high-impedance current source output. These
outputs can drive a 37.5 Ω load directly.
Video DAC output #2. This is a high-impedance current source output. These
outputs can drive a 37.5 Ω load directly.
Video DAC output #3. This is a high-impedance current source output. These
outputs can drive a 37.5 Ω load directly.
Video DAC output #4. This is a high-impedance current source output. These
outputs can drive a 37.5 Ω load directly.
Video DAC output #5. This is a high-impedance current source output. These
outputs can drive a 37.5 Ω load directly.
Servo Digital Interface (16)
TRAY_OUT
SC1_OUT
SPDC_OUT
SC_OUT
195
196
197
198
199
200
19
(Servo digital pins)
(Servo digital pins)
(Servo digital pins)
(Servo digital pins)
DMEA
(Servo digital pins)
FGIN
(Servo digital pins)
SRV_SCLK
SRV_SDATA
SRV_SDEN
SRV_DFCT
T_PLCK
(Servo digital pins)
20
(Servo digital pins)
21
(Servo digital pins)
22
(Servo digital pins)
23
(Servo digital pins)
T_SLRF
25
(Servo digital pins)
TDM_DX/ttin0_4/G
PIO
26
I/O
I/O
TDM output data or GPIO
TDM_CLK/ttin1_5/
GPIO
27
TDM master clock or GPIO
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Preliminary
SPHE8200A
Signal
Pin
State
Description
TDM input/output frame signal or GPIO
TDM_FSXR/ttin2_6
/GPIO
28
I/O
TDM_DR/ttin3_7/G
PIO/R_CS4_B
29
I/O
TDM input data or GPIO
Servo Analog Interface (25)
(Servo analog pins)
(Servo analog pins)
(Servo analog pins)
(Servo analog pins)
(Servo analog pins)
(Servo analog pins)
(Servo analog pins)
(Servo analog pins)
(Servo analog pins)
(Servo analog pins)
(Servo analog pins)
(Servo analog pins)
(Servo analog pins)
(Servo analog pins)
(Servo analog pins)
(Servo analog pins)
(Servo analog pins)
(Servo analog pins)
(Servo analog pins)
(Servo analog pins)
(Servo analog pins)
(Servo analog pins)
(Servo analog pins)
(Servo analog pins)
(Servo analog pins)
TEO
203
204
206
207
208
209
210
211
212
214
215
1
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
FEO
HGIN
LGIN2
LGIN1
LPFNIN
PDFLT1
FDFLT
VREFO
PDRSET
FDRSET
DRESET
CNIN
2
SLVL
3
RFO
5
RFRP
RFRPLP
TEXOLP
TEXO
TEI
7
8
9
10
12
13
14
15
16
17
FEI
CSI
SBAD
VREF
VRGD
Note: Please reference SPHE8200 servo datasheet for servo related information.
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Preliminary Version: 0.2
Preliminary
SPHE8200A
5.FUNCTIONAL DESCRIPTIONS
SPHE8200 is
a highly integrated system-on-chip design. It
XCK
PLLa
147.456MHz
135.4752MHz
CLKI
27MHz
includes DVD/CD servo controller, RISC processor, MPEG1/2
video decoder, programmable audio decoder, programmable
peripheral controller, audio ADC and multi-format TV-encoder on a
single chip.
CLK_PLLA
AUDCLK_GEN
ADCLK
IECCLK
5.2. Power Control
5.1. PLL and ClockGen
SPHE8200 provides various levels of power-control mechanism in
order to achieve minimum power consumption.
SPHE8200 contains two PLLs to generate system clock (PLLv)
and audio reference clocks (PLLa). Both the PLLs reference a
single external 27MHz clock or crystal to generate all the required
clocks.
ꢀAutomatic power-save:
Most hardware modules are automatically power-saved when
not operating.
System clock is then derived from division of the PLLv output.
ꢀModule-level stop-operation:
SPHE8200 provides a function to turn off specific module from
operating. Without explicit wake-up, the hardware module will
remain static and consume very little power.
ꢀSystem-level doze:
PLLv
CLKI
27MHz
SYSCLK_GEN
/2, /4 ~ /65536
CLK_PLL
SYSCLK
VIDCLK
Fractional multiples
of CLKI
For maximum power-saving, firmware could fine-tune system
performance according to system task.
Option Video Clock In
VIDCLK_GEN
5.3. Embedded 32-bit RISC Controller
SPHE8200 includes a powerful 32-bit RISC processor. This RISC
processor is utilized to manage decoding tasks as well as UI tasks.
It can access to all the memory and devices, cooperate between
processor systems. Audio decoder and I/O processor handshake
with RISC processor through the mailbox registers.
Some pre-defined PLLv/SYSCLK frequencies are listed below:
SYSCLK Frequency
101.25MHz
108MHz
PLLV Frequency
405MHz
216MHz
114.75MHz
121.5MHz
128.25MHz
135MHz
459MHz
486MHz
256.5MHz
270MHz
Audio
mailbo
(16x16
decoder
RISC
subsyste
141.75MHz
148.5MHz
155.25MHz
162MHz
283.5MHz
297MHz
I/O
processo
mailbo
(16x8)
310.5MHz
324MHz
168.75MHz
175.5MHz
182.25MHz
189MHz
337.5MHz
351MHz
Figure 5-1: Communication between processors
364.5MHz
378MHz
The RISC processor is equipped with instruction and data caches.
These caches can accelerate accesses to the SDRAM or ROM
cacheable regions.
PLLa supports two center frequencies (for 48kHz family or
44.1kHz family) and generates required audio clocks from the
audio system clock.
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SPHE8200A
edge-trigger and level-sensitive mode.
ꢀWatchdog:
I-CACHE
Peripheral
Control bus
Other
modules
Watchdog keeps monitoring RISC behavior and whenever
firmware is in a deadlock, it can try to reset the system and
keep the application functioning continuously.
RISC32
core
BIU
ROM
FLASH
SRAM
ROM/Flash
interface
D-CACHE
ꢀTimers
System Bus
Interface
DRAM
D-RAM
DMA
There are 4-channel timers and 2 cascade counters for timed
tasks. During A/V decoding, counters are utilized to
synchronize audio and video.
Figure 5-2: RISC subsystem
Table: RISC processor configuration
Specification
RISC
subsystem
RISC
monitor
monitor
interrupt
I-Cache
8kbyte (2-way set associated)
4kbyte (direct-mapped)
1kbyte scratch buffer
D-Cache
to RISC interrupt
watchdog
reset
Watchdog
Timers
D-RAM/DMA
Device
interrupt
controller
The RISC sub-system is able to bootstrap from multiple sources.
In typical application the RISC processor boots from external ROM
device #1. Besides that, it also supports standalone booting
without pre-loaded firmware.
timer
interrupt
Figure 5-3: RISC dedicated hardware
Table: Device interrupt controller sources
5.4. RISC interface
Symbol
INT_WDOG
INT_HSYNC
INT_VSYNC
INT_FLD_ACT
Description
RISC controllers interface to system via various interface control
modules. These interface modules are mapped to the processor
memory map and firmware could operate on them via typical
memory accesses. These controllers include:
Watchdog interrupt (if reset disabled)
Interrupt when horizontal resync
Interrupt when enter vertical resync
Interrupt when enter active region
ꢀROM/FLASH/SRAM (RFS) controller
INT_FLD_SYNC Interrupt when leave active region
ꢀRISC Memory Interface controller (SDRAM)
INT_HOST
INT_TIMER0
INT_TIMER1
INT_TIMER2A
INT_TIMER2B
INT_TIMER3A
INT_TIMER3B
INT_TIMERW
INT_UART0
INT_UART1
INT_VDP0
Host device interrupt
Timer 0 interrupt
ꢀPeripheral control interface
Timer 1 interrupt
The RISC memory mapping of these controllers is shown in
following table:
Table: RISC memory mapping
Timer 2 scale interrupt
Timer 2 count interrupt
Timer 3 scale interrupt
Timer 3 count interrupt
Watchdog timer interrupt
UART0 interrupt
Memory range
Description
SDRAM (cached)
8000_0000-87ff_ffff
a000_0000-a7ff_ffff
8800_0000-8fbf_ffff
a800_0000-afbf_ffff
affe_8000-affe_ffff
afff_0000-afff_03ff
SDRAM (uncached)
ROM/FLASH/SRAM (cached)
ROM/FLASH/SRAM (uncached)
Peripheral control registers
DMA buffer
UART1 interrupt
Video decoder interrupt
DSP interrupt
INT_DSP
INT_EXT0
External interrupt #0
External interrupt #1
External interrupt #2
External interrupt #3
IOP interrupt
INT_EXT1
In additional to that, SPHE8200 includes dedicated RISC
peripherals to assist the system tasks:
INT_EXT2
INT_EXT3
ꢀDevice interrupt controller:
Device interrupt controller takes care of interrupt sources from
on-chip devices and off chip sources. For each interrupt source
the firmware is able to configure the interrupt behavior between
INT_IOP
INT_AUD
Audio hardware interrupt
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SPHE8200A
5.5. ROM/Flash/SRAM controller
5.7. Peripheral Control Interface
The SPHE8200 provides flexible connections to external ROM,
Flash or SRAM (RFS). It can support up to 4 external RFS devices
by using different chip-selects (R_CS_B[3:0]). The firmware can
configure RFS memory anchor registers and map these devices
into locations of memory space. For each memory space it can
be in flash mode or in ISA mode. In FLASH mode the access
timing is decided by wait-state setting, while in ISA mode the
controller will reference external IO_CHRDY input.
RISC firmware controls on-chip devices (such as video decoder,
audio decoder..) by a dedicated peripheral control interface.
Firmware controls the hardware behavior by writing to specific
hardware registers with this interface.
5.8. CSS/CPPM support
SPHE8200 have built-in CSS and CPPM hardware support. For
CSS the system supports accelerated DMA. For CPPM the
system supports C2_D/C2_E and C2_DCBC functions.
Prefetch
buffer
5.9. MPEG Video Decoder
The system incorporates a powerful MPEG video decoding
datapath and provides real-time video decoding of MPEGI/II
bitstream. The bitstream can come from Servo hardware, ATAPI,
TDM or UART. This enables various applications to be built over
SPHE8200 such as real-time broadcasting over Ethernet.
External
ROM
interface
Processor
local bus
Address
translator
Address
sequencer
Wait state
generation
The video decoder is a hardwired MPEG1/2 datapath. The system
architecture is as in the figure. RISC subsystem is in charge of
de-multiplexing the data and buffering formatted video data into
video bitstream buffer resided in external SDRAM. Upon correct
timing video decoder will decode the bitstream and write back
reconstructed video frame for playback.
Figure 5-4: ROM/FLASH/SRAM controller
ROM/Flash mode
wait
wait
CSB
ADDR[]
Address (read)
Address (write)
oe_setup
oe_hold
OEB
WEB
we_setup
we_hold
DATA[]
Data (read)
DATA (for write)
RISC
subsystem
Video
decoder
control bus
data is sampled at this point
Figure 5-5: ROM/FLASH/SRAM mode timing
ISA MODE
CSB
memory bus
wait
iochrdy_hold
wait
iochrdy_hold
ADDR[]
OEB
Address (read)
Address (write)
oe_setup
oe_hold
External
SDRAM
we_setup
we_hold
WEB
IO_RDY
DATA[]
Data (read)
DATA (for write)
Figure 5-7: Interface between RISC and Video decoder
data is sampled at this point
Figure 5-6: ISA mode timing
Advanced video decoding and display control mechanism is
included to prevent tearing effect.
5.6. RISC Memory Interface
RISC memory interface provides a fast-path between processor
local bus and system memory bus. Local bus transactions are
mapped to system memory bus tasks.
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ꢀVideo contrast/bright/color enhancement
During runtime video post-processing hardware will fetch video
sources from framebuffer and process the data as in the following
figure.
Picture
control
Q matrix
Variable
length
decoder
input
FIFO
Inverse
quantization
line
buffer
Memory
Interface
Vertical
filtering
chroma
resampl
input
buffer
CIF and
horizonta
expansio
to
Inverse DCT
de-interlac
display
interface
Motion
compensation
from
memory
interface
input
buffer
output
buffer
DCT
buffer
de-interlac
buffer
display
information
Decoding
control
5.12. Audio DSP
Figure 5-8: architecture of video decoding pipeline
The SPHE8200 contains a high-performance 24-bit audio DSP
optimized for embedded systems. The DSP processor can fetch
5.10. Graphics Engine BondyPro®
operands
from
memories
and
perform
During
For thin-client or set-top box applications, 2D graphics capabilities
are key to system performance. This graphics engine is able to
perform fast BitBlt and 2D drawing functions. The graphics engine
is combined with 2 parts: graphics command interpreter and
graphics datapath. Upon receiving command from RISC,
interpreter will send micro-commands to graphics datapath, where
raster operations are executed.
multiplication-and-accumulation (MAC) in one cycle.
execution the DSP fetches instruction from main-memory or IROM,
at the same time the ICACHE will store the LRU instructions.
Data are loaded from and to main-memory by using the
cycle-stealing DMA channels. There are
3
independent
cycle-stealing DMA channels that allow DSP run without stalled by
memory access.
The DSP works closely with RISC processors by using mailbox
registers or shared-memory protocol. When downloaded with
different codec firmware the DSP could support multi-standard
audio and act as an accelerator for RISC in some case.
Grap
Grap
comma
data
interpret
RISC
subsyste
Graph
work
Memo
Interfa
IROM
Figure 5-9: BondyPro® architecture
ICACHE
5.11. Video Post Processing
data
ROM
Memory
interface
DSP
BIU
SPHE8200 includes powerful video-post-processing facilities to
provide high video quality. It perform following functions:
ꢀYUV411, YUV420, YUV422 and 8-bit indexed color
ꢀSIF to CCIR601 interpolation
data
RAM
data
RAM
ꢀMPEG1 CIF filter
data
audio
ROM
ꢀMPEG1/2 chroma vertical interpolation
ꢀUp to 1/2x horizontal decimation
interface
controller
ꢀUp to 1/512x vertical decimation
Figure 5-10: Audio DSP architecture
ꢀUp to 1024x horizontal expansion
ꢀUp to 1024x vertical expansion
ꢀPowerful de-interlacing hardware
ꢀPan and scan function
ꢀDe-flicker during interlaced display
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5.13. Audio Interface
For power-constrained applications SPHE8200 also implements
SDRAM power-down modes to save dynamic operating power.
The audio interface is in charge of servicing DSP and maintaining
all audio-related tasks. It will buffer the DSP processed audio
playback data and format them to audio DAC required format.
5.17. Sub-picture Decoder
For DVD and SVCD sub-picture content SPHE8200 includes an
advanced multi-format sub-picture decoder. It could support
real-time decode and display from raw sub-picture bitstream.
Vertical interpolation is supported for PAL/NTSC translation or
special effect.
Buffer
control
IEC958
IEC-958 input
digital input
interface
digital audio input
Memory
Interface
ADC ctrl
ADC
analog in
Audio
work
5.18. On Screen Display
buffer
The on screen display (OSD) function of the SPHE8200 provides
an overlay bitmap graphics on the final TV display. Applications
can use this function to display specific information over the video
display plane without operating on the video source.
PCM
playback
digital audio output
IEC-958 output
IEC958
The SPHE8200 can display multiple OSD regions on a single
display frame, where every OSD regions can be in different size,
location and color format. The OSD hardware supports 4, 16,
256 indexed color or 16-bit direct color. OSD regions are stored
in main memory before display. During display, OSD decoder
would read these header and data and interpret to be a graphic
data that overlay with video to be output to the display interface.
Figure 5-11: Audio Interface architecture
SPHE8200 support following audio DAC format combinations:
32k
ok
44.1k
ok
48k
ok
64k
ok
88.2k
ok
96k
ok
192k
ok
256fs
384fs
ok
ok
ok
ok
ok
ok
ok
5.19. Display Interface
Data alignment
LRCK frame width
Data bits
Left adjust, I2S, normal format
16b, 24b, 32b, 64b
The display interface of SPHE8200 integrates the video content
generated from video-post-processing, sub-picture-decoder and
on-screen-display modules. It also performs content cropping,
underflow and overflow detection, and overall bright/contrast
adjustment.
16b, 18b, 20b, 24b
Data sign extension
zero-extended, sign-extended
5.14. Integrated Audio Quality ADC
The embedded ADC is a 2-channel 64fs over-sampling ADC
of12-bit quality. If required it could operate under 128fs
over-sampling.
Video
active
Sub-picture
active
OSD
active
(1.0 - sup_blend_factor)
blank (black)
Video processed
source data
5.15. I/O Processor
TV data
output
The SPHE8200 includes an 8-bit micro-controller to handle most
I/O jobs. IR, VFD and other slow devices can be interfaced using
this I/O processor.
sub-picture source data
OSD source
(1.0 - osd_blend_factor)
(osd_blend_factor)
(sup_blend_factor)
5.16. SDRAM Controller
Figure 5-12: Display pipeline
SDRAM controller in SPHE8200 is very flexible and powerful. It
was designed to meet different SDRAM timing requirement while
achieving maximum performance. SDRAM tasks are optimized for
maximum system performance. DRAM refreshing is issued
automatically whenever required or SDRAM interface is idle for a
given time.
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The video enhancement process is show in following figure:
ATA/ATAPI compliant devices directly. The ATAPI/IDE interface is
a standard ATA-5 host interface capable of PIO mode 2 to PIO
mode 4 to external devices. By implementing this interface system
could support IDE hard-disk drives, compact flash cards, ATAPI
based DVDROM loaders or other ATA compliant devices.
OSD
sub-picture
Video
post processing
analog
video
Display interface
vid[]
TV-encoder
dac[]
DAC
video source
enhancement and bright/
contrast/color control
DAC gain, linearity
adjustment
5.22. GPIO
In SPHE8200 almost every pin that related to selectable features
can serve as general-purpose input-output control function. When
a pin is programmed to this mode, the RISC can take full control
over the direction and output level.
Figure 5-13: Display pipeline
5.20. Video DAC
SPHE8200 contains 6-channel 10-bit high-speed current-source
DACs operating from 27MHz to 60MHz (for 480p/576p or SVGA
display). The DAC outputs can drive a 37.5Ohm load directly.
5.23. UART
Two UART channels are provided for debugging or
communication purpose. The UART can support standard serial
port baud-rate and formats. It also supports auto baud-rate
detection and hardware flow-control (CTS/RTS pair).
5.21. ATAPI interface
SPHE8200 also supports ATAPI interface directly without glue
logic. Although the SPHE8200 has integrated DVD/CD servo
logics, with this interface the application could support other
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6.ELECTRICAL SPECIFICATIONS
6.1. Absolute Maximum Ratings
Parameter
Symbol
VIN
Value
-0.3 to 5.5
Unit
V
Voltage on any pin relative to Vss
Voltage on VDDIO supply relative to VSS
Voltage on VDDK supply relative to VSS
Storage Temperature
VDDIO
VDDK
-0.3 to 3.6
V
-0.3 to 1.98
-55 to 150
V
TSTG
°C
°C
mA
Soldering Temp. (Max. Time)
Short circuit current
TSOLDER
IOS
240 (for 5 Sec. Max.)
50
Note: Stresses above those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. Functional operation
of this device at these or any other conditions above those indicated in the operational sections of this specification is not implied and
exposure to absolute maximum rating conditions for extended periods may affect device reliability.
6.2. DC Operating Conditions
Recommended Operating Conditions (Voltage referenced to VSS=0V, TA=-0 to 70°C)
Parameter
Voltage on VDDK supply relative to VSS
Voltage on VDDIO supply relative to VSS
Input logic high voltage
Symbol
VDDK
VDDIO
VIH
Min.
1.62
3.0
2.0
-0.3
2.4
-
Typ.
Max.
1.98
3.6
5.5
0.8
-
Units
V
1.8
3.30
V
-
-
-
-
-
V
Input logic low voltage
VIL
V
Output logic high voltage
Output logic low voltage
VOH
VOL
V
0.4
10
V
Input leakage current
IL
-10
uA
6.3. Capacitance
(VDDIO=3.3V, TA=24°C, f=108MHz, VREF=1.4V+-200mV)
Parameter
Symbol
CIN
Min.
Typ.
3.5
Max.
Units
pF
Input pin capacitance
-
-
-
-
-
-
Input pin capacitance
COUT
3.5
pF
Bidirectional pin capacitance
CBIDIR
3.5
pF
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6.4. AC Characteristics
6.4.1. SDRAM interface timing diagrams
tCH
0
2
3
4
5
6
7
8
9
10
11
12
1
13
14
15
16
17
18
19
CLOCK
CKE
tCL
tCC
tRAS
tRC
CS
tRP
tSH
tSS
RAS
CAS
tCCD
tRCD
RAa
CAa
RBb
RBb
CBb
RAc
CAc
ADDR
BA
RAa
RAc
DBb1
DBb1
A10/AP
*Note 1
tRRD
tCDL
DQ CL=2
CAa0
CAa1
CAa0
CAa2
CAa3
DBb0
DBb0
DBb2
DBb2
DBb3
CAc0
CAc1
CAc0
CAc2
CAc1
tSAC
tSLZ
CAa1
CAa2
CAa3
DBb3
CL=3
WE
DH
DQM
Row Active
(A-Bank)
Read
(A-Bank)
Row Active
(B-Bank)
Write
Read
(A-Bank)
(B-Bank)
: Don't care
Precharge
(A-Bank)
Row Active
(A-Bank)
0
2
3
4
5
6
7
8
9
10
11
12
1
13
14
15
16
17
18
19
CLOCK
HIGH
CKE
CS
RAS
CAS
ADDR
BA
RAa
RAa
CAa
CAb
A10/AP
tBDL
tRDL
DQ
WE
DAa0
DAa1
DAa2
DAa3
DAa4
DAb0
DAb1
DAb2
DAb3
DAb4
DAb5
DQM
Row Active
(A-Bank)
Write
(A-Bank)
Write
Precharge
(A-Bank)
Burat Stop
(A-Bank)
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(Recommended condition for DVD playback is listed in typical condition with f=121.5MHz)
Parameter
Row active to row active delay
RAS to CAS delay
Symbol
tRRD
tRCD
tRP
Min
1
1
1
1
1
1
1
6
-
Typ
2
Max
4 *1
4 *1
4 *1
8 *1
32 *1
4 *1
1
Units
System clock cycle
2
System clock cycle
Row precharge time
2
System clock cycle
Row active time
tRAS
tRC
5
System clock cycle
Row cycle time
8
System clock cycle
Last data in to new column address delay
Column address to column address delay
CLK cycle time *2
tCDL
tCCD
tCC
1
System clock cycle
1
System clock cycle
8.2
6.0
2
1000
6.5
-
ns
ns
ns
ns
ns
ns
ns
CLK to valid SDRAM output delay *2
SDRAM output data hold time *2
CLK high pulse width *3
tSAC
tOH
1
-
tCH
3
-
CLK low pulse width *3
tCL
-
3
-
CLK to SDRAM output Low-Z
CLK to SDRAM output High-Z
tSLZ
tSHZ
-
1.0
6.0
(tCC
)
-
(tSAC
)
*1Using maximum values may limit system performance.
*2Width of data window can be estimated from (tCC-tSAC+tOH).
*3Width of clock pulse depends on system clock cycle.
6.4.2. ROM / flash interface timing diagrams
ROM Compatible Mode
tACCESS
tACCESS
CSB
ADDR[]
OEB
Address (read)
Address (write)
tWES
tWEH
WEB
tDS
tDH
DATA[]
Data (read)
DATA (for write)
Figure 6-1: ROM / flash interface ROM mode access timing
Parameter
Symbol
tACCESS
tDS
Min
2
Typ
8 *1
-
Max
Units
System clock cycle
ns
ROM / SRAM / flash access time
Data setup time for read
31
-
5
Data hold time for read
tDH
0
-
-
ns
Address/data setup time before write strobe
Address/data setup time after write strobe
*1Recommended value when f=121.5MHz
tWS
0
1
31
31
System clock cycle
System clock cycle
tWH
0
1
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ISA Compatible Mode
tACCESS
tACCESS
CSB
ADDR[]
OEB
Address (read)
Address (write)
tWES
tWEH
tIH
tWAIT
tOH
WEB
tWAIT
tOH
tIH
IO_RDY
DATA[]
Data (read)
Data (write)
Figure 6-2: ROM / flash interface ISA mode access timing
Parameter
Symbol
tACCESS
tWAIT
tOH
Min
2
Typ
Max
31
1000
-
Units
System clock cycle
ns
ISA access time *1
IO_RDY wait time
Output hold time
Input hold time
-
-
0
1
-
System clock cycle
ns
tIH
0
-
-
Address/data setup time before write strobe
Address/data setup time after write strobe
tWS
0
1
1
31
31
System clock cycle
System clock cycle
tWH
0
*1After this period of time IO_RDY_B must be stable and indicates correct status of target device.
6.4.3. Audio interface timing diagrams
Some audio interface configuration timing diagrams are shown below.
0
1
22
23
0
1
2
22 23
BCK
LRCK
left channel
right channel
23 22 21
MSB
2
1
0
23 22 21
2
1
0
AUDATA[]
LSB MSB
LSB
Figure 6-3: Normal mode / 24bit data / 24bit frame / MSB first
0
1
8
9
30
31
0
1
30 31
0
BCK
LRCK
left channel
right channel
2
23 22 21
MSB
2
1
0
1
0
AUDATA[]
LSB
Figure 6-4: Right justified (normal) mode / 24bit data / 32bit frame / MSB first
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0
1
2
22
23 24
31
0
1
2
31
0
BCK
LRCK
left channel
1
right channel
23 22 21
MSB
0
LSB
23 22 21
AUDATA[]
Figure 6-5: Left justified mode / 24bit data / 32bit frame / MSB first
0
1
2
3
23 24 25
31
0
1
2
3
31
0
BCK
D
left channel
D
right channel
LRCK
23 22 21
MSB
2
1
0
23 22
AUDATA[]
LSB
Figure 6-6: I2S mode / 24bit data / 32bit frame
0
1
2
22
23
0
1
2
22 23
0
1
BCK
LRCK
left channel
D
0
right channel
D
23 22 21
MSB
2
1
23 22 21
2
1
0
AUDATA[]
LSB MSB
LSB
Figure 6-7: I2S mode / 24bit data / 24bit frame
Parameter
Symbol
Min
Typ
Max
Units
System clock cycle
BCK rising to LRCK / AUDATA transition
tS
-
0.5
-
6.4.4. Video timing diagrams
Interlaced Modes
SP active period
active line period
SP active period
active line period
V blanking period (21)
Video line number
522 523 524 525
1
2
3
4
5
6
7
8
9
10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29
10 12
SP line number
473 475 477 479
0
2
4
6
8
Video line number
260 261 262 263 264 265 266 267 268 269 270 271 272 273 274 275 276 277 278 279 280 281 282 283 284 285 286 287 288 289 290 291
SP line number
474 476 478
active line period
1
3
5
7
9
11
V blanking period (21)
active line period
SP active period
SP active period
Figure 6-8: NTSC (480i) timing diagram
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SP active period
active line period
SP active period
active line period
V blanking period (23.5)
Video line number
619 620 621 622 623 624 625
1
2
3
4
5
6
7
8
9
10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27
SP line number
567 569 571 573
0
2
4
6
8
Video line number
307 308 309 310 311 312 313 314 315 316 317 318 319 320 321 322 323 324 325 326 327 328 329 330 331 332 333 334 335 336 337 338 339 340
SP line number
474 476 478
active line period
1
3
5
7
9
V blanking period (24)
active line period
SP active period
SP active period
Figure 6-9: PAL (576i) timing diagram
Progressive Modes
SP active period
active line period
SP active period
active line period
522 523 524 525
1
2
3
4
5
6
7
8
9
10 11 12 13 14
44 45 46 47
521
48 49 50 51
476 477 478 479
0
1
2
3
4
5
6
Figure 6-10: NTSC (480p) timing diagram
SP active period
active line period
SP active period
active line period
617 618 619 620 621 622 623 624 625
572 573 574 575
1
2
3
4
5
6
7
8
9
43 44 45 46 47 48 49 50 51
0
1
2
3
4
5
6
Figure 6-11: PAL (576p) timing diagram
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7.REGISTER LIST
Name
GROUP 0
sft_cfg0
Address
Description
System Control Registers
Configure pin-mux 0
Configure pin-mux 1
Configure pin-mux 2
Configure pin-mux 3
Configure pin-mux 5
Configure pin-mux 6
0xbffe8044
0xbffe8048
0xbffe804c
0xbffe8050
0xbffe8058
0xbffe805c
sft_cfg1
sft_cfg2
sft_cfg3
sft_cfg5
sft_cfg6
0xbffe8044 sft_cfg0
Description
Pin MUX control register #0 (General)
Attribute: RW
15
14
13
12
11
10
RA24
9
8
7
6
5
4
3
2
1
0
Bit-field
Reset_2
Reset_3
Reset_*
RA26
RA25
RA23
RA22
RA21
RA20
RA19
1
0
1
0
1
1
1
0
1
0
1
1
1
0
0
0
1
0
1
0
0
0
1
0
1
0
0
0
1
0
1
0
0
0
1
0
1
0
0
0
1
0
1
1
1
Reset_2: reset default when hardware-configuration is set to 2
Reset_3: reset default when hardware-configuration is set to 3
Reset_*: reset default for other hardware-configuration
RA19
RA20
ROM address bus bit 19 (R_A19) select
0: R_A19 is not available and ignored
1: Enable (default)
ROM address bus bit 20 (R_A20) select
00: R_A20 is not available and ignored
01: R_A20 is available at pin 19
10: R_A20 is available at pin 129
11: Reserved
RA21
RA22
ROM address bus bit 21 (R_A21) select
00: R_A21 is not available and ignored
01: R_A21 is available at pin 20
10: R_A21 is available at pin 130
11: Reserved
ROM address bus bit 22 (R_A22) select
00: R_A22 is not available and ignored
01: R_A22 is available at pin 21
10: R_A22 is available at pin 131
11: reserved
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RA23
RA24
RA25
RA26
ROM address bus bit 23 (R_A23) select
00: R_A23 is not available and ignored
01: R_A23 is available only at 256 pin package
10: R_A23 is available at pin 133
11: reserved
ROM address bus bit 24 (R_A24) select
00: R_A24 is not available and ignored
01: R_A24 is available only at 256 pin package
10: R_A24 is available at pin 134
11: reserved
ROM address bus bit 25 (R_A25) select
00: R_A25 is not available and ignored
01: R_A25 is available only at 256 pin package
10: R_A25 is available at pin 135
11: reserved
ROM address bus bit 26 (R_A26) select
00: R_A26 is not available and ignored
01: R_A26 is available only at 256 pin package
10: R_A26 is available at pin 136
11: reserved
0xbffe8048 sft_cfg1
Description
Pin MUX control register #1 (General)
Attribute: RW
15
14
13
12
11
10
9
8
7
6
5
WE
1
4
OE
1
3
2
1
0
Bit-field
Reset
LPT
BOOT
pcmcia_WAIT
0
pcmcia_IORW
CHRDY
CS4 CS3 CS2 CS1
0
0
0
0
0
0
0
0
0
1
1
1
1
CS1
CS1 (ROM/FLASH chip select 1) function control
1: Enable Chip Select 1 (default)
0: Disable (CS1 becomes GPIO)
CS2
CS3
CS4
CS2 (ROM/FLASH chip select 2) function control
1: Enable Chip Select 2 (default)
0: Disabled (CS2 becomes GPIO)
CS3 (ROM/FLASH chip select 3) function control
1: Enable Chip Select 3 (default)
0: Disabled (CS3 becomes GPIO)
CS4 (ROM/FLASH chip select 4) function control
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1: Enable Chip Select 4 (default)
0: Disabled (CS4 becomes GPIO)
OE
OEB (ROM/FLASH output enable) function control
1: Enable OE function (default)
0: Disabled (OEB becomes GPIO)
WE
WEB (FLASH/SRAM write enable) function control
1: Enable WEB function (default)
0: Disabled (WEB becomes GPIO)
IOCHRDY (ISA_IOCHRDY) function control
1: Enable IOCHRDY input (i.e. output always tri-stated)
0: Disabled (default)
CHRDY
pcmcia_IORW PCMCIA IOR/IOW select
000: Disabled (default)
001: IOR from pin 19, IOW from pin 20
010: IOR from pin 135, IOW from pin 136
011: IOR from pin 58, IOW from pin 59
100: Available only at 256 pin package
101 to 111: Reserved
pcmcia_WAIT bit 12-10 : PCMCIA_WAIT_B select
000: Disabled (default)
001: PCMCIA_WAIT_B is from pin 21
010: PCMCIA_WAIT_B is from pin 61
011: PCMCIA_WAIT_B is from pin 129
100: PCMCIA_WAIT_B is from pin 138
101: Available only at 256 pin package
011 to 111: reserved
BOOT
LPT
RISC32 reset boot address
0: RISC32 boots from bfc0_0000 (internal ROM) (default)
1: RISC32 boots from 8000_0000 (SDRAM region)
LPT handshake signals (STROBE, ACK) select
00: Disabled (default)
01: LPT STROBE is from pin 62, LPT ACK is from pin 64
10: LPT STROBE is from pin 135, LPT ACK is from pin 136
11: Available only at 256 pin package
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0xbffe804c sft_cfg2
Description
Pin MUX control register #2 (General)
Attribute: RW
15
14
13
12
11
0
10
TV_LCD
0
9
0
8
0
7
6
0
5
0
4
1
3
UART0
0
2
1
1
IOP
0
0
ATAPI
0
Bit-field
Reset
SWAP BRS BRP BRE
UART1
0
0
0
0
0
ATAPI
ATAPI interface
0: Disable (default)
1: Enabled
IOP
IOP reset system
0: Disable (default)
1: Enabled
UART0
UART0 select
000: Disabled
001: UA0_RX is from pin 19, UA0_TXD is from pin 20
010: UA0_RX is from pin 65, UA0_TXD is from pin 66
011: UA0_RX is from pin 130, UA0_TXD is from pin 131
100: UA0_RX is from pin 144, UA0_TXD is from pin 145
101: UA0_RX is from pin 175, UA0_TXD is from pin 176 (default)
011,111: available only at 256 pin package
UART1 function selection
UART1
TV_LCD
BRE
0000: Disable (default)
0001-1111: Please refer to pin-description
TV LCD function selection
000: Disable (default)
001-111: please refer to pin-description
Bootstrap enable bit
0: Disable (default)
1: Enable
BRP
Bootstrap RXD pull up enable (pin 175)
0: Internal pull up disable (default)
1: Internal pull up enable
BRS
Bootstrap UART select
0: Bootstrap from UART0 (default)
1: Bootstrap from UART1
SWAP
SWAP UART0 and UART1
0: No swap (default)
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1: Swap UART0 and UART1 signals
0xbffe8050 sft_cfg3 (Audio interface and TV interface control)
Description
Pin MUX control register #3 (reference pin multiplex table for detailed information)
Attribute: RW
15
14
13
12
11
10
SYNC
0
9
8
7
6
5
4
3
2
1
EADC
0
0
Bit-field
Reset
pc_SYNC
TELETEXT
AUD LRCK AU4
AU3 AU2
0
0
0
0
0
0
0
1
1
1
1
1
0
0
EDAC
External ADC select
000: Disabled (default)
001: BCK is from pin 19, LRCK is from pin 20, DATA is from pin 21
010: BCK is from pin 58, LRCK is from pin 59, DATA is from pin 60
011: BCK is from pin 34, LRCK is from pin 35, DATA is from pin 37
100: BCK is from pin 130, LRCK is from pin 131, DATA is from pin 133
101: BCK is from pin 141, LRCK is from pin 143, DATA is from pin 144
110: Available only at 256 pin package
111: reserved
AU2
Audio DAC interface data #2 (AU_DATA[2]) function control
0: Disabled (AU_DATA[2] becomes GPIO)
1: Enable (default)
AU3
Audio DAC interface data #3 (AU_DATA[3]) function control
0: Disabled (AU_DATA[3] becomes GPIO)
1: Enable (default)
AU4
Audio DAC interface data #4 (AU_DATA[4]) function control
0: Disabled (AU_DATA[4] becomes GPIO)
1: Enable (default)
LRCK
AUD
SYNC
Audio DAC interface LRCK function control
0: Disable
1: Enable (default)
Audio function
0: Disable
1: enable (default)
H/V SYNC select
000: Disabled (default)
001: Reserved
010: Slave mode: HSYNC is from pin 146, VSYNC is from pin 148
011: Master mode: HSYNC is on pin 146, VSYNC is on pin 148
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100: Slave mode: HSYNC is from pin 34, VSYNC is from pin 35
101: Master mode: HSYNC is on pin 34, VSYNC is on pin 35
110, 111: available only at 256 pin package
TELETEXT select
TELETEXT
pc_SYNC
00: Disable (default)
01: Teletext BIT is from pin 149, teletext REQ is from pin 150
10: Teletext BIT is from pin 37, teletext REQ is from pin 38
11: available only at 256 pin package
H/VSYNC PC select
00: Disabled (default)
01: HSYNC_PC is on pin 175, VSYNC_PC is on pin 176
10: HSYNC_PC is on pin 146, VSYNC_PC is on pin 148
11: HSYNC_PC is on pin 144, VSYNC_PC is on pin 145
0xbffe8058 sft_cfg5
Description
Pin MUX control register #5 (RISC interrupt control)
Attribute: RW
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Bit-field
Reset
RISC_INTEXT
RISC_INT5_2
0
RISC_INT1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
RISC_INT1
RID INT1 bit 15 to bit 11 interrupt select
000: Disable (default)
001: INT1[11] is from pin 141,
INT1[12] is from pin 143,
INT1[13] is from pin 144,
INT1[14] is from pin 145,
INT1[15] is from pin 146
010: INT1[11] is from pin 129,
INT1[12] is from pin 130,
INT1[13] is from pin 131,
INT1[14] is from pin 133,
INT1[15] is from pin 134
011: INT1[11] is from pin 29,
INT1[12] is from pin 31,
INT1[13] is from pin 34,
INT1[14] is from pin 35,
INT1[15] is from pin 37
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Preliminary Version: 0.2
Preliminary
SPHE8200A
100-110 : Available only at 256 pin package
111: Reserved
RISC_INT5_2 RISC INT bit 5 to bit 2 interrupt select (level, active low)
000: Disable (default)
001: INTRQ_N[2] is from pin 141,
INTRQ_N[3] is from pin 143,
INTRQ_N[4] is from pin 144,
INTRQ_N[5] is from pin 145
010: INTRQ_N[2] is from pin 129,
INTRQ_N[3] is from pin 130,
INTRQ_N[4] is from pin 131,
INTRQ_N[5] is from pin 133
011: INTRQ_N[2] is from pin 29,
INTRQ_N[3] is from pin 31,
INTRQ_N[4] is from pin 34,
INTRQ_N[5] is from pin 35
100-110: Available only at 256 pin package
111: Reserved
RISC_INTEXT RISC INTEXT_N bit 5 to bit 0 interrupt select (level, active low)
000: Disable (default)
001: INTRQ_N[0] is from pin 141,
INTRQ_N[1] is from pin 143,
INTRQ_N[2] is from pin 144,
INTRQ_N[3] is from pin 145,
INTRQ_N[4] is from pin 146
INTRQ_N[5] is from pin 148
010: INTRQ_N[0] is from pin 129,
INTRQ_N[1] is from pin 130,
INTRQ_N[2] is from pin 131,
INTRQ_N[3] is from pin 133,
INTRQ_N[4] is from pin 134,
INTRQ_N[5] is from pin 135
011: INTRQ_N[0] is from pin 29,
INTRQ_N[1] is from pin 31,
INTRQ_N[2] is from pin 34,
INTRQ_N[3] is from pin 35,
INTRQ_N[4] is from pin 37,
INTRQ_N[5] is from pin 38
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Preliminary Version: 0.2
Preliminary
SPHE8200A
100-110: Available only at 256 pin package
111: Reserved
0xbffe805c sft_cfg6
Description
Pin MUX control register #6 (SDRAM interface control)
Attribute: RW
15
14
13
12
11
10
9
8
SDQM3
1
7
SDQM2
1
6
5
4
3
2
1
0
Bit-field
Reset
SBA1 SA12 SA11
0
0
0
0
1
1
0
1
1
1
0
1
1
1
SA11
SDRAM address 11 enable
0: SDRAM address 11 is disabled
1: SDRAM address 11 is enabled (default)
SDRAM address 12 enable
SA12
0: SDRAM address 12 is disabled
1: SDRAM address 12 is enabled (default)
SDRAM BA1 enable
SBA1
0: SDRAM BA1 is disabled
1: SDRAM BA1 is enabled (default)
SDRAM DQM2 enable
SDQM2
SDQM3
0: SDRAM DQM2 is disabled
1: SDRAM DQM2 is enabled (default)
SDRAM DQM3 enable
0: SDRAM DQM3 is disabled
1: SDRAM DQM3 is enabled (default)
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Preliminary Version: 0.2
Preliminary
SPHE8200A
8.PACKAGE/PAD LOCATION
8.1. Outline Dimensions
216-pin LQFP
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Preliminary Version: 0.2
Preliminary
SPHE8200A
9.DISCLAIMER
The information appearing in this publication is believed to be accurate.
Integrated circuits sold by Sunplus Technology are covered by the warranty and patent indemnification provisions stipulated in the terms of
sale only. SUNPLUS makes no warranty, expressed, statutory implied or by description regarding the information in this publication or
regarding the freedom of the described chip(s) from patent infringement. FURTHERMORE, SUNPLUS MAKES NO WARRANTY OF
MERCHANTABILITY OR FITNESS FOR ANY PURPOSE. SUNPLUS reserves the right to halt production or alter the specifications and
prices at any time without notice. Accordingly, the reader is cautioned to verify that the data sheets and other information in this publication
are current before placing orders. Products described herein are intended for use in normal commercial applications. Applications involving
unusual environmental or reliability requirements, e.g. military equipment or medical life support equipment, are specifically not
recommended without additional processing by SUNPLUS for such applications. Please note that application circuits illustrated in this
document are for reference purposes only.
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Preliminary Version: 0.2
Preliminary
SPHE8200A
10. REVISION HISTORY
Date
Revision #
Description
Page
JUN. 10, 2003
OCT. 07, 2003
0.1
0.2
Original
Add Functional Description and Electrical Specification and Register List
14
18-37
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Preliminary Version: 0.2
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