SPLC100A1 [ETC]
40-CHANNEL SEG/COM LCD DRIVER; 40通道SEG / COM LCD驱动器
| 型号： | SPLC100A1 |
| 厂家： | 
ETC |
| 描述： | 40-CHANNEL SEG/COM LCD DRIVER |
| 文件： | 总15页 (文件大小：162K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
SPLC100A1
40-CHANNEL SEG/COM LCD DRIVER
GENERAL DESCRIPTION
The SPLC100A1 is a Liquid Crystal Display driver that contains two sets of 20-bit bi-directional shift registers, 20
data latch flip-flops and 20 Liquid Crystal Display drivers. It also features 40-channel outputs that can be applied
as common or segment driver. The SPLC100A1 receives serial display data from a display control LSI,
converts it into parallel data and supplies liquid crystal display waveforms to the liquid crystal.
FEATURES
BLOCK DIAGRAM
ꢀ Liquid Crystal Display driver with serial/parallel
ꢀꢀconversion function.
Y1
Y20
V1,V2
LCD Drivers
20-bit latch
ꢀ Serial transfer facilitates board design.
ꢀ Capable of interfacing to liquid crystal display
controllers: HD43160AH, HD61830, HD44780,
HD44790, SPLC780
V3,V4
Latch signal
CL1
Shift
direction
Data
SHL1
DR1
DL1
CL2
Data
Data
Shift signal
20-bit bidirectional shift register
Switching circuit
20-bit bidirectional shift register
20-bit latch
DR2
DL2
Data
FCS
SHL2
Shift
direction
ꢀ 40 internal LCD drivers.
M
V1,V2
LCD Drivers
V5,V6
ꢀ Internal serial/parallel conversion circuits:
— 20-bit shift registerꢁ2
Y21
Y40
— 20-bit latchꢁ2
ꢀ Power supply:
— Internal logic: 2.7V – 5.5V
— Liquid crystal display driver circuit: 3.0V – 11.0V
ꢀ CMOS process.
ꢀ Sunplus Technology Co., Ltd.
1
Rev.: 1.0
1999.10.04
SPLC100A1
FUNCTION DESCRIPTION
ꢀ SEGMENT DRIVER
When SPLC100A1 is used as a segment driver, FCS is connected to VSS. In this case, both channel 1 and
channel 2 shift data at the falling edge of CL2 and latch it at the falling edge of CL1. V3 and V5, V4 and V6 of
the liquid crystal display driver power supply are short-circuited, respectively.
7
8
1
2
3
4
5
6
7
8
1
2
(FLM)
M
CL1
Output of
latch
(Y1 ~ Y40)
Enlarged view
Latch
M
CL1
CL2
Shift
DL1/DR1
DL2/DR2
Segment data waveforms ( A type waveforms, 1/8 duty cycle )
ꢀ Sunplus Technology Co., Ltd.
2
Rev.: 1.0
1999.10.04
SPLC100A1
ꢀ COMMON DRIVER
In this case, channel 1 is used as a segment driver and channel 2 as common driver. When channel 2 of
SPLC100A1 is used as common driver, FCS is connected to VDD. In this case, channel 2 shifts data at the
rising edge of CL1 and latches it at the rising edge of CL2.
8
1
2
3
4
5
6
7
8
1
2
DL2/DR2(FLM)
CL1
Shift
Non-Select
Non-Select
Y21
(Y40)
Y22
Select
Select
(Y33)
to
Select
Select
Y28
(Y33)
Non-Select
Select
Select
Enlarged view
DL2/DR2(FLM)
M
Shift
CL1
Latch
CL2
Y21
(Y40)
Common data waveforms ( A type waveforms of channel 2, 1/8 duty cycle )
ꢀ Sunplus Technology Co., Ltd.
3
Rev.: 1.0
1999.10.04
SPLC100A1
Both Channel 1 and Channel 2 Used as Common Drivers ( FCS = VDD )
Common Drivers ( FCS = VDD )
When both of channel 1 and channel 2 are used common drives, FCS is connected to VDD and the signals (CL1,
CL2, FLM) from the controller are connected as following.
In this case, connection of the Liquid Crystal Display driver power supply is different from that of segment driver,
ꢁ V1,V2: Select level of segment and common
ꢁ V3,V4: Non-select level of segment
ꢁ V5,V6: Non-select level of common
VDD
CL2
Y40 - 1
CL1
Controller
DL1
Common
driver
LCD
DR1
DL2
DR2
SPLC100A1
Y40 - 1
SPLC100A1
Y40 - 1
SPLC100A1
V
V
V
V
V
V
1
2
3
4
5
6
Segment
driver
Segment
driver
ꢀ Sunplus Technology Co., Ltd.
4
Rev.: 1.0
1999.10.04
SPLC100A1
PIN DESCRIPTION
Mnemonic PIN No. Type
Description
Positive power supply voltage input
VDD
VSS
22
32
I
I
Ground input
VEE
29
I
Power supply voltage for liquid crystal display drive
Liquid crystal driver output ( Channel 1 )
Y6 – 1
Y20 – 7
Y27 – 21
Y40 – 28
V1, V2
V3, V4
V5, V6
SHL1
23-28
8-21
1-7
O
O
Liquid crystal driver output ( Channel 2 )
47-59
41,42
43,44
45,46
38
I
I
I
I
Power supply for liquid crystal display drive ( Select level )
Power supply for liquid crystal display drive (Non-select level for channel 1)
Power supply for liquid crystal display drive (Non-select level for channel 2)
Selection of the shift direction of channel 1 shift register
SHL1
VDD
GND
DL1
Out
In
DR1
In
Out
SHL2
39
I
Selection of the shift direction of channel 2 shift register
SHL2
VDD
GND
DL2
Out
In
DR2
In
Out
DL1, DR1
DL2, DR2
M
33,34
35,36
37
I/O
Data Input / Output of channel 1 shift register
Data Input / Output of channel 2 shift register
Alternated signal for liquid crystal driver output
I/O
I
I
CL1
30
Latch signal for channel 1 (
Used for channel 2 when FCS is GND
Shift signal for channel 1 ( ) *1
) *1
CL2
FCS
31
40
I
I
Used for channel 2 when FCS is GND
Mode select signal of channel 2. FCS signal exchanges the latch signal and
the shift of channel 2 and inverts M for channel 2.Thus, this signal exchanges
the function of channel 2.
FCS Level
Channel 2
M Polarity
Function
Latch signal Shift signal
VDD
GND
CL2
CL1
CL1
CL2
M
M
For common drive
For segment drive
*2
*1
*1
Notes: *1.
and
indicate the latches at rise and fall times, respectively.
*2. The output level relationship between channel 1 and channel 2 based on the FCS signal level as
follows:
ꢀ Sunplus Technology Co., Ltd.
5
Rev.: 1.0
1999.10.04
SPLC100A1
Output Level
FCS
Data
M
Channel 1(Y1 - Y20)
Channel 2(Y21 - Y40)
H
L
V1
V2
V3
V4
V1
V2
V3
V4
V2
V1
V6
V5
V1
V2
V5
V6
H
(Select)
VDD
( H )
H
L
L
(Non-select)
H
H
L
(Select)
L
GND
( L )
H
L
(Non-select)
ABSOLUTE MAXIMUM RATINGS
Characteristics
Symbol
Ratings
Operating Voltage
VDD *1
VEE *2
VIN1
-0.3V to + 7.0V
VDD - 13.5V to VDD+ 0.3V
-0.3V to VDD + 0.3V
VDD + 0.3V to VEE -0.3V
-20ꢂ to + 75ꢂ
LCD Driver Supply Voltage
Input Voltage 1
Input Voltage 2 ( V1 - V6 )
Operating Temperature
Storage Temperature
VIN2
TOPR
TSTG
-55ꢂ to + 125ꢂ
Note: 1.It will cause damage to IC if the supply voltage is greater than above.
2.Connect a protection resistor of 220ꢃꢄ5% to VEE.
ꢀ Sunplus Technology Co., Ltd.
6
Rev.: 1.0
1999.10.04
SPLC100A1
DC CHARACTERISTICS
( VDD = 5Vꢄ10%,VEE = -5Vꢄ10%, VSS = 0V, Ta = -20 to + 75ꢂ )
Characteristics
Input Voltage
Symbol
Min.
Typ. Max.
Unit
Test Condition
VIH
0.7VDD
-
-
VDD
V
(CL1, CL2, DL1, DL2, DR1, DR2, M,
SHL1, SHL2, FCS)
VIL
0
0.3VDD
V
VOH
VOL
VLCD
VD1
VDD-0.4
-
-
-
-
-
-
V
V
V
V
V
IOH = -0.4mA
Output Voltage
(DL1, DL2, DR1, DR2)
LCD Driver Voltage
-
3.0
-
0.4
11.0
1.1
1.5
IOL = +0.4mA
VDD - V5
ION = 0.1mA for one of Yj
ION = 0.05mA for each Yj
Vi-Yj Voltage Descending
V(V6 - 1)-Y(Y40 - 1)
VD2
-
Input Leakage Current
(CL1, CL2, DL1, DL2, DR1, DR2, M,
SHL1, SHL2, FCS )
IIL
-5.0
-
5.0
ꢁA
VIN = 0 to VDD
VIN = VDD - VEE
Vi Leakage Current V6 - 1
IVL
-10.0
-
10.0
ꢁA
(Output Y40 - 1: floating )
FCL2 = 400KHz
ICC
IEE
-
-
-
-
1.0
10
mA
Power Supply Current
ꢁA
FCL1 = 1KHz
SPLC100A vs. SPLC100A1
(1) The test condition has been improved from IOH = -0.35 mA (SPLC100A) to IOH = -0.4mA (SPLC100A1)
(2) The minimum working voltage of SPLC100A is 4.5V. In contrast, the minimum working voltage of
SPLC100A1 is improved to 3.0V.
ꢀ Sunplus Technology Co., Ltd.
7
Rev.: 1.0
1999.10.04
SPLC100A1
AC CHARACTERISTICS
Characteristics
Data Shift Frequency ( CL2 )
Symbol Min. Typ.
Max.
Unit Test Condition
FCL
tCWH
tCWL
-
-
-
-
400
KHz
ns
Clock
Width
High Level ( CL1, CL2 )
Low Level ( CL2 )
800
800
-
-
ns
Data Set-up Time
tSU
300
-
-
ns
( DL1, DL2, DR1, DR2, FLM )
Clock Set-up Time ( CL1, CL2 )
Clock Set-up Time ( CL1, CL2 )
Date Delay Time ( DL1, DL2, DR1, DR2 )
Clock Rise/Fall Time ( CL1, CL2 )
Date Hold Time
(CL2ꢅCL1)
(CL1ꢅCL2)
CL = 15pF
tSL
tLS
tPD
tCT
500
-
-
-
-
-
ns
ns
ns
ns
500
-
-
-
500
200
tDH
300
-
-
ns
( DL1, DL2, DR1, DR2, FLM )
V
IH
V
IH
t
CWL
CL2
V
IL
tCWH
t
CT
tCT
tDH
Data in
(DL1,DL2,DR1,DR2)
tSU
V
IH
tSL
VIL
tpd
Data out
(DL1,DL2,DR1,DR2)
V
OH
OL
t
LS
V
t
LS
V
IH
CL1
FLM
V
IL
t
CWH
t
CT
t
CT
V
V
IH
t
SU
IL
ꢀ Sunplus Technology Co., Ltd.
8
Rev.: 1.0
1999.10.04
SPLC100A1
APPLICATION NOTES
ꢀꢀꢀ SEGMENT DRIVER
COM16 - 1
LCD
Controller
Common
signal
M
CL2 CL1
D
Segment signal
40
40
Y40 - 1
Y40 - 1
SPLC100A1
(segment
driver)
DR
DL
DL
1
1
2
2
1
DR
DL
DR
1
2
2
FCS
SHL
SHL
FCS
SHL
SHL
DL
SPLC100A1
(segment
driver)
DR
1
2
1
2
ꢀꢀꢀ COMMON DRIVER
VDD
CL2
CL1
FLM
CL2
CL1
DL1
DR1
DL2
DR2
Y40 - 1
LCD
SPLC100A1
Controller
Common
driver
Y40 - 1
SPLC100A1
Y40 - 1
SPLC100A1
Segment
driver
Segment
driver
ꢀ Sunplus Technology Co., Ltd.
9
Rev.: 1.0
1999.10.04
SPLC100A1
ꢀꢀꢀ SEGMENT / COMMON DRIVER
LCD
Controller
M CL2 CL1 FLM
Common
D
signal
20
Segment signal
20
40
Y20 - 1
Y40 - 1
Y40 - 21
DL1
DL2
DL
1
DR
DL
DR
1
2
2
SPLC100A1
FCS
SHL
SHL
SPLC100A1
(segment
VDD
DR1
(segment
/common
driver)
1
2
FCS
SHL
1
2
driver)
SHL
ꢀ Sunplus Technology Co., Ltd.
10
Rev.: 1.0
1999.10.04
SPLC100A1
PAD ASSIGNMENT AND LOCATIONS
ꢀ PAD Assignment
Chip Size: 2152ꢁm x 2380ꢁm
This IC substrate should be connected to VDD
Note: To ensure IC function properly, please bond all of the VDD, VSS AVDD and AVSS pins.
Ordering Information
Product Number
Package Type
SPLC100A1-nnnnV-C
Chip form
Note1: Code number (nnnnV) is assigned for customer.
Note2: Code number (nnnn = 0000 - 9999); version (V = A - Z).
NOTE: SUNPLUS TECHNOLOGY GO., LTD reserves the right to make changes at any time without notice in
order to improve the design and performance to supply the best possible product.
ꢀ Sunplus Technology Co., Ltd.
11
Rev.: 1.0
1999.10.04
SPLC100A1
ꢀ PAD Locations
Pad No
Pad Name
X
Y
Pad No
Pad Name
X
Y
1
Y27
Y26
Y25
Y24
Y23
Y22
Y21
Y20
Y19
Y18
Y17
Y16
Y15
Y14
Y13
Y12
Y9
-912
-910
-913
-913
-913
-913
-912
-912
-912
-910
-912
-912
-913
-912
-913
-912
-744
-614
-484
-358
-234
-109
16
889
751
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
CL2
VSS
DL1
DR1
DL2
DR2
M
907
907
907
907
908
906
907
907
907
907
907
907
907
907
908
774
644
513
388
264
139
14
-826
-690
-565
-434
-312
-188
-63
2
3
628
4
498
5
373
6
249
7
123
8
-2
SHL1
SHL2
FCS
V1
61
9
-126
-249
-373
-500
-628
-756
-891
-1023
-1022
-1022
-1023
-1023
-1022
-1023
-1023
-1023
-1022
-1023
-1023
-1023
-1023
-958
186
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
309
433
V2
561
V3
687
V4
825
V5
970
V6
1020
1021
1021
1021
1022
1021
1022
1021
1022
1021
1021
1022
1022
1022
Y40
Y39
Y38
Y37
Y36
Y35
Y30
Y31
Y32
Y33
Y34
Y29
Y28
Y10
Y11
Y8
Y7
VDD
Y6
-110
-235
-360
-484
-614
-744
-912
Y5
139
Y4
265
Y3
390
Y2
513
Y1
642
VEE
CL1
772
908
ꢀ Sunplus Technology Co., Ltd.
12
Rev.: 1.0
1999.10.04
SPLC100A1
ꢀꢀꢀ PACKAGE Configuration
QFP 64L Top View
51
NC
V6
V5
1
2
3
50
49
Y29
Y28
V4
V3
48
47
Y27
Y26
4
5
V2
46
Y25
Y24
6
7
V1
FCS
SHL2
45
44
43
Y23
Y22
8
9
SHL1
M
42
Y21 10
Y20 11
SPLC100
41
40
39
NC
DR2
DL2
Y19 12
Y18 13
38
37
Y17 14
DR1
DL1
15
16
Y16
Y15
36
35
34
VSS
CL2
CL1
17
18
Y14
Y13
33
Y12 19
VEE
ꢀ Sunplus Technology Co., Ltd.
13
Rev.: 1.0
1999.10.04
SPLC100A1
ꢀꢀꢀ PACKAGE Information
QFP 64L Outline Dimensions
Unit: inch/mm
ꢀ Sunplus Technology Co., Ltd.
14
Rev.: 1.0
1999.10.04
SPLC100A1
DISCLAIMER
The information appearing in this publication is believed to be accurate.
Integrated circuits sold by Sunplus Technology are covered by the warranty and patent indemnification provisions
stipulated in the terms of sale only. SUNPLUS makes no warranty, express, statutory implied or by description
regarding the information in this publication or regarding the freedom of the described chip(s) from patent
infringement. FURTHER, SUNPLUS MAKES NO WARRANTY OF MERCHANTABILITY OR FITNESS FOR
ANY PURPOSE. SUNPLUS reserves the right to halt production or alter the specifications and prices at any
time without notice. Accordingly, the reader is cautioned to verify that the data sheets and other information in
this publication are current before placing orders. Products described herein are intended for use in normal
commercial applications. Applications involving unusual environmental or reliability requirements, e.g. military
equipment or medical life support equipment, are specifically not recommended without additional processing by
SUNPLUS for such applications. Please note that application circuits illustrated in this document are for
reference purposes only.
ꢀ Sunplus Technology Co., Ltd.
15
Rev.: 1.0
1999.10.04
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