SPT774CCS [ETC]
FAST, COMPLETE 12-BIT UP COMPATIBLE A/D CONVERTER WITH SAMPLE/HOLD; 快速，完整的12位向上兼容A / D与采样/保持转换器
| 型号： | SPT774CCS |
| 厂家： | 
ETC |
| 描述： | FAST, COMPLETE 12-BIT UP COMPATIBLE A/D CONVERTER WITH SAMPLE/HOLD |
| 文件： | 总12页 (文件大小：117K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
SPT774
FAST, COMPLETE 12-BIT µP COMPATIBLE
A/D CONVERTER WITH SAMPLE/HOLD
FEATURES
APPLICATIONS
• Improved Higher Performance Version of the HADC574Z
• Complete 12-Bit A/D Converter with Sample/Hold,
Reference and Clock
• Data Acquisition Systems
• 8 or 12-Bit µP Input Functions
• Process Control Systems
• Low Power Dissipation (120 mW Max)
• 12-Bit Linearity (Over Temp)
• Test and Scientific Instruments
• Personal Computer Interface
• 8 µs Max Conversion Time
• Single +5 V Supply
• Full Bipolar and Unipolar Input Range
The SPT774 has standard bipolar and unipolar input ranges
of 10 V and 20 V that are controlled by a bipolar offset pin and
lasertrimmedforspecifiedlinearity,gainandoffsetaccuracy.
GENERAL DESCRIPTION
The SPT774 is a complete, 12-bit successive approximation
A/D converter manufactured in CMOS technology. The de-
vice is an improved version of the HADC574Z. Included on
chip are an internal reference, clock, and a sample-and-hold.
The S/H is an additional feature not available on similar
devices.
The power supply is +5 V. The device also has an optional
mode control voltage which may be used depending on the
application. With a maximum dissipation of 120 mW at the
specified voltages, power consumption is about five times
lower than that of currently available devices.
The SPT774 features 8 µs (max) conversion time of 10 or
20 V input signals. Also, a three-state output buffer is added
for direct interface to an 8-, 12- or 16-bit µP bus.
The SPT774 is available in 28-lead ceramic sidebrazed DIP,
PDIP and SOIC packages in the commercial temperature
range.
Output
BLOCK DIAGRAM
Nibble A
Nibble B
Nibble C
Three-State Buffers And Control
STS
12-Bit SAR
12-Bit
Capacitance
DAC
+
Comp
-
Clock
Offset/Gain
Trim
20 V In
10 V In
BIP Off
AGND
Control Logic
A
Ref
12/8 CS
o
R/C
CE
Ref Out
Signal Processing Technologies, Inc.
4755 Forge Road, Colorado Springs, Colorado 80907, USA
Phone: (719) 528-2300 FAX: (719) 528-2370 Website: http://www.spt.com E-Mail: sales@spt.com
ABSOLUTE MAXIMUM RATINGS (Beyond which damage may occur) 1 25 °C
Supply Voltages
Mode Control Voltage (V to DGND) ....................0 to +7 V
Output
Reference Output Voltage .............. Indefinite Short to GND
Momentary Short to V
EE
Logic Supply Voltage (V
to DGND) ...................0 to +7 V
DD
DD
Analog to Digital Ground (AGND to DGND) .................±1 V
Temperature
Input Voltages
Operating Temperature, Ambient .................... 0 to +70 °C
Junction......................... +165 °C
Control Input Voltages (to DGND)
(CE, CS, Ao, 12/8, R/C) ......................... -0.5 to V
Analog Input Voltage (to AGND)
+0.5 V
Lead Temperature, (Soldering 10 Seconds)........... +300 °C
Storage Temperature....................................-65 to +150 °C
DD
(REF IN, BIP OFF, 10 V ) ......................................±16.5 V
IN
20 V V Input Voltage (to AGND) ..............................±24 V
IN
Note: Operation at any Absolute Maximum Rating is not implied. See Operating Conditions for proper nominal applied
conditions in typical applications.
ELECTRICAL SPECIFICATIONS
T
= T
to T
, V = 0 to +5 V, V = +5 V, f = 117 kHz, f = 10 kHz, unless otherwise specified..
A
MIN
MAX EE
DD
S
IN
TEST
CONDITIONS
TEST
LEVEL
SPT774C
TYP
SPT774B
TYP
PARAMETER
MIN
MAX
MIN
MAX
UNITS
DC ELECTRICAL CHARACTERISTICS
Resolution
VI
VI
VI
VI
VI
VI
12
12
Bits
Linearity Error
T = 0 to +70 °C
A
±1
±0.5
LSB
Differential Linearity
No Missing Codes
12
12
Bits
Unipolar Offset; 10 V, 20 V
Bipolar Offset; ±5 V, ±10 V
Full Scale Calibration Error
Full Scale Calibration Error
+25 °C Adjustable to Zero
+25 °C Adjustable to Zero
+25 °C Adjustable to Zero
No Adjustment to Zero
±2
±10
±2
±4
LSB
LSB
1
1
0.30
0.30
% of FS
T = 0 to +70 °C
A
V
0.47
0.37
% of FS
Temperature Coefficients
Unipolar Offset
Using Internal Reference
V
V
V
±1.0
±2.0
±12
±1.0
±2.0
±12
ppm/°C
ppm/°C
ppm/°C
Bipolar Offset
Full Scale Calibration
Power Supply Rejection
Max change in full
scale calibration
VI
±0.5
±0.5
LSB
+4.75 V<V <+5.25 V
DD
Analog Input Ranges
Bipolar
VI
VI
VI
VI
-5
-10
0
+5
+10
+10
+20
-5
-10
0
+5
+10
+10
+20
Volts
Volts
Volts
Volts
Unipolar
0
0
Input Impedance
10 Volt Span
VI
VI
8.5
35
12
50
8.5
35
12
50
kΩ
kΩ
20 Volt Span
SPT774
SPT
2
8/1/00
ELECTRICAL SPECIFICATIONS
T
= T
to T
, V = 0 to +5 V, V = +5 V, f = 117 kHz, f = 10 kHz, unless otherwise specified.
A
MIN
MAX EE
DD
S
IN
TEST
CONDITIONS
TEST
LEVEL
SPT774C
TYP
SPT774B
TYP
PARAMETER
MIN
MAX
MIN
MAX
UNITS
DC ELECTRICAL CHARACTERISTICS
Power Supplies Operating
Voltage Range
V
V
IV
IV
+4.5
+5.5
+4.5
+5.5
Volts
Volts
DD
2
V
DD
V
DD
EE
Operating Current
I
I
IV
IV
15
24
15
24
mA
DD
2
EE
V
= +5 V
167
167
µA
EE
Power Dissipation
VI
75
120
2.6
75
120
2.6
mW
Internal Reference
Voltage
VI
VI
2.4
0.5
2.5
2.4
0.5
2.5
Volts
mA
3
Output Current
DIGITAL CHARACTERISTICS
Logic Inputs
(CE,
, R/ , Ao, 12/ )
C 8
CS
Logic 0
Logic1
VI
VI
-0.5
2.0
+0.8
5.5
-0.5
2.0
+0.8
5.5
Volts
Volts
Current
VI
V
-5.0
0. 1
5
5.0
-5.0
0. 1
5
5.0
µA
Capacitance
Logic Outputs
(DB11-DB0, STS)
Logic 0
pF
(I
(I
= 1.6 mA)
VI
VI
VI
+0.4
+5
+0.4
+5
Volts
Volts
µA
Sink
Logic 1
= 500 µA)
+2.4
-5
+2.4
-5
SOURCE
Leakage
(High Z State,
0.1
5
0.1
5
DB11-DB0 Only)
Capacitance
AC Accuracy
V
pF
f =117 kHz, f =10 kHz
S
IN
Spurious Free Dyn. Range
Total Harmonic Distortion
Signal-to-Noise Ratio
Signal-to-Noise & Distortion
(SINAD)
V
V
V
V
73
78
-77
72
76
78
-77
72
dB
dB
dB
dB
-72
-75
69
68
71
70
71
71
Intermodulation Distortion f =20 kHz;
V
-75
-75
dB
IN
f
=23 kHz
IN2
Note 1: Fixed 50 Ω resistor from REF OUT to REF IN and REF OUT to BIP OFF.
Note 2: V is optional and is only used to set the mode for the internal sample/hold. When not using V , the pin should be treated
EE
EE
as a no connect. If V is connected to 0 to -15 V, aperture delay (t ) will increase from 20 ns (typ) to 4000 ns (typ).
EE
AP
Note 3: Available for external loads; external load should not change during conversion.
SPT774
SPT
3
8/1/00
ELECTRICAL SPECIFICATIONS
T
= T
to T
, V = 0 to +5 V, V = +5 V, f = 117 kHz, f = 10 kHz, unless otherwise specified.
MAX EE DD S IN
A
MIN
TEST
CONDITIONS
TEST
LEVEL
SPT774C
TYP
SPT774B
TYP
PARAMETER
MIN
MAX
MIN
MAX
UNITS
4
AC ELECTRICAL CHARACTERISTICS
Convert Mode Timing
t
t
STS Delay from CE
CE Pulse Width
VI
VI
60
30
200
60
30
200
ns
ns
DSC
HEC
50
50
50
50
t
t
to CE Setup
VI
VI
VI
VI
20
20
0
20
20
0
ns
ns
ns
ns
CS
CS
SSC
Low during CE High
50
50
50
50
50
50
HSC
t
R/ to CE Setup
C
SRC
HRC
t
R/ Low During CE High
C
20
20
t
t
t
Ao to CE Setup
VI
VI
0
50
0
50
ns
ns
SAC
Ao Valid During CE High
5
20
20
HAC
Conversion Time
12-Bit Cycle
C
VI
VI
7.5
5.5
8
5.9
7.5
5.5
8
5.9
µs
µs
8-Bit Cycle
Read Mode Timing
t
t
t
Access Time from CE
Data Valid After CE Low
Output Float Delay
VI
VI
VI
75
35
100
150
150
75
35
100
150
150
ns
ns
ns
DD
HD
HL
25
50
25
50
t
to CE Setup
VI
0
0
ns
CS
SSR
t
t
t
R/ to CE Setup
VI
VI
VI
0
50
0
0
50
0
ns
ns
ns
C
SRR
SAR
HSR
Ao to CE Setup
25
25
Valid After CE Low
CS
t
R/ High After CE Low
C
VI
0
0
ns
HRR
t
t
STS Delay After Data Valid
VI
VI
75
50
150
375
75
50
150
375
ns
ns
HS
Ao Valid after CE Low
HAR
Note 4: Time is measured from 50% level of digital transitions.
Note 5: Includes acquisition time.
Figure 1 - Convert Mode Timing Diagram
Figure 2 - Read Mode Timing Diagram
CE
CE
CS
tSSR
t
t
HSR
HRR
tHEC
t SSC
CS
R/C
t HSC
t SRC
R/C
t SRR
t HRC
Ao
Ao
t SAR
t
HAR
tSAC
t HAC
STS
STS
t DSC
tC
t HD
t HS
HIGH
DATA
VALID
DB11-DB0
IMPEDANCE
High Impedance
DB11-DB0
tDD
tHL
SPT774
SPT
4
8/1/00
ELECTRICAL SPECIFICATIONS
T
= T
to T
, V = 0 to +5 V, V = +5 V, f = 117 kHz, f = 10 kHz, unless otherwise specified.
MAX EE DD S IN
A
MIN
TEST
CONDITIONS
TEST
LEVEL
SPT774C
TYP
SPT774B
TYP
PARAMETER
MIN
MAX
MIN
MAX UNITS
4
AC ELECTRICAL CHARACTERISTICS
Stand-Alone Mode Timing
t
t
Low R/ Pulse Width
VI
VI
25
25
ns
C
HRL
STS Delay from R/
200
200 ns
C
DS
t
t
t
t
Data Valid After R/ Low
VI
VI
VI
VI
25
75
25
75
ns
375 ns
ns
C
HDR
STS Delay After Data Valid
150
375
150
150
HS
High R/ Pulse Width
100
100
C
HRH
Data Access Time
150 ns
DDR
Sample-and-Hold
Aperture Delay
Aperture Uncertainty Time
V
V
= +5 V
= +5 V
IV
V
20
300
20
300
ns
ps, RMS
EE
EE
TEST LEVEL
TEST PROCEDURE
100% production tested at the specified temperature.
TEST LEVEL CODES
All electrical characteristics are subject to the
following conditions:
I
II
100% production tested at T =25 °C, and sample
A
tested at the specified temperatures.
All parameters having min/max specifications
are guaranteed. The Test Level column indi-
cates the specific device testing actually per-
formed during production and Quality Assur-
ance inspection. Any blank section in the data
column indicates that the specification is not
tested at the specified condition.
III
QA sample tested only at the specified temperatures.
IV
Parameter is guaranteed (but not tested) by design
and characterization data.
V
Parameter is a typical value for information purposes
only.
VI
100% production tested at T = 25 °C. Parameter is
A
guaranteed over specified temperature range.
Figure 3 - Low Pulse for R/ - Outputs Enabled
Figure 4 - High Pulse for R/ - Outputs Enabled While
C
C
After Conversion
R/ is High, Otherwise High Impedance
C
t
HRL
R/C
R/C
t
t
HRH
DS
t
DS
STS
t
C
t
t
STS
DDR
HDR
t
C
t
t
HS
HDR
HIGH-Z
HIGH-Z
DATA VALID
DB11-DB0
DB11-DB0
DATA VALID
DATA VALID
SPT774
SPT
5
8/1/00
other 774 circuits will cause a transient load current on the
sample-and-hold which will upset the buffer output and may
add error to the conversion itself.
CIRCUIT OPERATION
The SPT774 is a complete 12-bit analog-to-digital converter
that consists of a single chip version of the industry standard
774. This single chip contains a precision 12-bit capacitor
digital-to-analog converter (CDAC) with voltage reference,
comparator, successiveapproximationregister(SAR), sample-
and-hold, clock, output buffers and control circuitry to make it
possible to use the SPT774 with few external components.
Furthermore, the isolation of the input after the acquisition
time in the SPT774 allows the user an opportunity to release
the hold on an external sample-and-hold and start it tracking
the next sample. This increases system throughput with the
user’s existing components.
WhenthecontrolsectionoftheSPT774initiatesaconversion
command, the clock is enabled and the successive-approxi-
mation register is reset to all zeros. Once the conversion
cycle begins, it cannot be stopped or restarted and data is not
available from the output buffers.
TYPICAL INTERFACE CIRCUIT
The SPT774 is a complete A/D converter that is fully opera-
tional when powered up and issued a Start Convert Signal.
Only a few external components are necessary as shown in
figures 5 and 6. The two typical interface circuits are for
operating the SPT774 in either an unipolar or bipolar input
mode. Information on these connections and on conditions
concerning board layout to achieve the best operation are
discussed below.
The SAR, timed by the clock, sequences through the conver-
sion cycle and returns an end-of-convert flag to the control
section of the ADC. The clock is then disabled by the control
section, the output status goes low, and the control section is
enabled to allow the data to be read by external command.
For each application of this device, strict attention must be
given to power supply decoupling, board layout (to reduce
pickup between analog and digital sections), and grounding.
Digital timing, calibration and the analog signal source must
be considered for correct operation.
The internal SPT774 12-bit CDAC is sequenced by the SAR
starting from the MSB to the LSB at the beginning of the
conversion cycle to provide an output voltage from the CDAC
thatisequaltotheinputsignalvoltage(whichisdividedbythe
input voltage divider network). The comparator determines
whether the addition of each successively-weighted bit volt-
age causes the CDAC output voltage summation to be
greater or less than the input voltage; if the sum is less, the
bit is left on; if more, the bit is turned off. After testing all the
bits, the SAR contains a 12-bit binary code which accurately
represents the input signal to within ±1/2 LSB.
POWER SUPPLIES
The supply voltage for the SPT774 must be kept as quiet as
possiblefromnoisepickupandalsoregulatedfromtransients
or drops. Because the part has 12-bit accuracy, voltage
spikes on the supply lines can cause several LSB deviations
on the output. Switching power supply noise can be a
problem. Careful filtering and shielding should be employed
to prevent the noise from being picked up by the converter.
The internal reference provides the voltage reference to the
CDACwithexcellentstabilityovertemperatureandtime. The
reference is trimmed to 2.5 volts and can supply at least
0.5 mA to an external load. Any external load on the SPT774
reference must remain constant during conversion.
V
DD
should be bypassed with a 10 µF tantalum capacitor
located close to the converter to filter noise and counter the
problems caused by the variations in supply current. V is
EE
The sample-and-hold feature is a bonus of the CDAC archi-
tecture. Therefore the majority of the S/H specifications are
included within the A/D specifications.
only used as a logic input and is immune to typical supply
variation.
GROUNDING CONSIDERATIONS
Although the sample-and-hold circuit is not implemented in
the classical sense, the sampling nature of the capacitive
DAC makes the SPT774 appear to have a built-in sample-
and-hold. This sample-and-hold action substantially in-
creases the signal bandwidth of the SPT774 over that of
similar competing devices.
Resistance of any path between the analog and digital
grounds should be as low as possible to accommodate the
ground currents present with this device.
To achieve specified accuracy, a double-sided printed circuit
board with a copper ground plane on the component side is
recommended. Keep analog signal traces away from digital
lines. It is best to lay the PC board out such that there is an
analog section and a digital section with a single point ground
connection between the two through an RF bead located as
closetothedeviceaspossible. Ifpossible, runanalogsignals
between ground traces and cross digital lines at right angles
only.
Note that even though the user may use an external sample-
and-hold for very high frequency inputs, the internal sample-
and-hold still provides a very useful isolation function. Once
the internal sample is taken by the CDAC capacitance, the
input of the SPT774 is disconnected from the user’s sample-
and-hold. This prevents transients occurring during conver-
sion from affecting the attached sample-and-hold buffer. All
SPT774
SPT
6
8/1/00
The analog and digital common pins should be tied together
as close to the package as possible to guarantee best
performance. The code dependent currents flow through the
Thegainadjustmentshouldbedoneatpositivefullscale.The
ideal input corresponding to the last code change is applied.
This is 1 and 1/2 LSB below the nominal full scale which is
+9.9963 V for the 10 V range and +19.9927 V for the 20 V
range. Adjust the gain potentiometer R2 for flicker between
codes 1111 1111 1110 and 1111 1111 1111. If calibration is
not necessary for the intended application, replace R2 with a
50 Ω, 1% metal film resistor and remove the network from the
BIPOFFpin. ConnecttheBIPOFFpintoAGND. Connectthe
analog input to the 10 V IN pin for the 0 to 10 V range or to the
20 V IN pin for the 0 to 20 V range.
V
DD
terminal and not through the analog and digital common
pins.
RANGE CONSIDERATIONS
The SPT774 may be operated by a microprocessor or in the
stand-alone mode. The part has four standard input ranges:
0 V to +10 V, 0 V to +20 V, ±5 V and ±10 V. The maximum
errors that are listed in the specifications for gain and offset
may be adjusted externally to zero as explained in the next
two sections.
BIPOLAR
The gain and offset errors listed in the specification may be
adjusted to zero using the potentiometers R1 and R2. (See
figure 6.) If adjustment is not needed, either or both pots may
be replaced by a 50 Ω, 1% metal film resistor.
CALIBRATION & CONNECTION PROCEDURES
UNIPOLAR
The calibration procedure consists of adjusting the
converter’s most negative output to its ideal value for offset
adjustment and then adjusting the most positive output to its
ideal value for gain adjustment.
Tocalibrate, connecttheanaloginputsignaltothe10VINpin
for a ±5 V range or to the 20 V IN pin for a ±10 V range. First
apply a DC input voltage 1/2 LSB above negative full scale
which is -4.9988 V for the ±5 V range or -9.9976 V for the ±10
V range. Adjust the offset potentiometer R1 for flicker be-
tween output codes 0000 0000 0000 and 0000 0000 0001.
Next, apply a DC input voltage 1 and 1/2 LSB below positive
full scale which is +4.9963 V for the ±5 V range or +9.9927 V
for the ±10 V range. Adjust the gain potentiometer R2 for
flicker between codes 1111 1111 1110 and 1111 1111 1111.
Starting with offset adjustment and referring to figure 5, the
midpoint of the first LSB increment should be positioned at
the origin to get an output code of all 0s. To do this, an input
of +1/2 LSB or +1.22 mV for the 10 V range and +2.44 mV for
the 20 V range should be applied to the SPT774. Adjust the
offset potentiometer R1 for code transition flickers between
0000 0000 0000 and 0000 0000 0001.
Figure 5 - Unipolar Input Connections
Figure 6 - Bipolar Input Connections
Output Bits
Output Bits
R/C
R/C
CS
Ao
Nibble A
Nibble B
Nibble C
CS
Ao
Nibble A
Nibble B
Nibble C
Control
Logic
Control
Logic
Three-State Buffers And Control
Three-State Buffers And Control
12/8
CE
12/8
CE
12-Bits
12-Bits
STS
V
12-Bit SAR
Oscillator
12-Bit SAR
Oscillator
STS
V
+5 V
+5 V
R1
DD
DD
100 kΩ
.1 µF
DGND
Strobe
Strobe
.1 µF
-15 V
+15 V
12-Bits
12-Bits
DGND
Comp
Comp
0 to 10 V
CDAC
Sample/Hold
MSB
±5 V
CDAC
10 V In
20 V In
Sample/Hold
MSB
10 V In
LSB
Analog
Inputs
LSB
Analog
Inputs
100 kΩ
20 V In
BIP Off
0 to 20 V
BIP Off
±10 V
100 Ω
100 Ω
R1
Offset/Gain
Trim Network
Offset/Gain
Trim Network
Ref
Ref
V
Out
Ref
Ref
Amp
V
Out
Ref
Amp
Ref
R2
100 Ω
(Calibration)
100 Ω
V
In
R1
Ref
V
In
Ref
V
EE
V
EE
SPT774
SPT
7
8/1/00
ALTERNATIVE
Figure 7 - Interfacing the SPT774 to an 8-Bit Data Bus
In some applications, a full scale of 10.24 V (for an LSB of
2.5 mV)or20.48V(foranLSBof5.0mV)ismoreconvenient.
In the unipolar mode of operation, replace R2 with a 200 Ω
potentiometer and add 150 Ω in series with the 10 V IN pin for
10.24 V input range or 500 Ω in series with the 20 V IN pin for
20.48 V input range. In bipolar mode of operation, replace R1
with a 500 Ω potentiometer (in addition to the previous
changes). The calibration will remain similar to the standard
calibration procedure.
Address Bus
Ao
~
STS
MSB
12/8
Ao
Data
Bus
CONTROLLING THE SPT774
The SPT774 can be operated by most microprocessor sys-
tems due to the control input pins and on-chip logic. It may
alsobeoperatedinthestand-alonemodeandenabledbythe
R/ input pin. Full µP control consists of selecting an 8 or
C
12-bitconversioncycle,initiatingtheconversion,andreading
the output data when ready. The output read has the options
of choosing either 12-bits at once or 8 bits followed by
4-bits in a left-justified format. AllfivecontrolinputsareTTL/
LSB
DIG
COM
CMOS compatible and include 12/ ,
, Ao, R/ and CE.
C
CS
8
CONTROLLED OPERATION
The use of these inputs in controlling the converter’s opera-
tionsisshownintableI, andtheinternalcontrollogicisshown
in a simplified schematic in figure 10.
CONVERSION LENGTH
A conversion start transition latches the state of Ao as shown
in figure 7 and table I. The latched state determines if the
conversion stops with 8 bits (Ao high) or continues for 12 bits
(Aolow). Ifall12bitsarereadfollowingan8-bitconversion, the
threeLSBswillbealogic0andDB3willbealogic1.Aoislatched
because it is also involved in enabling the output buffers as
will be explained later. No other control inputs are latched.
STAND-ALONE OPERATION
The simplest interface is a control line connected to R/ . The
output controls must be tied to known states as follows: CE
C
and12/ arewiredhigh, Aoand
arewiredlow. Theoutput
CS
8
C
data arrives in words of 12-bits each. The limits on R/ duty
cycle are shown in figures 3 and 4. It may have a duty cycle
within and including the extremes shown in the specifica-
C
tions. In general, data may be read when R/ is high unless
CONVERSION START
STS is also high, indicating a conversion is in progress.
A conversion may be initiated by a logic transition on any of
Table I - Truth Table for the SPT774 Control Inputs
C
, R/ , as shown in table I. The last
the three inputs: CE,
CS
of the three to reach the correct state starts the conversions,
so one, two or all three may be dynamically controlled. The
nominal delay from each is the same and all three may
change state simultaneously. In order to assure that a par-
ticular input controls the start of conversion, the other two
should be set up at least 50 ns earlier. Refer to the convert
modetimingspecifications.TheConvertStarttimingdiagram
is illustrated in figure 1.
Operation
CE
0
CS
X
R/C
X
12/8
X
Ao
X
X
0
None
X
1
X
X
None
0
0
X
Initiate 12 bit conversion
Initiate 8 bit conversion
Initiate 12 bit conversion
Initiate 8 bit conversion
Initiate 12 bit conversion
Initiate 8 bit conversion
Enable 12 bit Output
Enable 8 MSB's Only
0
0
X
1
1
1
1
1
1
1
1
0
X
0
0
X
1
0
0
0
0
0
X
0
The output signal STS is the status flag and goes high only
when a conversion is in progress. While STS is high, the
output buffers remain in a high impedance state so that data
can not be read. Also, when STS is high, an additional Start
Convert will not reset the converter or reinitiate a conversion.
Note, if Ao changes state after a conversion begins, an
additional Start Convert command will latch the new start of
Ao and possibly cause a wrong cycle length for that conver-
sion (8 versus 12 bits).
X
1
1
1
1
1
X
0
0
0
1
Enable 4 LSB's Plus 4
Trailing Zeroes
SPT774
SPT
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READING THE OUTPUT DATA
SAMPLE-AND-HOLD (S/H) CONTROL MODE
Theoutputdatabuffersremaininahighimpedancestateuntil
This control mode is provided to allow full use of the internal
S/H, eliminating the need for an external S/H in most applica-
tions. The SPT774 in the control mode also eliminates the
need for one of the control signals, usually the convert
command. The command that puts the internal S/H in the
hold state also initiates a conversion, reducing time con-
straints in many systems. As soon as the conversion is
completed the internal S/H immediately begins slewing to
track the input signal. See figure 9.
C
the following four conditions are met: R/ is high, STS is low,
CE is high, and is low. The data lines become active in
CS
response to the four conditions and output data according to
8
the conditions of 12/ and Ao. The timing diagram for this
8
process is shown in figure 2. When 12/ is high, all 12 data
outputs become active simultaneously and the Ao input is
ignored. This is for easy interface to a 12 or 16-bit data bus.
The 12/ input is usually tied high or low, although it is
8
8
TTL/CMOS compatible. When 12/ is low, the output is
In the control mode it is assumed that during the required 1.4
µs acquisition time the signal is not slewing faster than the
slew rate of the SPT774. No assumption is made about the
input level after the convert command arrives since the input
signal is sampled and conversion begins immediately after
the convert command. This means that the convert com-
mand can be used to switch an input multiplexer or change
gains on a programmable gain amplifier, allowing the input
signal to settle before the next acquisition at the end of the
conversion. Because aperture jitter is minimized by the
internal S/H, a high input frequency can be converted without
an external S/H. See table II.
separated into two 8-bit bytes as shown below.
8
Figure 8 - Output When 12/ Is Low
BYTE 1
BYTE 2
X X X X
X X X X
X X X X O O O O
MSB
LSB
This configuration makes it easy to connect to an 8-bit data
bus as shown in figure 7. The Ao control can be connected to
the least significant bit of the address bus in order to store the
outputdataintotwoconsecutivememorylocations. WhenAo
is pulled low, the 8 MSBs are enabled only. When Ao is high,
the 4 MSBs are disabled, bits 4 through 7 are forced to a zero
and the four LSBs are enabled. The two byte format is left
justified data as shown above and can be considered to have
a decimal point or binary to the left of byte 1.
Table II - Conversion Timing (V = +5 V)
EE
S/H Control Mode
Parameter
Min
Typ Max Units
Throughput Time (t + )
AQ tC
12-Bit Conversions
8-Bit Conversions
8
6
8.5
6.3
µs
µs
Ao may be toggled without damage to the converter at any
time. Break-before-make action is guaranteed between the
two data bytes. This assures that the outputs in figure 7 will
never be enabled at the same time.
Conversion Time (t )
C
12-Bit Conversions
8-Bit Conversions
6.4
4.4
1.4
20
µs
µs
µs
ns
ns
Acquisition Time(t
)
AC
Aperture Delay (t
)
AP
In figure 2, it can be seen that a read operation usually begins
after the conversion is completed and STS is low. If earlier
access is needed, the read can begin no later than the
Aperture Uncertainty (t )
0.3
J
addition of time t
and t before STS goes low.
HS
DD
Figure 9 - S/H Control Mode Timing (V = +5 V)
EE
R/C
t
C
t
AP
Signal Acquisition
Conversion
Signal Acquisition
t
AQ
SPT774
SPT
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Figure 10 - Control Logic
Nibble B Zero
Override
Nibble A,B
Input Buffers
12/8
CS
Nibble C
Read Control
A
R/C
CE
H
D
Q
CK
R
EOC8
CK
Delay
Q
STS
D
Q
AO Latch
EOC12
PACKAGE OUTLINES
28-Lead PDIP
INCHES
MILLIMETERS
MIN MAX
SYMBOL
MIN
MAX
0.250
A
B
C
D
E
F
G
H
I
6.35
5.08
0.115
0.200
0.022
0.100
0.070
0.015
0.195
0.625
0.580
1.565
0.040
2.92
0.014
0.36
0.56
2.54
K
0.030
0.008
0.125
0.600
0.485
1.380
0.005
0.76
0.20
1.78
0.38
28
3.18
4.95
15.24
12.32
35.05
0.13
15.88
14.73
39.75
1.02
I
J
1
K
J
H
G
A
B
F
C
D
E
SPT774
SPT
10
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PACKAGE OUTLINES
28-Lead Sidebrazed
28
1
H
INCHES
MILLIMETERS
MIN MAX
2.36
SYMBOL
MIN
MAX
A
B
C
D
E
F
G
H
I
0.077
0.016
0.095
0.093
0.020
0.105
.050 typ
0.060
0.235
1.412
0.605
0.012
0.620
1.96
0.41
2.41
0.51
2.67
I
J
1.27 typ
1.52
0.040
0.215
1.388
0.585
0.009
0.600
1.02
5.46
G
5.97
A
35.26
14.86
0.23
35.86
15.37
0.30
E
F
J
15.24
15.75
C
B
D
28-Lead SOIC
INCHES
MILLIMETERS
SYMBOL
MIN
MAX
MIN
MAX
A
B
C
D
E
F
G
H
I
0.696
0.004
0.712
0.012
.050 typ
0.019
0.012
0.104
0.050
0.419
0.299
17.68
0.10
18.08
0.30
28
1.27 typ
0.48
0.014
0.009
0.080
0.016
0.394
0.291
0.36
0.23
2.03
0.41
10.01
7.39
I
H
0.30
2.64
1
1.27
10.64
7.59
A
H
F
B
C
D
G
E
SPT774
SPT
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PIN ASSIGNMENTS
PIN FUNCTIONS
NAME
FUNCTION
1
2
3
V
DD
STS 28
DB11 27
DB10 26
DB9 25
DB8 24
DB7 23
DB6 22
DB5 21
DB4 20
DB3 19
DB2 18
DB1 17
DB0 16
DGND 15
V
Logic Supply Voltage, Nominally +5 V
Data Mode Selection
Chip Selection
12/8
CS
DD
12/
CS
Ao
8
4
5
Ao
Byte Address/Short Cycle
Read/Convert
R/C
CE
N/C
R/
C
6
7
CE
Chip Enable
V
Mode Control Voltage, Nominally +5 V
Reference Output, Nominally +2.5 V
Analog Ground
EE
8
9
REF OUT
AGND
REF OUT
AGND
10 REF IN
11
REF IN
N/C
Reference Input
V
EE
Pin Not Connected to Device
Bipolar Offset
12 BIP OFF
13 10 V IN
BIP OFF
10 V IN
20 V IN
DGND
10 Volt Analog Input
20 Volt Analog Input
Digital Ground
14 20 V IN
28-LEAD DIP/SOIC
DB0 - DB11 Digital Data Output
DB11 - MSB
DB0 - LSB
STS
Status
ORDERING INFORMATION
LINEARITY ERROR
PACKAGE
TYPE
PART NUMBER
TEMPERATURE RANGE
MAX
SPT774BCN
0 to +70 °C
±1/2 LSB
28L Plastic DIP
SPT774BCJ
SPT774BCS
SPT774CCN
SPT774CCJ
SPT774CCS
0 to +70 °C
0 to +70 °C
0 to +70 °C
0 to +70 °C
0 to +70 °C
±1/2 LSB
±1/2 LSB
±1 LSB
28L Sidebrazed DIP
28L SOIC
28L Plastic DIP
28L Sidebrazed DIP
28L SOIC
±1 LSB
±1 LSB
SignalProcessingTechnologies,Inc.reservestherighttochangeproductsandspecificationswithoutnotice.Permissionisherebyexpressly
granted to copy this literature for informational purposes only. Copying this material for any other use is strictly prohibited.
WARNING - LIFE SUPPORT APPLICATIONS POLICY - SPT products should not be used within Life Support Systems without the specific
written consent of SPT. A Life Support System is a product or system intended to support or sustain life which, if it fails, can be reasonably
expected to result in significant personal injury or death.
Signal Processing Technologies believes that ultrasonic cleaning of its products may damage the wire bonding, leading to device
failure. It is therefore not recommended, and exposure of a device to such a process will void the product warranty.
SPT774
SPT
12
8/1/00
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