SS1621_技术文档

RAM Mapping 32 X 4 LCD Controller for I/O uC

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General Descriptions

The SS1621 is a 128-pattern (32x4), memory mapping, and multi-function LCD driver. The

S/W configuration feature of the SS1621 makes it suitable for multiple LCD applications including

LCD modules and display subsystems. Only three or four lines are required for the interface be-

tween the host controller and the SS1621. The SS1621 contains a power down command to reduce

power consumption.

Features

• Operating voltage: 2.4V~5.2V.

• Built-in 256kHz RC oscillator.

• External 32.768kHz crystal or 256kHz frequency source input.

• Selection of 1/2 or 1/3 bias, and selection of 1/2 or 1/3 or 1/4 duty LCD applications.

• Internal time base frequency sources.

• Two selectable buzzer frequencies (2kHz/4kHz).

• Built-in time base generator and WDT.

• Time base or WDT overflow output.

• Power down command reduces power Consumption.

• 8 kinds of time base/WDT clock sources.

• 32x4 LCD driver.

• Built-in 32x4 bit display RAM.

• 3-wire serial interface.

• Internal LCD driving frequency source.

• Software configuration feature.

• Data mode and command mode instructions.

• R/W address auto increment.

• Three data accessing modes.

• VLCD pin for adjusting LCD operating voltage.

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SS1621

Block Diagram

BZ

Watchdog Timer

&

Time Base Generator

Tone

Generator

IRQ

VDD

GND

VLCD

COM0

CS

WR

COM3

SEG0

LCD Driver

&

Bias Circuit

RD

Control

Logic

DATA

SEG31

&

Timing

Generator

OSCI

OSCO

Display Memory

Note: CS: Chip selection

BZ, BZ: Tone outputs

WR, RD, DATA: Serial interface

IRQ: Time base or WDT overflow output

COM0~COM3, SEG0~SEG31: LCD outputs

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SS1621

Pin Assignment

SS1621B-48SSOP

SS1621D-28SKDIP

SS1621BL

-48LQFP

SS1621B

-48LQFP

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SS1621

PIN Description

PIN Name

I/O

Function

Chip selection input with pull-high resistor

When the CS is logic high, the data and command read from or written

to the SS1621 are disabled. The serial interface circuit is also reset. But

if CS is at logic low level and is input to the CS pad, the data and com-

mand transmission between the host controller and the SS1621 are all

enabled.

CS

I

READ clock input with pull-high resistor

Data in the RAM of the SS1621 are clocked out on the falling edge of

the RD signal. The clocked out data will appear on the DATA line. The

host controller can use the next rising edge to latch the clocked out data.

RD

I

WRITE clock input with pull-high resistor

Data on the DATA line are latched into the SS1621 on the rising edge of

the WR signal.

WR

DATA

GND

I/O Serial data input/output with pull-high resistor

—

O

Negative power supply, ground

OSCO

The OSCI and OSCO pads are connected to a 32.768kHz crystal in order

to generate a system clock. If the system clock comes from an external

clock source, the external clock source should be connected to the OSCI

pad. But if and on-chip RC oscillator is selected instead, the OSCI and

OSCO pads can be left open.

OSCI

I

VLCD

VDD

I

LCD power input

—

O

Positive power supply

IRQ

Time base or WDT overflow flag, NMOS open drain output

2kHz or 4kHz tone frequency output pair

LCD common outputs

BZ, BZ

COM0~COM3

SEG0~SEG31

LCD segment outputs

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SS1621

Absolute Maximum Ratings

Supply Voltage…………...…..…-0.3V ~ 5.5V

Input Voltage……… V_SS- 0.3V ~ V_DD+ 0.3V

Storage Temperature……………-50^°C ~ 125^°C

Operating Temperature…………..-25^°C ~ 75^°C

Note: These are stress ratings only. Stresses exceeding the range specified under “Absolute Maxi-

mum Ratings” may cause substantial damage to the device. Functional operation of this de-

vice at other conditions beyond those listed in the specification is not implied and prolonged

exposure to extreme conditions may affect device reliability.

D.C. Characteristics

Test Conditions

Symbol

Parameter

Min.

Typ.

Max.

Unit

V_DD

Conditions

V_DDOperating Voltage

I_DD1Operating Current

—

3V

5V

3V

5V

3V

5V

3V

5V

3V

5V

3V

5V

—

2.4

—

150

300

60

5.2

300

600

120

240

200

400

5

V

µA

V

No load/LCD ON

On-chip RC oscillator

—

No load/LCD ON

Crystal oscillator

I_DD2Operating Current

I_DD3Operating Current

I_STBStandby Current

—

120

100

200

0.1

0.3

—

No load/LCD ON

External clock source

—

No load

Power down mode

—

10

0

0.6

1.0

3.0

5.0

—

V_IL

V_IH

I_OL1

I_OH1

Input Low Voltage

Input High Voltage

DATA, BZ, BZ, IRQ

DATA, BZ, BZ

DATA, WR, CS, RD

0

—

V

2.4

4.0

0.5

1.3

-0.4

-0.9

80

—

V

—

V

3V V_OL=0.3V

5V V_OL=0.5V

3V V_OH=2.7V

5V V_OH=4.5 V

3V V_OL=0.3V

1.2

2.6

-0.8

-1.8

150

250

-120

-200

120

200

-70

-100

80

mA

µA

kΩ

—

I_OL2LCD Common Sink Current

5V

V

_OL=0.5V

150

-80

-120

60

—

3V V_OH=2.7V

5V V_OH=4.5 V

3V V_OL=0.3V

—

LCD Common Source Cur-

I_OH2

rent

—

I_OL3LCD Segment Sink Current

5V

V

_OL=0.5V

120

-40

-70

40

—

3V V_OH=2.7V

5V V_OH=4.5 V

3V

—

LCD Segment Source Cur-

I_OH3

rent

—

150

100

R_PHPull-high Resistor

DATA, WR, CS, RD

5V

30

60

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SS1621

A.C. Characteristics

Test Conditions

Conditions

Sym.

Parameter

Min.

Typ.

Max.

Unit

V_DD

3V

5V

3V

5V

3V

5V

—

256

—

kHz

Hz

f_SYS1System Clock

f_SYS2System Clock

f_SYS3System Clock

On-chip RC oscillator

Crystal oscillator

32.768

256

—

External clock source

256

—

On-chip RC oscillator

Crystal oscillator

F_SYS1/1024

F_SYS2/128

F_SYS3/1024

n/f_LCD

—

f_LCDLCD Clock

—

Hz

External clock source

n: Number of COM

—

Hz

—

t_COMLCD Common Period

s

3V

5V

3V

5V

150

300

75

kHz

f_CLK1Serial Data Clock (WR Pin)

Duty cycle 50%

f_CLK2Serial Data Clock (RD Pin)

f_TONETone Frequency

Duty cycle 50%

On-chip RC oscillator

CS

150

—

2.0 or 4.0

250

3V

5V

Serial Interface Reset Pulse Width

t_CS

—

ns

μs

(Figure 3)

Write mode

Read mode

Write mode

Read mode

3.34

6.67

1.67

3.34

—

3V

5V

WR, RD Input Pulse Width

t_CLK

(Figure 1)

Rise/Fall Time Serial Data Clock

3V

5V

3V

5V

3V

5V

3V

5V

3V

5V

t_r,t_f

—

120

100

—

ns

Width

(Figure 1)

Setup Time for DATA to WR, RD

Clock Width

t_su

(Figure 2)

Hold Time for DATA to WR, RD

Clock Width

t_h

(Figure 2)

Setup Time for CS to WR, RD

Clock Width

t_su1

(Figure 3)

Hold Time for CS to WR, RD

Clock Width

t_h1

(Figure 3)

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SS1621

t_f

VALID DATA

V_DD

WR, RD

Clock

V_DD

90%

50%

10%

DB

50%

t_SU

GND

t_CLK

t_h

V_DD

WR, RD

Clock

Figure 1

50%

GND

Figure 2

t_CS

V_DD

CS

50%

GND

t_h1

t_su1

V_DD

WR, RD

Clock

50%

GND

FIRST

Clock

LAST

Clock

Figure 3

Functional Description

the

READ,

WRITE,

and

Display memory – RAM

READ-MODIFY-WRITE commands. The

following is a mapping from the RAM to the

LCD pattern:

The static display memory (RAM) is or-

ganized into 32x4 bits and stores the dis-

played data. The contents of the RAM are di-

rectly mapped to the contents of the LCD

System oscillator

The SS1621 system clock is used to

generate the time base/Watchdog Timer

(WDT) clock frequency, LCD driving clock,

and tone frequency. The source of the clock

may be from an on-chip RC oscillator

(256kHz), a crystal oscillator (32.768kHz), or

an external 256kHz clock by the S/W setting.

The configuration of the system oscillator is

as shown. After the SYS DIS command is

executed, the system clock will stop and the

LCD bias generator will turn off. That com-

mand is, however, available only for the

COM3 COM2 COM1 COM0

SEG0

SEG1

SEG2

SEG3

0

1

2

3

Address 6 bits

(A5, A4, …, A0)

SEG31

31

Data

Addr

D3

D2

D1

D0

Data 4 bits

(D3, D2, D1, D0)

RAM mapping

driver. Data in the RAM can be accessed by

OSCI

Crystal Oscillator

32768Hz

OSCO

External Clock Source

256kHz

System

Clock

1/8

On-chip RC Oscillator

256kHz

System oscillator configuration

p. 7

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SS1621

on-chip RC oscillator or for the crystal oscil-

lator. Once the system clock stops, the LCD

display will become blank, and the time

base/WDT lose its function as well.

Where the value of n ranges from 0 to 7

by command options. The 32kHz in the above

equation indicates that the source of the sys-

tem frequency is derived from a crystal oscil-

lator of 32.768kHz, an on-chip oscillator

(256kHz), or an external frequency of

256kHz.

The LCD OFF command is used to turn

the LCD bias generator off. After the LCD

bias generator switches off by issuing the

LCD OFF command, using the SYS DIS

command reduces power consumption, serv-

ing as a system power down command. But if

the external clock source is chosen as the sys-

tem clock, using the SYS DIS command can

neither turn the oscillator off nor carry out the

power down mode. The crystal oscillator op-

tion can be applied to connect an external

frequency source of 32kHz to the OSCI pin.

In this case, the system fails to enter the

power down mode, similar to the case in the

external 256kHz clock source operation. At

the initial system power on, the SS1621 is at

the SYS DIS state.

If an on-chip oscillator (256kHz) or an

external 256kHz frequency is chosen as the

source of the system frequency, the frequency

source is by default prescaled to 32kHz by a

3-stage prescaler. Employing both the time

base generator and the WDT related com-

mands, one should be careful since the time

base generator and WDT share the same

8-stage counter. For example, invoking the

WDT DIS command disables the time base

generator whereas executing the WDT EN

command not only enables the time base gen-

erator but activates the WDT time-out flag

output (connect the WDT time-out flag to the

IRQ pin). After the TIMER EN command is

transferred, the WDT is disconnected from

the IRQ pin, and the output of the time base

generator is connected to the IRQ pin. The

WDT can be cleared by executing the CLR

WDT command, and the contents of the base

time generator is cleared by executing the

CLR WDT or the CLR TIMER command.

The CLR WDT or the CLR TIMER com-

mand should be executed prior to the WDT

EN or the TIMER EN command respectively.

Before executing the IRQ EN command the

CLR WDT or CLR TIMER command should

be executed first. The CLR TIMER command

has to be executed before switching from the

WDT mode to the time base mode. Once the

WDT time-out occurs, the IRQ pin will stay

at a logic low level until the CLR WDT or the

IRQ DIS command is issued. After the IRQ

output is disabled the IRQ pin will remain at

the floating state. The IRQ output can be en-

abled or disabled by executing the IRQ EN

or the IRQ DIS command, respectively. The

IRQ EN makes the output of the time base

Time base and Watchdog Timer (WDT)

The time base generator is comprised by

an 8-stage count-up ripple counter and is de-

signed to generate an accurate time base. The

watch dog timer (WDT), on the other hand, is

composed of and 8-stage time base generator

along with a 2-stage count-up counter, and is

designed to break the host controller or other

subsystems from abnormal states such as un-

known or unwanted jump, execution errors,

etc. The WDT time-out will result in the set-

ting of and internal WDT time-out flag. The

outputs of the time base generator and of the

WDT time-out flag can be connected to the

IRQ output by a command option. There are

totally eight frequency sources available for

the time base generator and the WDT clock.

The frequency is calculated by the following

equation.

32kHz

f_WDT

=

2ⁿ

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SS1621

Name

LCD OFF

LCD ON

Command Code

1 0 0 0 0 0 0 0 0 1 0 X

1 0 0 0 0 0 0 0 0 1 1 X

Function

Turn off LCD outputs

Turn on LCD outputs

c=0:1/2 bias option

c=1:1/3 bias option

BIAS & COM 1 0 0 0 0 1 0 a b X c X

ab=00:2 commons option

ab=01:3 commons option

ab=10:4 commons option

generator or of the WDT time-out flag appear

on the IRQ pin. The configuration of the time

base generator along with the WDT are as

shown. In the case of on-chip RC oscillator or

crystal oscillator, the power down mode can

reduce power consumption since the oscillator

can be turned on or off by the corresponding

system commands. At the power down mode

the time base/WDT loses all its functions.

LCD driver

The SS1621 is a 128 (32x4) patterns

LCD driver. It can be configured as 1/2 or 1/3

bias and 2 or 3 or 4 commons of LCD driver

by the S/W configuration. This feature makes

the SS1621 suitable for multiply LCD appli-

cations. The LCD driving clock is derived

from the system clock. The value of the driv-

ing clock is always 256Hz even when it is at a

32.768kHz crystal oscillator frequency, or an

external frequency. The LCD corresponding

commands are summarized in the table.

On the other hand, if an external clock is

selected as the source of sys tem frequency

the SYS DIS command turns out invalid and

the power down mode fails to be carried out.

That is, after the external clock source is se-

lected, the SS1621 will continue working un-

til system power fails or the external clock

source is removed. After the system power on,

the IRQ will be disabled.

The bold form of 100, namely 100, in-

dicates the command mode ID. If successive

commands have been issued, the command

mode ID except for the first command will be

omitted. The LCD OFF command turns the

LCD display off by disabling the LCD bias

generator. The LCD ON command, on the

other hand, turns the LCD display on by ena-

bling the LCD bias generator. The BIAS and

COM are the LCD panel related commands.

Using the LCD related commands; the

SS1621 can be compatible with most types of

LCD panels.

Tone output

A simple tone generator is implemented

in the SS1621. The tone generator can output

a pair of differential driving signals on the BZ

and BZ, which are used to generate a single

tone. By executing the TONE4K and

TONE2K commands there are two tone fre-

quency outputs selectable. The TONE4K and

TONE2K commands set the tone frequency to

4kHz and 2kHz, respectively. The tone output

can be turned on or off by invoking the TONE

ON or the TONE OFF command. The tone

outputs, namely BZ and BZ, area pair of dif-

ferential driving outputs used to drive a piezo

buzzer. Once the system is disabled or the

tone output is inhibited, the BZ and the BZ

output will remain at low level.

Command format

The SS1621 can be configured by the

S/W setting. There are two mode commands

to configure the SS1621 resources and to

transfer the LCD display data. The configura-

tion mode of the SS1621 is called command

mode, and its command mode IC is 100. The

command mode consists of system configura-

tion command, a system frequency selection

command, a LCD configuration command, a

tone frequency selection command,

a

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SS1621

timer/WDT setting command, and an operat-

ing command. The data mode, on the other

hand, includes READ, WRITE, and

READ-MODIFY-WRITE operations. The

following are the data mode Ids and the com-

mand mode ID:

controller and the SS1621. If the CS pin is

set to 1, the data and command issued be-

tween the host controller and the SS1621 are

first disabled and then initialized. Before is-

suing a mode command or mode switching, a

high level pulse is required to initialize the

serial interface of the SS1621. The DATA

line is the serial data input/output line. Data to

be read or written or commands to be written

have to be passed through the DATA line.

The RD line is the READ clock input. Data

in the RAM are clocked out on the falling

edge of the RD signal, and the clocked out

data will then appear on the DATA line. It is

recommended that the host controller read in

correct data during the interval between the

rising edge and the next falling edge of the

RD signal. The WR line is the WRITE clock

input. The data, address, and command on the

DATA line are all clocked into the SS1621 on

the rising edge of the WR signal. There is an

optional IRQ line to be used as an interface

between the host controller and the SS1621.

The IRQ pin can be selected as a timer output

or a WDT overflow flag output by the S/W

setting. The host controller can perform the

time base or the WDT function by being con-

nected with the IRQ pin of the SS1621.

Operation

Mode

Data

ID

READ

WRITE

1 10

1 01

READ-MODIFY-WRITE

COMMAND

Command 1 00

The mode command should be issued

before the data or command is transferred. If

successive commands have been issued, the

command mode ID, namely 100, can be

omitted. While the system is operating in the

non-successive

command

or

the

non-successive address data mode, the CS

pin should be set to “1” and the previous op-

eration mode will be reset also. Once the CS

pin returns to “0” a new operation mode ID

should be issued first.

Interfacing

Only four lines are required to interface

with the SS1621. The CS line is used to ini-

tialize the serial interface circuit and to ter-

minate the communication between the host

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SS1621

Timing Diagrams

READ mode (command code: 1 1 0 )

CS

WR

RD

DATA

1

0

A5 A4 A3 A2 A1 A0 D0 D1 D2 D3

1

0

A5 A4 A3 A2 A1 A0 D0 D1 D2 D3

Memory Address 1 (MA1) Data (MA1)

Memory Address 2 (MA2) Data (MA2)

CS

WR

RD

DATA

1

0

A5 A4 A3 A2 A1 A0 D0 D1 D2 D3 D0 D1 D2 D3 D0 D1 D2 D3 D0 D1 D2 D3 D0

Memory Address (MA) Data (MA) Data (MA+1) Data (MA+2) Data (MA+3)

READ mode (successive address reading)

WRITE mode (command code: 1 0 1 )

WRITE mode (successive address writing)

CS

WR

DATA

1

0

1

A5 A4 A3 A2 A1 A0 D0 D1 D2 D3 D0 D1 D2 D3 D0 D1 D2 D3 D0 D1 D2 D3 D0

Memory Address (MA) Data (MA) Data (MA+1) Data (MA+2) Data (MA+3)

CS

WR

DATA

1

0

1

A5 A4 A3 A2 A1 A0 D0 D1 D2 D3

1

0

1

A5 A4 A3 A2 A1 A0 D0 D1 D2 D3

Memory Address 1 (MA1) Data (MA1)

Memory Address 2 (MA2) Data (MA2)

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SS1621

READ-MODIFY-WRITE mode (command code: 1 0 1 )

CS

WR

RD

1

0

1 A5 A4 A3 A2 A1 A0 D0 D1 D2 D3 D0 D1 D2 D3

Memory Address 1 (MA1) Data (MA1) Data (MA1)

1

0

1 A5 A4 A3 A2 A1 A0 D0 D1 D2 D3 D0 D1 D2 D3

Memory Address 2 (MA2) Data (MA2) Data (MA2)

DATA

READ-MODIFY-WRITE mode (successive address accessing)

CS

WR

RD

1

0

1 A5 A4 A3 A2 A1 A0 D0 D1 D2 D3 D0 D1 D2 D3 D0 D1 D2 D3 D0 D1 D2 D3 D0 D1 D2 D3 D0 D1 D2 D3 D0 D1 D2

Memory Address (MA) Data (MA) Data (MA) Data (MA+1) Data (MA+1) Data (MA+2) Data (MA+2)

DATA

Command mode (command code: 1 0 0 )

CS

WR

DATA

1

0

C8 C7 C6 C5 C4 C3 C2 C1 C0

Command 1

C8 C7 C6 C5 C4 C3 C2 C1 C0

Command i

Command

or

Data Mode

Command…

Mode (data and command mode)

CS

WR

DATA

Command

or

Command

Address & Data

or

Data Mode

RD

Note: It is recommended that the host controller should read in the data from the DATA line be-

tween the rising edge of the RD line and the falling edge of the next RD line.

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SS1621

Application Circuits

Host controller with a SS1621 display system

CS

VDD

*

RD

*

VR

WR

VLCD

DATA

SS1621

μC

*

R

BZ

Piezo

IRQ

OSCI

Clock Out

OSCO COM0 ~COM3

SEG0~SEG31

External Clock 1

1/2 or 1/3 Bias; 1/2, 1/3 or 1/4 Duty

External Clock 2

On-chip OSC

LCD PANEL

Crystal

32768Hz

Note: The connection of IRQ and RD pin can be selected depending on the requirement of the μC.

The voltage applied to V_LCDpin must be lower than V_DD.

Adjust VR to fit LCD display, at V_DD=5V, V_LCD=4V, VR=15kΩ+20%

Adjust R (external pull-high resistance) to fit user’s time base clock.

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p. 13

SS1621

Command Summary

Name

ID

Command Code

D/C

Function

Def.

READ

1 10 A5A4A3A2A1A0D0D1D2D3

1 01 A5A4A3A2A1A0D0D1D2D3

D Read data from the RAM

D Write data to the RAM

WRITE

READ-MODIFY-WRITE

D READ and WRITE to the RAM

Turn off system oscillator and LCD

SYS DIS

1 00 0000-0000-X

C

Yes

bias generator

SYS EN

1 00 0000-0001-X

1 00 0000-0010-X

1 00 0000-0011-X

1 00 0000-0100-X

1 00 0000-0101-X

1 00 0000-0110-X

1 00 0000-0111-X

1 00 0000-1000-X

1 00 0000-1001-X

C

Turn on system oscillator

Turn off LCD bias generator

Turn on LCD bias generator

Disable time base output

Disable WDT time-out flag output

Enable time base output

LEC OFF

LCD ON

TIMER DIS

WDT DIS

TIMER EN

WDT EN

TONE OFF

TONE ON

Enable WDT time-out flag output

Turn off tone outputs

Yes

Turn on tone outputs

Clear the contents of time base gen-

erator

CLR TIMER

CLR WDT

XTAL 32K

1 00 0000-11XX-X

1 00 0000-111X-X

1 00 0001-01XX-X

C

Clear the contents of WDT stage

System clock source, crystal oscil-

lator

System clock source, external clock

source

RC 256K

1 00 0001-10XX-X

1 00 0001-11XX-X

C

Yes

System clock source, external clock

source

EXT 256K

LCD 1/2 bias option

ab=00:2 commons option

ab=01:3 commons option

ab=10:4 commons option

BLAS 1/2

BLAS 1/3

1 00 0010-abX0-X

1 00 0010-abX1-X

C

LCD 1/3 bias option

ab=00:2 commons option

ab=01:3 commons option

ab=10:4 commons option

TONE 4K

TONE 2K

IRQ DIS

IRQ EN

1 00 010X-XXXX-X

1 00 011X-XXXX-X

1 00 100X-0XXX-X

1 00 100X-1XXX-X

C

Tone frequency, 4kHz

Tone frequency, 2kHz

Disable IRQ output

Enable IRQ output

Yes

Time base/WDT clock

Output: 1Hz

F1

F2

1 00 101X-X000-X

1 00 101X-X001-X

C

The WDT time-out flag after: 4s

Time base/WDT clock

Output: 2Hz

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p. 14

SS1621

Name

ID

Command Code

D/C

Function

Def.

The WDT time-out flag after: 2s

Time base/WDT clock

Output: 4Hz

F4

1 00 101X-X010-X

1 00 101X-X011-X

1 00 101X-X100-X

1 00 101X-X101-X

1 00 101X-X110-X

1 00 101X-X111-X

C

The WDT time-out flag after: 1s

Time base/WDT clock

Output: 8Hz

F8

The WDT time-out flag after: 1/2s

Time base/WDT clock

Output: 16Hz

F16

F32

F64

F128

The WDT time-out flag after: 1/4s

Time base/WDT clock

Output: 32Hz

The WDT time-out flag after: 1/8s

Time base/WDT clock

Output: 64Hz

The WDT time-out flag after: 1/16s

Time base/WDT clock

Output: 128Hz

Yes

The WDT time-out flag after: 1/32s

TEST

1 00 1110-0000-X

1 00 1110-0011-X

C

NORMAL

Note: X: Don’t care

A5~A0: RAM addresses

D3~D0: RAM data

D/C: Data/command mode

Def.: Power on reset default

All the bold forms, namely 110, 101, and 100, are mode commands. Of these, 100

indicates the command mode ID. If successive commands have been issued, the command mode ID

except for the first command will be omitted. The source of the tone frequency and of the time

base/WDT clock frequency can be derived from an on-chip 256kHz RC oscillator, a 32.768kHz

crystal oscillator, or an external 256kHz clock. Calculation of the frequency is based on the system

frequency sources as stated above. It is recommended that the host controller should initialize the

SS1621 after power on reset, for power on reset may fail, which in turn leads to the malfunctioning

of the SS1621.

Last update: 2008-06-03 04:36

p. 15


型号：	SS1621
厂家：	ETC
描述：	RAM MAPPING 32 X 4 LCD CONTROLLER FOR I/O UC 内存映射32× 4 LCD控制器的I / O的uC 控制器 CD
文件：	总15页 (文件大小：309K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

SS1621 [ETC]

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